Digital Design & Dependability Research Group

Publications

2021

BALIHAR, T. and M. NOVOTNÝ. Influence of Synthesis Parameters on Vulnerability to Side-Channel Attacks. In: Proceedings of the 10th Mediterranean Conference on Embedded Computing (MECO'2020), Budva, 2021-06-07/2021-06-10. p. 735-740. ISSN 2637-9511. ISBN 978-0-7381-3361-4. DOI 10.1109/MECO52532.2021.9460288
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Optically induced static power in combinational logic: Vulnerabilities and countermeasures. Microelectronics Reliability. 2021, 124. ISSN 0026-2714. DOI 10.1016/j.microrel.2021.114281
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Standard Cell Design For Data-Independent Static Power Under Illumination. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03, 2021. ISBN 978-80-01-06858-8. Available from: https://pesw.fit.cvut.cz/2021/index.php?page=Proceedings
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Zapojení standardní buňky CMOS se sníženou datovou závislostí statické spotřeby. Patent CZ 308895. 2021-06-30. Available from: https://isdv.upv.cz/doc/FullFiles/Patents/FullDocuments/308/308895.pdf
BOSIO, A., et al. Emerging Technologies: Challenges and Opportunities for Logic Synthesis. In: Proceedings of 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 2021-04-07/2021-04-09. 2021. p. 93-98. ISBN 978-1-6654-3595-6. DOI 10.1109/DDECS52668.2021.9417062
DAS, S., et al. Minimization of Switching Activity of Graphene Based Circuits. In: Proc. of the 34th International Conference on VLSI Design, Guwahati (virtual), 2021-02-20/2021-02-24, 2021. p. 139-144. ISSN 1063-9667. ISBN 978-1-6654-4087-5. DOI 10.1109/VLSID51830.2021.00029
HYNIOVÁ, K. A Design and Stand Tests of Real-time Vehicle Active Suspension. International scientific journal tran&MOTAUTO WORLD. 2021, (4), 116-119. ISSN 2367-8399.
HYNIOVÁ, K. A Design and Stand Tests of Real-timeVehicle Active Suspension. In: Proceedings of the VII International Scientific Congress "Innovations 21", Varna, 2021-06-21/2021-11-24. Sofia: Scientific-technical union of mechanical engineering, 2021. p. 32-36. vol. 1. ISSN 2603-3763.
KHUN, J. and J. SCHMIDT. Satisfiability Modulo Simulation: What Can It Do?. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03, 2021. p. 32-41. ISBN 978-80-01-06858-8.
LUXEMBURK, J., K. HYNEK, and T. ČEJKA. Detection of HTTPS Brute-Force Attacks with Packet-Level Feature Set. In: 11th Annual Computing and Communication Workshop and Conference (CCWC2021), Las Vegas, 2021-01-27/2021-01-30, 2021. p. 0115-0123. ISBN 978-0-7381-4394-1. DOI 10.1109/CCWC51732.2021.9375998. Available from: https://ieeexplore.ieee.org/document/9375998
MIŠKOVSKÝ, V., H. KUBÁTOVÁ, and M. NOVOTNÝ. Secure and dependable: Area-efficient masked and fault-tolerant architectures. In: Proceedings of the 2021 24th Euromicro Conference on Digital System Design, Palermo, 2021-09-01/2021-09-03, 2021. p. 333-338. ISBN 978-1-6654-2703-6. DOI 10.1109/DSD53832.2021.00057
ONDERKA, J. Fast fixed-point arithmetic in three-valued binary number abstraction. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03. 2021. p. 18. ISBN 978-80-01-06858-8. Available from: https://pesw.fit.cvut.cz/2021/PESW_2021.pdf
MICHAL ORSÁK, O. and T. BENEŠ. High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories. In: Proceedings of 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 2021-04-07/2021-04-09, 2021. p. 151-156. ISBN 978-1-6654-3595-6. DOI 10.1109/DDECS52668.2021.9417060
POKORNÝ, D., P. SOCHA, and M. NOVOTNÝ. Side-channel attack on Rainbow post-quantum signature. In: Proceedings of the 2021 Design, Automation & Test in Europe (DATE) 2021, Grenoble, 2021-02-01/2021-02-05. p. 565-568. ISSN 1558-1101. ISBN 978-3-9819263-5-4. DOI 10.23919/DATE51398.2021.9474157. Available from: https://ieeexplore.ieee.org/document/9474157
SCHMIDT, J. and P. FIŠER. Nonlinear codes for test patterns compression: the old school way. In: Recent Findings in Boolean Techniques. Cham: Springer International Publishing AG, 2021. p. 125-142. 1. ISBN 978-3-030-68070-1. DOI 10.1007/978-3-030-68071-8_6
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation. Microprocessors and Microsystems. 2021, 85 1-13. ISSN 0141-9331. DOI 10.1016/j.micpro.2021.104311
SOUKUP, D., et al. Towards Evaluating Quality of Datasets for Network Traffic Domain. In: Proceedings of the 2021 17th International Conference on Network and Service Management, Izmir, 2021-10-25/2021-12-29. 2021. p. 264-268. ISSN 2165-963X. ISBN 978-3-903176-36-2. DOI 10.23919/CNSM52442.2021.9615601
TROPKOVÁ, Z., K. HYNEK, and T. ČEJKA. Novel HTTPS classifier driven by packet bursts, flows, and machine learning. In: Proceedings of the 2021 17th International Conference on Network and Service Management, Izmir, 2021-10-25/2021-12-29, 2021. p. 345-349. ISSN 2165-963X. ISBN 978-3-903176-36-2. DOI 10.23919/CNSM52442.2021.9615561
VEKSHIN, D., K. HYNEK, and T. ČEJKA. Brief Summary of Observations and Research on Encrypted DNS. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03, 2021. ISBN 978-80-01-06858-8. Available from: https://pesw.fit.cvut.cz/2021/index.php?page=Proceedings

2020

BARTÍK, M., T. BENEŠ, and P. KUBALÍK. An In-sight into How Compression Dictionary Architecture can Affect the Overall Performance in FPGAs. IEEE Access. 2020, 2020(8), 183101-183116. ISSN 2169-3536. DOI 10.1109/ACCESS.2020.3029691. Available from: https://ieeexplore.ieee.org/document/9217430
BARTÍK, M. Reverse Engineering of Arrow USB Programmer2 JTAG Adapter for Intel/Altera FPGAs. In: 2020 9th Mediterranean Conference on Embedded Computing (MECO), Budva, 2020-06-08/2020-06-11. 2020. ISSN 2637-9511. ISBN 978-1-7281-6949-1. DOI 10.1109/MECO49872.2020.9134358. Available from: https://ieeexplore.ieee.org/document/9134358
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Standard Cell Tuning Enables Data-Independent Static Power Consumption. In: Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2020), Novi Sad, 2020-04-22/2020-04-24. 2020. ISSN 2334-3133. ISBN 978-1-7281-9938-2. DOI 10.1109/DDECS50862.2020.9095656.
BENEŠ, T., et al. Pipelined ALU for effective external memory access in FPGA. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design. Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 97-100. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00026.
BENEŠ, T., T. ČEJKA, and H. KUBÁTOVÁ. The next step of P4 FPGA architectures: External Memories. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. p. 5-7. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
BORECKÝ, J., R. HÜLLE, and P. FIŠER. Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28, 2020. p. 684-691. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00111.
HULÁK, M. and T. ČEJKA. Classification of Network Traffic using Traffic Features. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. p. 17-18. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
HYNEK, K. and T. ČEJKA. Privacy Illusion: Beware of Unpadded DoH. In: 2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), Vancouver, 2020-11-04/2020-11-07, Montreal, p. 621-628. ISSN 2644-3163. ISBN 978-1-7281-8416-6. DOI 10.1109/IEMCON51383.2020.9284864. Available from: https://ieeexplore.ieee.org/abstract/document/9284864
HYNEK, K., T. ČEJKA, and D. VEKSHIN. DoH detection: Discovering hidden DNS. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. p. 14-16. ISBN 978-80-01-06772-7. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
HYNEK, K., et al. Evaluating Bad Hosts Using Adaptive Blacklist Filter. In: Proceedings of the 9th Mediterranean Conference on Embedded Computing - MECO'2020, Budva, 2020-06-08/2020-06-11. 2020. ISSN 2637-9511. ISBN 978-1-7281-6949-1. DOI 10.1109/MECO49872.2020.9134244. Available from: https://ieeexplore.ieee.org/document/9134244
HYNEK, K., et al. Refined detection of SSH brute-force attackers using machine learning. In: 35th International Conference on ICT Systems Security and Privacy Protection, Maribor, 2020-09-21/2020-09-23. 2020. p. 49-63. IFIP Advances in Information and Communication Technology. vol. 580. ISSN 1868-4238. ISBN 978-3-030-58200-5. DOI 10.1007/978-3-030-58201-2_4.
HYNIOVÁ, K. On Electromagnetic Actuator Control in The Active Suspension Systems. International scientific journal tran&MOTAUTO WORLD. 2020, 2020(1), 6-9. ISSN 2367-8399.
HYNIOVÁ, K. On Electromagnetic Actuator Control in The Active Suspension Systems. In: Proceedings of the VI international Congress "INNOVATIONS 2020", Varna, 2020-06-22/2020-06-26. 2020. p. 98-100. vol. I. ISSN 2603-3763.
KLEMSA, J. and M. NOVOTNÝ. Exploiting Linearity in White-Box AES with Differential Computation Analysis. In: Proceedings of the 2020 Computing Conference, Volume 3. London, 2020-07-16/2020-07-17. p. 404-419. ISSN 2194-5365. ISBN 978-3-030-52243-8. DOI 10.1007/978-3-030-52243-8_29. Available from: https://link.springer.com/chapter/10.1007%2F978-3-030-52243-8_29
KLEMSA, J. and M. NOVOTNÝ. WTFHE: neural-netWork-ready Torus Fully Homomorphic Encryption. In: Proceedings of the 9th Mediterranean Conference on Embedded Computing - MECO'2020, Budva, 2020-06-08/2020-06-11. 2020. p. 1-5. ISSN 2637-9511. ISBN 978-1-7281-6949-1. DOI 10.1109/MECO49872.2020.9134331. Available from: https://ieeexplore.ieee.org/document/9134331
KOLÁRIK, T. and S. RATSCHAN. SAT Modulo Differential Equation Simulations. In: Tests and Proofs. 14th International Conference on Tests and Proofs, Bergen, 2020-06-23/2020-06-26, 2020. p. 80-99. ISSN 0302-9743. ISBN 978-3-030-50994-1. DOI 10.1007/978-3-030-50995-8_5.
LUXEMBURK, J. Detection of HTTPS brute-force attacks in high-speed computer networks. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
MOUCHA, P., S. JEŘÁBEK, and M. NOVOTNÝ. Novel Controller for Dummy Rounds Scheme DPA Countermeasure. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 281-284. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00053.
MOUCHA, P., S. JEŘÁBEK, and M. NOVOTNÝ. Novel Dummy Rounds Schemes as a DPA Countermeasure in PRESENT Cipher. In: Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2020), Novi Sad, 2020-04-22/2020-04-24. Piscataway, NJ: IEEE, 2020. p. 1-4. ISBN 978-1-7281-9938-2. DOI 10.1109/DDECS50862.2020.9095720.
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Non-Homogeneous Continuous Time Markov Chains Calculations. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 664-671. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00108.
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Non-homogeneous hierarchical Continuous Time Markov Chains. Microprocessors and Microsystems. 2020, 2020(78), ISSN 0141-9331. DOI 10.1016/j.micpro.2020.103206.
SCHMIDT, J. and P. FIŠER. Nonlinear codes for test patterns compression: the old school way. In: Proc. of 14th International Workshop on Boolean Problems, Bremen (virtual), 2020-09-24/2020-09-25. p. 1-16.
SOCHA, P. and M. NOVOTNÝ. Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 193-199. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00040.
SOCHA, P., et al. Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware. Microprocessors and Microsystems. 2020, 78 1-10. ISSN 0141-9331. DOI 10.1016/j.micpro.2020.103208.
SOUKUP, D., K. HYNEK, and T. ČEJKA. QoD: Ideas about Evaluating Quality of Datasets. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. p. 8-9. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
SVATOŇ, J., et al. Novel Partial Correlation Method Algorithm for Acquisition of GNSS Tiered Signals. Navigation. 2020, 2020(9), 1-18. ISSN 2161-4296. DOI 10.1002/navi.390. Available from: https://onlinelibrary.wiley.com/doi/full/10.1002/navi.390
VEKSHIN, D., K. HYNEK, and T. ČEJKA. DoH Insight: Detecting DNS over HTTPS by Machine Learning. In: ARES '20: Proceedings of the 15th International Conference on Availability, Reliability and Security, Dublin, 2020-08-25/2020-08-28. 2020. p. 1-8. ISBN 978-1-4503-8833-7. DOI 10.1145/3407023.3409192. Available from: https://dl.acm.org/doi/abs/10.1145/3407023.3409192
SOUKUP, D., T. ČEJKA, and K. HYNEK. Behavior Anomaly Detection in IoT Networks. In: Proceeding of the International Conference on Computer Networks, Big Data and IoT (ICCBI - 2019). 2020. p. 465-473. Lecture Notes on Data Engineering and Communications Technologies. vol. 49. ISSN 2367-4520. ISBN 978-3-030-43192-1. DOI 10.1007/978-3-030-43192-1_53. Available from: https://www.springer.com/gp/book/9783030431914

2019

BARTÍK, M., T. BENEŠ, and K. HYNEK. An Example of PCB Reverse Engineering - Reconstruction of Digilent JTAG SMT3 Schematic. In: The 7th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering. Liepaja, 2019-11-15/2019-11-16, IEEE, 2019. ISBN 978-1-7281-5709-2.
BARTÍK, M., T. BENEŠ, and P. KUBALÍK. Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms. In: The 9th IEEE Annual Computing and Communication Workshop and Conference (CCWC), Las Vegas, 2019-01-07/2019-01-09, IEEE, 2019. p. 732-738. ISBN 9781728105543. DOI 10.1109/CCWC.2019.8666521. Available from: https://ieeexplore.ieee.org/document/866652
M. BARTÍK and S. UBIK. System for Implementation of a Hash Table. United States. Patent US10262702. 2019-04-16. Available from: https://patents.google.com/patent/US10262702B2/en
BĚLOHOUBEK, J. Modulated CMOS Static Power is Data Dependendent and Observable. [Unpublished Lecture] Cryptarchi 2019. 2019-06-25.
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Using Voters May Lead to Secret Leakage. In: Proceedings of the 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cluj-Napoca, 2019-04-24/2019-04-26, IEEE, 2019. p. 1-4. ISBN 978-1-7281-0073-9. DOI: 10.1109/DDECS.2019.8724663.
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. CMOS Illumination Discloses Processed Data. In: Proceedings of the 22nd Euromicro Conference on Digital Systems Design, Kallithea, Chalkidiki, 2019-08-28/2019-08-30, IEEE Computer Soc., 2019. p. 381-388. ISBN 978-1-7281-2861-0. DOI: 10.1109/DSD.2019.00062.
BĚLOHOUBEK, J. and R. VIK. Low-Cost CMOS Power Consumption Data Dependence Demonstrator Concept. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/index.php?page=Proceedings
BENEŠ, T., M. BARTÍK, and P. KUBALÍK. High Throughput and Low Latency LZ4 Compressor on FPGA. In: 2019 International Conference on ReConFigurable Computing and FPGAs. Cancún, 2019-12-09/2019-12-11. Piscataway, NJ: IEEE, 2019. ISBN 978-1-7281-1957-1.
HAVRÁNEK, J., T. ČEJKA, and P. BENÁČEK. L7 capable flow exporter described in P4. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. p. 29-32. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf
HÜLLE, R., P. FIŠER, and J. SCHMIDT. PBO-Based Fault Selection for Compact Test Generation. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf
HYNEK, K., et al. Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks. In: The 9th IEEE Annual Computing and Communication Workshop and Conference (CCWC). Las Vegas, 2019-01-07/2019-01-09, 2019. p. 847-851. ISBN 9781728105543. DOI 10.1109/CCWC.2019.8666446. Available from: https://ieeexplore.ieee.org/document/8666446
HYNEK, K., et al. Future approaches to monitoring in high-speed backbone networks. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. p. 27-28. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf
HYNIOVÁ, K. Energy Control Principles in An Automotive Active Suspension System. In: Proceedings of the V. International Scientific Congress Innovations 2019, Varna, 2019-06-19/2019-06-22, 2019. p. 88-92. III. vol. 3. ISSN 2603-3763.
HYNIOVÁ, K. LIMITATIONS TO SUSPENSION PERFORMANCE IN A TWO-DEGREE-OF-FREEDOM CAR ACTIVE SUSPENSION. In: Proceedings of the V. International Scientific Congress Innovations 2019, Varna, 2019-06-19/2019-06-22, 2019. p. 28-32. III. vol. 3. ISSN 2603-3763.
HYNIOVÁ, K. LIMITATIONS TO SUSPENSION PERFORMANCE IN A TWO-DEGREE-OF-FREEDOM CAR ACTIVE SUSPENSION. INNOVATIONS. 2019, VII(7), 111-115. ISSN 2603-3763.
HYNIOVÁ, K. ENERGY CONTROL PRINCIPLES IN AN AUTOMOTIVE ACTIVE SUSPENSION SYSTEM. international scientific journal tran&MOTAUTO WORLD. 2019, 3/2019(3), 107-111. ISSN 2367-8399.
HYNIOVÁ, K. On Control of Energy Flow in The Automotive Active Suspension System. In: Proceedings of Researchfora- International Conference on Research, Engineering and Technology. IRAJ, 2019. p. 19-23. III. vol. 1.
JEŘÁBEK, S. Analýza Dummy Rounds jako opatření proti DPA v hardwaru. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. ISBN 978-80-88214-20-5.
JEŘÁBEK, S. and J. SCHMIDT. Analyzing and Optimizing the Dummy Rounds Scheme. In: Proceedings of the 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cluj-Napoca, 2019-04-24/2019-04-26, 2019. DOI: 10.1109/DDECS.2019.8724632.
KHUN, J. Akcelerace imunitních algoritmů pomocí FPGA. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. p. 11-14. ISBN 978-80-88214-20-5.
KHUN, J., M. NOVOTNÝ, and M. SKRBEK. High-Performance Spiking Neural Network Simulator. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 88-91. ISSN 2377-5475. DOI: 10.1109/MECO.2019.8760291.
KOLÁRIK, T. SAT modulo differential equations. In: Informal Proceedings of European Test Symposium 2019, Baden Baden, 2019-05-27/2019-05-30, 2019.
KUBÁTOVÁ, H. Dependability Problems in Interconnected World. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 9.
MIŠKOVSKÝ, V. Area-efficient fault-tolerant architectures exploiting masking scheme randomness. [Unpublished Lecture] CryptArchi 2019, Průhonice, Czech Republic. 2019-06-24.
MIŠKOVSKÝ, V. Útoky postranními kanály: efektivní implementace a ochrany odolné proti poruchám. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. p. 68-72. ISBN 978-80-88214-20-5.
PŘEUČIL, T. and M. NOVOTNÝ. Low-Cost Portable ECG. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 660-663. ISSN 2377-5475. ISBN 978-1-7281-1739-3. DOI: 10.1109/MECO.2019.8760086.
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Hierarchical Dependability Models based on Non-Homogeneous Continuous Time Markov Chains. In: 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Mykonos, 2019-04-16/2019-04-18, 2019. ISBN 978-1-7281-3424-6. DOI: 10.1109/DTIS.2019.8735006, [pdf].
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Accurate Inexact Calculations of Non-Homogeneous Markov Chains. In: Proceedings of the 22nd Euromicro Conference on Digital Systems Design, Kallithea, Chalkidiki, 2019-08-28/2019-08-30, 2019. p. 470-477. ISBN 978-1-7281-2861-0. DOI: 10.1109/DSD.2019.00074, [pdf].
ŘÍHA, J. Efektivnía bezpečné homomorfní šifrování v FPGA. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. ISBN 978-80-88214-20-5.
ŘÍHA, J., J. KLEMSA, and M. NOVOTNÝ. Multiprecision ANSI C Library for Implementation of Cryptographic Algorithms on Microcontrollers. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 275-278. ISSN 2377-5475. ISBN 978-1-7281-1739-3. DOI: 10.1109/MECO.2019.8760285.
SOCHA, P., et al. Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent. In: Proceedings of the 22nd Euromicro Conference on Digital Systems Design, Kallithea, Chalkidiki, 2019-08-28/2019-08-30, 2019. p. 277-282. ISBN 978-1-7281-2861-0. DOI: 10.1109/DSD.2019.00048.
SOCHA, P., et al. Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. Microprocessors and Microsystems. 2019, 2019(71), 1-8. ISSN 0141-9331. DOI: 10.1016/j.micpro.2019.102858.
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. First-Order and Higher-Order Power Analysis: Computational Approaches and Aspects. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 83-87. ISSN 2377-5475. ISBN 978-1-7281-1739-3. DOI: 10.1109/MECO.2019.8760033.
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. SICAK: An open-source SIde-Channel Analysis toolKit. In: 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2019). Baden-Baden, 2019-05-30/2019-05-31, 2019.
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. Toolkit for side-channel analysis: SICAK. [Unpublished Lecture] CryptArchi 2019, Průhonice, Czech Republic. 2019-06-24.
SOUKUP, D., T. ČEJKA, and S. ŠTEFUNKO. Multi-level Anomaly Detection in IoT Networks. In: Proceedings of the 7th Prague Embedded Systems Workshop, 2019-06-27/2019-06-29, 2019. p. 37-38. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf

2018

APELTAUER, T. Automated Testing of Models of Cyber-Physical Systems. [Technical Report] 2018. Report no. TR-FIT-18-02.
BARTÍK, M. Clock Domain Crossing – An Advanced Course for Future Digital Design Engineers. In: 7th Mediterranean Conference on Embedded Computing MECO 2018, Budva, Montenegro, 2018-06-10/2018-06-14, pp. 76-80. Available from: https://ieeexplore.ieee.org/document/8406004/
BARTÍK, M. Xilinx 7-Series FPGA Based Evaluation Platform for Physically Unclonable Function. In: TRUDEVICE 2018, Dresden, Germany, 2018-03-23.
BARTÍK, M., UBIK, S., KUBALÍK, P. and T. BENEŠ. Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary. In: Proceedings of the 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, USA, 2018-02-25/2018-02-27, p. 290. Available from: https://dl.acm.org/citation.cfm?id=3174976
BĚLOHOUBEK, J. Zvyšování spolehlivosti a bezpečnosti číslicových obvodů na úrovni mikroarchitektury. In: Počítačové architektury a diagnostika 2018, Stachy, Zadov, Czech Rep., 2018-09-05/2018-09-07.
BĚLOHOUBEK, J., J. SCHMIDT, and P. FIŠER. Effect of Power Trace Set Properties to Differential Power Analysis. [Unpublished Lecture] TRUDEVICE 2018, 2018-03-23.
BENÁČEK, P., PUŠ, V.P., KUBÁTOVÁ, H., and T. ČEJKA. P4-To-VHDL: Automatic generation of high-speed input and output network blocks. Microprocessors and Microsystems, 2018, vol. 56 pp. 22-33. ISSN 0141-9331. DOI: 10.1016/j.micpro.2017.10.012.
ČEJKA, T., VELAN, P., HAVRÁNEK, J., and P. BENÁČEK. Enhanced Flow Monitoring with P4 Generated Flexible Packet Parser. In: Proceedings of the 12th International Conference on Autonomous Infrastructure, Management and Security, Mnichov, Germany, 2018-06-04/2018-06-05, pp. 21-32. Available from: http://www.aims-conference.org/2018/AIMS-2018-Proceedings.pdf
DANEL, M. and M. SKRBEK. Review of Reinforcement Learning Methods for Humanoid Robot Control. [Technical Report] 2018. Report no. TR-FIT-18-06.
DAŇHEL, M. Prediction and Analysis of Mission Critical Systems Dependability. PhD Thesis. CTU FIT. Department of Digital Design.
FERRANDINO, U., TRAIOLA, M., BARBARESCHI, M., MAZZEO, A., FIŠER, P., and A. BOSIO. Synthesis of Finite State Machines on Memristor Crossbars. In: Proc. of 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Budapest, Hungary, 2018-04-25/2018-04-27, pp. 107-112. DOI: 10.1109/DDECS.2018.000-3
FIŠER, P. and V. ŠIMEK. Optimum Polymorphic Circuits Synthesis Method. In: Proc. of 13th IEEE International Conference on Design and Technology of Integrated Systems in nanoscale era, Taormina, Italy, 2018-04-10/2018-04-12. DOI: 10.1109/DTIS.2018.8368585
HÁLEČEK, I., P. FIŠER, and J. SCHMIDT. XOR-Based Synthesis: Does it Pay off? In: Proc. of 13th International Workshop on Boolean Problems, Bremen, Germany, 2018-09-19/2018-09-21, pp. 167-176. [pdf]
HÁLEČEK, I., P. FIŠER, and J. SCHMIDT. Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR. Microelectronics Reliability, 2018, vol. 81, pp. 274-286. ISSN 0026-2714. DOI: 10.1016/j.microrel.2017.12.031.
HÜLLE, R., P. FIŠER, and J. SCHMIDT. ZATPG: SAT-based ATPG for Zero-Aliasing Compaction. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 8-11.
HÜLLE, R., P. FIŠER, and SCHMIDT, J. ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction. Microprocessors and Microsystems, 2018(61), 43-57. ISSN 0141-9331. DOI: 10.1016/j.micpro.2018.05.001.
HYNIOVÁ, K. A Sky-Hook Control Concept of Vehicle Active Suspensions. In: International scientific journal tran. 2018, 3(3), 106-109. ISSN 2367-8399.
HYNIOVÁ, K. A Processes Control Simulation Tool. In: International journal for science, technics and innovations for the industry MACHINES TECHNOLOGIES MATERIALS. 2018, 12(4), 182-184. ISSN 1313-0226.
HYNIOVÁ, K. A Simulation Tool of Technological Process Control. In: Proceedings of the IVth International Scientific Congress Innovations, Varna, 2018-06-20/2018-06-23, pp. 92-95. vol. 1.
HYNIOVÁ, K. Fuzzy Skyhook Control for Active One-Half-Car Suspension Model. In: WSEAS Transactions on Information Science and Applications. 2018, 15(15), 133-139.
HYNIOVÁ, K. A Sky-Hook Control Concept of Vehicle Active Suspensions. In: Proceedings of the IVth International Scientific Congress Innovations 2018, Varna, 2018-06-20/2018-06-23, pp. 92-95. vol. 1.
JÁNSKÝ, T., ČEJKA, T., ŽÁDNÍK, M., and V. BARTOŠ. Augmented DDoS Mitigation with Reputation Scores. In: Proceedings of the 13th International Conference on Availability, Reliability and Security, Hamburg, Germany, 2018-08-27/2018-09-30. Available from: https://dl.acm.org/citation.cfm?id=3233279.
JÁNSKÝ, T., ČEJKA, T., ŽÁDNÍK, M., and V. BARTOŠ. Informed DDoS Mitigation at 100 Gb/s. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 41-42.
JEŘÁBEK, S., J. SCHMIDT, and M. NOVOTNÝ. Dummy Rounds jako opatření proti DPA v hardwaru. In: Počítačové architektury a diagnostika 2018. Stachy, Zadov, Czech Rep., 2018-09-05/2018-09-07, pp. 33-36.
JEŘÁBEK, S., SCHMIDT, J., NOVOTNÝ, M., and V. MIŠKOVSKÝ. Dummy Rounds as a DPA countermeasure in hardware. In: Proceedings of the 21st Euromicro Conference on Digital System Design, Prague, Czech Rep., 2018-08-29/2018-08-31, pp. 523-528. Available from: https://ieeexplore.ieee.org/document/8491863
JEŘÁBEK, S. Differential power analysis countermeasures in programmable hardware technical research report. [Technical Report] 2018. Report no. TR-FIT-18-07.
KŘÍŽEK, F., FERENCEI, J., MATLOCHA, T., POSPÍŠIL, J., PRÍBELI, P., RASKINA, V., ISAKOV, A., ŠTURSA, J. et al. Irradiation setup at the U-120M cyclotron facility. Nuclear Instruments and Methods in Physics Research, Section A, Accelerators, Spectrometers, Detectors and Associated Equipment. 2018, vol. 894, pp. 87-95. ISSN 0168-9002. DOI 10.1016/j.nima.2018.03.066.
MIŠKOVSKÝ, V., H. KUBÁTOVÁ, and M. NOVOTNÝ. Speeding up differential power analysis using integrated power traces. In: 7th Mediterranean Conference on Embedded Computing MECO 2018, Budva, Montenegro, 2018-06-10/2018-06-14, pp. 19-23.
MIŠKOVSKÝ, V., H. KUBÁTOVÁ, and M. NOVOTNÝ. Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of AES implemented in FPGA. In: TRUDEVICE 2018. Dresden, Gremany, 2018-03-23.
SCHMIDT, J. and P. FIŠER. A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization. In: Further Improvements in the Boolean Domain. Newcastle upon Tyne: Cambridge Scholars Publishing, 2018. p. 280-301. ISBN 978-1-5275-0371-7.
SOCHA, P., MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and M. NOVOTNÝ. Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative. In: Proceedings of the 21st Euromicro Conference on Digital System Design, Prague, Czech Rep., 2018-08-29/2018-08-31, pp. 565-568. Available from: https://ieeexplore.ieee.org/document/8491869
SOCHA, P., J. BREJNÍK, and M. BARTÍK. Attacking AES Implementations Using Correlation Power Analysis on ZYBO Zynq-7000 SoC Board. In: 7th Mediterranean Conference on Embedded Computing MECO 2018, Budva, Montenegro, 2018-06-10/2018-06-14, pp. 29-32. Available from: https://ieeexplore.ieee.org/document/8406034/
SLABIHOUDEK, M. and T. ČEJKA. Stream-wise Aggregation of Flow Data. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, p. 37.
STEJSKALOVÁ, L. and T. ČEJKA. Grouping evil IP addresses. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, p. 30.
ŠUSTER, F. and T. ČEJKA. Stream-wise adaptive blacklist filter based on flow data. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 38-39.
SVATOŇ, J., VEJRAŽKA, F., KUBALÍK, P., and J. SCHMIDT. Proposal of a Memory Architecture for Pre and Post-Correlation coherent Processing of GNSS Signal with SoC based Acquisition Uni. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 21-25. Available from: http://pesw.fit.cvut.cz/2018/PESW_2018.pdf

2017

APELTAUER, T. Automatické testování modelů kyber-fyzikálních systémů. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. pp. 5-8.
BARTÍK, M. and UBIK, S. Systém pro realizaci rozptylovací tabulky. CESNET z.s.p.o;ČVUT FIT. 24.05.2017.
BĚLOHOUBEK, J. The Design-Time Side-Channel Information Leakage Estimation. 19.06.2017.
BĚLOHOUBEK, J., FIŠER, P., and SCHMIDT, J. Error Masking Method Based On The Short-Duration Offline Test. Microprocessors and Microsystems. 2017, vol. 52, pp. 236-250. ISSN 0141-9331. [pdf], doi
BORECKÝ, J., KOHLÍK, M., and KUBÁTOVÁ, H. Parity driven reconfigurable duplex system. Microprocessors and Microsystems, 2017, vol. 52, pp. 251-260. ISSN 0141-9331. [pdf], doi
BUČEK, J., NOVOTNÝ, M., and ŠTĚPÁNEK, F. Practical Session: Differential Power Analysis for Beginners. In: Hardware Security and Trust. Springer International Publishing. 2017, pp. 77-91.
BUČEK, J., et al. Design of a Residue Number System Based Linear System Solver in Hardware. Journal of Signal Processing Systems. 2017, 87(3), pp. 343-356. ISSN 1939-8018.
ČEJKA, T. and ŽÁDNÍK, M. Preserving Relations in Parallel Flow Data Processing. In: Proc. of Security of Networks and Services in an All-Connected World. Autonomous Infrastructure, Management, and Security. Zurich, 10.07.2017 - 13.07.2017. pp. 153-156. Available from: https://link.springer.com/chapter/10.1007/978-3-319-60774-0_14
ČEJKA, T., ŠVEPEŠ, M., and VIKTORIN, J. Gateway for IoT Security. In: Proc. of The 5th Prague Embedded Systems Workshop. Roztoky u Prahy, 29.06.2017 - 30.06.2017.
ČEJKA, T., et al. NEMEA: A Framework for Network Traffic Analysis. In: 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016. pp. 195-201. Available from: https://edas.info/showManuscript.php?m=1570291169&ext=pdf&random=1622993478&type=stamped
DANEL, M. Reinforcement Learning for Humanoid Robot Control. In: Proceedings of the International Student Scientific Conference Poster – 21/2017. Praha, 23.05.2017. [pdf]
DANEL, M. and SKRBEK, M. Humanoid Robot Control by Offline Actor-Critic Learning. In: ITAT 2017: Information Technologies – Applications and Theory. Martinské hole, Malá Fatra, 22.09.2017 - 26.09.2017, pp. 71-77. [pdf]
DANEL, M. and SKRBEK, M. Towards Learning Humanoid Robot Control. In: Proceedings of the Work in Progress Session SEAA/DSD 2017. 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017.
DAŇHEL, M., ŠTĚPÁNEK, F., and KUBÁTOVÁ, H. Dependability Prediction Involving Temporal Redundancy and the Effect of Transient Faults. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017, pp. 360-363.
DAŇHEL, M. and KUBÁTOVÁ, H. Dependability or Reliability in the Real World. In: Proc. of 6th Mediterranean Conference on Embedded Computing (MECO 2017). Bar, 11.06.2017 - 15.06.2017. pp. 17-20.
DAŇHEL, M., ŠTĚPÁNEK, F., and KUBÁTOVÁ, H. The effect of the transient faults in dependability prediction. Microprocessors and Microsystems. 2017, 52(C), pp. 498-504. ISSN 0141-9331.
FIŠER, P., HÁLEČEK, I., and SCHMIDT, J. SAT-Based Generation of Optimum Function Implementations with XOR Gates. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017. pp. 163-170. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Logická syntéza založená na obecných operátorech. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. On XAIG Rewriting. In: Proc. of 26th International Workshop on Logic & Synthesis. Austin, TX, USA, 17.06.2017 - 18.06.2017. pp. 89-96. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Are XORs in logic synthesis really necessary?. In: Proceedings of the 20th IEEE International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden, 19.04.2017 - 21.04.2017. pp. 134-139. [pdf]
HÁLEČEK, I. The State-of-the-Art of the Logic representations for the synthesis. 2017, TR-FIT-17-06.
HÜLLE, R., FIŠER, P., and SCHMIDT, J. Generování testu s nulovým maskováním poruch. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. pp. 35-38. [pdf]
HÜLLE, R., FIŠER, P., and SCHMIDT, J. SAT-based ATPG for Zero-Aliasing Compaction. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017. pp. 307-314. [pdf]
HÜLLE, R. The State-of-the-Art of Logical Circuits Automated Test Pattern Generation and Output Response Compaction. 2017, TR-FIT-17-04.
HYNIOVÁ, K. A Simulation Tool of Technological Process Control. In: Proceedings Book Of Second International Conference on Advances in Science, ICAS 2017, Istanbul, 13.09.2017 - 16.09.2017, pp. 26-30. vol. 1.
HYNIOVÁ, K. Robust Control of Vehicle Active Suspension and Its Verification. In: Proceedings Book Of Second International Conference on Advances in Science, ICAS 2017, Istanbul, 13.09.2017 - 16.09.2017, pp. 4-9. vol. 1.
HYNIOVÁ, K. Usage of One-Quarter-Car Active Suspension Test Stand for Experimental Verification. WSEAS Transactions on Applied and Theoretical Mechanics. 2017, pp. 17-24.
HYNIOVÁ, K. One-Quarter-Car Active Suspension Model Verification. In: Open Access proceedings in Information technology, Computer Science and Mathematics. Rome, Italy, 05.11.2016 - 07.11.2016. pp. 121-125. vol. 9. Available from: http://www.itm-conferences.org/articles/itmconf/abs/2017/01/itmconf_amcse2017_03003/itmconf_amcse2017_03003.html
JÁNSKÝ, T., ČEJKA, T., and BARTOŠ, V. Hunting SIP Authentication Attacks Efficiently. In: Proc. of Security of Networks and Services in an All-Connected World. Autonomous Infrastructure, Management, and Security. Zurich, 10.07.2017 - 13.07.2017. pp. 125-130. ISBN 978-3-319-60773-3. Available from: https://link.springer.com/chapter/10.1007/978-3-319-60774-0_9
JÁNSKÝ, T., ČEJKA, T., and BARTOŠ, V. Detection of SIP Scans and Bruteforce Attacks. In: Proc. of The 5th Prague Embedded Systems Workshop. Roztoky u Prahy, 29.06.2017 - 30.06.2017.
JEŘÁBEK, S., SCHMIDT, J., and NOVOTNÝ, M. Dynamic Reconfiguration as Countermeasure against DPA. In: Proceedings of the Work in Progress Session SEAA/DSD 2017. 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017.
JEŘÁBEK, S., SCHMIDT, J., and NOVOTNÝ, M. Dynamická rekonfigurace jako opatření proti DPA. In: Proc. of Počítačové architektury a diagnostika, Smolenice, 06.09.2017 - 08.09.2017.
JEŘÁBEK, S., et al. Emulator of Contactless Smart Cards in FPGA. In: Proc. of 6th Mediterranean Conference on Embedded Computing (MECO 2017). Bar, 11.06.2017 - 15.06.2017. pp. 96-99.
MAZUR, L. and NOVOTNÝ, M. Differential Power Analysis on FPGA board: Boundaries of Success. In: Proc. of 6th Mediterranean Conference on Embedded Computing (MECO 2017). Bar, 11.06.2017 - 15.06.2017. pp. 92-95.
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA. Microprocessors and Microsystems, 2017, vol. 51, pp. 220-226. ISSN 0141-9331. Available from: http://www.sciencedirect.com/science/article/pii/S0141933116304677
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Číslicový návrh spojující odolnost proti poruchám a odolnost proti útokům. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. pp. 43-46.
MIŠKOVSKÝ, V. Fault tolerance and resistance against side channel attacks in FPGA. 2017, TR-FIT-17-03.
NOVÁK, P., et al. Predicting the Life Expectancy of Railway Fail-safe Signaling Systems Using Dynamic Models with Censoring. In: Proc. of 2017 IEEE International Conference on Software Quality, Reliability and Security (QRS), Prague, 25.07.2017 - 29.07.2017, pp. 329-339. Available from: http://ieeexplore.ieee.org/document/8009937/
NOVOTNÝ, M. Cryptanalytic attacks on cyber-physical systems. Microprocessors and Microsystems. 2017, vol. 52, pp. 534-539. ISSN 0141-9331. Available from: http://www.sciencedirect.com/science/article/pii/S0141933117300674
ROSA, Z., et al. Building a Feedback Loop to Capture Evidence of Network Incidents. In: 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016. pp. 292-296. Available from: https://edas.info/showManuscript.php?m=1570287530&ext=pdf&random=551856465&type=stamped
ŘÍHA, J., et al. Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017. pp. 260-267.
SCHMIDT, J. On Quality in Experimental Evaluation. In: Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED 2017). Santa Clara, 14.03.2017 - 15.03.2017.
SIELEWICZ, K.M., et al. Prototype readout electronics for the upgraded ALICE Inner Tracking System. Journal of Instrumentation. 2017, 12(01), ISSN 1748-0221. Available from: http://stacks.iop.org/1748-0221/12/i=01/a=C01008
SOCHA, P., et al. Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. In: Proceedings of the 20th IEEE International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden, 19.04.2017 - 21.04.2017. pp. 188-193.
SVATOŇ, J., et al. Acquisition of Modern GNSS Signals in SoC ZYNQ with its Limited Computational Resources in Frequency Domain. In: Proc. of The 5th Prague Embedded Systems Workshop. Roztoky u Prahy, 29.06.2017 - 30.06.2017. pp. 64-66.
SVATOŇ, J., et al. Methods and Hardware achitecture for Multi-constellation GNSS signal acqusition unit in frequency domain. In: Proc. of The European Navigation Conference 2017. Lausanne, 09.05.2017 - 12.05.2017. pp. 252-261. Available from: http://enc2017.eu/site/downloads/
ŠVEPEŠ, M. and ČEJKA, T. Making Flow-Based Security Detection Parallel. In: Proc. of Security of Networks and Services in an All-Connected World. Autonomous Infrastructure, Management, and Security. Zurich, 10.07.2017 - 13.07.2017. pp. 3-15.Available from: https://link.springer.com/chapter/10.1007/978-3-319-60774-0_1

2016

ALEXA, D. Future plans for bulk configuration and visualization of NETCONF devices. In Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016.
BARTÍK, M. and BUČEK, J. A Low-Cost Unified Experimental FPGA Board for Cryptography Applications. In TRUDEVICE 2016 Final Conference. Conference on Trustworthy Manufacturing and Utilization of Secure Devices. Barcelona, 14.11.2016 - 16.11.2016., pp. 75-80. Available from: http://hdl.handle.net/2117/99297
BARTÍK, M. and BUČEK, J. A Low-Cost Multi-Purpose Experimental FPGA Board for Cryptography Applications . In 2016 IEEE 4th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE). Vilnius, 10.11.2016 - 12.11.2016, ISBN 978-1-5090-4473-3. Available from: http://ieeexplore.ieee.org/document/7821811/
BARTÍK, M., PICHLOVÁ, D., and KUBÁTOVÁ, H. Hardware-software co-design: A practical course for future embedded engineers. In Proceedings of the 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 347-350. ISBN 978-1-5090-2220-5. Available from: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7525779
BARTÍK, M., UBIK, S., and KUBALÍK, P. Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase. Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016. Available from: http://www.fit.vutbr.cz/events/pad2016/download/sbornik/14-Bartik.pdf
BARTÍK, M., UBIK, S., and KUBALÍK, P. A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time. In Proc. of ReConFig’16. 2016 International Conference on Reconfigurable Computing and FPGAs. Cancún, 30.11.2016 - 02.12.2016, ISBN 978-1-5090-3706-3.
BĚLOHOUBEK, J. Využití rychlého offline testu v systému se schopností maskování jedné chyby. Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016. ISBN 978-80-214-5376-0.
BĚLOHOUBEK, J., FIŠER, P., and SCHMIDT, J. Error Correction Method Based on the Short-Duration Offline Test. In Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016. Limassol, Cyprus, 31.08.2016 - 02.09.2016, pp. 495-502. ISBN 978-1-5090-2816-0. [pdf]
BENÁČEK, P. and KUBÁTOVÁ, H. P4-to-FPGA: Translating P4 to VHDL. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016.
BENÁČEK, P., KUBÁTOVÁ, H., and PUŠ, VP. P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. In Proc. of 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016), 01.05.2016 - 03.05.2016, pp. 148-155. ISBN 978-1-5090-2356-1.
BORECKÝ, J., KOHLÍK, M., and KUBÁTOVÁ, H. Parity Waterfall Method. In Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice, 20.04.2016 - 22.04.2016, pp. 21-26. ISBN 978-1-5090-2467-4. [pdf]
BORECKÝ, J., et al. Enhanced duplication method with TMR-like masking abilities. In Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016. Limassol, Cyprus, 31.08.2016 - 02.09.2016, pp. 690-693. ISBN 978-1-5090-2816-0.
BUČEK, J., KUBALÍK, P., LÓRENCZ, R., and Zahradnický, T. Design of a Residue Number System Based Linear System Solver in Hardware. Journal of Signal Processing Systems. 2016, pp. 1-14. ISSN 1939-8018.
ČEJKA, T., et al. NEMEA: A Framework for Network Traffic Analysis [online]. In 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016. ISBN 978-3-901882-85-2. Available from: https://edas.info/showManuscript.php?m=1570291169&ext=pdf&random=1622993478&type=stamped
ČEJKA, T. and ROBLEDO, A. Detecting Spoofed Time in NTP Traffic. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, pp. 49-52. ISBN 978-80-01-05984-5.
ČEJKA, T. and ŠVEPEŠ, M. Analysis of Vertical Scans Discovered by Naive Detection [online]. In Proc. of 10th International Conference on Autonomous Infrastructure, Management and Security (AIMS 2016). Mnichov, 20.06.2016 - 23.06.2016, pp. 165-169. ISBN 978-3-319-39814-3. Available from: http://link.springer.com/chapter/10.1007/978-3-319-39814-3_19
DAŇHEL, M. and ŠTĚPÁNEK, F. Reliability prediction in dependability models considering transient faults. In Proceedings of the 20th International Scientific Student Conferenece POSTER 2016. Praha, 24.05.2016, ISBN 978-80-01-05950-0.
DAŇHEL, M., ŠTĚPÁNEK, F., and KUBÁTOVÁ, H. The Effect of the Transient Faults in Dependability Prediction. In Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016, Limassol, Cyprus, 31.08.2016 - 02.09.2016, pp. 9-13. ISBN 978-1-5090-2816-0.
DAS, S., DASGUPTA, P., FIŠER, P, et al. A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits. In Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice, 20.04.2016 - 22.04.2016, pp. 237-242. ISBN 978-1-5090-2467-4. [pdf]
FIŠER, P. and SCHMIDT, J. A Comprehensive Set of Logic Synthesis and Optimization Examples. In Proceedings of the 12th International Workshop on Boolean Problems. Freiberg, 22.09.2016 - 23.09.2016, pp. 151-158. ISBN 978-3-86012-540-3. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Logická syntéza s nativní podporou XOR hradel. In Proc. of Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016, ISBN 978-80-214-5376-0.
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Utilization of XOR gates in logic synthesis. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, ISBN 978-80-01-05984-5.
HÜLLE, R., FIŠER, P., and SCHMIDT, J. Generování testu pro prostředky vestavěné diagnostiky. In Proc. of Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016, ISBN 978-80-214-5376-0.
HÜLLE, R., et al. SAT-ATPG for Application-Oriented FPGA Testing. In Proceedings of the 15th Biennial Baltic Electronics Conference. Tallinn, 03.10.2016 - 05.10.2016, pp. 83-86. ISBN 978-1-5090-1393-7. Available from: http://ieeexplore.ieee.org/document/7743734/ [pdf]
HYNIOVÁ, K. A Tool for Modelling of Technological Processes Control. In: Automatizace a řízení v teorii a praxi. Automatizace a řízení v teorii a praxi. Stará Lesná, 10.02.2016 - 12.02.2016., ISBN 978-80-553-2474-6.
HYNIOVÁ, K. On Testing of Vehicle Active Suspension Robust Control on An One-Quarter-Car Test Stand [online]. In Proc. of International Journal of Mechanical Engineering. 2016, 2016 (1)(1), pp. 1-7. ISSN 2367-8968. Available from: http://www.iaras.org/iaras/filedownloads/ijme/2016/012-0001.pdf
HYNIOVÁ, K. A Tool for Modelling of Technological Processes Control [online]. Strojírenství. 2016, XX(6/2016), pp. 94-95. ISSN 1335-2938.
HYNIOVÁ, K. Laboratorní model technologického procesu a jeho řízení [online]. In Proc. of ARTEP 2016. Automatizace a řízení v teorii a praxi. Stará Lesná, 10.02.2016 - 12.02.2016. ISBN 978-80-553-2474-6.
HYNIOVÁ, K. Vibrational Analysis of Suspension System for One- Half- Car Model with Fuzzy Logic Controller [online]. In International Scientific Congress Innovations in Engineering , Varna, 20.06.2016 - 22.06.2016., pp. 82-85. ISSN 1310-3946. Available from: http://www.innova-eng.eu/proceedings/2016.pdf
HYNIOVÁ, K. Nástroj pro modelování řízení technologických procesů. AT&P Journal. 2016, 2016(10/2016), pp. 58-61. ISSN 1335-2237. Available from: http://www.atpjournal.sk/buxus/docs/casopisy_cele/ATP%20Journal%2010%202016.pdf
JEŘÁBEK, S. Emulator of Contactless Smart Cards in FPGA. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, ISBN 978-80-01-05984-5.
KUBÁTOVÁ, H. and NOVOTNÝ, M. Education of Computer Engineering at CTU in Prague. In Proc. of 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 22-25. ISBN 978-1-5090-2220-5.
LIPOVSKÝ, M., ŠVARC, J. GRAMATOVÁ, E. and FIŠER, P. A New User-Friendly ATPG Platform for Digital Circuits. In Proceedings of the 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Košice, 20.04.2016 - 22.04.2016., pp. 210-213. ISBN 978-1-5090-2467-4. [pdf]
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of fault-tolerant design methods on differential power analysis resistance of AES cipher: Methodics and challenges. In Proc. of 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 14-17. ISBN 978-1-5090-2220-5. Available from: http://ieeexplore.ieee.org/document/7525685/
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, pp. 38-39. ISBN 978-80-01-05984-5.
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Číslicový návrh spojující odolnost proti útokům a odolnost proti poruchám. In Proc. of Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016. ISBN 978-80-214-5376-0. Available from: http://www.fit.vutbr.cz/events/pad2016/download/sbornik/26-Miskovsky.pdf
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis in FPGA. In: TRUDEVICE 2016 Final Conference. Conference on Trustworthy Manufacturing and Utilization of Secure Devices. Barcelona, 14.11.2016 - 16.11.2016.
NOVOTNÝ, M. Cryptanalytical Attacks on Cyber-Physical Systems. 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 10. ISBN 978-1-5090-2221-2.
PICHLOVÁ, D. and BARTÍK, M. Development of a sound recording system for audio cassette duplication on an industrial scale. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, pp. 2-3. ISBN 978-80-01-05984-5.
ROSA, Z., et al. Building a Feedback Loop to Capture Evidence of Network Incidents [online]. In Proc. of 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016, pp. 248-252. ISBN 978-1-5090-3236-5. Available from: https://edas.info/showManuscript.php?m=1570287530&ext=pdf&random=551856465&type=stamped
SCHAMBACH, J., ROSSEWIJ, M.J., SIELEWICZ, K.M., AGLIERI RINELLA, G., BORONA, M., FERENCEI, J., GIUBILATO, P., VAŇÁT, T. ALICE inner tracking system readout electronics prototype testing with the CERN "Giga Bit Transceiver" [online]. Journal of Instrumentation. 2016, 11(12), ISSN 1748-0221. Available from: http://stacks.iop.org/1748-0221/11/i=12/a=C12074
SCHMIDT, J., BLAŽEK, R., and FIŠER, P. Towards Understanding the Performance of Randomized Algorithms. In: Problems and New Solutions in the Boolean Domain. Cambridge Scholars Publishing. 2016, pp. 167-186. ISBN 978-1-4438-8947-6.
SCHMIDT, J. and FIŠER, P. A Prudent Approach to Benchmark Collection. In Proc. of the 12th International Workshop on Boolean Problems. Freiberg, 22.09.2016 - 23.09.2016, pp. 129-136. ISBN 978-3-86012-540-3. [pdf]
ŠVEPEŠ, M. and ČEJKA, T. Overload-resistant Network Traffic Analysis. In Proceedings of the 4th Prague Embedded Systems Workshop, Roztoky u Prahy, 30.06.2016 - 02.07.2016. pp. 53-58. ISBN 978-80-01-05984-5.
TAMÁŠI, R., SIEBERT, M., GRAMATOVÁ, E., and FIŠER, P., A New Method for Path Criticality Calculation. In: Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Košice, 20.04.2016 - 22.04.2016, pp. 190-193. ISBN 978-1-5090-2467-4. [pdf]
VAŇÁT, T., et al. Comparing Proton and Neutron Induced SEU Cross Section in FPGA. In: Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice, 20.04.2016 - 22.04.2016, pp. 214-217. ISBN 978-1-5090-2467-4.

2015

Alexa, D. - Čejka, T.: Easy configuration of NETCONF devices, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 3-9. ISBN 978-80-01-05776-6.
Bartík, M. - Ubik, S. - Kubalík, P.: Rychlé bezztrátové kompresní algoritmy, In: PAD 2015, Zlín, 2015, pp. 31-36. ISBN 978-80-7454-522-1.
Bartík, M. - Ubik, S. - Kubalík, P.: LZ4 Compression Algorithm on FPGA, In: 21st IEEE International Conference on Electronics, Circuits, and Systems, 2015, pp. 179-182. ISBN 978-1-4799-2451-6.
Bartík, M. - Novotný, M.: Advanced control unit for linear motor for precise measurements in biomechanics, In: EMBEDDED COMPUTING. MEDITERRANEAN CONFERENCE. 4TH 2015. (MECO 2015), 2015, pp. 129-133. ISBN 978-1-4799-8999-7.
Bělohoubek, J.: Smart re-use of hardware peripherals for better software UART, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 17-23. ISBN 978-80-01-05776-6.
Bělohoubek, J.: Novel Gate Design Method for Short-Duration Test, In: Proceedings of the 19th International Scientific Student Conferenece POSTER 2015, Prague, ISBN 978-80-01-05499-4.
Bělohoubek, J.: Novel Error Detection and Correction Method Combining Time and Area Redundancy, In: PAD 2015, Zlín, 2015, pp. 48-53. ISBN 978-80-7454-522-1.
Bělohoubek, J. - Fišer, P. - Schmidt, J.: Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy, In: Proceedings of the Euromicro Conference on Digital System Design, 2015, pp. 280-283. ISBN 978-1-4673-8035-5. DOI: 10.1109/DSD.2015.95
Benáček, P. - Kubátová, H. - Puš, V.: Automatic Generation of 100 Gbps Packet Parsers from P4 Description, In: First International Workshop on Heterogeneous High-performance Reconfigurable Computing. 2015
Čejka, T. - Bartoš, V. - Truxa, L. - Kubátová, H.: Using Application-Aware Flow Monitoring for SIP Fraud Detection, In: Intelligent Mechanisms for Network Configuration and Security. Springer International Publishing, 2015, pp. 87-99. ISSN 0302-9743. ISBN 978-3-319-20033-0.
Čejka, T. - Bodó, R. - Kubátová, H.: Nemea: Searching for Botnet Footprints, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 11-16. ISBN 978-80-01-05776-6.
Daňhel, M.: The Determination of Operational Reliability and Predictive Analysis of Reliability of the Railway Signaling Systems, In: Proceedings of the 19th International Scientific Student Conferenece POSTER 2015, 2015, ISBN 978-80-01-05499-4.
Fišer, P. - Schmidt, J.: Introduction to Lethal Circuit Transformations, In: Proc. of Design and Analysis of Control Systems, March 20-23, 2015, Athens, Greece, p. 4. ISSN 0094-243X. ISBN 978-0-7354-1349-8. DOI: 10.1063/1.4938891
Háleček, I. - Fišer, P. - Schmidt, J.: On Identification of XOR Gates in AIGs, In: Proceedings of the Work in Progress Session of the 18th EUROMICRO Conference on Digital System Design, 2015, ISBN 978-3-902457-44-8.
Hyniová, K.: External Fuzzy Logic Control of Simulated Technological Processes, In: Recent Advances in Systems. Athens: World Scientific and Engineering Society Press, 2015, vol. 1, pp. 129-132. ISSN 1790-5117. ISBN 978-1-61804-321-4.
Tamaši, R. - Siebert, M. - Fišer, P.: A New Method for Speficication of Parameters to Path Delay Fautls Testing, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 26-32. ISBN 978-80-01-05776-6.
Vaňát, T. - Pospíšil, J. - Křížek, F. - Ferencei, J. - Kubátová, H.: A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other Electronics, In: Proceedings of the Euromicro Conference on Digital System Design, ISBN 978-1-4673-8035-5.

2014

Balcárek, J. - Fišer, P. - Schmidt, J.: On don't cares in test compression. In: Microprocessors and Microsystems. 2014, vol. 38, no. 8, p. 754-765. ISSN 0141-9331. DOI: 10.1016/j.micpro.2014.07.006
Balcárek, J. - Fišer, P. - Schmidt, J.: PBO-Based Test Compression. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 679-682. ISBN 978-1-4799-5793-4. [pdf]
Bartík, M.: Practical use of FPGA Chips for Implementation. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014, p. 15.
Benáček, P. - Blažek, R. - Čejka, T. - Kubátová, H.: Change-point detection method on 100 Gb/s ethernet interface In: Architectures for Networking and Communications Systems (ANCS), 2014 ACM/IEEE Symposium on. New York: ACM, 2014, p. 245-246. ISBN 978-1-4503-2839-5.
Benáček, P. - Kubátová, H. Architecture of Effective High-Speed Network Stream Merger. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 459-464. ISBN 978-1-4799-5793-4.
Bernasconi, A. - Ciriani, V. - Fišer, P. - Trucco, G.: Weighted Don't Cares in Logic Synthesis. In: Recent Progress in the Boolean Domain. Cambridge: Cambridge Scholars Publishing, 2014, p. 263-277. ISBN 978-1-4438-5638-6.
Borecký, J. - Vít, P. - Kubátová, H.: Fault Recovery Method of Modular Systems based on Reconfigurations. In: Designing with Uncertainty - Opportunities and Challenges Workshop. 2014.
Borecký, J. - Vít, P. - Kubátová, H.: Fault Recovery Method with High Availability for Practical Applications. In: MEMICS proceedings. Brno: NOVPRESS, 2014, p. 127. ISBN 978-80-214-5022-6.
Buček, J. - Kubalík, P. - Lórencz, R. - Zahradnický, T.: System Design of an FPGA Linear Solver. In: Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0.
Čejka, T. - Kekely, L. - Benáček, P. - Blažek, R. - Kubátová, H.: FPGA Accelerated Change-Point Detection Method for 100 Gb/s Networks. In: MEMICS proceedings. Brno: NOVPRESS, 2014, p. 40-51. ISBN 978-80-214-5022-6.
Čejka, T. - Rosa, Z. - Kubátová, H.: Stream-wise Detection of Surreptitious Traffic over DNS. In: 2014 IEEE 19th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD 2014). Pomona, California: IEEE Communications Society, 2014, ISBN 978-1-4799-5726-2.
Fišer, P. - Schmidt, J.: Permuting Variables to Improve Iterative Resynthesis. In: Recent Progress in the Boolean Domain. Cambridge: Cambridge Scholars Publishing, 2014, p. 213-230. ISBN 978-1-4438-5638-6.
Fišer, P. - Schmidt, J. - Balcárek, J.: Sources of Bias in EDA Tools and Its Influence. In: Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Piscataway: IEEE, 2014, p. 258-261. ISBN 978-1-4799-4560-3. [pdf]
Hyniová, K.: On Experimental Verification Of Vehicle Active Suspension Robust Control. In: Proceedings of the 18 th International Conference on systems. Athens: WSEAS, 2014, p. 353-358. ISSN 1790-5117. ISBN 978-1-61804-243-9.
Hyniová, K. - Smítková Janků, L.: Using Fuzzy Logic to Control an Innovative Active Vehicle Suspension System. In: Proceedings of the 18 th International Conference on systems. Athens: WSEAS, 2014, p. 161-167. ISSN 1790-5117. ISBN 978-1-61804-243-9.
Kohlík, M. - Kubátová, H.: Hierarchical Models of Markov Chains: Optimizations with Limited Pessimism. In: Proceedings of the 18th International Conference Electronics 2014. Kaunas: Technologija, 2014, p. 59-62. ISBN 978-609-02-1065-9. [pdf]
Kohlík, M. - Kubátová, H.: Pessimistic Dependability Models Based on Hierarchical Markov Chains. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014.
Lemberski, I. - Fišer, P.: Dual-Rail Asynchronous Logic Multi-Level Implementation. In: Integration, the VLSI Journal. 2014, vol. 47, no. 1, p. 148-159. ISSN 0167-9260. DOI: 10.1016/j.vlsi.2013.02.002
Lemberski, I. - Fišer, P. - Suleimanov, R.: Asynchronous sum-of-products logic minimization and orthogonalization. In: International Journal of Circuit Theory and Applications. 2014, vol. 42, no. 6, p. 562-571. ISSN 0098-9886. DOI: 10.1002/cta.1870
Pospíšil, J. - Vaňát, T. - Schmidt, J.: Towards Trusted Devices in FPGA by Modeling. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014, p. 16.
Schmidt, J. - Blažek, R.B. - Fišer, P.: On Probability Density Distribution of Randomized Algorithms Performance. In: Proceedings of the 11th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2014, p. 67-74. ISBN 978-3-86012-488-8. [pdf]
Schmidt, J. - Fišer, P. - Balcárek, J.: On Robustness of EDA Tools. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 427-434. ISBN 978-1-4799-5793-4. [pdf]
Štěpánek, F.: Case study: Comparison of various approaches in Fault-Tolerant and Attack-Resistant system design. In: Sborník příspěvků PAD 2014. Liberec: Technical University of Liberec, 2014, p. 81-86. ISBN 978-80-7494-026-2.
Štěpánek, F. - Novotný, M.: Comparison of various approaches in Fault-Tolerant and Attack-Resistant system design. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014.
Vít, P. - Borecký, J. - Kohlík, M. - Kubátová, H.: Fault Tolerant Duplex System with High Availability for Practical Applications. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 320-325. ISBN 978-1-4799-5793-4.

2013

Balcárek, J. - Fišer, P. - Schmidt, J.: Techniques for SAT-Based Constrained Test Pattern Generation. Microprocessors and Microsystems. 2013, vol. 37, no. 2, pp. 185-195. ISSN 0141-9331. DOI: 10.1109/DSD.2011.50
Hyniová, K.H.: An Innovative Active Suspension System for Autonomous Vehicles: A safe and Comfortable Ride and Good Handling. ERCIM News. 2013, no. 94, pp. 28-29. ISSN 0926-4981.
Gueneysu, T. - Kasper, T. - Novotný, M. - Paar, C. - Wienbrandt, L. - et al.: High-Performance Cryptanalysis on RIVYERA and COPACOBANA Computing Systems. In High-Performance Computing Using FPGAs. New York: Springer, 2013, pp. 335-366. ISBN 978-1-4614-1790-3.
Balcárek, J. - Fišer, P. - Schmidt, J.: Simulation and SAT Based ATPG for Compressed Test Generation. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center , 2013, p. 445-452. ISBN 978-0-7695-5074-9. [pdf]
Benáček, P.: Architektura pro měření v reálném čase na vysokorychlostních sítích. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 45-50. ISBN 978-80-261-0270-0.
Buček, J. - Kubalík, P. - Lórencz, R. - Zahradnický, T.: Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. In Proceedings of 16th Euromicro Conference on Digital System Design, 2013, pp. 284-287. ISBN 978-0-7695-5074-9. [pdf]
Daňhel, M.: Predikce a analýza spolehlivosti kritických systémů. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 69-74. ISBN 978-80-261-0270-0.
Daňhel, M. D. - Kubátová, H. K. - Dobiáš, R. D.: Predictive Analysis of Mission Critical Systems Dependability. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center, 2013, ISBN 978-0-7695-5074-9.

[pdf]

Daňhel, M. D. - Kubátová, H. K. - Dobiáš, R. D.: Predikce a analýza spolehlivosti kritických systémů. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 69-74. ISBN 978-80-261-0270-0.
Kohlík, M. - Kubátová, H.: Hierarchical Dependability Models Based on Markov Chains. In Proceedings of 2013 26th International Conference on Architecture of Computing Systems (ARCS). Berlin: VDE VERLAG GMBH Berlin, 2013, ISBN 978-3-8007-3492-4. [pdf]
Kohlík, M. - Kubátová, H.: Markov chains hierarchical dependability models: Worst-case computations. In 14th Latin American Test Workshop. Los Alamitos: IEEE Computer Society, 2013, ISBN 978-1-4799-0595-9. [pdf]
Kubátová, H. - Daňhel, M. - Dobiáš, R.: Predictive Analysis of Mission Critical Systems. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center , 2013, pp. 561-566. ISBN 978-0-7695-5074-9.
Kyncl, J. - Hariram, A. - Novotný, M.: On Measurement of Synchronous Phasors in Electrical Grids. In ISCAS 2013 Conference Proceedings. Piscataway: IEEE, 2013, pp. 2972-2975. ISSN 0271-4302.ISBN 978-1-4673-5760-9.
Pospíšil, J.: Modelováním poruch ke spolehlivým architekturám FPGA. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 117-122. ISBN 978-80-261-0270-0.
Pospíšil, J. - Schmidt, J. - Fišer, P.: New SEU Modeling by Architecture Analysis. In Proceeding of the Work in Progress Session of 16th Euromicro Conference on Digital System Design. 2013, ISBN 978-3-902457-38-7. [pdf]
Richta, K. - Kubátová, H. - Richta, T.: Petri Nets versus UML State Machines. In SDOT 2013. Praha: Vysoká škola manažerské informatiky a ekonomiky, a.s., 2013, pp. 1-7. ISBN 978-80-86847-66-5.
Štěpánek, F. - Buček, J. - Novotný, M.: Differential Power Analysis under Constrained Budget: Low Cost Education of Hackers. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center , 2013, pp. 645-648. ISBN 978-0-7695-5074-9. [pdf]

2012

Benáček, P. - Kubátová, H.: Metodologie pro analýzu rychlých síťových přenosů. In Počítačové architektury a diagnostika - PAD 2012. Praha: ČVUT v Praze, 2012, p. 9-12. ISBN 978-80-01-05106-1.
Bernasconi, A. - Ciriani, V. - Fišer, P. - Trucco, G.: Weighted Don't Cares. In Proc. of 10th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2012, p. 123-130. ISBN 978-3-86012-438-3. [pdf]
Borecký, J. - Kohlík, M. - Kubátová, H.: Miscellaneous Types of Partial Duplication Modifications for Availability Improvements. In Proceedings of the 15th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2012, p. 79-83. ISBN 978-0-7695-4798-5. [pdf]
Buček, J. - Kubalík, P. - Lórencz, R. - Zahradnický, T.: Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA. In The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012. Monterey: IEEE Circuits and Systems Society, 2012, p. 689-692. ISBN 978-1-4673-1259-2. [pdf]
Čejka, T. : Hardwarově akcelerovaná detekce anomálií v počítačových sítích s využitím FPGA. In Počítačové architektury a diagnostika - PAD 2012. Praha: ČVUT v Praze, 2012, p. 13-16. ISBN 978-80-01-05106-1.
Fišer, P. - Schmidt, J.: Improving the Iterative Power of Resynthesis. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 30-33. ISBN 978-1-4673-1185-4. [pdf]
Fišer, P. - Schmidt, J.: On Using Permutation of Variables to Improve the Iterative Power of Resynthesis. In Proc. of 10th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2012, p. 107-114. ISBN 978-3-86012-438-3. [pdf]
Fišer, P. - Schmidt, J.: A Difficult Example Or a Badly Represented One? In Proc. of 10th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2012, p. 115-122. ISBN 978-3-86012-438-3. [pdf]
Hyniová, K. - Smítková Janků, L. - Honců, J. - Stříbrský, A.: On Experiments Taken on The Active Shock Absorber Test Stand. In APPLIED MATHEMATICS in ELECTRICAL and COMPUTER ENGINEERING. New York: WSEAS Press, 2012, vol. 1, p. 104-109. ISBN 978-1-61804-064-0.
Hyniová, K. - Krajl, M. - Smítková Janků, L.: Experiments Taken on Energy Management in Active Suspension of Vehicles. International Journal of Circuits, Systems and Signal Processing [online]. 2012, vol. 6, no. 1, p. 196-203. Internet: http://www.naun.org/wseas/cms.action?id=3113. ISSN 1998-4464.
Chloupek, M. - Novák, O. - Jeníček, J.: On test time reduction using pattern overlapping, broadcasting and on-chip decompression. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 300-305. ISBN 978-1-4673-1185-4.
Kohlík, M. - Kubátová, H.: Reduction of Complex Safety Models based on Markov Chaints. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 183-186. ISBN 978-1-4673-1185-4. [pdf]
Kohlík, M. - Kubátová, H.: Hierarchical Dependability Models Based on Markov Chains. In Počítačové architektury a diagnostika - PAD 2012. Praha: ČVUT v Praze, 2012, p. 145-150. ISBN 978-80-01-05106-1. [pdf]
Pospíšil, J. - Novotný, M.: Lightweight Cipher Resistivity against Brute-Force Attack: Analysis of PRESENT. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 197-198. ISBN 978-1-4673-1185-4. [pdf], [poster]
Pospíšil, J. - Novotný, M.: Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable Hardware. In Proceedings of the 15th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2012, p. 560-567. ISBN 978-0-7695-4798-5.
Schmidt, J. - Fišer, P. - Balcárek, J.: The Influence of Implementation Technology on Dependability Parameters. In Proceedings of the 15th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2012, p. 368-373. ISBN 978-0-7695-4798-5. [pdf]
Schmidt, J. - Fišer, P. - Balcárek, J.: Generalized Miter and its Application in Hardware Design. In Proceedings of the 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS, 2012, p. 119-120. ISBN 978-80-87342-15-2.
Vít, P.: Dependability structures testing device based on real model of a railway station. In POSTER 2012 - 16th International Student Conference on Electrical Engineering [CD-ROM]. Praha: Czech Technical University in Prague, 2012, p. 1-3. ISBN 978-80-01-05043-9.
Ubik, S. - Trávníček, Z. - Žejdl, P. - Halák, J.: Remote Access to 3D Models for Research, Engineering, and Art. IEEE Multimedia. 2012, vol. 19, no. 4, p. 12-19. ISSN 1070-986X.

2011

BALCÁREK J.: Implicit Representations in the Diagnostic of the Digital Circuits. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 67–72. ISBN 978-80-227-3552-0.
BALCÁREK J. – FIŠER P. – SCHMIDT J.: Techniques for SAT-Based Constrained Test Pattern Generation. In Proceedings of the 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, p. 360–366. ISBN 978-0-7695-4494-6. [pdf]
BALCÁREK J. – FIŠER P. – SCHMIDT J.: Implicit Techniques for Constrained Test Patterns Generation. In Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011, p. 106. ISBN 978-80-214-4305-1.
BORECKÝ J. – KOHLÍK M. – KUBALÍK P. – KUBÁTOVÁ H.: Fault Models Usability Study for On-line Tested FPGA. In Proceedings of the 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, p. 287–290. ISBN 978-0-7695-4494-6. [pdf]
BORECKÝ J. – VÍT P. – KUBÁTOVÁ H.: Self Repair Architectures Based on Partial Dynamic and Static Reconfiguration. In Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011, p. 11–18. ISBN 978-80-214-4305-1.
DAŇHEL M.: Hierarchical reliability block diagrams in the program SHAMAP. In POSTER 2011 - 15th International Student Conference on Electrical Engineering. Prague: CTU, Faculty of Electrical Engineering, 2011, p. 25–29. ISBN 978-80-01-04806-1.
DAŇHEL M. – KUBÁTOVÁ H.: Methods of hierarchical reliability block diagrams in the program SHAMAP. In Proceedings of the Work in Progress Session - DSD 2011. Oulu: University of Oulu, 2011, p. 31–32. ISBN 978-3-902457-30-1.
DAŇHEL M. D. – DOBIÁŠ R. D. – KUBÁTOVÁ H. K.: Hierarchické blokové modely. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, s. 44–49. ISBN 978-80-227-3552-0.
FIŠER P. – SCHMIDT J.: How Much Randomness Makes a Tool Randomized?. In Proc. of 20th International Workshop on Logic and Synthesis 2011. La Jolla: University of California San Diego, 2011, p. 136–143. [pdf]
HYNIOVÁ K. – HONCŮ J.: Theoretical Limitations in Vehicle System Dynamics. In Recent Researches in System Science. Athens: WSEAS Press, 2011, vol. 1, p. 48–53. ISBN 978-1-61804-023-7. [pdf]
CHLOUPEK M.: On Test Compression Based on Pattern Overlapping and Broadcasting. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 121–126. ISBN 978-80-227-3552-0.
CHLOUPEK M. – NOVÁK O.: Scan Chain Configuration Method for Broadcast Decompressor Architecture. In 12th IEEE Latin-American Test Workshop. New York: IEEE, 2011, p. 1–5. ISBN 978-1-4577-1489-4.
CHLOUPEK M. – NOVÁK O.: Test Pattern Compression Based on Pattern Overlapping and Broadcasting. In 2011 10th International workshop on Electronics, Control, Measurement and Signals (ECMS). New York: IEEE Computer Society Press, 2011, p. 1–5. ISBN 978-1-61284-397-1.
CHLOUPEK M. – NOVÁK O.: Test pattern compression based on pattern overlapping and broadcasting. In Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011, p. 111. ISBN 978-80-214-4305-1.
JENÍČEK J. – NOVÁK O. – CHLOUPEK M.: Advanced Scan Chain Configuration Method for Broadcast Decompressor Architecture. In 9th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM. Kharkiv: Kharkov National University of Radioelectronics, 2011, p. 140–143.
KUBÁTOVÁ H. – KUBALÍK P.: Fault-tolerant and fail-safe design based on reconfiguration. In Technology for Dependable Systems-on-Chip. Hershey, Pennsylvania: IGI Global, 2011, p. 175–194. ISBN 978-1-60960-212-3.
KYNCL J. – NOVOTNÝ M.: Education of Digital and Analog Circuits Supported by Computer Algebra System. In ISCAS 2011 Conference Proceedings. Piscataway: IEEE, 2011, p. 341–344. ISBN 978-1-4244-9472-9.
ŠTEMBERA P. – NOVOTNÝ M.: Breaking Hitag2 with Reconfigurable Hardware. In Proceedings of the 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, p. 558–563. ISBN 978-0-7695-4494-6.
VAŇÁT T. – KUBÁTOVÁ H.: SEU Experiments Using Real FPGAs. In POSTER 2011 - 15th International Student Conference on Electrical Engineering [CD–ROM]. Prague: CTU, Faculty of Electrical Engineering, 2011, ISBN 978-80-01-04806-1.
VAŇÁT T. – KUBÁTOVÁ H.: Experiments with Physical Error Injection into FPGA Circuits. In Proceedings of the Work in Progress Session - DSD 2011. Oulu: University of Oulu, 2011, p. 35–36. ISBN 978-3-902457-30-1.
VAŇÁT T. – KUBÁTOVÁ H.: Physical Injection of Errors Into the FPGA. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 103–108. ISBN 978-80-227-3552-0.
VÍT P.: Increasing Dependability by Fitting Circuit on FPGA. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 9–13. ISBN 978-80-227-3552-0.
VÍT P. – KUBÁTOVÁ H.: Impact of FPGA Technology Process on Depandability of Counters. In Proceedings of the Work in Progress Session - DSD 2011. Oulu: University of Oulu, 2011, p. 33–34. ISBN 978-3-902457-30-1.
VÍT P. – KUBÁTOVÁ H.: Using Decomposition to Create Fault Secure Counters of the Railway Station Safety Device. In POSTER 2011 - 15th International Student Conference on Electrical Engineering. Prague: CTU, Faculty of Electrical Engineering, 2011, ISBN 978-80-01-04806-1.

2010

BALACH J. – NOVÁK O.: Reconfigurable Fault-Tolerant System Synchronization. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 817–820. ISBN 978-0-7695-4171-6.
BALACH J. – NOVÁK O.: Reconfiguration Based Fault Tolerant Systems Design - Survey of Approaches. In 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS, 2010, p. 3–10. ISBN 978-80-87342-10-7.
BALCÁREK J.: Implicit Rrepresentations in Customized Testing of Digital Circuits. In Počítačové architektury & diagnostika. Brno: Vysoké učení technické v Brně, 2010, p. 15–20. ISBN 978-80-214-4140-8.
BALCÁREK J. - FIŠER P. - SCHMIDT J.: Implicit Representations in Test Patterns Compression for Scan-Based Digital Circuits. In Informal Proceedings of European Test Symposium. Praha: ČVUT v Praze, 2010. [pdf]
BALCÁREK J. - FIŠER P. - SCHMIDT J.: Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 805-808. ISBN 978-0-7695-4171-6. [pdf]
BENÁČEK P. - NOVOTNÝ M.: Implementing Brute-Force Attack on PRESENT Cipher. In Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010. Linz: Johannes Kepler University, 2010, p. 51-52. ISBN 978-3-902457-27-1.
BORECKÝ J. - KOHLÍK M. - KUBÁTOVÁ H.: How to Measure Dependability Parameters of Programmable Digital Circuits - A Survey. In 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS, 2010, p. 28-35. ISBN 978-80-87342-10-7. [pdf]
BORECKÝ J. - KOHLÍK M. - KUBÁTOVÁ H. - KUBALÍK P.: Faults Coverage Improvement based on Fault Simulation and Partial Duplication. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 380-386. ISBN 978-0-7695-4171-6. [pdf]
BORECKÝ J. - KUBÁTOVÁ H.: Dependable Interconnection of Dependable Blocks. In Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010. Linz: Johannes Kepler University, 2010, p. 17-18. ISBN 978-3-902457-27-1.
FIŠER P. - SCHMIDT J.: It Is Better to Run Iterative Resynthesis on Parts of the Circuit. In Proceedings of the 19th International Workshop on Logic and Synthesis. Irvine, CA: University of California, Irvine, 2010, p. 17-24. [pdf]
FIŠER P. - SCHMIDT J.: New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools. In Proceedings of the 9th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2010, p. 157-164. ISBN 978-3-86012-404-8. [pdf]
FIŠER P. - SCHMIDT J. - SEKANINA L. - VAŠÍČEK Z.: On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. In Proc. of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Piscataway: IEEE, 2010, p. 346-351. ISBN 978-1-4244-6610-8. [pdf]
CHLOUPEK M.: Simple Heuristic for Broadcast Scan Chain Configuration. In Počítačové architektury & diagnostika. Brno: Vysoké učení technické v Brně, 2010, p. 39-44. ISBN 978-80-214-4140-8.
KOHLÍK M. - KUBÁTOVÁ H.: Model of Modular Secured Designs for Calculations of Availability. In Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010. Linz: Johannes Kepler University, 2010, p. 15-16. ISBN 978-3-902457-27-1. [pdf]
LEMBERSKI I. - FIŠER P.: Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 155-162. ISBN 978-0-7695-4171-6. [pdf]
TOMAN D. - FIŠER P.: A SOP Minimizer for Logic Functions Described by Many Product Terms Based on Ternary Trees. In Proceedings of the 9th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2010, p. 165-172. ISBN 978-3-86012-404-8. [pdf]
VÍT P.: Návrh obvodů s volitelnou úrovní spolehlivosti na bázi FPGA. In Počítačové architektury & diagnostika. Brno: Vysoké učení technické v Brně, 2010, s. 87-90. ISBN 978-80-214-4140-8. [pdf]

2009

BALACH, J.: Synchronizace rekonfigurovatelného systému, In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 13-19. ISBN 978-80-7318-847-4.
BALCÁREK, J.: Test Patterns Compression Techniques Based on SAT Solving for Scan-Based Digital Circuits, In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 26-31. ISBN 978-80-7318-847-4.
BALCÁREK J. - FIŠER P. - SCHMIDT J.: On Properties of SAT Instances Produced by SAT-Based ATPGs. In Fifth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: neuveden, 2009, p. 3-10. ISBN 978-80-87342-04-6. [pdf]
BORECKÝ, J.: Dependable Universal Blocks (DUBs), In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 42-47. ISBN 978-80-7318-847-4.
BORECKÝ J. - KUBALÍK P. - KUBÁTOVÁ H.: Reliable Railway Station System based on Regular Structure implemented in FPGA. In Proc. of 12th EUROMICRO Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2009, p. 348-354. ISBN 978-0-7695-3782-5.
FIŠER, P. - TOMAN, D.: A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms, Proc. of 12th Euromicro Conference on Digital Systems Design (DSD'09), Patras (Greece), 27. - 29.8.2009, pp. 757-764 [pdf]
FIŠER P. - SCHMIDT J.: The Case for a Balanced Decomposition Process. In Proc. of 12th EUROMICRO Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2009, p. 601-604. ISBN 978-0-7695-3782-5. [pdf]
FIŠER P. - SCHMIDT J.: The Observed Role of Structure in Logic Synthesis Examples. In Proceedings of the International Workshop on Logic and Synthesis 2009. Berkeley, CA: IWLS Organizing Committee, 2009, p. 210-213. [pdf]
KOHLÍK, M.: Dependability models based on Petri nets and Markov chains, In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 95-103. ISBN 978-80-7318-847-4. [pdf]
KOHLÍK M. - KUBÁTOVÁ H.: Reconfiguration Strategy for FPGA Dependability Characteristics Improvement based on Stochastic Petri Net. In Proc. of 4th Descrete-Event System Design. Valencia: University of Valencia, 2009, p. 253-257. [pdf]
KVASNIČKA J. - KUBÁTOVÁ H.: Single Event Upset Tolerant FPGA Design. In Proceedings of the Work in Progress Session SEAA 2009 and DSD 2009. Linz: J. Kepler University - FAW, 2009, p. 37-38. ISBN 978-3-902457-25-7.
LEMBERSKI I. - FIŠER P.: Asynchronous Two-Level Logic of Reduced Cost. In Proc. of 12th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2009 (DDECS'09). Los Alamitos: IEEE Computer Society Press, 2009, p. 68-73. ISBN 978-1-4244-3339-1. [pdf]
LEMBERSKI I. - FIŠER P.: Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes. In Proc. of 4th Descrete-Event System Design. Valencia: University of Valencia, 2009, p. 213-218. [pdf]
KUBÁTOVÁ H.: Teaching Principles of Petri Nets in Hardware Courses and Student' Projects. In Handbook of Research on Discrete Event Simulation Environments: Technologies and Applications. Hershey: Information science Reference, 2009, p. 178-190. ISBN 978-1-60566-774-4.
NOVOTNÝ M.: COPACOBANA-Assisted Cryptanalysis of GSM Communication. In Fifth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno, 2009, p. 236. ISBN 978-80-87342-04-6.

2008

DOBIÁŠ R. - FARAN A. - SCHRÖTTER J. - SRB S.: Digitalizace kolejových obvodů, Nová železniční technika. 2008, roč. 16, č. 5, s. 7-10. ISSN 1210-3942.
DOBIÁŠ R. - KONARSKI J. - KUBÁTOVÁ H.: Dependability Evaluation of Real Railway Interlocking Device. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 228-233. ISBN 978-0-7695-3277-6.
FIŠER P. - KUBÁTOVÁ H.: Column-matching based mixed-mode test pattern generator design technique for BIST. Microprocessors and Microsystems. 2008, vol. 32, no. 5-6, p. 340-350. ISSN 0141-9331.
FIŠER P. - KUBALÍK P. - KUBÁTOVÁ H.: An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 96-99. ISBN 978-0-7695-3277-6. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Scalable Test Pattern Generator Design Method for BIST. In Proc. of 9th IEEE Latin-American Test Workshop. Mexico City: INAOE, 2008, p. 69-74. [pdf]
FIŠER P. - RUCKÝ P. - VÁŇOVÁ I.: Fast Boolean Minimizer for Completely Specified Functions. In Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 (DDECS'08). Los Alamitos: IEEE Computer Society Press, 2008, p. 122-127. ISBN 978-1-4244-2276-0. [pdf]
FIŠER P. - SCHMIDT J.: Small but Nasty Logic Synthesis Examples. In Proc. of 8th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2008, p. 183-190. ISBN 978-3-86012-346-1. [pdf]
FIŠER P. - TOMAN D.: BoolTool: A Tool for Manipulation of Boolean Functions. In Proc. of 8th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2008, p. 109-114. ISBN 978-3-86012-346-1. [pdf]
GENDRULLIS T. - NOVOTNÝ M. - RUPP A.: A Real-World Attack Breaking A5/1 within Hours, In Proceedings of the 10th Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008). Heidelberg: Springer, 2008, vol. 5154, p. 266-282. ISBN 978-3-540-85052-6.
GUENEYSU T. - KASPER T. - NOVOTNÝ M. - PAAR C. - RUPP A.: Cryptanalysis with COPACOBANA, IEEE Transactions on Computers. 2008, vol. 57, no. 11, p. 1498-1513. ISSN 0018-9340.
KUBALÍK P. - KUBÁTOVÁ H.: Dependable design technique for system-on-chip. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621.
KVASNIČKA J. - KUBALÍK P. - KUBÁTOVÁ H.: Experimental SEU Impact on Digital Design Implemented in FPGAs. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 100-103. ISBN 978-0-7695-3277-6.
KVASNIČKA J. - KUBALÍK P. - KUBÁTOVÁ H.: Experimental emulation of FPGA bitstream faults in combinatorial circuits. In Proceedings of CSE 2008 International Scientific Conference on Computer Science and Engineering. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2008, vol. 1, p. 328-335. ISBN 978-80-8086-092-9. [pdf]
KVASNIČKA J. - KUBÁTOVÁ H.: Emulation of SEU Effect In Bitstream of FPGA. In 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Ing. Zdenek Novotny, CSc., 2008, p. 140-147. ISBN 978-80-7355-082-0. [pdf]
KVASNIČKA J.: FPGA bitstream analysis and emulation of SEU effect, In Počítačové architektury & diagnostika. Liberec: Technická univerzita v Liberci, 2008, p. 63-68. ISBN 978-80-7372-378-1. [pdf]
NOVÁK O. - PLÍVA Z. - JENÍČEK J. - MADER Z. - JARKOVSKÝ M.: A Self/Testing SoC with Reduced Memory Requirements, Acta Electrotechnica et Informatica. 2008, vol. 2008, no. 1, p. 22-31. ISSN 1335-8243.

2007

BEČVÁŘ M. - KAHÁNEK S.: VLIW-DLX simulator for educational purposes, 2007, In Proceedings of the 2007 Workshop on Computer Architecture Education. New York: ACM Press, 2007, s. 8-13. ISBN 978-1-59593-797-1.
DAVIDOVIČ T. - HAVLAN M. - NOVOTNÝ M. - SCHMIDT J. - BEZPALEC P.: Framework for Research of ECDSA. In Proceedings CD-ROM of Digital Technologies 2007. Žilina: Slovenská elektrotechnická společnost, 2007, ISBN 978-80-8070-786-6.
FARAN A. - MLNAŘÍK K. - SRB S. - BUKAČ P. - DOBIÁŠ R.: Method for a One-time Calibration of a Multiple Branches Digital Measurement System Working in Minimum Number of Branches Mode (Patent) 2007, Patent World Intellectual Property Organization, WO/2007/085208. 2007-08-02.
FARAN A. - SRB S. - VOTOČEK L. - KONARSKI J. - DOBIÁŠ R. - KRÁL J.: Method of the Phase-sensitive Evaluation of the Conductive Current of the Track Circuit (Patent), 2007, Patent World Intellectual Property Organization, WO/2007/016878. 2007-02-15.
FARAN A. - MLNAŘÍK K. - SRB S. - BUKAČ P. - DOBIÁŠ R.: Způsob jednorázové kalibrace digitální měřicí soustavy pracující v režimu minimálního počtu větví ze všech možných větví (Patent), 2007, Patent Úřad průmyslového vlastnictví, 297929. 2007-03-21.
FIŠER P.: Pseudo-Random Pattern Generator Design for Column Matching BIST. In Proceedings of 10th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2007, p. 657-663. ISBN 0-7695-2978-X. [pdf]
JENÍČEK J. - NOVÁK O.: Test Pattern Compression Based on Pattern Overlapping. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 29-34. ISBN 1-4244-1161-0.
KUBALÍK P. - KVASNIČKA J. - KUBÁTOVÁ H.: Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. [pdf]
KVASNIČKA J. - KUBALÍK P. - KUBÁTOVÁ H.: An FPGA based fault emulator. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. [pdf]
NOVÁK O.: Efficient Test Pattern Compression and Decompression System. In 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07). Ribno at Bled: MIDEM, 2007, vol. 1, p. 147-152. ISBN 978-961-91023-7-4.
NOVÁK O.: COMPAS and Other Test Pattern Compression Methods. In Computer Science Reports. Cottbus: Brandenburg University of Technology at Cottbus, 2007, p. 1-6. ISSN 1437-7969.
NOVOTNÝ M. - SCHMIDT J.: General Digit-Serial Normal Basis Multiplier with Distributed Overlap. In Proceedings of 10th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2007, p. 94-101. ISBN 0-7695-2978-X. [pdf]
UBIK S. - ŽEJDL P. - HALÁK J.: Real-time anonymization in passive network monitoring, 2007, In Proceedings of the Third International Conference on Networking and Services. New York: IEEE Computer Society Press, 2007, s. 100-106. ISBN 0-7695-2858-9.

2006

BEČVÁŘ M. - KUBÁTOVÁ H. - NOVOTNÝ M.: Massive Digital Design Education for Large Amount of Undergraduate Students. In Proceedings of EWME 2006. Stockholm: Royal Institute of Technology, 2006, p. 108-111. ISBN 91-7178-402-0. [pdf]
BŮBELA T. - FARAN A. - SRB S. - DOBIÁŠ R.: Způsob kompenzace ohrožujících proudů emitovaných z trakčního pohonu silového obvodu hnacího železničního vozidla do kolejového obvodu a zapojení kompenzátoru k provádění tohoto způsobu (Patent), 2006, Patent Úřad průmyslového vlastnictví, 297154. 2006-08-03.
DAVIDOVIČ T. - HAVLAN M. - NOVOTNÝ M. - SCHMIDT J.: Implementation of ECDSA in Combo6X Card. In Digital Technologies 2006 - 3rd International Workshop [CD-ROM]. Žilina: University of Žilina, Fakulty of electrical engineering, 2006, vol. 1, ISBN 80-8070-637-9.
FARAN A. - SRB S. - VOTOČEK L. - KONARSKI J. - DOBIÁŠ R. - KRÁL J.: Způsob fázově citlivého vyhodnocení konduktivního proudu kolejového obvodu (Patent), 2006, Patent Úřad průmyslového vlastnictví, 297442. 2006-11-01.
FIŠER P. - KUBALÍK P. - KUBÁTOVÁ H.: Output Grouping Method Based on a Similarity of Boolean Functions. In Proceedings of the 7th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2006, p. 107-113. ISBN 3-86012-287-8. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Multiple-Vector Column-Matching BIST Design Method. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 268-273. ISBN 1-4244-0184-4. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Flexible Two-Level Boolean Minimizer BOOM II and Its Applications. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 369-376. ISBN 0-7695-2609-8. [pdf]
KAFKA L. - NOVÁK O.: FPGA-based Fault Simulator, 2006, In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, s. 274-278. ISBN 1-4244-0184-4.
KUBALÍK P. - DOBIÁŠ R. - KUBÁTOVÁ H.: Dependability Computation for Fault Tolerant Reconfigurable Duplex System. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 100-102. ISBN 1-4244-0184-4.
KUBALÍK P. - DOBIÁŠ R. - KUBÁTOVÁ H.: Dependable Design for FPGA based on Duplex System and Reconfiguration. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 139-145. ISBN 0-7695-2609-8.
KUBALÍK P. - FIŠER P. - KUBÁTOVÁ H.: Fault Tolerant System Design Method Based on Self-Checking Circuits. In Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2006, p. 185-186. ISBN 0-7695-2620-9. DOI: 10.1109/IOLTS.2006.37
KUBALÍK P. - KUBÁTOVÁ H.: Design Methodology for High Reliable System. In Proceedings of the Seventh International Scientific Conference on Electronic Computers and Informatics ECI 2006. Košice: Technická univerzita v Košiciach, 2006, vol. 1, p. 274-279. ISBN 80-8073-598-0.
KUBÁTOVÁ H.: Teaching Principles of Petri Nets in Hardware Courses and Student's Projects. In Workshop on Teching Concurrency. Lisboa: University of Lisbon, 2006, p. 61-75.
KVASNIČKA J.: Vliv poruch v bitsreamu na funkci obvodů v FPGA. In Počítačové architektúry a diagnostika. Bratislava: Ústav informatiky SAV, 2006, s. 89-94. ISBN 80-969202-2-7.
NOVÁK O. - PLÍVA Z.: Scan Based Circuits with Low Power Consumption. In Proceedings of the IEEE East-West Design & Test International Workshop. Kharkov: Kharkov Institute of Physics and Technology, 2006, vol. 1, p. 206-211. ISBN 966-659-124-3.
NOVÁK O. - PLÍVA Z. - JENÍČEK J. - MADER Z. - JARKOVSKÝ M.: Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems. Los Alamitos: IEEE Computer Society, 2006, vol. 1, p. 300-308. ISBN 0-7695-2706-X.
NOVOTNÝ M. - SCHMIDT J.: Normal Basis Multipliers of General Digit Width Applicable in ECC. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 145-146. ISBN 1-4244-0184-4.
NOVOTNÝ M. - SCHMIDT J.: General Digit Width Normal Basis Multipliers with Circular and Linear Structure. In International Conference on Field Programmable Logic and Applications. Piscataway: IEEE, 2006, p. 873-876. ISBN 1-4244-0312-X.
NOVOTNÝ M. - SCHMIDT J.: Two Architectures of a General Digit-Serial Normal Basis Multiplier. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 550-553. ISBN 0-7695-2609-8.
ŠŤÁVA M.: A Backtracing Unit Implemented in FPGA. In POSTER 2006. Prague: CTU, 2006.
ŠŤÁVA M. - NOVÁK O.: An Illustrative Case Study of Backward Determination of Input Vectors by HW. In Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems. Ostrava: MARQ, 2006, vol. 1, p. 253-258. ISBN 80-86840-21-2.
ŠŤÁVA M. - NOVÁK O.: Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 251-256. ISBN 0-7695-2609-8.
ŠŤÁVA M. - NOVÁK O.: Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process. In Proceedings of the 2006 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics. Piscataway: IEEE, 2006, vol. 2, p. 59-64. ISBN 1-4244-0360-X.
ŠŤÁVA M. - NOVÁK O.: A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation. In Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems. Ostrava: MARQ, 2006, vol. 1, p. 51-57. ISBN 80-86840-21-2.
ŠŤÁVA M. - NOVÁK O.: HW Implementation of the Backtrace Algorithm. In IEEE European Test Symposium Informal Digest of Papers. Southampton: University of Southampton, 2006, vol. 1, p. 75-80.
ŠŤÁVA M. - NOVÁK O.: HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 250-252. ISBN 1-4244-0184-4.
ŠŤÁVA M. - NOVÁK O.: Implementation of the Backtrace Algorithm in an FPGA. In Proceedings of Workshop 2006. Prague: CTU, 2006, p. 256-257. ISBN 80-01-03439-9.

2005

BEČVÁŘ M. - ŠTUKJUNGER P.: Fixed-Point Arithmetic in FPGA. Acta Polytechnica. 2005, vol. 45, no. 2, p. 67-72. ISSN 1210-2709.
DOBIÁŠ R.: Fail-Safe System Design. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 33-38. ISBN 80-01-03298-1.
DOBIÁŠ R. - KUBÁTOVÁ H.: The Reliability and Safety Modelling for Safety Critical Application. In Proceedings of Workshop 2005 - Part A,B. Prague: CTU, 2005, vol. 9, p. 218-219. ISBN 80-01-03201-9.
DOBIÁŠ R. - KUBALÍK P. - KUBÁTOVÁ H.: Dependability Computations for Fault-Tolerant System Based on FPGA. In Proceedings of the 12th International Conferrence on Electronics, Circuits and Systems. Monterey: IEEE Circuits and Systems Society, 2005, vol. 1, p. 377-380. ISBN 9973-61-100-4. [pdf]
DOBIÁŠ R. - KUBÁTOVÁ H.: The Common 2oo2 Safety Model for Signalling and Interlocking Equipments. In Electronic Circuits and Systems Conference. Bratislava: FEI, Slovak University of Technology, 2005, p. 81-84.
DOBIÁŠ R. - KUBÁTOVÁ H.: Fail-Safe System Architectures. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 47-48. ISBN 3-902457-09-0.
FARAN A. - MLNAŘÍK K., SRB S. - BUKAČ P. - DOBIÁŠ R.: Způsob bezpečného vyhodnocování volnosti kolejového úseku s ohledem na zvýšení odolnosti proti rušivým vlivům a zapojení kolejového obvodu k provádění tohoto způsobu (Patent), 2005, Patent Úřad průmyslového vlastnictví, 296242. 2005-12-20.
FIŠER P.: Mixed-Mode BIST Based on Column Matching. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 45-50. ISBN 80-01-03298-1.
FIŠER P. - KUBÁTOVÁ H.: Pseudorandom Testability - Study of the Effect of the Generator Type. Acta Polytechnica. 2005, vol. 45, no. 2, p. 47-54. ISSN 1210-2709.
FIŠER P. - KUBÁTOVÁ H.: Output Grouping-Based Decomposition of Logic Functions. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 137-144. ISBN 963-9364-48-7. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST. In Proceedings Eighth EUROMICRO Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005, p. 56-63. ISBN 0-7695-2433-8. DOI: 10.1109/DSD.2005.51
KAFKA L. - KUBALÍK P. - KUBÁTOVÁ H. - NOVÁK O.: Fault Classification for Self-checking Circuits Implemented in FPGA. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 228-231. ISBN 963-9364-48-7. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 13-14. ISBN 3-902457-09-0. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: Highly Reliable Design Based on TSC Circuits. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 101-106. ISBN 80-01-03298-1.
KUBALÍK P. - KUBÁTOVÁ H.: Parity Codes Used for On-line Testing in FPGA. Acta Polytechnica. 2005, vol. 45, no. 6, p. 53-59. ISSN 1210-2709.
KUBÁTOVÁ H.: Modeling by Petri Nets . Acta Polytechnica. 2005, vol. 45, no. 2, p. 5-13. ISSN 1210-2709.
KUBÁTOVÁ H.: Finite State Machine Implementation in FPGAs. In Design of Embedded Control Systems. New York: Springer, 2005, p. 175-184. ISBN 0-387-23630-9.
KUBÁTOVÁ H. - NOVOTNÝ M.: Contemporary Methods of Digital Design Education. In Electronic Circuits and Systems Conference. Bratislava: FEI, Slovak University of Technology, 2005, p. 115-118. [pdf]
MAREK T. - PLUHÁČEK A.: Multiplier Execution Latency Reduction Using Variable Latency Pipeline. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 13-14. ISBN 3-902457-09-0.
NOVÁK O.: Self-test in logic blocks, In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, s. 268. ISBN 963 9364 48 7.
NOVÁK O. - GRAMATOVÁ E. - UBAR R. - PLÍVA Z. - PLESKACZ W. - MOSIN S. - STOPJAKOVÁ V. - HLAWICZKA A. - GARBOLINO T. - GUCZWA K. - FIŠEROVÁ M. - PLEŠTIL A. - KOTÁSEK Z. - DRÁBEK V.: Handbook of Electronic Testing. 1. ed. Praha: Vydavatelství ČVUT, 2005. 405 p. ISBN 80-01-03318-X.
NOVÁK O. - GRAMATOVÁ E. - UBAR R.: IST project REASON - Handbook of Testing Electronic Systems, 2005, In EDCC-5 Suplementary volume. Budapest: Technical University, 2005, s. 15-18.
NOVÁK O. - MADER Z.: SOC Diagnostic System Using the RESPIN Architecture. In Proceedings of the IFIP International Conference on Very Large Scale Integration System-onChip. Perth: Curtin University of Technology, 2005, vol. 1, p. 344-349. ISBN 0-7298-0610-3.
NOVÁK O. - ZAHRÁDKA J.: Test Pattern Compression for Circuits with the RESPIN Architecture. In IEEE European Test Symposium Informal Digest of Papers. Tallinn: Tallinn Technical University, 2005, vol. 1, p. 141-146.
NOVOTNÝ M. - SCHMIDT J.: General Digit-Serial Normal Basis Multiplier. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 99-104. ISBN 963-9364-48-7.
PROX J. - DOUŠA J.: SIMNET: Computer Network Simulator. In Proceedings of XXVII International Autumn Colloquium. Ostrava: MARQ, 2005, p. 132-137. ISBN 80-86840-16-6.
SCHMIDT J.: Investigation of Cellular Automata for Diagnostic Purposes. In Proceedings of Workshop 2005. Prague: CTU, 2005, ISBN 80-01-03201-9.
SCHMIDT J. - NOVOTNÝ M.: Scalable Normal Basis Aritmetic Unit for Elliptic Curve Cryptography. Acta Polytechnica. 2005, vol. 45, no. 2, p. 55-60. ISSN 1210-2709.
ŠŤÁVA M. - NOVÁK O.: Zpětné odvození vstupních vektorů kombinačního obvodu ze znalosti výstupních vektorů pomocí HW. In Počítačové architektury & diagnostika. Praha: ČVUT FEL, Katedra počítačů, 2005, díl 1, s. 153-158. ISBN 80-01-03298-1.
ŠŤÁVA M. - NOVÁK O.: How to Use the Reconfiguration at the Backtrace Implemented in an FPGA. In Sborník příspěvků konference Vršov 2005. Brno: VUT v Brně, FEKT, 2005, p. 168-171. ISBN 80-214-3008-7.
ŠŤÁVA M. - NOVÁK O.: Zpětná logická simulace pro odvození vstupních vektorů kombinačního obvodu pomocí HW. In Proceedings of XXVII International Autumn Colloquium. Ostrava: MARQ, 2005, s. 215-220. ISBN 80-86840-16-6.
ULRICH J. - DOUŠA J.: SIMCP_PAR2: Event Oriented Parallel and Pseudo-Parallel Simulator. In Simulation Almanac 2005. Praha: Ediční středisko ČVUT, 2005, p. 132-141. ISBN 80-01-03322-8.

2004

DOBIÁŠ R.: Stanovení spolehlivosti a bezpečnosti pro systémy odolné a bezpečné proti poruše. In Počítačové architektúry a diagnostika. Bratislava: Ústav informatiky SAV, 2004, s. 16-21. ISBN 80-969202-0-0.
DOBIÁŠ R. - GRILLINGER P. - RACEK S.: Using Markov Models for Evaluation of Single Event Upset in TTP/C Systems. In Proceedings of IFAC Workshop on Programmable Devices and Systems. Gliwice: Silesian Technical University, 2004, p. 100-104. ISBN 83-908409-8-7.
DOBIÁŠ R. - KUBÁTOVÁ H.: FPGA Based Design of Raiway's Interlocking Equipment. In EUROMICRO Symposium on Digital System Design. Piscataway: IEEE, 2004, p. 467-473. ISBN 0-7695-2203-3. [pdf]
DOBIÁŠ R. - KUBÁTOVÁ H.: Reliability Characteristic's Computations for Railway Crossing Interlocking Equipment. In Proceedings of Workshop 2004. Prague: CTU, 2004, vol. A, p. 228-229. ISBN 80-01-02945-X.
DOUŠA J. - ULRICH J.: Parallel Strategies and Simulation. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 347-352. ISBN 80-8073-150-0.
DOUŠA J. - VŠETEČKA J.: Parallel and Process Oriented Simulation System. In Proceedings of 38th International Conference MOSIS '04. Ostrava: MARQ, 2004, p. 21-27. ISBN 80-85988-98-4.
FIŠER P. - KUBÁTOVÁ H.: An Efficient Mixed-Mode BIST Technique. In DDECS - Proceedings of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Stará Lesná: Institute of Informatics, Slovak Akademy of Sciences, Bratislava, 2004, p. 227-230. ISBN 80-969117-9-1. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Two-Level Boolean Minimizer BOOM-II. In Boolean Problems - 6th International Workshop. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2004, p. 221-228. ISBN 3-86012-233-9. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST. In Proceedings of the 9th Biennial Baltic Electronics Conference. Tallinn: Tallinn Technical University, 2004, p. 201-204. ISBN 9985-59-462-2. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Boolean Minimizer FC-Min: Coverage Finding Process. In EUROMICRO Symposium on Digital System Design. Piscataway: IEEE, 2004, p. 152-159. ISBN 0-7695-2203-3. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Pseudorandom Testability - Study of the Effect of the Generator Type. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 200-205. ISBN 80-8073-150-0. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Survey of the Algorithms in the Column-Matching BIST Method. In 10th IEEE International On-Line Testing Symposium - IOLTS 2004. Piscataway: IEEE, 2004, p. 181. ISBN 0-7695-2180-0. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Single-Level Partitioning Support in BOOM-II. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 149-154. ISBN 83-89712-15-6. [pdf]
KUBALÍK P. - FIŠER P. - KUBÁTOVÁ H.: Minimization of the Hamming Code Generator in Self Checking Circuits. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 161-166. ISBN 83-89712-15-6. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: High Reliable FPGA Based System Design Methodology. In Work in Progress Session of 30th EUROMICRO and DSD 2004. Linz: Universität Linz, 2004, p. 30-31. ISBN 3-902457-05-8. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: On-line Testing for FPGA. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 194-199. ISBN 80-8073-150-0. [pdf]
KUBÁTOVÁ H.: Direct Implementation of Petri Net Based model in FPGA. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 31-36. ISBN 83-89712-15-6. [pdf]
KUNEŠ M. - KUBÁTOVÁ H. - DANĚK M.: Partitioning Problem in HW/SW Codesign. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 206-211. ISBN 80-8073-150-0.
MAREK T. - NOVOTNÝ M. - CRHA L.: Design and Implementation of the Memory Scheduler for the PC-Based Router, 2004, In Field Programmable Logic and Applications - FPL2004. Berlin: Springer, 2004, s. 1133-1135. ISBN 3-540-22989-2.
NOVOTNÝ M.: Scalable Normal Basis Multipliers. In Počítačové architektúry a diagnostika. Bratislava: Ústav informatiky SAV, 2004, p. 7-12. ISBN 80-969202-0-0.
NOVOTNÝ M. - SCHMIDT J.: The Finite State Machine in Fairy Tale World. In Workshop 2004. Prague: CTU, 2004, vol. A, p. 310-311. ISBN 80-01-02945-X.
NOVOTNÝ M. - SCHMIDT J.: Optimization of Shifter in Normal Basis Arithmetic Unit. In Workshop 2004. Prague: CTU, 2004, vol. A, p. 326-327. ISBN 80-01-02945-X.
NOVOTNÝ M. - SCHMIDT J.: Cryptographic Hardware Scalable Aritmetic Unit. In Workshop 2004. Prague: CTU, 2004, vol. A, p. 324-325. ISBN 80-01-02945-X.
PLUHÁČEK A.: Korobovův kód a návrh čítačů. In Informatika a informačné technológie 2004. Banská Bystrica: Univerzita Mateja Bela, 2004, s. 136-141. ISBN 80-8083-017-7.
SCHMIDT J. - NOVOTNÝ M.: Scalable Shifter Synthesis for a Finite Field Arithmetic Unit. In DDECS - Proceedings of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Stará Lesná: Institute of Informatics, Slovak Akademy of Sciences, Bratislava, 2004, p. 195-198. ISBN 80-969117-9-1.
ULRICH J. - DOUŠA J.: Virtual Processor for Event Oriented Optimistic Parallel Simulation. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 253-258. ISBN 80-8073-150-0.

2003

BEČVÁŘ M. - PLUHÁČEK A. - DANĚČEK J.: DOP - a CPU Core for Teaching Basics of Computer Architecture, 2003, In Proceedings of the Workshop on Computer Architecture Education (WCAE 2003). New York: ACM, 2003, s. 14-21.
BEČVÁŘ M. - PLUHÁČEK A. - DANĚČEK J.: DOP - A Simple Processor Core for Educational Purposes, 2003, In Programmable Devices and Systems 2003. Oxford: Elsevier Science, 2003, vol. 1, s. 208-213. ISBN 0-08-044130-0.
BEČVÁŘ M.: Optimization of Simple CPU Core for FPGA. In Proceedings of Workshop 2003 (online). Prague: CTU, 2003, vol. A, p. 354-355. ISBN 80-01-02708-2.
DANĚK M. - KUBÁTOVÁ H. - MUZIKÁŘ Z.: Evolutionary Techniques in Physical Design for FPGAs. In Proceedings of Workshop 2003. Prague: CTU, 2003, vol. A, p. 306-307. ISBN 80-01-02708-2.
FIŠER P. - HLAVIČKA J.: BOOM - A Heuristic Boolean Minimizer, 2003, Computing and Informatics. 2003, vol. 22, no. 1, s. 19-51. ISSN 1335-9150.
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: CD-A Based BIST Method, 2003, In ECMS 2003. Liberec: Technical University, 2003, s. 279-283. ISBN 80-7083-708-X. [pdf]
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: Column-Matching BIST Exploiting Test Don't-Cares, 2003, In ETW 2003. Maastricht: IEEE Computer Society TTTC, 2003, s. 215-216. ISBN 0-7695-1908-3. [pdf]
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: Coverage-Directed Assignment Approach to BIST, 2003, In Proceedings of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Poznaň: University of Technology, 2003, s. 87-92. ISBN 83-7143-557-6. [pdf]
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: FC-Min: A Fast Multi-Output Boolean Minimizer, 2003, In DSD 2003 - EUROMICRO Symposium on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2003, s. 451-454. ISBN 0-7695-2003-0. [pdf]
FIŠER P. - HLAVIČKA J.: A Flexible Minimization and Partitioning Method. In Proceedings of Workshop 2003 (online). Prague: CTU, 2003, vol. A, p. 312-313. ISBN 80-01-02708-2.
KUBALÍK P. - KUBÁTOVÁ H.: Design of Self Checking Circuits Based on FPGA, 2003, In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, s. 378-381. ISBN 977-05-2010-1. [pdf]
KUBALÍK P. - BUČEK J.: FPGA Implementation of USB 1.1 Device Core. In Poster 2003. Prague: CTU, Faculty of Electrical Engineering, 2003, p. IC22.
KUBÁTOVÁ H.: Direct Hardware Implementation of Petri Net Based Model, 2003, In Proceedings of the Work in Progress Session of EUROMICRO 2003. Linz: J. Kepler University - FAW, 2003, s. 56-57. ISBN 3-902457-21-X.
KUBÁTOVÁ H.: Petri Net Models in Hardware, 2003, In ECMS 2003. Liberec: Technical University, 2003, s. 158-162. ISBN 80-7083-708-X.
KUBÁTOVÁ H. - HLAVIČKA J., RACEK S., KOLÁŘ J.: Fault Injection for Time Triggered Architecture (FIT). In Proceedings of Workshop 2003. Prague: CTU, 2003, vol. A, p. 352-353. ISBN 80-01-02708-2.
SCHMIDT J. - NOVOTNÝ M.: Normal Basis Multiplication and Inversion Unit for Elliptic Curve Cryptography, 2003, In Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2003, s. 82-85. ISBN 0-7803-8163-7.
SCHMIDT J. - NOVOTNÝ M.: Optimum Shifter Synthesis Using a Genetic Algorithm, 2003, In Recent Trends in Multimedia Information Processing. Praha: Sdělovací technika, 2003, vol. 1, s. 146-149. ISBN 80-86645-05-3.
SCHMIDT J. - NOVOTNÝ M.: Scalable Multiplication and Inversion Unit for ECDSA, 2003, In Programmable Devices and Systems 2003. Oxford: Elsevier Science, 2003, vol. 1, s. 226-231. ISBN 0-08-044130-0.
SCHMIDT J. - NOVOTNÝ M.: Exploration of Design Space in ECDSA. In Proceedings of Workshop 2003. Prague: CTU, 2003, vol. A, p. 318-320. ISBN 80-01-02708-2.

2002

DANĚK M. - MUZIKÁŘ Z.: Integrated Iterative Approach to FPGA Placement. In Field-Programmable Logic and Applications - FPL2002. Berlin: Springer, 2002, p. 253-262. ISBN 3-540-44108-5.
DANĚK M. - MUZIKÁŘ Z.: Integrated Timing-Driven Approach to the FPGA Layout. In The 9th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2002, p. 693-696. ISBN 0-7803-7596-3.
DOUŠA J.: Thread Oriented Discrete Event Simulation System. In Proceedings of the Fifth International Scientific Conference - Electronic Computers and Informatics 2002. Košice: Vienala, 2002, p. 216-220. ISBN 80-7099-879-2.
FIŠER P. - HLAVIČKA J.: A Flexible Minimization and Partitioning Method. In 5th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2002, p. 83-90. ISBN 3-86012-180-4. [pdf]
FIŠER P. - HLAVIČKA J.: A Set of Logic Design Benchmarks. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, p. 324-327. ISBN 80-214-2094-4. [pdf]
FIŠER P. - HLAVIČKA J.: Column-Matching Based BIST Design Method. In ETW'02 - 7th IEEE European Test Workshop. Athens: University of Athens, 2002, p. 15-16. [pdf]
HLAVIČKA J. - FIŠER P.: Minimization and Partitioning Method Reducing Input Sets. In The First IEEE International Workshop on Electronic Design, Test, and Applications 2002. Los Alamitos: IEEE Computer Society Press, 2002, p. 434-436. ISBN 0-7695-1453-7. [pdf]
JÁCHIM M. - JÄGER M. - BEČVÁŘ M.: Elliptic Coprocessor GF(2^162]. In POSTER 2002 - Book of Extended Abstracts. Prague: CTU, Faculty of Electrical Engineering, 2002, p. IC24.
JÁCHIM M. - JÄGER M. - BEČVÁŘ M.: Tuning up the PCI Devices. In POSTER 2002 - Book of Extended Abstracts. Prague: CTU, Faculty of Electrical Engineering, 2002, p. IC25.
KUBÁTOVÁ H. - JELINEK R.: Digital Testing and Reliability Education (DTRE) Computer Tool. In The 9th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2002, p. 1227-1230. ISBN 0-7803-7596-3.
KUBÁTOVÁ H.: DTRE - Digital Testing and Reliability Education Tool. In Proceedings of the Fifth International Scientific Conference - Electronic Computers and Informatics 2002. Košice: Vienala, 2002, p. 148-153. ISBN 80-7099-879-2.
KUBÁTOVÁ H. - BEČVÁŘ M.: FEL-Code: FSM Internal State Encoding Method. In 5th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2002, p. 109-114. ISBN 3-86012-180-4.
KUBÁTOVÁ H.: How to Obtain Better Implementation of FSM in FPGA. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, p. 332-335. ISBN 80-214-2094-4.
SCHMIDT J. - NOVOTNÝ M. - JÄGER M. - BEČVÁŘ M. - JÁCHIM M.: Comparison of the Polynomial and Optimal Normal Basis ECDSA for GF(2^162). In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, p. 150-157. ISBN 80-214-2094-4.
SCHMIDT J. - NOVOTNÝ M. - JÄGER M. - BEČVÁŘ M. - JÁCHIM M.: Exploration of Design Space in ECDSA. In Field-Programmable Logic and Applications - FPL2002. Berlin: Springer, 2002, p. 1072-1075. ISBN 3-540-44108-5.

2001

BEČVÁŘ M. - JÁCHIM M. - JÄGER M.: Case Study: FPGA Acceleration of CRC Computation. In IFAC Workshop on Programmable Devices and Systems PDS2001. Gliwice: IESUT, 2001, p. 218-223.
BEČVÁŘ M. - SCHMIDT J.: Reconfigurable Acceleration of Intel PC: A Quantitative Analysis. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Gyor: Széchenyi István University of Applied Sciences, 2001, p. 93-96. ISBN 963-7175-16-4.
DANĚČEK J.: Programovací systém MiniJava. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, s. 162-168. ISBN 80-7099-705-2.
ELSHAFEY K. - SCHMIDT J. - HLAVIČKA J.: Design and Analysis of a Suitable Serial Approach to CORDIC Magnitude Processor in an FPGA. In Poster 2001. Prague: CTU, Faculty of Electrical Engineering, 2001, p. IC9.
ELSHAFEY K. - HLAVIČKA J. - SCHMIDT J.: A Comparison of Serial and Parallel Approaches to FPGA Implementations of Arithmetic Functions. In Proceedings of Workshop 2001. Prague: CTU, 2001, vol. A, p. 202-203. ISBN 80-01-02335-4.
FIŠER P. - HLAVIČKA J.: Implicant Expansion Methods Used in the Boom Minimizer. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Gyor: Széchenyi István University of Applied Sciences, 2001, p. 291-298. ISBN 963-7175-16-4. [pdf]
FIŠER P., HLAVIČKA J., FIŠER P. - HLAVIČKA J.: On the Use of Mutations in Boolean Minimization. In EUROMICRO Symposium on Digital Systems Design. Los Alamitos: IEEE Computer Society Press, 001, p. 300-307. ISBN 0-7695-1239-9. [pdf]
HLAVIČKA J. - FIŠER P.: A Heuristic Method of Two-Level Logic Synthesis. In World Multiconference on Systemics, Cybernetics and Informatics. Orlando: IIIS - International Institute of Informatics and Systemics, 2001, vol. 2, p. 283-288. ISBN 980-07-7552-8. [pdf]
HLAVIČKA J. - FIŠER P.: BOOM - a Heuristic Boolean Minimizer. In IEEE/ACM International Conference on CAD-01. Monterey: IEEE Circuits and Systems Society, 2001, p. 439-442. ISBN 0-7803-7247-6. [pdf]
JÁCHIM M. - SCHMIDT J.: Speeding up the SDRAM Controller Macro-block. In International Conference Applied Electronics 2001. Pilsen: University of West Bohemia, 2001, p. 126-129. ISBN 80-7082-758-0.
KUBÁTOVÁ H.: Hardware Implementation and Simulation of Petri Nets. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, p. 103-106. ISBN 80-7099-705-2.
KUBÁTOVÁ H.: Implementation of the FSM into FPGA. In Proceedings of the International Workshop on Discrete-Event System Design. Zielona Góra: Oficyna Wydawnicza Politechniki Zielonogórskiej, 2001, p. 141-146. ISBN 83-85911-62-6.
KUBÁTOVÁ H.: Optimal Implementation of FSM in FPGA. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, p. 107-110. ISBN 80-7099-705-2.
KUBÁTOVÁ H.: Petri Net Simulation Using FPGA. In Proceedings of XXIIIrd International Autumn Colloquium. Ostrava: MARQ, 2001, p. 129-134. ISBN 80-85988-61-5.
PLUHÁČEK A. - DOUŠA J. - DANĚČEK J. - BEČVÁŘ M.: Návrh procesorů ve výuce. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, s. 152-156. ISBN 80-7099-705-2.

2000

BEČVÁŘ M.: Advantage of using FPGA for Implemntation of Interfaces in the VoN Applications, 2000, In Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: POLYGRAFIA SAV, 2000, p. 178-181. ISBN 80-968320-3-4.
FIŠER P. - HLAVIČKA J.: Efficient Minimization Method for Incompletely Defined Boolean Functions, 2000, In 4th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2000, p. 91-98. ISBN 3-86012-124-3. [pdf]
HLAVIČKA J. - FIŠER P.: Algorithm for Minimization of Partial Boolean Functions, 2000, In Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: POLYGRAFIA SAV, 2000, p. 130-133. ISBN 80-968320-3-4.
KOLÁŘ J. - MÜLLER K. - PLUHÁČEK A.: Structured Study and CS&E Curriculum at the Faculty of Electrical Engineering, CTU Prague, 2000, In Proceedings of the Computer Science Education Workshop. Prague: CTU, 2000, p. 38-41. ISBN 80-01-02264-1.
KUBÁTOVÁ H. - ANDRLE J.: Predikce průběhu EKG pomocí neuronové sítě, 2000, In Modelling and Simulation of Systems - Modelling in Manager Work. Ostrava: MARQ, 2000, p. 167-172. ISBN 80-85988-46-1.
KUBÁTOVÁ H., HRDÝ T.: PROKEŠ M., State Encoding of the FSM with the Relation to its Implementation by FPGA, 2000, In Proceedings of the Fourth International Scientific Conference Electronic Computers and Informatics 2000. Košice: TU Košice, FEI, 2000, p. 183-188. ISBN 80-88922-25-9.
NOVÁK O. - HLAVIČKA J.: An Efficient Deterministic Test Pattern Compaction Scheme using Modified IC Scan Chain, 2000, In ETW 2000 - IEEE European Test Workshop. Lisboa: INESC-ID, 2000, p. 305-306.
PLUHÁČEK A.: A Simple Way to Evaluate Logarithms, 2000, In Proceedings of the Fourth International Scientific Conference Electronic Computers and Informatics 2000. Košice: TU Košice, FEI, 2000, p. 62-67. ISBN 80-88922-25-9.

1999

DANĚČEK J. - ROZEHNAL Z.: New Language for Programmable Control Logic. In Proceedings of the 4th International Workshop on ECMS'99. Liberec: Technical University, 1999, p. 80-83. ISBN 80-7083-339-4.
DANĚČEK J. - SLAVÍK P.: Teaching Java at CTU Prague. In Proceedings of Java in Computing Curriculum 3. London: South Bank University, 1999, p. 1-7.
DANĚK M. - MUZIKÁŘ Z.: Global Routing Models. In Field-Programmable Logic and Applications. Berlin: Springer, 1999, p. 391-395. ISBN 3-540-66457-2.
DOUŠA J. - HOLUB A.: Performance Simulation of Local Area Networks. In Proceedings of the First International Conference on Advanced Engineering Design. Prague: CTU, 1999, p. 144-152. ISBN 80-01-02055-X.
KUBÁTOVÁ H.: Hardware Implementation of Petri Nets. In MOSIS'99, Proceedings of the 33rd International Conference "Modelling and Simulation of Systems". Ostrava: MARQ, 1999, p. 87-92. ISBN 80-85988-32-1.
KUBÁTOVÁ H. - RYDLO P.: Model of Computer Network with Router Using Design/CPN. In Proceedings of XXIst International Colloquium ASIS 1999. Ostrava: MARQ, 1999, p. 191-196. ISBN 80-85988-41-0.
PLUHÁČEK A.: Geographic Addressing Using the m-out-of-n Codes. In I & IT - Informatika a informačné technológie. Banská Bystrica: Univerzita Mateja Bela v Banskej Bystrici, Fakulta prírodných vied, 1999, p. 83-88. ISBN 80-8055-335-1.

1998

KUBÁTOVÁ H.: Petri Nets in Hardware Design. In Proceedings of the 32nd International Conference MOSIS98. Ostrava: VSB-TUO, Department of Computer Science of FEI, 1998, p. 249-254. ISBN 80-85988-24-0.
KUBÁTOVÁ H. - RYDLO P.: Design/CPN in System Modelling and Design. In Advanced Simulation of Systems ASIS 1998. Ostrava: VSB-TUO, Department of Computer Science of FEI, 1998, p. 39-44. ISBN 80-85988-26-7.
NOVÁK O. - HLAVIČKA J.: Design of a Cellular Automaton for Efficient Test Pattern Generation. In IEEE European Test Workshop. Barcelona: Publications d'Abast, 1998, p. 30-31.

1997

DANĚČEK J.: Dejte inteligenci svým www stránkám. 1. vyd. Praha: PROFESS, 1997. 154 s. ISBN 80-85235-50-1.
DABROWSKA-WOLAK J. - DRAHOZAL R. - MUZIKÁŘ Z. - SERVÍT M.: Integrated Timing-Driven Layout in an FPGA Environment. In DMMS'97 Proceedings. Budapest: PANEM, 1997, p. 203-212. ISBN 963-545-183-0.

1996

DOUŠA J.: Educational Simulation System. In MOSIS'96. Ostrava: MARQ, 1996, vol. 1, p. 199-204. ISBN 80-85988-02-X.
HLAVIČKA J. - NOVÁK O.: Enhancing Pseudoexhaustive Test Set Quality by Code Bit Inversions. In Proceedings of IEEE European Test Workshop. Montpellier: IEEE Computer Society - TC on Test Technology, 1996, p. 70-74.

1995

DOUŠA J. - BENKOVSKÝ J.: Digital Circuit Simulation in C++. In System Modelling Control. Lodz: Polish Society of Medical Informatics, 1995, p. 235-239. ISBN 83-902115-2-1.
DRÁPAL F. - DANĚČEK J. - PLUHÁČEK A. - SERVÍT M.: Implementation of a General-Purpose Processor Macro. In Proceedings of Workshop on Design Methodologies for Microelectronics. Bratislava: Slovak Academy of Sciences, Institute of Computer Systems, 1995, p. 89-97.
NOVÁK O. - HLAVIČKA J.: Enhancing Fault Coverage of Pseudoexhaustive Test Sets. In Proceedings of 1st IEEE International On-line testing Workshop. Montpellier: IEEE Computer Society - TC on Test Technology, 1995, p. 173-177.
SEVINC S. - BAGDE K. - RICHARDSON D. - RYAN P. - KUBÁTOVÁ H.: Visual and Interactive Modelling of Mine Warfare. In Computer Science. Ostrava: VSB-TUO, 1995, p. 173-178. ISBN 80-901751-7-1.

1994

DANĚČEK J. - PLUHÁČEK A. - DRÁPAL F. - SALČIČ Z. - SERVÍT M.: DOP - A Simple Processor for Custom Computing Machines. Journal of Microcomputer Applications. 1994, vol. 17, no. 11, p. 239-253. ISSN 0745-7138.
DANĚČEK J. - PLUHÁČEK A. - SERVÍT M.: The Architecture of a General-Purpose Processor Cell. In Field-Programmable Logic - Architectures, Synthesis, Applications. Berlin: Springer, 1994, p. 321-325. ISBN 3-540-58419-6.
SERVÍT M. - MUZIKÁŘ Z.: Integrated Layout Synthesis for FPGAS. In Field-Programmable Logic - Architectures, Synthesis, Applications. Berlin: Springer, 1994, p. 23-33. ISBN 3-540-58419-6.

1993

SCHMIDT J.: Generalized Referents: A Neat Interface for the Scruffy Work. In Proceedings of the 1st International Conference on Conceptual Structures. Quebec: Universite Laval, 1993, p. 1-16.

Publications

2021

BALIHAR, T. and M. NOVOTNÝ. Influence of Synthesis Parameters on Vulnerability to Side-Channel Attacks. In: Proceedings of the 10th Mediterranean Conference on Embedded Computing (MECO'2020), Budva, 2021-06-07/2021-06-10. p. 735-740. ISSN 2637-9511. ISBN 978-0-7381-3361-4. DOI 10.1109/MECO52532.2021.9460288
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Optically induced static power in combinational logic: Vulnerabilities and countermeasures. Microelectronics Reliability. 2021, 124. ISSN 0026-2714. DOI 10.1016/j.microrel.2021.114281
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Standard Cell Design For Data-Independent Static Power Under Illumination. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03, 2021. ISBN 978-80-01-06858-8. Available from: https://pesw.fit.cvut.cz/2021/index.php?page=Proceedings
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Zapojení standardní buňky CMOS se sníženou datovou závislostí statické spotřeby. Patent CZ 308895. 2021-06-30. Available from: https://isdv.upv.cz/doc/FullFiles/Patents/FullDocuments/308/308895.pdf
BOSIO, A., et al. Emerging Technologies: Challenges and Opportunities for Logic Synthesis. In: Proceedings of 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 2021-04-07/2021-04-09. 2021. p. 93-98. ISBN 978-1-6654-3595-6. DOI 10.1109/DDECS52668.2021.9417062
DAS, S., et al. Minimization of Switching Activity of Graphene Based Circuits. In: Proc. of the 34th International Conference on VLSI Design, Guwahati (virtual), 2021-02-20/2021-02-24, 2021. p. 139-144. ISSN 1063-9667. ISBN 978-1-6654-4087-5. DOI 10.1109/VLSID51830.2021.00029
HYNIOVÁ, K. A Design and Stand Tests of Real-time Vehicle Active Suspension. International scientific journal tran&MOTAUTO WORLD. 2021, (4), 116-119. ISSN 2367-8399.
HYNIOVÁ, K. A Design and Stand Tests of Real-timeVehicle Active Suspension. In: Proceedings of the VII International Scientific Congress "Innovations 21", Varna, 2021-06-21/2021-11-24. Sofia: Scientific-technical union of mechanical engineering, 2021. p. 32-36. vol. 1. ISSN 2603-3763.
KHUN, J. and J. SCHMIDT. Satisfiability Modulo Simulation: What Can It Do?. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03, 2021. p. 32-41. ISBN 978-80-01-06858-8.
LUXEMBURK, J., K. HYNEK, and T. ČEJKA. Detection of HTTPS Brute-Force Attacks with Packet-Level Feature Set. In: 11th Annual Computing and Communication Workshop and Conference (CCWC2021), Las Vegas, 2021-01-27/2021-01-30, 2021. p. 0115-0123. ISBN 978-0-7381-4394-1. DOI 10.1109/CCWC51732.2021.9375998. Available from: https://ieeexplore.ieee.org/document/9375998
MIŠKOVSKÝ, V., H. KUBÁTOVÁ, and M. NOVOTNÝ. Secure and dependable: Area-efficient masked and fault-tolerant architectures. In: Proceedings of the 2021 24th Euromicro Conference on Digital System Design, Palermo, 2021-09-01/2021-09-03, 2021. p. 333-338. ISBN 978-1-6654-2703-6. DOI 10.1109/DSD53832.2021.00057
ONDERKA, J. Fast fixed-point arithmetic in three-valued binary number abstraction. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03. 2021. p. 18. ISBN 978-80-01-06858-8. Available from: https://pesw.fit.cvut.cz/2021/PESW_2021.pdf
MICHAL ORSÁK, O. and T. BENEŠ. High-speed stateful packet classifier based on TSS algorithm optimized for off-chip memories. In: Proceedings of 24th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Vienna, 2021-04-07/2021-04-09, 2021. p. 151-156. ISBN 978-1-6654-3595-6. DOI 10.1109/DDECS52668.2021.9417060
POKORNÝ, D., P. SOCHA, and M. NOVOTNÝ. Side-channel attack on Rainbow post-quantum signature. In: Proceedings of the 2021 Design, Automation & Test in Europe (DATE) 2021, Grenoble, 2021-02-01/2021-02-05. p. 565-568. ISSN 1558-1101. ISBN 978-3-9819263-5-4. DOI 10.23919/DATE51398.2021.9474157. Available from: https://ieeexplore.ieee.org/document/9474157
SCHMIDT, J. and P. FIŠER. Nonlinear codes for test patterns compression: the old school way. In: Recent Findings in Boolean Techniques. Cham: Springer International Publishing AG, 2021. p. 125-142. 1. ISBN 978-3-030-68070-1. DOI 10.1007/978-3-030-68071-8_6
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. High-level synthesis, cryptography, and side-channel countermeasures: A comprehensive evaluation. Microprocessors and Microsystems. 2021, 85 1-13. ISSN 0141-9331. DOI 10.1016/j.micpro.2021.104311
SOUKUP, D., et al. Towards Evaluating Quality of Datasets for Network Traffic Domain. In: Proceedings of the 2021 17th International Conference on Network and Service Management, Izmir, 2021-10-25/2021-12-29. 2021. p. 264-268. ISSN 2165-963X. ISBN 978-3-903176-36-2. DOI 10.23919/CNSM52442.2021.9615601
TROPKOVÁ, Z., K. HYNEK, and T. ČEJKA. Novel HTTPS classifier driven by packet bursts, flows, and machine learning. In: Proceedings of the 2021 17th International Conference on Network and Service Management, Izmir, 2021-10-25/2021-12-29, 2021. p. 345-349. ISSN 2165-963X. ISBN 978-3-903176-36-2. DOI 10.23919/CNSM52442.2021.9615561
VEKSHIN, D., K. HYNEK, and T. ČEJKA. Brief Summary of Observations and Research on Encrypted DNS. In: Proceedings of the 9th Prague Embedded Systems Workshop, Horoměřice, 2021-07-01/2021-07-03, 2021. ISBN 978-80-01-06858-8. Available from: https://pesw.fit.cvut.cz/2021/index.php?page=Proceedings

2020

BARTÍK, M., T. BENEŠ, and P. KUBALÍK. An In-sight into How Compression Dictionary Architecture can Affect the Overall Performance in FPGAs. IEEE Access. 2020, 2020(8), 183101-183116. ISSN 2169-3536. DOI 10.1109/ACCESS.2020.3029691. Available from: https://ieeexplore.ieee.org/document/9217430
BARTÍK, M. Reverse Engineering of Arrow USB Programmer2 JTAG Adapter for Intel/Altera FPGAs. In: 2020 9th Mediterranean Conference on Embedded Computing (MECO), Budva, 2020-06-08/2020-06-11. 2020. ISSN 2637-9511. ISBN 978-1-7281-6949-1. DOI 10.1109/MECO49872.2020.9134358. Available from: https://ieeexplore.ieee.org/document/9134358
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Standard Cell Tuning Enables Data-Independent Static Power Consumption. In: Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2020), Novi Sad, 2020-04-22/2020-04-24. 2020. ISSN 2334-3133. ISBN 978-1-7281-9938-2. DOI 10.1109/DDECS50862.2020.9095656.
BENEŠ, T., et al. Pipelined ALU for effective external memory access in FPGA. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design. Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 97-100. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00026.
BENEŠ, T., T. ČEJKA, and H. KUBÁTOVÁ. The next step of P4 FPGA architectures: External Memories. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. p. 5-7. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
BORECKÝ, J., R. HÜLLE, and P. FIŠER. Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28, 2020. p. 684-691. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00111.
HULÁK, M. and T. ČEJKA. Classification of Network Traffic using Traffic Features. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. p. 17-18. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
HYNEK, K. and T. ČEJKA. Privacy Illusion: Beware of Unpadded DoH. In: 2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON), Vancouver, 2020-11-04/2020-11-07, Montreal, p. 621-628. ISSN 2644-3163. ISBN 978-1-7281-8416-6. DOI 10.1109/IEMCON51383.2020.9284864. Available from: https://ieeexplore.ieee.org/abstract/document/9284864
HYNEK, K., T. ČEJKA, and D. VEKSHIN. DoH detection: Discovering hidden DNS. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. p. 14-16. ISBN 978-80-01-06772-7. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
HYNEK, K., et al. Evaluating Bad Hosts Using Adaptive Blacklist Filter. In: Proceedings of the 9th Mediterranean Conference on Embedded Computing - MECO'2020, Budva, 2020-06-08/2020-06-11. 2020. ISSN 2637-9511. ISBN 978-1-7281-6949-1. DOI 10.1109/MECO49872.2020.9134244. Available from: https://ieeexplore.ieee.org/document/9134244
HYNEK, K., et al. Refined detection of SSH brute-force attackers using machine learning. In: 35th International Conference on ICT Systems Security and Privacy Protection, Maribor, 2020-09-21/2020-09-23. 2020. p. 49-63. IFIP Advances in Information and Communication Technology. vol. 580. ISSN 1868-4238. ISBN 978-3-030-58200-5. DOI 10.1007/978-3-030-58201-2_4.
HYNIOVÁ, K. On Electromagnetic Actuator Control in The Active Suspension Systems. International scientific journal tran&MOTAUTO WORLD. 2020, 2020(1), 6-9. ISSN 2367-8399.
HYNIOVÁ, K. On Electromagnetic Actuator Control in The Active Suspension Systems. In: Proceedings of the VI international Congress "INNOVATIONS 2020", Varna, 2020-06-22/2020-06-26. 2020. p. 98-100. vol. I. ISSN 2603-3763.
KLEMSA, J. and M. NOVOTNÝ. Exploiting Linearity in White-Box AES with Differential Computation Analysis. In: Proceedings of the 2020 Computing Conference, Volume 3. London, 2020-07-16/2020-07-17. p. 404-419. ISSN 2194-5365. ISBN 978-3-030-52243-8. DOI 10.1007/978-3-030-52243-8_29. Available from: https://link.springer.com/chapter/10.1007%2F978-3-030-52243-8_29
KLEMSA, J. and M. NOVOTNÝ. WTFHE: neural-netWork-ready Torus Fully Homomorphic Encryption. In: Proceedings of the 9th Mediterranean Conference on Embedded Computing - MECO'2020, Budva, 2020-06-08/2020-06-11. 2020. p. 1-5. ISSN 2637-9511. ISBN 978-1-7281-6949-1. DOI 10.1109/MECO49872.2020.9134331. Available from: https://ieeexplore.ieee.org/document/9134331
KOLÁRIK, T. and S. RATSCHAN. SAT Modulo Differential Equation Simulations. In: Tests and Proofs. 14th International Conference on Tests and Proofs, Bergen, 2020-06-23/2020-06-26, 2020. p. 80-99. ISSN 0302-9743. ISBN 978-3-030-50994-1. DOI 10.1007/978-3-030-50995-8_5.
LUXEMBURK, J. Detection of HTTPS brute-force attacks in high-speed computer networks. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
MOUCHA, P., S. JEŘÁBEK, and M. NOVOTNÝ. Novel Controller for Dummy Rounds Scheme DPA Countermeasure. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 281-284. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00053.
MOUCHA, P., S. JEŘÁBEK, and M. NOVOTNÝ. Novel Dummy Rounds Schemes as a DPA Countermeasure in PRESENT Cipher. In: Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS 2020), Novi Sad, 2020-04-22/2020-04-24. Piscataway, NJ: IEEE, 2020. p. 1-4. ISBN 978-1-7281-9938-2. DOI 10.1109/DDECS50862.2020.9095720.
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Non-Homogeneous Continuous Time Markov Chains Calculations. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 664-671. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00108.
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Non-homogeneous hierarchical Continuous Time Markov Chains. Microprocessors and Microsystems. 2020, 2020(78), ISSN 0141-9331. DOI 10.1016/j.micpro.2020.103206.
SCHMIDT, J. and P. FIŠER. Nonlinear codes for test patterns compression: the old school way. In: Proc. of 14th International Workshop on Boolean Problems, Bremen (virtual), 2020-09-24/2020-09-25. p. 1-16.
SOCHA, P. and M. NOVOTNÝ. Towards High-Level Synthesis of Polymorphic Side-Channel Countermeasures. In: Proceedings of the 23rd Euromicro Conference on Digital Systems Design, Virtual Event organized from Kranj, Slovenia, 2020-08-26/2020-08-28. 2020. p. 193-199. ISBN 978-1-7281-9535-3. DOI 10.1109/DSD51259.2020.00040.
SOCHA, P., et al. Side-channel countermeasures utilizing dynamic logic reconfiguration: Protecting AES/Rijndael and Serpent encryption in hardware. Microprocessors and Microsystems. 2020, 78 1-10. ISSN 0141-9331. DOI 10.1016/j.micpro.2020.103208.
SOUKUP, D., K. HYNEK, and T. ČEJKA. QoD: Ideas about Evaluating Quality of Datasets. In: Proceedings of the 8th Prague Embedded Systems Workshop, Praha, 2020. ISBN 978-80-01-06772-7. p. 8-9. Available from: https://pesw.fit.cvut.cz/2020/PESW_2020.pdf
SVATOŇ, J., et al. Novel Partial Correlation Method Algorithm for Acquisition of GNSS Tiered Signals. Navigation. 2020, 2020(9), 1-18. ISSN 2161-4296. DOI 10.1002/navi.390. Available from: https://onlinelibrary.wiley.com/doi/full/10.1002/navi.390
VEKSHIN, D., K. HYNEK, and T. ČEJKA. DoH Insight: Detecting DNS over HTTPS by Machine Learning. In: ARES '20: Proceedings of the 15th International Conference on Availability, Reliability and Security, Dublin, 2020-08-25/2020-08-28. 2020. p. 1-8. ISBN 978-1-4503-8833-7. DOI 10.1145/3407023.3409192. Available from: https://dl.acm.org/doi/abs/10.1145/3407023.3409192
SOUKUP, D., T. ČEJKA, and K. HYNEK. Behavior Anomaly Detection in IoT Networks. In: Proceeding of the International Conference on Computer Networks, Big Data and IoT (ICCBI - 2019). 2020. p. 465-473. Lecture Notes on Data Engineering and Communications Technologies. vol. 49. ISSN 2367-4520. ISBN 978-3-030-43192-1. DOI 10.1007/978-3-030-43192-1_53. Available from: https://www.springer.com/gp/book/9783030431914

2019

BARTÍK, M., T. BENEŠ, and K. HYNEK. An Example of PCB Reverse Engineering - Reconstruction of Digilent JTAG SMT3 Schematic. In: The 7th IEEE Workshop on Advances in Information, Electronic and Electrical Engineering. Liepaja, 2019-11-15/2019-11-16, IEEE, 2019. ISBN 978-1-7281-5709-2.
BARTÍK, M., T. BENEŠ, and P. KUBALÍK. Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms. In: The 9th IEEE Annual Computing and Communication Workshop and Conference (CCWC), Las Vegas, 2019-01-07/2019-01-09, IEEE, 2019. p. 732-738. ISBN 9781728105543. DOI 10.1109/CCWC.2019.8666521. Available from: https://ieeexplore.ieee.org/document/866652
M. BARTÍK and S. UBIK. System for Implementation of a Hash Table. United States. Patent US10262702. 2019-04-16. Available from: https://patents.google.com/patent/US10262702B2/en
BĚLOHOUBEK, J. Modulated CMOS Static Power is Data Dependendent and Observable. [Unpublished Lecture] Cryptarchi 2019. 2019-06-25.
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. Using Voters May Lead to Secret Leakage. In: Proceedings of the 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cluj-Napoca, 2019-04-24/2019-04-26, IEEE, 2019. p. 1-4. ISBN 978-1-7281-0073-9. DOI: 10.1109/DDECS.2019.8724663.
BĚLOHOUBEK, J., P. FIŠER, and J. SCHMIDT. CMOS Illumination Discloses Processed Data. In: Proceedings of the 22nd Euromicro Conference on Digital Systems Design, Kallithea, Chalkidiki, 2019-08-28/2019-08-30, IEEE Computer Soc., 2019. p. 381-388. ISBN 978-1-7281-2861-0. DOI: 10.1109/DSD.2019.00062.
BĚLOHOUBEK, J. and R. VIK. Low-Cost CMOS Power Consumption Data Dependence Demonstrator Concept. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/index.php?page=Proceedings
BENEŠ, T., M. BARTÍK, and P. KUBALÍK. High Throughput and Low Latency LZ4 Compressor on FPGA. In: 2019 International Conference on ReConFigurable Computing and FPGAs. Cancún, 2019-12-09/2019-12-11. Piscataway, NJ: IEEE, 2019. ISBN 978-1-7281-1957-1.
HAVRÁNEK, J., T. ČEJKA, and P. BENÁČEK. L7 capable flow exporter described in P4. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. p. 29-32. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf
HÜLLE, R., P. FIŠER, and J. SCHMIDT. PBO-Based Fault Selection for Compact Test Generation. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf
HYNEK, K., et al. Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks. In: The 9th IEEE Annual Computing and Communication Workshop and Conference (CCWC). Las Vegas, 2019-01-07/2019-01-09, 2019. p. 847-851. ISBN 9781728105543. DOI 10.1109/CCWC.2019.8666446. Available from: https://ieeexplore.ieee.org/document/8666446
HYNEK, K., et al. Future approaches to monitoring in high-speed backbone networks. In: Proceedings of the 7th Prague Embedded Systems Workshop, Roztoky u Prahy, 2019-06-27/2019-06-29, 2019. p. 27-28. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf
HYNIOVÁ, K. Energy Control Principles in An Automotive Active Suspension System. In: Proceedings of the V. International Scientific Congress Innovations 2019, Varna, 2019-06-19/2019-06-22, 2019. p. 88-92. III. vol. 3. ISSN 2603-3763.
HYNIOVÁ, K. LIMITATIONS TO SUSPENSION PERFORMANCE IN A TWO-DEGREE-OF-FREEDOM CAR ACTIVE SUSPENSION. In: Proceedings of the V. International Scientific Congress Innovations 2019, Varna, 2019-06-19/2019-06-22, 2019. p. 28-32. III. vol. 3. ISSN 2603-3763.
HYNIOVÁ, K. LIMITATIONS TO SUSPENSION PERFORMANCE IN A TWO-DEGREE-OF-FREEDOM CAR ACTIVE SUSPENSION. INNOVATIONS. 2019, VII(7), 111-115. ISSN 2603-3763.
HYNIOVÁ, K. ENERGY CONTROL PRINCIPLES IN AN AUTOMOTIVE ACTIVE SUSPENSION SYSTEM. international scientific journal tran&MOTAUTO WORLD. 2019, 3/2019(3), 107-111. ISSN 2367-8399.
HYNIOVÁ, K. On Control of Energy Flow in The Automotive Active Suspension System. In: Proceedings of Researchfora- International Conference on Research, Engineering and Technology. IRAJ, 2019. p. 19-23. III. vol. 1.
JEŘÁBEK, S. Analýza Dummy Rounds jako opatření proti DPA v hardwaru. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. ISBN 978-80-88214-20-5.
JEŘÁBEK, S. and J. SCHMIDT. Analyzing and Optimizing the Dummy Rounds Scheme. In: Proceedings of the 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Cluj-Napoca, 2019-04-24/2019-04-26, 2019. DOI: 10.1109/DDECS.2019.8724632.
KHUN, J. Akcelerace imunitních algoritmů pomocí FPGA. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. p. 11-14. ISBN 978-80-88214-20-5.
KHUN, J., M. NOVOTNÝ, and M. SKRBEK. High-Performance Spiking Neural Network Simulator. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 88-91. ISSN 2377-5475. DOI: 10.1109/MECO.2019.8760291.
KOLÁRIK, T. SAT modulo differential equations. In: Informal Proceedings of European Test Symposium 2019, Baden Baden, 2019-05-27/2019-05-30, 2019.
KUBÁTOVÁ, H. Dependability Problems in Interconnected World. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 9.
MIŠKOVSKÝ, V. Area-efficient fault-tolerant architectures exploiting masking scheme randomness. [Unpublished Lecture] CryptArchi 2019, Průhonice, Czech Republic. 2019-06-24.
MIŠKOVSKÝ, V. Útoky postranními kanály: efektivní implementace a ochrany odolné proti poruchám. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. p. 68-72. ISBN 978-80-88214-20-5.
PŘEUČIL, T. and M. NOVOTNÝ. Low-Cost Portable ECG. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 660-663. ISSN 2377-5475. ISBN 978-1-7281-1739-3. DOI: 10.1109/MECO.2019.8760086.
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Hierarchical Dependability Models based on Non-Homogeneous Continuous Time Markov Chains. In: 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS), Mykonos, 2019-04-16/2019-04-18, 2019. ISBN 978-1-7281-3424-6. DOI: 10.1109/DTIS.2019.8735006, [pdf].
ŘEZNÍČEK, J., M. KOHLÍK, and H. KUBÁTOVÁ. Accurate Inexact Calculations of Non-Homogeneous Markov Chains. In: Proceedings of the 22nd Euromicro Conference on Digital Systems Design, Kallithea, Chalkidiki, 2019-08-28/2019-08-30, 2019. p. 470-477. ISBN 978-1-7281-2861-0. DOI: 10.1109/DSD.2019.00074, [pdf].
ŘÍHA, J. Efektivnía bezpečné homomorfní šifrování v FPGA. In: Počítačové architektury & diagnostika 2019, Doksy, 2019-09-04/2019-09-06, 2019. ISBN 978-80-88214-20-5.
ŘÍHA, J., J. KLEMSA, and M. NOVOTNÝ. Multiprecision ANSI C Library for Implementation of Cryptographic Algorithms on Microcontrollers. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 275-278. ISSN 2377-5475. ISBN 978-1-7281-1739-3. DOI: 10.1109/MECO.2019.8760285.
SOCHA, P., et al. Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and Serpent. In: Proceedings of the 22nd Euromicro Conference on Digital Systems Design, Kallithea, Chalkidiki, 2019-08-28/2019-08-30, 2019. p. 277-282. ISBN 978-1-7281-2861-0. DOI: 10.1109/DSD.2019.00048.
SOCHA, P., et al. Efficient algorithmic evaluation of correlation power analysis: Key distinguisher based on the correlation trace derivative. Microprocessors and Microsystems. 2019, 2019(71), 1-8. ISSN 0141-9331. DOI: 10.1016/j.micpro.2019.102858.
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. First-Order and Higher-Order Power Analysis: Computational Approaches and Aspects. In: Proceedings of the 8th Mediterranean Conference on Embedded Computing - MECO'2019, Budva, 2019-06-10/2019-06-14, 2019. p. 83-87. ISSN 2377-5475. ISBN 978-1-7281-1739-3. DOI: 10.1109/MECO.2019.8760033.
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. SICAK: An open-source SIde-Channel Analysis toolKit. In: 8th Workshop on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE 2019). Baden-Baden, 2019-05-30/2019-05-31, 2019.
SOCHA, P., V. MIŠKOVSKÝ, and M. NOVOTNÝ. Toolkit for side-channel analysis: SICAK. [Unpublished Lecture] CryptArchi 2019, Průhonice, Czech Republic. 2019-06-24.
SOUKUP, D., T. ČEJKA, and S. ŠTEFUNKO. Multi-level Anomaly Detection in IoT Networks. In: Proceedings of the 7th Prague Embedded Systems Workshop, 2019-06-27/2019-06-29, 2019. p. 37-38. ISBN 978-80-01-06607-2. Available from: http://pesw.fit.cvut.cz/2019/PESW_2019.pdf

2018

APELTAUER, T. Automated Testing of Models of Cyber-Physical Systems. [Technical Report] 2018. Report no. TR-FIT-18-02.
BARTÍK, M. Clock Domain Crossing – An Advanced Course for Future Digital Design Engineers. In: 7th Mediterranean Conference on Embedded Computing MECO 2018, Budva, Montenegro, 2018-06-10/2018-06-14, pp. 76-80. Available from: https://ieeexplore.ieee.org/document/8406004/
BARTÍK, M. Xilinx 7-Series FPGA Based Evaluation Platform for Physically Unclonable Function. In: TRUDEVICE 2018, Dresden, Germany, 2018-03-23.
BARTÍK, M., UBIK, S., KUBALÍK, P. and T. BENEŠ. Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary. In: Proceedings of the 26th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, USA, 2018-02-25/2018-02-27, p. 290. Available from: https://dl.acm.org/citation.cfm?id=3174976
BĚLOHOUBEK, J. Zvyšování spolehlivosti a bezpečnosti číslicových obvodů na úrovni mikroarchitektury. In: Počítačové architektury a diagnostika 2018, Stachy, Zadov, Czech Rep., 2018-09-05/2018-09-07.
BĚLOHOUBEK, J., J. SCHMIDT, and P. FIŠER. Effect of Power Trace Set Properties to Differential Power Analysis. [Unpublished Lecture] TRUDEVICE 2018, 2018-03-23.
BENÁČEK, P., PUŠ, V.P., KUBÁTOVÁ, H., and T. ČEJKA. P4-To-VHDL: Automatic generation of high-speed input and output network blocks. Microprocessors and Microsystems, 2018, vol. 56 pp. 22-33. ISSN 0141-9331. DOI: 10.1016/j.micpro.2017.10.012.
ČEJKA, T., VELAN, P., HAVRÁNEK, J., and P. BENÁČEK. Enhanced Flow Monitoring with P4 Generated Flexible Packet Parser. In: Proceedings of the 12th International Conference on Autonomous Infrastructure, Management and Security, Mnichov, Germany, 2018-06-04/2018-06-05, pp. 21-32. Available from: http://www.aims-conference.org/2018/AIMS-2018-Proceedings.pdf
DANEL, M. and M. SKRBEK. Review of Reinforcement Learning Methods for Humanoid Robot Control. [Technical Report] 2018. Report no. TR-FIT-18-06.
DAŇHEL, M. Prediction and Analysis of Mission Critical Systems Dependability. PhD Thesis. CTU FIT. Department of Digital Design.
FERRANDINO, U., TRAIOLA, M., BARBARESCHI, M., MAZZEO, A., FIŠER, P., and A. BOSIO. Synthesis of Finite State Machines on Memristor Crossbars. In: Proc. of 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Budapest, Hungary, 2018-04-25/2018-04-27, pp. 107-112. DOI: 10.1109/DDECS.2018.000-3
FIŠER, P. and V. ŠIMEK. Optimum Polymorphic Circuits Synthesis Method. In: Proc. of 13th IEEE International Conference on Design and Technology of Integrated Systems in nanoscale era, Taormina, Italy, 2018-04-10/2018-04-12. DOI: 10.1109/DTIS.2018.8368585
HÁLEČEK, I., P. FIŠER, and J. SCHMIDT. XOR-Based Synthesis: Does it Pay off? In: Proc. of 13th International Workshop on Boolean Problems, Bremen, Germany, 2018-09-19/2018-09-21, pp. 167-176. [pdf]
HÁLEČEK, I., P. FIŠER, and J. SCHMIDT. Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR. Microelectronics Reliability, 2018, vol. 81, pp. 274-286. ISSN 0026-2714. DOI: 10.1016/j.microrel.2017.12.031.
HÜLLE, R., P. FIŠER, and J. SCHMIDT. ZATPG: SAT-based ATPG for Zero-Aliasing Compaction. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 8-11.
HÜLLE, R., P. FIŠER, and SCHMIDT, J. ZATPG: SAT-based Test Patterns Generator with Zero-Aliasing in Temporal Compaction. Microprocessors and Microsystems, 2018(61), 43-57. ISSN 0141-9331. DOI: 10.1016/j.micpro.2018.05.001.
HYNIOVÁ, K. A Sky-Hook Control Concept of Vehicle Active Suspensions. In: International scientific journal tran. 2018, 3(3), 106-109. ISSN 2367-8399.
HYNIOVÁ, K. A Processes Control Simulation Tool. In: International journal for science, technics and innovations for the industry MACHINES TECHNOLOGIES MATERIALS. 2018, 12(4), 182-184. ISSN 1313-0226.
HYNIOVÁ, K. A Simulation Tool of Technological Process Control. In: Proceedings of the IVth International Scientific Congress Innovations, Varna, 2018-06-20/2018-06-23, pp. 92-95. vol. 1.
HYNIOVÁ, K. Fuzzy Skyhook Control for Active One-Half-Car Suspension Model. In: WSEAS Transactions on Information Science and Applications. 2018, 15(15), 133-139.
HYNIOVÁ, K. A Sky-Hook Control Concept of Vehicle Active Suspensions. In: Proceedings of the IVth International Scientific Congress Innovations 2018, Varna, 2018-06-20/2018-06-23, pp. 92-95. vol. 1.
JÁNSKÝ, T., ČEJKA, T., ŽÁDNÍK, M., and V. BARTOŠ. Augmented DDoS Mitigation with Reputation Scores. In: Proceedings of the 13th International Conference on Availability, Reliability and Security, Hamburg, Germany, 2018-08-27/2018-09-30. Available from: https://dl.acm.org/citation.cfm?id=3233279.
JÁNSKÝ, T., ČEJKA, T., ŽÁDNÍK, M., and V. BARTOŠ. Informed DDoS Mitigation at 100 Gb/s. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 41-42.
JEŘÁBEK, S., J. SCHMIDT, and M. NOVOTNÝ. Dummy Rounds jako opatření proti DPA v hardwaru. In: Počítačové architektury a diagnostika 2018. Stachy, Zadov, Czech Rep., 2018-09-05/2018-09-07, pp. 33-36.
JEŘÁBEK, S., SCHMIDT, J., NOVOTNÝ, M., and V. MIŠKOVSKÝ. Dummy Rounds as a DPA countermeasure in hardware. In: Proceedings of the 21st Euromicro Conference on Digital System Design, Prague, Czech Rep., 2018-08-29/2018-08-31, pp. 523-528. Available from: https://ieeexplore.ieee.org/document/8491863
JEŘÁBEK, S. Differential power analysis countermeasures in programmable hardware technical research report. [Technical Report] 2018. Report no. TR-FIT-18-07.
KŘÍŽEK, F., FERENCEI, J., MATLOCHA, T., POSPÍŠIL, J., PRÍBELI, P., RASKINA, V., ISAKOV, A., ŠTURSA, J. et al. Irradiation setup at the U-120M cyclotron facility. Nuclear Instruments and Methods in Physics Research, Section A, Accelerators, Spectrometers, Detectors and Associated Equipment. 2018, vol. 894, pp. 87-95. ISSN 0168-9002. DOI 10.1016/j.nima.2018.03.066.
MIŠKOVSKÝ, V., H. KUBÁTOVÁ, and M. NOVOTNÝ. Speeding up differential power analysis using integrated power traces. In: 7th Mediterranean Conference on Embedded Computing MECO 2018, Budva, Montenegro, 2018-06-10/2018-06-14, pp. 19-23.
MIŠKOVSKÝ, V., H. KUBÁTOVÁ, and M. NOVOTNÝ. Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of AES implemented in FPGA. In: TRUDEVICE 2018. Dresden, Gremany, 2018-03-23.
SCHMIDT, J. and P. FIŠER. A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization. In: Further Improvements in the Boolean Domain. Newcastle upon Tyne: Cambridge Scholars Publishing, 2018. p. 280-301. ISBN 978-1-5275-0371-7.
SOCHA, P., MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and M. NOVOTNÝ. Correlation Power Analysis Distinguisher Based on the Correlation Trace Derivative. In: Proceedings of the 21st Euromicro Conference on Digital System Design, Prague, Czech Rep., 2018-08-29/2018-08-31, pp. 565-568. Available from: https://ieeexplore.ieee.org/document/8491869
SOCHA, P., J. BREJNÍK, and M. BARTÍK. Attacking AES Implementations Using Correlation Power Analysis on ZYBO Zynq-7000 SoC Board. In: 7th Mediterranean Conference on Embedded Computing MECO 2018, Budva, Montenegro, 2018-06-10/2018-06-14, pp. 29-32. Available from: https://ieeexplore.ieee.org/document/8406034/
SLABIHOUDEK, M. and T. ČEJKA. Stream-wise Aggregation of Flow Data. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, p. 37.
STEJSKALOVÁ, L. and T. ČEJKA. Grouping evil IP addresses. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, p. 30.
ŠUSTER, F. and T. ČEJKA. Stream-wise adaptive blacklist filter based on flow data. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 38-39.
SVATOŇ, J., VEJRAŽKA, F., KUBALÍK, P., and J. SCHMIDT. Proposal of a Memory Architecture for Pre and Post-Correlation coherent Processing of GNSS Signal with SoC based Acquisition Uni. In: Proceedings of the 6th Prague Embedded Systems Workshop, Roztoky u Prahy, Czech Rep., 2018-06-28/2018-06-30, pp. 21-25. Available from: http://pesw.fit.cvut.cz/2018/PESW_2018.pdf

2017

APELTAUER, T. Automatické testování modelů kyber-fyzikálních systémů. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. pp. 5-8.
BARTÍK, M. and UBIK, S. Systém pro realizaci rozptylovací tabulky. CESNET z.s.p.o;ČVUT FIT. 24.05.2017.
BĚLOHOUBEK, J. The Design-Time Side-Channel Information Leakage Estimation. 19.06.2017.
BĚLOHOUBEK, J., FIŠER, P., and SCHMIDT, J. Error Masking Method Based On The Short-Duration Offline Test. Microprocessors and Microsystems. 2017, vol. 52, pp. 236-250. ISSN 0141-9331. [pdf], doi
BORECKÝ, J., KOHLÍK, M., and KUBÁTOVÁ, H. Parity driven reconfigurable duplex system. Microprocessors and Microsystems, 2017, vol. 52, pp. 251-260. ISSN 0141-9331. [pdf], doi
BUČEK, J., NOVOTNÝ, M., and ŠTĚPÁNEK, F. Practical Session: Differential Power Analysis for Beginners. In: Hardware Security and Trust. Springer International Publishing. 2017, pp. 77-91.
BUČEK, J., et al. Design of a Residue Number System Based Linear System Solver in Hardware. Journal of Signal Processing Systems. 2017, 87(3), pp. 343-356. ISSN 1939-8018.
ČEJKA, T. and ŽÁDNÍK, M. Preserving Relations in Parallel Flow Data Processing. In: Proc. of Security of Networks and Services in an All-Connected World. Autonomous Infrastructure, Management, and Security. Zurich, 10.07.2017 - 13.07.2017. pp. 153-156. Available from: https://link.springer.com/chapter/10.1007/978-3-319-60774-0_14
ČEJKA, T., ŠVEPEŠ, M., and VIKTORIN, J. Gateway for IoT Security. In: Proc. of The 5th Prague Embedded Systems Workshop. Roztoky u Prahy, 29.06.2017 - 30.06.2017.
ČEJKA, T., et al. NEMEA: A Framework for Network Traffic Analysis. In: 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016. pp. 195-201. Available from: https://edas.info/showManuscript.php?m=1570291169&ext=pdf&random=1622993478&type=stamped
DANEL, M. Reinforcement Learning for Humanoid Robot Control. In: Proceedings of the International Student Scientific Conference Poster – 21/2017. Praha, 23.05.2017. [pdf]
DANEL, M. and SKRBEK, M. Humanoid Robot Control by Offline Actor-Critic Learning. In: ITAT 2017: Information Technologies – Applications and Theory. Martinské hole, Malá Fatra, 22.09.2017 - 26.09.2017, pp. 71-77. [pdf]
DANEL, M. and SKRBEK, M. Towards Learning Humanoid Robot Control. In: Proceedings of the Work in Progress Session SEAA/DSD 2017. 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017.
DAŇHEL, M., ŠTĚPÁNEK, F., and KUBÁTOVÁ, H. Dependability Prediction Involving Temporal Redundancy and the Effect of Transient Faults. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017, pp. 360-363.
DAŇHEL, M. and KUBÁTOVÁ, H. Dependability or Reliability in the Real World. In: Proc. of 6th Mediterranean Conference on Embedded Computing (MECO 2017). Bar, 11.06.2017 - 15.06.2017. pp. 17-20.
DAŇHEL, M., ŠTĚPÁNEK, F., and KUBÁTOVÁ, H. The effect of the transient faults in dependability prediction. Microprocessors and Microsystems. 2017, 52(C), pp. 498-504. ISSN 0141-9331.
FIŠER, P., HÁLEČEK, I., and SCHMIDT, J. SAT-Based Generation of Optimum Function Implementations with XOR Gates. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017. pp. 163-170. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Logická syntéza založená na obecných operátorech. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. On XAIG Rewriting. In: Proc. of 26th International Workshop on Logic & Synthesis. Austin, TX, USA, 17.06.2017 - 18.06.2017. pp. 89-96. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Are XORs in logic synthesis really necessary?. In: Proceedings of the 20th IEEE International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden, 19.04.2017 - 21.04.2017. pp. 134-139. [pdf]
HÁLEČEK, I. The State-of-the-Art of the Logic representations for the synthesis. 2017, TR-FIT-17-06.
HÜLLE, R., FIŠER, P., and SCHMIDT, J. Generování testu s nulovým maskováním poruch. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. pp. 35-38. [pdf]
HÜLLE, R., FIŠER, P., and SCHMIDT, J. SAT-based ATPG for Zero-Aliasing Compaction. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017. pp. 307-314. [pdf]
HÜLLE, R. The State-of-the-Art of Logical Circuits Automated Test Pattern Generation and Output Response Compaction. 2017, TR-FIT-17-04.
HYNIOVÁ, K. A Simulation Tool of Technological Process Control. In: Proceedings Book Of Second International Conference on Advances in Science, ICAS 2017, Istanbul, 13.09.2017 - 16.09.2017, pp. 26-30. vol. 1.
HYNIOVÁ, K. Robust Control of Vehicle Active Suspension and Its Verification. In: Proceedings Book Of Second International Conference on Advances in Science, ICAS 2017, Istanbul, 13.09.2017 - 16.09.2017, pp. 4-9. vol. 1.
HYNIOVÁ, K. Usage of One-Quarter-Car Active Suspension Test Stand for Experimental Verification. WSEAS Transactions on Applied and Theoretical Mechanics. 2017, pp. 17-24.
HYNIOVÁ, K. One-Quarter-Car Active Suspension Model Verification. In: Open Access proceedings in Information technology, Computer Science and Mathematics. Rome, Italy, 05.11.2016 - 07.11.2016. pp. 121-125. vol. 9. Available from: http://www.itm-conferences.org/articles/itmconf/abs/2017/01/itmconf_amcse2017_03003/itmconf_amcse2017_03003.html
JÁNSKÝ, T., ČEJKA, T., and BARTOŠ, V. Hunting SIP Authentication Attacks Efficiently. In: Proc. of Security of Networks and Services in an All-Connected World. Autonomous Infrastructure, Management, and Security. Zurich, 10.07.2017 - 13.07.2017. pp. 125-130. ISBN 978-3-319-60773-3. Available from: https://link.springer.com/chapter/10.1007/978-3-319-60774-0_9
JÁNSKÝ, T., ČEJKA, T., and BARTOŠ, V. Detection of SIP Scans and Bruteforce Attacks. In: Proc. of The 5th Prague Embedded Systems Workshop. Roztoky u Prahy, 29.06.2017 - 30.06.2017.
JEŘÁBEK, S., SCHMIDT, J., and NOVOTNÝ, M. Dynamic Reconfiguration as Countermeasure against DPA. In: Proceedings of the Work in Progress Session SEAA/DSD 2017. 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017.
JEŘÁBEK, S., SCHMIDT, J., and NOVOTNÝ, M. Dynamická rekonfigurace jako opatření proti DPA. In: Proc. of Počítačové architektury a diagnostika, Smolenice, 06.09.2017 - 08.09.2017.
JEŘÁBEK, S., et al. Emulator of Contactless Smart Cards in FPGA. In: Proc. of 6th Mediterranean Conference on Embedded Computing (MECO 2017). Bar, 11.06.2017 - 15.06.2017. pp. 96-99.
MAZUR, L. and NOVOTNÝ, M. Differential Power Analysis on FPGA board: Boundaries of Success. In: Proc. of 6th Mediterranean Conference on Embedded Computing (MECO 2017). Bar, 11.06.2017 - 15.06.2017. pp. 92-95.
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of passive hardware redundancy on differential power analysis resistance of AES cipher implemented in FPGA. Microprocessors and Microsystems, 2017, vol. 51, pp. 220-226. ISSN 0141-9331. Available from: http://www.sciencedirect.com/science/article/pii/S0141933116304677
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Číslicový návrh spojující odolnost proti poruchám a odolnost proti útokům. In: Proc. of Počítačové architektury a diagnostika. Smolenice, 06.09.2017 - 08.09.2017. pp. 43-46.
MIŠKOVSKÝ, V. Fault tolerance and resistance against side channel attacks in FPGA. 2017, TR-FIT-17-03.
NOVÁK, P., et al. Predicting the Life Expectancy of Railway Fail-safe Signaling Systems Using Dynamic Models with Censoring. In: Proc. of 2017 IEEE International Conference on Software Quality, Reliability and Security (QRS), Prague, 25.07.2017 - 29.07.2017, pp. 329-339. Available from: http://ieeexplore.ieee.org/document/8009937/
NOVOTNÝ, M. Cryptanalytic attacks on cyber-physical systems. Microprocessors and Microsystems. 2017, vol. 52, pp. 534-539. ISSN 0141-9331. Available from: http://www.sciencedirect.com/science/article/pii/S0141933117300674
ROSA, Z., et al. Building a Feedback Loop to Capture Evidence of Network Incidents. In: 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016. pp. 292-296. Available from: https://edas.info/showManuscript.php?m=1570287530&ext=pdf&random=551856465&type=stamped
ŘÍHA, J., et al. Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic Design. In: Proc. of 20th Euromicro Conference on Digital System Design. Vienna, 30.08.2017 - 01.09.2017. pp. 260-267.
SCHMIDT, J. On Quality in Experimental Evaluation. In: Proceedings of the 18th International Symposium on Quality Electronic Design (ISQED 2017). Santa Clara, 14.03.2017 - 15.03.2017.
SIELEWICZ, K.M., et al. Prototype readout electronics for the upgraded ALICE Inner Tracking System. Journal of Instrumentation. 2017, 12(01), ISSN 1748-0221. Available from: http://stacks.iop.org/1748-0221/12/i=01/a=C01008
SOCHA, P., et al. Optimization of Pearson correlation coefficient calculation for DPA and comparison of different approaches. In: Proceedings of the 20th IEEE International Symposium on Design and Diagnotics of Electronic Circuit & Systems. Dresden, 19.04.2017 - 21.04.2017. pp. 188-193.
SVATOŇ, J., et al. Acquisition of Modern GNSS Signals in SoC ZYNQ with its Limited Computational Resources in Frequency Domain. In: Proc. of The 5th Prague Embedded Systems Workshop. Roztoky u Prahy, 29.06.2017 - 30.06.2017. pp. 64-66.
SVATOŇ, J., et al. Methods and Hardware achitecture for Multi-constellation GNSS signal acqusition unit in frequency domain. In: Proc. of The European Navigation Conference 2017. Lausanne, 09.05.2017 - 12.05.2017. pp. 252-261. Available from: http://enc2017.eu/site/downloads/
ŠVEPEŠ, M. and ČEJKA, T. Making Flow-Based Security Detection Parallel. In: Proc. of Security of Networks and Services in an All-Connected World. Autonomous Infrastructure, Management, and Security. Zurich, 10.07.2017 - 13.07.2017. pp. 3-15.Available from: https://link.springer.com/chapter/10.1007/978-3-319-60774-0_1

2016

ALEXA, D. Future plans for bulk configuration and visualization of NETCONF devices. In Proceedings of the 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016.
BARTÍK, M. and BUČEK, J. A Low-Cost Unified Experimental FPGA Board for Cryptography Applications. In TRUDEVICE 2016 Final Conference. Conference on Trustworthy Manufacturing and Utilization of Secure Devices. Barcelona, 14.11.2016 - 16.11.2016., pp. 75-80. Available from: http://hdl.handle.net/2117/99297
BARTÍK, M. and BUČEK, J. A Low-Cost Multi-Purpose Experimental FPGA Board for Cryptography Applications . In 2016 IEEE 4th Workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE). Vilnius, 10.11.2016 - 12.11.2016, ISBN 978-1-5090-4473-3. Available from: http://ieeexplore.ieee.org/document/7821811/
BARTÍK, M., PICHLOVÁ, D., and KUBÁTOVÁ, H. Hardware-software co-design: A practical course for future embedded engineers. In Proceedings of the 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 347-350. ISBN 978-1-5090-2220-5. Available from: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7525779
BARTÍK, M., UBIK, S., and KUBALÍK, P. Nová a efektivní metoda pro zajištení platnosti dat ve vestavných pamětech FPGA se zaměřením na kompresi IP packetů v reálném čase. Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016. Available from: http://www.fit.vutbr.cz/events/pad2016/download/sbornik/14-Bartik.pdf
BARTÍK, M., UBIK, S., and KUBALÍK, P. A Novel and Efficient Method to Initialize FPGA Embedded Memory Content in Asymptotically Constant Time. In Proc. of ReConFig’16. 2016 International Conference on Reconfigurable Computing and FPGAs. Cancún, 30.11.2016 - 02.12.2016, ISBN 978-1-5090-3706-3.
BĚLOHOUBEK, J. Využití rychlého offline testu v systému se schopností maskování jedné chyby. Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016. ISBN 978-80-214-5376-0.
BĚLOHOUBEK, J., FIŠER, P., and SCHMIDT, J. Error Correction Method Based on the Short-Duration Offline Test. In Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016. Limassol, Cyprus, 31.08.2016 - 02.09.2016, pp. 495-502. ISBN 978-1-5090-2816-0. [pdf]
BENÁČEK, P. and KUBÁTOVÁ, H. P4-to-FPGA: Translating P4 to VHDL. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016.
BENÁČEK, P., KUBÁTOVÁ, H., and PUŠ, VP. P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. In Proc. of 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM 2016), 01.05.2016 - 03.05.2016, pp. 148-155. ISBN 978-1-5090-2356-1.
BORECKÝ, J., KOHLÍK, M., and KUBÁTOVÁ, H. Parity Waterfall Method. In Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice, 20.04.2016 - 22.04.2016, pp. 21-26. ISBN 978-1-5090-2467-4. [pdf]
BORECKÝ, J., et al. Enhanced duplication method with TMR-like masking abilities. In Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016. Limassol, Cyprus, 31.08.2016 - 02.09.2016, pp. 690-693. ISBN 978-1-5090-2816-0.
BUČEK, J., KUBALÍK, P., LÓRENCZ, R., and Zahradnický, T. Design of a Residue Number System Based Linear System Solver in Hardware. Journal of Signal Processing Systems. 2016, pp. 1-14. ISSN 1939-8018.
ČEJKA, T., et al. NEMEA: A Framework for Network Traffic Analysis [online]. In 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016. ISBN 978-3-901882-85-2. Available from: https://edas.info/showManuscript.php?m=1570291169&ext=pdf&random=1622993478&type=stamped
ČEJKA, T. and ROBLEDO, A. Detecting Spoofed Time in NTP Traffic. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, pp. 49-52. ISBN 978-80-01-05984-5.
ČEJKA, T. and ŠVEPEŠ, M. Analysis of Vertical Scans Discovered by Naive Detection [online]. In Proc. of 10th International Conference on Autonomous Infrastructure, Management and Security (AIMS 2016). Mnichov, 20.06.2016 - 23.06.2016, pp. 165-169. ISBN 978-3-319-39814-3. Available from: http://link.springer.com/chapter/10.1007/978-3-319-39814-3_19
DAŇHEL, M. and ŠTĚPÁNEK, F. Reliability prediction in dependability models considering transient faults. In Proceedings of the 20th International Scientific Student Conferenece POSTER 2016. Praha, 24.05.2016, ISBN 978-80-01-05950-0.
DAŇHEL, M., ŠTĚPÁNEK, F., and KUBÁTOVÁ, H. The Effect of the Transient Faults in Dependability Prediction. In Proceedings of 19th Euromicro Conference on Digital System Design DSD 2016, Limassol, Cyprus, 31.08.2016 - 02.09.2016, pp. 9-13. ISBN 978-1-5090-2816-0.
DAS, S., DASGUPTA, P., FIŠER, P, et al. A Rule-Based Approach for Minimizing Power Dissipation of Digital Circuits. In Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice, 20.04.2016 - 22.04.2016, pp. 237-242. ISBN 978-1-5090-2467-4. [pdf]
FIŠER, P. and SCHMIDT, J. A Comprehensive Set of Logic Synthesis and Optimization Examples. In Proceedings of the 12th International Workshop on Boolean Problems. Freiberg, 22.09.2016 - 23.09.2016, pp. 151-158. ISBN 978-3-86012-540-3. [pdf]
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Logická syntéza s nativní podporou XOR hradel. In Proc. of Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016, ISBN 978-80-214-5376-0.
HÁLEČEK, I., FIŠER, P., and SCHMIDT, J. Utilization of XOR gates in logic synthesis. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, ISBN 978-80-01-05984-5.
HÜLLE, R., FIŠER, P., and SCHMIDT, J. Generování testu pro prostředky vestavěné diagnostiky. In Proc. of Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016, ISBN 978-80-214-5376-0.
HÜLLE, R., et al. SAT-ATPG for Application-Oriented FPGA Testing. In Proceedings of the 15th Biennial Baltic Electronics Conference. Tallinn, 03.10.2016 - 05.10.2016, pp. 83-86. ISBN 978-1-5090-1393-7. Available from: http://ieeexplore.ieee.org/document/7743734/ [pdf]
HYNIOVÁ, K. A Tool for Modelling of Technological Processes Control. In: Automatizace a řízení v teorii a praxi. Automatizace a řízení v teorii a praxi. Stará Lesná, 10.02.2016 - 12.02.2016., ISBN 978-80-553-2474-6.
HYNIOVÁ, K. On Testing of Vehicle Active Suspension Robust Control on An One-Quarter-Car Test Stand [online]. In Proc. of International Journal of Mechanical Engineering. 2016, 2016 (1)(1), pp. 1-7. ISSN 2367-8968. Available from: http://www.iaras.org/iaras/filedownloads/ijme/2016/012-0001.pdf
HYNIOVÁ, K. A Tool for Modelling of Technological Processes Control [online]. Strojírenství. 2016, XX(6/2016), pp. 94-95. ISSN 1335-2938.
HYNIOVÁ, K. Laboratorní model technologického procesu a jeho řízení [online]. In Proc. of ARTEP 2016. Automatizace a řízení v teorii a praxi. Stará Lesná, 10.02.2016 - 12.02.2016. ISBN 978-80-553-2474-6.
HYNIOVÁ, K. Vibrational Analysis of Suspension System for One- Half- Car Model with Fuzzy Logic Controller [online]. In International Scientific Congress Innovations in Engineering , Varna, 20.06.2016 - 22.06.2016., pp. 82-85. ISSN 1310-3946. Available from: http://www.innova-eng.eu/proceedings/2016.pdf
HYNIOVÁ, K. Nástroj pro modelování řízení technologických procesů. AT&P Journal. 2016, 2016(10/2016), pp. 58-61. ISSN 1335-2237. Available from: http://www.atpjournal.sk/buxus/docs/casopisy_cele/ATP%20Journal%2010%202016.pdf
JEŘÁBEK, S. Emulator of Contactless Smart Cards in FPGA. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, ISBN 978-80-01-05984-5.
KUBÁTOVÁ, H. and NOVOTNÝ, M. Education of Computer Engineering at CTU in Prague. In Proc. of 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 22-25. ISBN 978-1-5090-2220-5.
LIPOVSKÝ, M., ŠVARC, J. GRAMATOVÁ, E. and FIŠER, P. A New User-Friendly ATPG Platform for Digital Circuits. In Proceedings of the 19th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems. Košice, 20.04.2016 - 22.04.2016., pp. 210-213. ISBN 978-1-5090-2467-4. [pdf]
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of fault-tolerant design methods on differential power analysis resistance of AES cipher: Methodics and challenges. In Proc. of 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 14-17. ISBN 978-1-5090-2220-5. Available from: http://ieeexplore.ieee.org/document/7525685/
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, pp. 38-39. ISBN 978-80-01-05984-5.
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Číslicový návrh spojující odolnost proti útokům a odolnost proti poruchám. In Proc. of Počítačové architektury a diagnostika. Bořetice, 14.09.2016 - 16.09.2016. ISBN 978-80-214-5376-0. Available from: http://www.fit.vutbr.cz/events/pad2016/download/sbornik/26-Miskovsky.pdf
MIŠKOVSKÝ, V., KUBÁTOVÁ, H., and NOVOTNÝ, M. Influence of Fault-tolerant Design Methods on Resistance against Differential Power Analysis in FPGA. In: TRUDEVICE 2016 Final Conference. Conference on Trustworthy Manufacturing and Utilization of Secure Devices. Barcelona, 14.11.2016 - 16.11.2016.
NOVOTNÝ, M. Cryptanalytical Attacks on Cyber-Physical Systems. 5th Mediterranean Conference on Embedded Computing (MECO 2016). Bar, 12.06.2016 - 16.06.2016, pp. 10. ISBN 978-1-5090-2221-2.
PICHLOVÁ, D. and BARTÍK, M. Development of a sound recording system for audio cassette duplication on an industrial scale. In Proc. of The 4th Prague Embedded Systems Workshop. Roztoky u Prahy, 30.06.2016 - 02.07.2016, pp. 2-3. ISBN 978-80-01-05984-5.
ROSA, Z., et al. Building a Feedback Loop to Capture Evidence of Network Incidents [online]. In Proc. of 12th International Conference on Network and Service Management. Montréal, 31.10.2016 - 04.11.2016, pp. 248-252. ISBN 978-1-5090-3236-5. Available from: https://edas.info/showManuscript.php?m=1570287530&ext=pdf&random=551856465&type=stamped
SCHAMBACH, J., ROSSEWIJ, M.J., SIELEWICZ, K.M., AGLIERI RINELLA, G., BORONA, M., FERENCEI, J., GIUBILATO, P., VAŇÁT, T. ALICE inner tracking system readout electronics prototype testing with the CERN "Giga Bit Transceiver" [online]. Journal of Instrumentation. 2016, 11(12), ISSN 1748-0221. Available from: http://stacks.iop.org/1748-0221/11/i=12/a=C12074
SCHMIDT, J., BLAŽEK, R., and FIŠER, P. Towards Understanding the Performance of Randomized Algorithms. In: Problems and New Solutions in the Boolean Domain. Cambridge Scholars Publishing. 2016, pp. 167-186. ISBN 978-1-4438-8947-6.
SCHMIDT, J. and FIŠER, P. A Prudent Approach to Benchmark Collection. In Proc. of the 12th International Workshop on Boolean Problems. Freiberg, 22.09.2016 - 23.09.2016, pp. 129-136. ISBN 978-3-86012-540-3. [pdf]
ŠVEPEŠ, M. and ČEJKA, T. Overload-resistant Network Traffic Analysis. In Proceedings of the 4th Prague Embedded Systems Workshop, Roztoky u Prahy, 30.06.2016 - 02.07.2016. pp. 53-58. ISBN 978-80-01-05984-5.
TAMÁŠI, R., SIEBERT, M., GRAMATOVÁ, E., and FIŠER, P., A New Method for Path Criticality Calculation. In: Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Košice, 20.04.2016 - 22.04.2016, pp. 190-193. ISBN 978-1-5090-2467-4. [pdf]
VAŇÁT, T., et al. Comparing Proton and Neutron Induced SEU Cross Section in FPGA. In: Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), Košice, 20.04.2016 - 22.04.2016, pp. 214-217. ISBN 978-1-5090-2467-4.

2015

Alexa, D. - Čejka, T.: Easy configuration of NETCONF devices, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 3-9. ISBN 978-80-01-05776-6.
Bartík, M. - Ubik, S. - Kubalík, P.: Rychlé bezztrátové kompresní algoritmy, In: PAD 2015, Zlín, 2015, pp. 31-36. ISBN 978-80-7454-522-1.
Bartík, M. - Ubik, S. - Kubalík, P.: LZ4 Compression Algorithm on FPGA, In: 21st IEEE International Conference on Electronics, Circuits, and Systems, 2015, pp. 179-182. ISBN 978-1-4799-2451-6.
Bartík, M. - Novotný, M.: Advanced control unit for linear motor for precise measurements in biomechanics, In: EMBEDDED COMPUTING. MEDITERRANEAN CONFERENCE. 4TH 2015. (MECO 2015), 2015, pp. 129-133. ISBN 978-1-4799-8999-7.
Bělohoubek, J.: Smart re-use of hardware peripherals for better software UART, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 17-23. ISBN 978-80-01-05776-6.
Bělohoubek, J.: Novel Gate Design Method for Short-Duration Test, In: Proceedings of the 19th International Scientific Student Conferenece POSTER 2015, Prague, ISBN 978-80-01-05499-4.
Bělohoubek, J.: Novel Error Detection and Correction Method Combining Time and Area Redundancy, In: PAD 2015, Zlín, 2015, pp. 48-53. ISBN 978-80-7454-522-1.
Bělohoubek, J. - Fišer, P. - Schmidt, J.: Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy, In: Proceedings of the Euromicro Conference on Digital System Design, 2015, pp. 280-283. ISBN 978-1-4673-8035-5. DOI: 10.1109/DSD.2015.95
Benáček, P. - Kubátová, H. - Puš, V.: Automatic Generation of 100 Gbps Packet Parsers from P4 Description, In: First International Workshop on Heterogeneous High-performance Reconfigurable Computing. 2015
Čejka, T. - Bartoš, V. - Truxa, L. - Kubátová, H.: Using Application-Aware Flow Monitoring for SIP Fraud Detection, In: Intelligent Mechanisms for Network Configuration and Security. Springer International Publishing, 2015, pp. 87-99. ISSN 0302-9743. ISBN 978-3-319-20033-0.
Čejka, T. - Bodó, R. - Kubátová, H.: Nemea: Searching for Botnet Footprints, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 11-16. ISBN 978-80-01-05776-6.
Daňhel, M.: The Determination of Operational Reliability and Predictive Analysis of Reliability of the Railway Signaling Systems, In: Proceedings of the 19th International Scientific Student Conferenece POSTER 2015, 2015, ISBN 978-80-01-05499-4.
Fišer, P. - Schmidt, J.: Introduction to Lethal Circuit Transformations, In: Proc. of Design and Analysis of Control Systems, March 20-23, 2015, Athens, Greece, p. 4. ISSN 0094-243X. ISBN 978-0-7354-1349-8. DOI: 10.1063/1.4938891
Háleček, I. - Fišer, P. - Schmidt, J.: On Identification of XOR Gates in AIGs, In: Proceedings of the Work in Progress Session of the 18th EUROMICRO Conference on Digital System Design, 2015, ISBN 978-3-902457-44-8.
Hyniová, K.: External Fuzzy Logic Control of Simulated Technological Processes, In: Recent Advances in Systems. Athens: World Scientific and Engineering Society Press, 2015, vol. 1, pp. 129-132. ISSN 1790-5117. ISBN 978-1-61804-321-4.
Tamaši, R. - Siebert, M. - Fišer, P.: A New Method for Speficication of Parameters to Path Delay Fautls Testing, In: Proceedings of the 3rd Prague Embedded Systems Workshop, 2015, pp. 26-32. ISBN 978-80-01-05776-6.
Vaňát, T. - Pospíšil, J. - Křížek, F. - Ferencei, J. - Kubátová, H.: A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other Electronics, In: Proceedings of the Euromicro Conference on Digital System Design, ISBN 978-1-4673-8035-5.

2014

Balcárek, J. - Fišer, P. - Schmidt, J.: On don't cares in test compression. In: Microprocessors and Microsystems. 2014, vol. 38, no. 8, p. 754-765. ISSN 0141-9331. DOI: 10.1016/j.micpro.2014.07.006
Balcárek, J. - Fišer, P. - Schmidt, J.: PBO-Based Test Compression. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 679-682. ISBN 978-1-4799-5793-4. [pdf]
Bartík, M.: Practical use of FPGA Chips for Implementation. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014, p. 15.
Benáček, P. - Blažek, R. - Čejka, T. - Kubátová, H.: Change-point detection method on 100 Gb/s ethernet interface In: Architectures for Networking and Communications Systems (ANCS), 2014 ACM/IEEE Symposium on. New York: ACM, 2014, p. 245-246. ISBN 978-1-4503-2839-5.
Benáček, P. - Kubátová, H. Architecture of Effective High-Speed Network Stream Merger. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 459-464. ISBN 978-1-4799-5793-4.
Bernasconi, A. - Ciriani, V. - Fišer, P. - Trucco, G.: Weighted Don't Cares in Logic Synthesis. In: Recent Progress in the Boolean Domain. Cambridge: Cambridge Scholars Publishing, 2014, p. 263-277. ISBN 978-1-4438-5638-6.
Borecký, J. - Vít, P. - Kubátová, H.: Fault Recovery Method of Modular Systems based on Reconfigurations. In: Designing with Uncertainty - Opportunities and Challenges Workshop. 2014.
Borecký, J. - Vít, P. - Kubátová, H.: Fault Recovery Method with High Availability for Practical Applications. In: MEMICS proceedings. Brno: NOVPRESS, 2014, p. 127. ISBN 978-80-214-5022-6.
Buček, J. - Kubalík, P. - Lórencz, R. - Zahradnický, T.: System Design of an FPGA Linear Solver. In: Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design. Linz: Johannes Kepler University, 2014, ISBN 978-3-902457-40-0.
Čejka, T. - Kekely, L. - Benáček, P. - Blažek, R. - Kubátová, H.: FPGA Accelerated Change-Point Detection Method for 100 Gb/s Networks. In: MEMICS proceedings. Brno: NOVPRESS, 2014, p. 40-51. ISBN 978-80-214-5022-6.
Čejka, T. - Rosa, Z. - Kubátová, H.: Stream-wise Detection of Surreptitious Traffic over DNS. In: 2014 IEEE 19th International Workshop on Computer Aided Modeling and Design of Communication Links and Networks (CAMAD 2014). Pomona, California: IEEE Communications Society, 2014, ISBN 978-1-4799-5726-2.
Fišer, P. - Schmidt, J.: Permuting Variables to Improve Iterative Resynthesis. In: Recent Progress in the Boolean Domain. Cambridge: Cambridge Scholars Publishing, 2014, p. 213-230. ISBN 978-1-4438-5638-6.
Fišer, P. - Schmidt, J. - Balcárek, J.: Sources of Bias in EDA Tools and Its Influence. In: Proceedings of the 2014 IEEE 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems. Piscataway: IEEE, 2014, p. 258-261. ISBN 978-1-4799-4560-3. [pdf]
Hyniová, K.: On Experimental Verification Of Vehicle Active Suspension Robust Control. In: Proceedings of the 18 th International Conference on systems. Athens: WSEAS, 2014, p. 353-358. ISSN 1790-5117. ISBN 978-1-61804-243-9.
Hyniová, K. - Smítková Janků, L.: Using Fuzzy Logic to Control an Innovative Active Vehicle Suspension System. In: Proceedings of the 18 th International Conference on systems. Athens: WSEAS, 2014, p. 161-167. ISSN 1790-5117. ISBN 978-1-61804-243-9.
Kohlík, M. - Kubátová, H.: Hierarchical Models of Markov Chains: Optimizations with Limited Pessimism. In: Proceedings of the 18th International Conference Electronics 2014. Kaunas: Technologija, 2014, p. 59-62. ISBN 978-609-02-1065-9. [pdf]
Kohlík, M. - Kubátová, H.: Pessimistic Dependability Models Based on Hierarchical Markov Chains. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014.
Lemberski, I. - Fišer, P.: Dual-Rail Asynchronous Logic Multi-Level Implementation. In: Integration, the VLSI Journal. 2014, vol. 47, no. 1, p. 148-159. ISSN 0167-9260. DOI: 10.1016/j.vlsi.2013.02.002
Lemberski, I. - Fišer, P. - Suleimanov, R.: Asynchronous sum-of-products logic minimization and orthogonalization. In: International Journal of Circuit Theory and Applications. 2014, vol. 42, no. 6, p. 562-571. ISSN 0098-9886. DOI: 10.1002/cta.1870
Pospíšil, J. - Vaňát, T. - Schmidt, J.: Towards Trusted Devices in FPGA by Modeling. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014, p. 16.
Schmidt, J. - Blažek, R.B. - Fišer, P.: On Probability Density Distribution of Randomized Algorithms Performance. In: Proceedings of the 11th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2014, p. 67-74. ISBN 978-3-86012-488-8. [pdf]
Schmidt, J. - Fišer, P. - Balcárek, J.: On Robustness of EDA Tools. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 427-434. ISBN 978-1-4799-5793-4. [pdf]
Štěpánek, F.: Case study: Comparison of various approaches in Fault-Tolerant and Attack-Resistant system design. In: Sborník příspěvků PAD 2014. Liberec: Technical University of Liberec, 2014, p. 81-86. ISBN 978-80-7494-026-2.
Štěpánek, F. - Novotný, M.: Comparison of various approaches in Fault-Tolerant and Attack-Resistant system design. In: Proceedings of the 2nd Prague Embedded Systems Workshop. 2014.
Vít, P. - Borecký, J. - Kohlík, M. - Kubátová, H.: Fault Tolerant Duplex System with High Availability for Practical Applications. In: Proceedings of 2014 17th Euromicro Conference. Piscataway: IEEE, 2014, p. 320-325. ISBN 978-1-4799-5793-4.

2013

Balcárek, J. - Fišer, P. - Schmidt, J.: Techniques for SAT-Based Constrained Test Pattern Generation. Microprocessors and Microsystems. 2013, vol. 37, no. 2, pp. 185-195. ISSN 0141-9331. DOI: 10.1109/DSD.2011.50
Hyniová, K.H.: An Innovative Active Suspension System for Autonomous Vehicles: A safe and Comfortable Ride and Good Handling. ERCIM News. 2013, no. 94, pp. 28-29. ISSN 0926-4981.
Gueneysu, T. - Kasper, T. - Novotný, M. - Paar, C. - Wienbrandt, L. - et al.: High-Performance Cryptanalysis on RIVYERA and COPACOBANA Computing Systems. In High-Performance Computing Using FPGAs. New York: Springer, 2013, pp. 335-366. ISBN 978-1-4614-1790-3.
Balcárek, J. - Fišer, P. - Schmidt, J.: Simulation and SAT Based ATPG for Compressed Test Generation. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center , 2013, p. 445-452. ISBN 978-0-7695-5074-9. [pdf]
Benáček, P.: Architektura pro měření v reálném čase na vysokorychlostních sítích. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 45-50. ISBN 978-80-261-0270-0.
Buček, J. - Kubalík, P. - Lórencz, R. - Zahradnický, T.: Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. In Proceedings of 16th Euromicro Conference on Digital System Design, 2013, pp. 284-287. ISBN 978-0-7695-5074-9. [pdf]
Daňhel, M.: Predikce a analýza spolehlivosti kritických systémů. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 69-74. ISBN 978-80-261-0270-0.
Daňhel, M. D. - Kubátová, H. K. - Dobiáš, R. D.: Predictive Analysis of Mission Critical Systems Dependability. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center, 2013, ISBN 978-0-7695-5074-9.

[pdf]

Daňhel, M. D. - Kubátová, H. K. - Dobiáš, R. D.: Predikce a analýza spolehlivosti kritických systémů. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 69-74. ISBN 978-80-261-0270-0.
Kohlík, M. - Kubátová, H.: Hierarchical Dependability Models Based on Markov Chains. In Proceedings of 2013 26th International Conference on Architecture of Computing Systems (ARCS). Berlin: VDE VERLAG GMBH Berlin, 2013, ISBN 978-3-8007-3492-4. [pdf]
Kohlík, M. - Kubátová, H.: Markov chains hierarchical dependability models: Worst-case computations. In 14th Latin American Test Workshop. Los Alamitos: IEEE Computer Society, 2013, ISBN 978-1-4799-0595-9. [pdf]
Kubátová, H. - Daňhel, M. - Dobiáš, R.: Predictive Analysis of Mission Critical Systems. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center , 2013, pp. 561-566. ISBN 978-0-7695-5074-9.
Kyncl, J. - Hariram, A. - Novotný, M.: On Measurement of Synchronous Phasors in Electrical Grids. In ISCAS 2013 Conference Proceedings. Piscataway: IEEE, 2013, pp. 2972-2975. ISSN 0271-4302.ISBN 978-1-4673-5760-9.
Pospíšil, J.: Modelováním poruch ke spolehlivým architekturám FPGA. In Počítačové architektury a diagnostika - PAD 2013. Plzeň: Západočeská universita, Fakulta aplikovaných věd, 2013, pp. 117-122. ISBN 978-80-261-0270-0.
Pospíšil, J. - Schmidt, J. - Fišer, P.: New SEU Modeling by Architecture Analysis. In Proceeding of the Work in Progress Session of 16th Euromicro Conference on Digital System Design. 2013, ISBN 978-3-902457-38-7. [pdf]
Richta, K. - Kubátová, H. - Richta, T.: Petri Nets versus UML State Machines. In SDOT 2013. Praha: Vysoká škola manažerské informatiky a ekonomiky, a.s., 2013, pp. 1-7. ISBN 978-80-86847-66-5.
Štěpánek, F. - Buček, J. - Novotný, M.: Differential Power Analysis under Constrained Budget: Low Cost Education of Hackers. In Proceedings of 16th Euromicro Conference on Digital System Design. Piscataway: IEEE Service Center , 2013, pp. 645-648. ISBN 978-0-7695-5074-9. [pdf]

2012

Benáček, P. - Kubátová, H.: Metodologie pro analýzu rychlých síťových přenosů. In Počítačové architektury a diagnostika - PAD 2012. Praha: ČVUT v Praze, 2012, p. 9-12. ISBN 978-80-01-05106-1.
Bernasconi, A. - Ciriani, V. - Fišer, P. - Trucco, G.: Weighted Don't Cares. In Proc. of 10th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2012, p. 123-130. ISBN 978-3-86012-438-3. [pdf]
Borecký, J. - Kohlík, M. - Kubátová, H.: Miscellaneous Types of Partial Duplication Modifications for Availability Improvements. In Proceedings of the 15th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2012, p. 79-83. ISBN 978-0-7695-4798-5. [pdf]
Buček, J. - Kubalík, P. - Lórencz, R. - Zahradnický, T.: Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA. In The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012. Monterey: IEEE Circuits and Systems Society, 2012, p. 689-692. ISBN 978-1-4673-1259-2. [pdf]
Čejka, T. : Hardwarově akcelerovaná detekce anomálií v počítačových sítích s využitím FPGA. In Počítačové architektury a diagnostika - PAD 2012. Praha: ČVUT v Praze, 2012, p. 13-16. ISBN 978-80-01-05106-1.
Fišer, P. - Schmidt, J.: Improving the Iterative Power of Resynthesis. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 30-33. ISBN 978-1-4673-1185-4. [pdf]
Fišer, P. - Schmidt, J.: On Using Permutation of Variables to Improve the Iterative Power of Resynthesis. In Proc. of 10th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2012, p. 107-114. ISBN 978-3-86012-438-3. [pdf]
Fišer, P. - Schmidt, J.: A Difficult Example Or a Badly Represented One? In Proc. of 10th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2012, p. 115-122. ISBN 978-3-86012-438-3. [pdf]
Hyniová, K. - Smítková Janků, L. - Honců, J. - Stříbrský, A.: On Experiments Taken on The Active Shock Absorber Test Stand. In APPLIED MATHEMATICS in ELECTRICAL and COMPUTER ENGINEERING. New York: WSEAS Press, 2012, vol. 1, p. 104-109. ISBN 978-1-61804-064-0.
Hyniová, K. - Krajl, M. - Smítková Janků, L.: Experiments Taken on Energy Management in Active Suspension of Vehicles. International Journal of Circuits, Systems and Signal Processing [online]. 2012, vol. 6, no. 1, p. 196-203. Internet: http://www.naun.org/wseas/cms.action?id=3113. ISSN 1998-4464.
Chloupek, M. - Novák, O. - Jeníček, J.: On test time reduction using pattern overlapping, broadcasting and on-chip decompression. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 300-305. ISBN 978-1-4673-1185-4.
Kohlík, M. - Kubátová, H.: Reduction of Complex Safety Models based on Markov Chaints. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 183-186. ISBN 978-1-4673-1185-4. [pdf]
Kohlík, M. - Kubátová, H.: Hierarchical Dependability Models Based on Markov Chains. In Počítačové architektury a diagnostika - PAD 2012. Praha: ČVUT v Praze, 2012, p. 145-150. ISBN 978-80-01-05106-1. [pdf]
Pospíšil, J. - Novotný, M.: Lightweight Cipher Resistivity against Brute-Force Attack: Analysis of PRESENT. In Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). New York: IEEE Computer Society Press, 2012, p. 197-198. ISBN 978-1-4673-1185-4. [pdf], [poster]
Pospíšil, J. - Novotný, M.: Evaluating Cryptanalytical Strength of Lightweight Cipher PRESENT on Reconfigurable Hardware. In Proceedings of the 15th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2012, p. 560-567. ISBN 978-0-7695-4798-5.
Schmidt, J. - Fišer, P. - Balcárek, J.: The Influence of Implementation Technology on Dependability Parameters. In Proceedings of the 15th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2012, p. 368-373. ISBN 978-0-7695-4798-5. [pdf]
Schmidt, J. - Fišer, P. - Balcárek, J.: Generalized Miter and its Application in Hardware Design. In Proceedings of the 8th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS, 2012, p. 119-120. ISBN 978-80-87342-15-2.
Vít, P.: Dependability structures testing device based on real model of a railway station. In POSTER 2012 - 16th International Student Conference on Electrical Engineering [CD-ROM]. Praha: Czech Technical University in Prague, 2012, p. 1-3. ISBN 978-80-01-05043-9.
Ubik, S. - Trávníček, Z. - Žejdl, P. - Halák, J.: Remote Access to 3D Models for Research, Engineering, and Art. IEEE Multimedia. 2012, vol. 19, no. 4, p. 12-19. ISSN 1070-986X.

2011

BALCÁREK J.: Implicit Representations in the Diagnostic of the Digital Circuits. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 67–72. ISBN 978-80-227-3552-0.
BALCÁREK J. – FIŠER P. – SCHMIDT J.: Techniques for SAT-Based Constrained Test Pattern Generation. In Proceedings of the 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, p. 360–366. ISBN 978-0-7695-4494-6. [pdf]
BALCÁREK J. – FIŠER P. – SCHMIDT J.: Implicit Techniques for Constrained Test Patterns Generation. In Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011, p. 106. ISBN 978-80-214-4305-1.
BORECKÝ J. – KOHLÍK M. – KUBALÍK P. – KUBÁTOVÁ H.: Fault Models Usability Study for On-line Tested FPGA. In Proceedings of the 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, p. 287–290. ISBN 978-0-7695-4494-6. [pdf]
BORECKÝ J. – VÍT P. – KUBÁTOVÁ H.: Self Repair Architectures Based on Partial Dynamic and Static Reconfiguration. In Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011, p. 11–18. ISBN 978-80-214-4305-1.
DAŇHEL M.: Hierarchical reliability block diagrams in the program SHAMAP. In POSTER 2011 - 15th International Student Conference on Electrical Engineering. Prague: CTU, Faculty of Electrical Engineering, 2011, p. 25–29. ISBN 978-80-01-04806-1.
DAŇHEL M. – KUBÁTOVÁ H.: Methods of hierarchical reliability block diagrams in the program SHAMAP. In Proceedings of the Work in Progress Session - DSD 2011. Oulu: University of Oulu, 2011, p. 31–32. ISBN 978-3-902457-30-1.
DAŇHEL M. D. – DOBIÁŠ R. D. – KUBÁTOVÁ H. K.: Hierarchické blokové modely. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, s. 44–49. ISBN 978-80-227-3552-0.
FIŠER P. – SCHMIDT J.: How Much Randomness Makes a Tool Randomized?. In Proc. of 20th International Workshop on Logic and Synthesis 2011. La Jolla: University of California San Diego, 2011, p. 136–143. [pdf]
HYNIOVÁ K. – HONCŮ J.: Theoretical Limitations in Vehicle System Dynamics. In Recent Researches in System Science. Athens: WSEAS Press, 2011, vol. 1, p. 48–53. ISBN 978-1-61804-023-7. [pdf]
CHLOUPEK M.: On Test Compression Based on Pattern Overlapping and Broadcasting. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 121–126. ISBN 978-80-227-3552-0.
CHLOUPEK M. – NOVÁK O.: Scan Chain Configuration Method for Broadcast Decompressor Architecture. In 12th IEEE Latin-American Test Workshop. New York: IEEE, 2011, p. 1–5. ISBN 978-1-4577-1489-4.
CHLOUPEK M. – NOVÁK O.: Test Pattern Compression Based on Pattern Overlapping and Broadcasting. In 2011 10th International workshop on Electronics, Control, Measurement and Signals (ECMS). New York: IEEE Computer Society Press, 2011, p. 1–5. ISBN 978-1-61284-397-1.
CHLOUPEK M. – NOVÁK O.: Test pattern compression based on pattern overlapping and broadcasting. In Proceeding of the 7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Brno University of Technology, 2011, p. 111. ISBN 978-80-214-4305-1.
JENÍČEK J. – NOVÁK O. – CHLOUPEK M.: Advanced Scan Chain Configuration Method for Broadcast Decompressor Architecture. In 9th IEEE EAST-WEST DESIGN & TEST SYMPOSIUM. Kharkiv: Kharkov National University of Radioelectronics, 2011, p. 140–143.
KUBÁTOVÁ H. – KUBALÍK P.: Fault-tolerant and fail-safe design based on reconfiguration. In Technology for Dependable Systems-on-Chip. Hershey, Pennsylvania: IGI Global, 2011, p. 175–194. ISBN 978-1-60960-212-3.
KYNCL J. – NOVOTNÝ M.: Education of Digital and Analog Circuits Supported by Computer Algebra System. In ISCAS 2011 Conference Proceedings. Piscataway: IEEE, 2011, p. 341–344. ISBN 978-1-4244-9472-9.
ŠTEMBERA P. – NOVOTNÝ M.: Breaking Hitag2 with Reconfigurable Hardware. In Proceedings of the 14th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2011, p. 558–563. ISBN 978-0-7695-4494-6.
VAŇÁT T. – KUBÁTOVÁ H.: SEU Experiments Using Real FPGAs. In POSTER 2011 - 15th International Student Conference on Electrical Engineering [CD–ROM]. Prague: CTU, Faculty of Electrical Engineering, 2011, ISBN 978-80-01-04806-1.
VAŇÁT T. – KUBÁTOVÁ H.: Experiments with Physical Error Injection into FPGA Circuits. In Proceedings of the Work in Progress Session - DSD 2011. Oulu: University of Oulu, 2011, p. 35–36. ISBN 978-3-902457-30-1.
VAŇÁT T. – KUBÁTOVÁ H.: Physical Injection of Errors Into the FPGA. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 103–108. ISBN 978-80-227-3552-0.
VÍT P.: Increasing Dependability by Fitting Circuit on FPGA. In Počítačové architektury & diagnostika. Bratislava: STU v Bratislave, 2011, p. 9–13. ISBN 978-80-227-3552-0.
VÍT P. – KUBÁTOVÁ H.: Impact of FPGA Technology Process on Depandability of Counters. In Proceedings of the Work in Progress Session - DSD 2011. Oulu: University of Oulu, 2011, p. 33–34. ISBN 978-3-902457-30-1.
VÍT P. – KUBÁTOVÁ H.: Using Decomposition to Create Fault Secure Counters of the Railway Station Safety Device. In POSTER 2011 - 15th International Student Conference on Electrical Engineering. Prague: CTU, Faculty of Electrical Engineering, 2011, ISBN 978-80-01-04806-1.

2010

BALACH J. – NOVÁK O.: Reconfigurable Fault-Tolerant System Synchronization. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 817–820. ISBN 978-0-7695-4171-6.
BALACH J. – NOVÁK O.: Reconfiguration Based Fault Tolerant Systems Design - Survey of Approaches. In 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS, 2010, p. 3–10. ISBN 978-80-87342-10-7.
BALCÁREK J.: Implicit Rrepresentations in Customized Testing of Digital Circuits. In Počítačové architektury & diagnostika. Brno: Vysoké učení technické v Brně, 2010, p. 15–20. ISBN 978-80-214-4140-8.
BALCÁREK J. - FIŠER P. - SCHMIDT J.: Implicit Representations in Test Patterns Compression for Scan-Based Digital Circuits. In Informal Proceedings of European Test Symposium. Praha: ČVUT v Praze, 2010. [pdf]
BALCÁREK J. - FIŠER P. - SCHMIDT J.: Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 805-808. ISBN 978-0-7695-4171-6. [pdf]
BENÁČEK P. - NOVOTNÝ M.: Implementing Brute-Force Attack on PRESENT Cipher. In Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010. Linz: Johannes Kepler University, 2010, p. 51-52. ISBN 978-3-902457-27-1.
BORECKÝ J. - KOHLÍK M. - KUBÁTOVÁ H.: How to Measure Dependability Parameters of Programmable Digital Circuits - A Survey. In 6th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: NOVPRESS, 2010, p. 28-35. ISBN 978-80-87342-10-7. [pdf]
BORECKÝ J. - KOHLÍK M. - KUBÁTOVÁ H. - KUBALÍK P.: Faults Coverage Improvement based on Fault Simulation and Partial Duplication. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 380-386. ISBN 978-0-7695-4171-6. [pdf]
BORECKÝ J. - KUBÁTOVÁ H.: Dependable Interconnection of Dependable Blocks. In Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010. Linz: Johannes Kepler University, 2010, p. 17-18. ISBN 978-3-902457-27-1.
FIŠER P. - SCHMIDT J.: It Is Better to Run Iterative Resynthesis on Parts of the Circuit. In Proceedings of the 19th International Workshop on Logic and Synthesis. Irvine, CA: University of California, Irvine, 2010, p. 17-24. [pdf]
FIŠER P. - SCHMIDT J.: New Ways of Generating Large Realistic Benchmarks for Testing Synthesis Tools. In Proceedings of the 9th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2010, p. 157-164. ISBN 978-3-86012-404-8. [pdf]
FIŠER P. - SCHMIDT J. - SEKANINA L. - VAŠÍČEK Z.: On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming. In Proc. of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems. Piscataway: IEEE, 2010, p. 346-351. ISBN 978-1-4244-6610-8. [pdf]
CHLOUPEK M.: Simple Heuristic for Broadcast Scan Chain Configuration. In Počítačové architektury & diagnostika. Brno: Vysoké učení technické v Brně, 2010, p. 39-44. ISBN 978-80-214-4140-8.
KOHLÍK M. - KUBÁTOVÁ H.: Model of Modular Secured Designs for Calculations of Availability. In Proceedings of the Work in Progress Session SEAA 2010 and DSD 2010. Linz: Johannes Kepler University, 2010, p. 15-16. ISBN 978-3-902457-27-1. [pdf]
LEMBERSKI I. - FIŠER P.: Area and Speed Oriented Implementations of Asynchronous Logic Operating Under Strong Constraints. In Proceedings of the 13th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2010, p. 155-162. ISBN 978-0-7695-4171-6. [pdf]
TOMAN D. - FIŠER P.: A SOP Minimizer for Logic Functions Described by Many Product Terms Based on Ternary Trees. In Proceedings of the 9th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2010, p. 165-172. ISBN 978-3-86012-404-8. [pdf]
VÍT P.: Návrh obvodů s volitelnou úrovní spolehlivosti na bázi FPGA. In Počítačové architektury & diagnostika. Brno: Vysoké učení technické v Brně, 2010, s. 87-90. ISBN 978-80-214-4140-8. [pdf]

2009

BALACH, J.: Synchronizace rekonfigurovatelného systému, In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 13-19. ISBN 978-80-7318-847-4.
BALCÁREK, J.: Test Patterns Compression Techniques Based on SAT Solving for Scan-Based Digital Circuits, In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 26-31. ISBN 978-80-7318-847-4.
BALCÁREK J. - FIŠER P. - SCHMIDT J.: On Properties of SAT Instances Produced by SAT-Based ATPGs. In Fifth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: neuveden, 2009, p. 3-10. ISBN 978-80-87342-04-6. [pdf]
BORECKÝ, J.: Dependable Universal Blocks (DUBs), In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 42-47. ISBN 978-80-7318-847-4.
BORECKÝ J. - KUBALÍK P. - KUBÁTOVÁ H.: Reliable Railway Station System based on Regular Structure implemented in FPGA. In Proc. of 12th EUROMICRO Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2009, p. 348-354. ISBN 978-0-7695-3782-5.
FIŠER, P. - TOMAN, D.: A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms, Proc. of 12th Euromicro Conference on Digital Systems Design (DSD'09), Patras (Greece), 27. - 29.8.2009, pp. 757-764 [pdf]
FIŠER P. - SCHMIDT J.: The Case for a Balanced Decomposition Process. In Proc. of 12th EUROMICRO Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2009, p. 601-604. ISBN 978-0-7695-3782-5. [pdf]
FIŠER P. - SCHMIDT J.: The Observed Role of Structure in Logic Synthesis Examples. In Proceedings of the International Workshop on Logic and Synthesis 2009. Berkeley, CA: IWLS Organizing Committee, 2009, p. 210-213. [pdf]
KOHLÍK, M.: Dependability models based on Petri nets and Markov chains, In Počítačové architektury & diagnostika. Soláň: Universita Tomáše Bati ve Zlíně, 2009, p. 95-103. ISBN 978-80-7318-847-4. [pdf]
KOHLÍK M. - KUBÁTOVÁ H.: Reconfiguration Strategy for FPGA Dependability Characteristics Improvement based on Stochastic Petri Net. In Proc. of 4th Descrete-Event System Design. Valencia: University of Valencia, 2009, p. 253-257. [pdf]
KVASNIČKA J. - KUBÁTOVÁ H.: Single Event Upset Tolerant FPGA Design. In Proceedings of the Work in Progress Session SEAA 2009 and DSD 2009. Linz: J. Kepler University - FAW, 2009, p. 37-38. ISBN 978-3-902457-25-7.
LEMBERSKI I. - FIŠER P.: Asynchronous Two-Level Logic of Reduced Cost. In Proc. of 12th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2009 (DDECS'09). Los Alamitos: IEEE Computer Society Press, 2009, p. 68-73. ISBN 978-1-4244-3339-1. [pdf]
LEMBERSKI I. - FIŠER P.: Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes. In Proc. of 4th Descrete-Event System Design. Valencia: University of Valencia, 2009, p. 213-218. [pdf]
KUBÁTOVÁ H.: Teaching Principles of Petri Nets in Hardware Courses and Student' Projects. In Handbook of Research on Discrete Event Simulation Environments: Technologies and Applications. Hershey: Information science Reference, 2009, p. 178-190. ISBN 978-1-60566-774-4.
NOVOTNÝ M.: COPACOBANA-Assisted Cryptanalysis of GSM Communication. In Fifth Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno, 2009, p. 236. ISBN 978-80-87342-04-6.

2008

DOBIÁŠ R. - FARAN A. - SCHRÖTTER J. - SRB S.: Digitalizace kolejových obvodů, Nová železniční technika. 2008, roč. 16, č. 5, s. 7-10. ISSN 1210-3942.
DOBIÁŠ R. - KONARSKI J. - KUBÁTOVÁ H.: Dependability Evaluation of Real Railway Interlocking Device. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 228-233. ISBN 978-0-7695-3277-6.
FIŠER P. - KUBÁTOVÁ H.: Column-matching based mixed-mode test pattern generator design technique for BIST. Microprocessors and Microsystems. 2008, vol. 32, no. 5-6, p. 340-350. ISSN 0141-9331.
FIŠER P. - KUBALÍK P. - KUBÁTOVÁ H.: An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 96-99. ISBN 978-0-7695-3277-6. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Scalable Test Pattern Generator Design Method for BIST. In Proc. of 9th IEEE Latin-American Test Workshop. Mexico City: INAOE, 2008, p. 69-74. [pdf]
FIŠER P. - RUCKÝ P. - VÁŇOVÁ I.: Fast Boolean Minimizer for Completely Specified Functions. In Proc. of 11th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2008 (DDECS'08). Los Alamitos: IEEE Computer Society Press, 2008, p. 122-127. ISBN 978-1-4244-2276-0. [pdf]
FIŠER P. - SCHMIDT J.: Small but Nasty Logic Synthesis Examples. In Proc. of 8th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2008, p. 183-190. ISBN 978-3-86012-346-1. [pdf]
FIŠER P. - TOMAN D.: BoolTool: A Tool for Manipulation of Boolean Functions. In Proc. of 8th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2008, p. 109-114. ISBN 978-3-86012-346-1. [pdf]
GENDRULLIS T. - NOVOTNÝ M. - RUPP A.: A Real-World Attack Breaking A5/1 within Hours, In Proceedings of the 10th Workshop on Cryptographic Hardware and Embedded Systems (CHES 2008). Heidelberg: Springer, 2008, vol. 5154, p. 266-282. ISBN 978-3-540-85052-6.
GUENEYSU T. - KASPER T. - NOVOTNÝ M. - PAAR C. - RUPP A.: Cryptanalysis with COPACOBANA, IEEE Transactions on Computers. 2008, vol. 57, no. 11, p. 1498-1513. ISSN 0018-9340.
KUBALÍK P. - KUBÁTOVÁ H.: Dependable design technique for system-on-chip. Journal of Systems Architecture. 2008, vol. 2008, no. 54, p. 452-464. ISSN 1383-7621.
KVASNIČKA J. - KUBALÍK P. - KUBÁTOVÁ H.: Experimental SEU Impact on Digital Design Implemented in FPGAs. In Proceedings of 11th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2008, p. 100-103. ISBN 978-0-7695-3277-6.
KVASNIČKA J. - KUBALÍK P. - KUBÁTOVÁ H.: Experimental emulation of FPGA bitstream faults in combinatorial circuits. In Proceedings of CSE 2008 International Scientific Conference on Computer Science and Engineering. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2008, vol. 1, p. 328-335. ISBN 978-80-8086-092-9. [pdf]
KVASNIČKA J. - KUBÁTOVÁ H.: Emulation of SEU Effect In Bitstream of FPGA. In 4th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science. Brno: Ing. Zdenek Novotny, CSc., 2008, p. 140-147. ISBN 978-80-7355-082-0. [pdf]
KVASNIČKA J.: FPGA bitstream analysis and emulation of SEU effect, In Počítačové architektury & diagnostika. Liberec: Technická univerzita v Liberci, 2008, p. 63-68. ISBN 978-80-7372-378-1. [pdf]
NOVÁK O. - PLÍVA Z. - JENÍČEK J. - MADER Z. - JARKOVSKÝ M.: A Self/Testing SoC with Reduced Memory Requirements, Acta Electrotechnica et Informatica. 2008, vol. 2008, no. 1, p. 22-31. ISSN 1335-8243.

2007

BEČVÁŘ M. - KAHÁNEK S.: VLIW-DLX simulator for educational purposes, 2007, In Proceedings of the 2007 Workshop on Computer Architecture Education. New York: ACM Press, 2007, s. 8-13. ISBN 978-1-59593-797-1.
DAVIDOVIČ T. - HAVLAN M. - NOVOTNÝ M. - SCHMIDT J. - BEZPALEC P.: Framework for Research of ECDSA. In Proceedings CD-ROM of Digital Technologies 2007. Žilina: Slovenská elektrotechnická společnost, 2007, ISBN 978-80-8070-786-6.
FARAN A. - MLNAŘÍK K. - SRB S. - BUKAČ P. - DOBIÁŠ R.: Method for a One-time Calibration of a Multiple Branches Digital Measurement System Working in Minimum Number of Branches Mode (Patent) 2007, Patent World Intellectual Property Organization, WO/2007/085208. 2007-08-02.
FARAN A. - SRB S. - VOTOČEK L. - KONARSKI J. - DOBIÁŠ R. - KRÁL J.: Method of the Phase-sensitive Evaluation of the Conductive Current of the Track Circuit (Patent), 2007, Patent World Intellectual Property Organization, WO/2007/016878. 2007-02-15.
FARAN A. - MLNAŘÍK K. - SRB S. - BUKAČ P. - DOBIÁŠ R.: Způsob jednorázové kalibrace digitální měřicí soustavy pracující v režimu minimálního počtu větví ze všech možných větví (Patent), 2007, Patent Úřad průmyslového vlastnictví, 297929. 2007-03-21.
FIŠER P.: Pseudo-Random Pattern Generator Design for Column Matching BIST. In Proceedings of 10th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2007, p. 657-663. ISBN 0-7695-2978-X. [pdf]
JENÍČEK J. - NOVÁK O.: Test Pattern Compression Based on Pattern Overlapping. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 29-34. ISBN 1-4244-1161-0.
KUBALÍK P. - KVASNIČKA J. - KUBÁTOVÁ H.: Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. In Design and Diagnostics of Electronic Circuits and Systems. Los Alamitos: IEEE Computer Society, 2007, p. 357-360. ISBN 1-4244-1161-0. [pdf]
KVASNIČKA J. - KUBALÍK P. - KUBÁTOVÁ H.: An FPGA based fault emulator. In Proceedings of the Work in Progress Session held in connection with the EUROMICRO Conferences SEAA and DSD 2007. Linz: Johannes Kepler University, 2007, p. 42-43. ISBN 978-3-902457-16-5. [pdf]
NOVÁK O.: Efficient Test Pattern Compression and Decompression System. In 43rd International Conference on Microelectronics, Devices and Material with the Workshop on Electronic Testing (MIDEM'07). Ribno at Bled: MIDEM, 2007, vol. 1, p. 147-152. ISBN 978-961-91023-7-4.
NOVÁK O.: COMPAS and Other Test Pattern Compression Methods. In Computer Science Reports. Cottbus: Brandenburg University of Technology at Cottbus, 2007, p. 1-6. ISSN 1437-7969.
NOVOTNÝ M. - SCHMIDT J.: General Digit-Serial Normal Basis Multiplier with Distributed Overlap. In Proceedings of 10th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2007, p. 94-101. ISBN 0-7695-2978-X. [pdf]
UBIK S. - ŽEJDL P. - HALÁK J.: Real-time anonymization in passive network monitoring, 2007, In Proceedings of the Third International Conference on Networking and Services. New York: IEEE Computer Society Press, 2007, s. 100-106. ISBN 0-7695-2858-9.

2006

BEČVÁŘ M. - KUBÁTOVÁ H. - NOVOTNÝ M.: Massive Digital Design Education for Large Amount of Undergraduate Students. In Proceedings of EWME 2006. Stockholm: Royal Institute of Technology, 2006, p. 108-111. ISBN 91-7178-402-0. [pdf]
BŮBELA T. - FARAN A. - SRB S. - DOBIÁŠ R.: Způsob kompenzace ohrožujících proudů emitovaných z trakčního pohonu silového obvodu hnacího železničního vozidla do kolejového obvodu a zapojení kompenzátoru k provádění tohoto způsobu (Patent), 2006, Patent Úřad průmyslového vlastnictví, 297154. 2006-08-03.
DAVIDOVIČ T. - HAVLAN M. - NOVOTNÝ M. - SCHMIDT J.: Implementation of ECDSA in Combo6X Card. In Digital Technologies 2006 - 3rd International Workshop [CD-ROM]. Žilina: University of Žilina, Fakulty of electrical engineering, 2006, vol. 1, ISBN 80-8070-637-9.
FARAN A. - SRB S. - VOTOČEK L. - KONARSKI J. - DOBIÁŠ R. - KRÁL J.: Způsob fázově citlivého vyhodnocení konduktivního proudu kolejového obvodu (Patent), 2006, Patent Úřad průmyslového vlastnictví, 297442. 2006-11-01.
FIŠER P. - KUBALÍK P. - KUBÁTOVÁ H.: Output Grouping Method Based on a Similarity of Boolean Functions. In Proceedings of the 7th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2006, p. 107-113. ISBN 3-86012-287-8. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Multiple-Vector Column-Matching BIST Design Method. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 268-273. ISBN 1-4244-0184-4. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Flexible Two-Level Boolean Minimizer BOOM II and Its Applications. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 369-376. ISBN 0-7695-2609-8. [pdf]
KAFKA L. - NOVÁK O.: FPGA-based Fault Simulator, 2006, In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, s. 274-278. ISBN 1-4244-0184-4.
KUBALÍK P. - DOBIÁŠ R. - KUBÁTOVÁ H.: Dependability Computation for Fault Tolerant Reconfigurable Duplex System. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 100-102. ISBN 1-4244-0184-4.
KUBALÍK P. - DOBIÁŠ R. - KUBÁTOVÁ H.: Dependable Design for FPGA based on Duplex System and Reconfiguration. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 139-145. ISBN 0-7695-2609-8.
KUBALÍK P. - FIŠER P. - KUBÁTOVÁ H.: Fault Tolerant System Design Method Based on Self-Checking Circuits. In Proceedings IOLTS 2006 12th IEEE International On-Line Testing Symposium. Los Alamitos: IEEE Computer Society, 2006, p. 185-186. ISBN 0-7695-2620-9. DOI: 10.1109/IOLTS.2006.37
KUBALÍK P. - KUBÁTOVÁ H.: Design Methodology for High Reliable System. In Proceedings of the Seventh International Scientific Conference on Electronic Computers and Informatics ECI 2006. Košice: Technická univerzita v Košiciach, 2006, vol. 1, p. 274-279. ISBN 80-8073-598-0.
KUBÁTOVÁ H.: Teaching Principles of Petri Nets in Hardware Courses and Student's Projects. In Workshop on Teching Concurrency. Lisboa: University of Lisbon, 2006, p. 61-75.
KVASNIČKA J.: Vliv poruch v bitsreamu na funkci obvodů v FPGA. In Počítačové architektúry a diagnostika. Bratislava: Ústav informatiky SAV, 2006, s. 89-94. ISBN 80-969202-2-7.
NOVÁK O. - PLÍVA Z.: Scan Based Circuits with Low Power Consumption. In Proceedings of the IEEE East-West Design & Test International Workshop. Kharkov: Kharkov Institute of Physics and Technology, 2006, vol. 1, p. 206-211. ISBN 966-659-124-3.
NOVÁK O. - PLÍVA Z. - JENÍČEK J. - MADER Z. - JARKOVSKÝ M.: Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. In The 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems. Los Alamitos: IEEE Computer Society, 2006, vol. 1, p. 300-308. ISBN 0-7695-2706-X.
NOVOTNÝ M. - SCHMIDT J.: Normal Basis Multipliers of General Digit Width Applicable in ECC. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 145-146. ISBN 1-4244-0184-4.
NOVOTNÝ M. - SCHMIDT J.: General Digit Width Normal Basis Multipliers with Circular and Linear Structure. In International Conference on Field Programmable Logic and Applications. Piscataway: IEEE, 2006, p. 873-876. ISBN 1-4244-0312-X.
NOVOTNÝ M. - SCHMIDT J.: Two Architectures of a General Digit-Serial Normal Basis Multiplier. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 550-553. ISBN 0-7695-2609-8.
ŠŤÁVA M.: A Backtracing Unit Implemented in FPGA. In POSTER 2006. Prague: CTU, 2006.
ŠŤÁVA M. - NOVÁK O.: An Illustrative Case Study of Backward Determination of Input Vectors by HW. In Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems. Ostrava: MARQ, 2006, vol. 1, p. 253-258. ISBN 80-86840-21-2.
ŠŤÁVA M. - NOVÁK O.: Using Conflict-Based On-line Learning to Accelerate the Backtrace Algorithm Implemented in HW. In Proceedings of 9th Euromicro Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2006, p. 251-256. ISBN 0-7695-2609-8.
ŠŤÁVA M. - NOVÁK O.: Reconfiguration of the Backtrace Algorithm Implemented in HW to Speed up a Vector Generation Process. In Proceedings of the 2006 IEEE-TTTC International Conference on Automation, Quality and Testing, Robotics. Piscataway: IEEE, 2006, vol. 2, p. 59-64. ISBN 1-4244-0360-X.
ŠŤÁVA M. - NOVÁK O.: A Structure Model for Input Vector Determination of Combinational Circuits and Its Simulation. In Proceedings of 40th Spring International Conference MOSIS 06, Modelling and Simulation of Systems. Ostrava: MARQ, 2006, vol. 1, p. 51-57. ISBN 80-86840-21-2.
ŠŤÁVA M. - NOVÁK O.: HW Implementation of the Backtrace Algorithm. In IEEE European Test Symposium Informal Digest of Papers. Southampton: University of Southampton, 2006, vol. 1, p. 75-80.
ŠŤÁVA M. - NOVÁK O.: HW Implementation of the Backtrace Algorithm with Conflict-Driven Dynamic Reconfiguration. In Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Praha: CTU Publishing House, 2006, vol. 1, p. 250-252. ISBN 1-4244-0184-4.
ŠŤÁVA M. - NOVÁK O.: Implementation of the Backtrace Algorithm in an FPGA. In Proceedings of Workshop 2006. Prague: CTU, 2006, p. 256-257. ISBN 80-01-03439-9.

2005

BEČVÁŘ M. - ŠTUKJUNGER P.: Fixed-Point Arithmetic in FPGA. Acta Polytechnica. 2005, vol. 45, no. 2, p. 67-72. ISSN 1210-2709.
DOBIÁŠ R.: Fail-Safe System Design. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 33-38. ISBN 80-01-03298-1.
DOBIÁŠ R. - KUBÁTOVÁ H.: The Reliability and Safety Modelling for Safety Critical Application. In Proceedings of Workshop 2005 - Part A,B. Prague: CTU, 2005, vol. 9, p. 218-219. ISBN 80-01-03201-9.
DOBIÁŠ R. - KUBALÍK P. - KUBÁTOVÁ H.: Dependability Computations for Fault-Tolerant System Based on FPGA. In Proceedings of the 12th International Conferrence on Electronics, Circuits and Systems. Monterey: IEEE Circuits and Systems Society, 2005, vol. 1, p. 377-380. ISBN 9973-61-100-4. [pdf]
DOBIÁŠ R. - KUBÁTOVÁ H.: The Common 2oo2 Safety Model for Signalling and Interlocking Equipments. In Electronic Circuits and Systems Conference. Bratislava: FEI, Slovak University of Technology, 2005, p. 81-84.
DOBIÁŠ R. - KUBÁTOVÁ H.: Fail-Safe System Architectures. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 47-48. ISBN 3-902457-09-0.
FARAN A. - MLNAŘÍK K., SRB S. - BUKAČ P. - DOBIÁŠ R.: Způsob bezpečného vyhodnocování volnosti kolejového úseku s ohledem na zvýšení odolnosti proti rušivým vlivům a zapojení kolejového obvodu k provádění tohoto způsobu (Patent), 2005, Patent Úřad průmyslového vlastnictví, 296242. 2005-12-20.
FIŠER P.: Mixed-Mode BIST Based on Column Matching. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 45-50. ISBN 80-01-03298-1.
FIŠER P. - KUBÁTOVÁ H.: Pseudorandom Testability - Study of the Effect of the Generator Type. Acta Polytechnica. 2005, vol. 45, no. 2, p. 47-54. ISSN 1210-2709.
FIŠER P. - KUBÁTOVÁ H.: Output Grouping-Based Decomposition of Logic Functions. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 137-144. ISBN 963-9364-48-7. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Improvement of the Fault Coverage of the Pseudo-Random Phase in Column Matching BIST. In Proceedings Eighth EUROMICRO Conference on Digital System Design. Los Alamitos: IEEE Computer Society, 2005, p. 56-63. ISBN 0-7695-2433-8. DOI: 10.1109/DSD.2005.51
KAFKA L. - KUBALÍK P. - KUBÁTOVÁ H. - NOVÁK O.: Fault Classification for Self-checking Circuits Implemented in FPGA. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 228-231. ISBN 963-9364-48-7. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: Reconfigurable Duplex System Increasing Fault Tolerance for Circuits Based on FPGAs. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 13-14. ISBN 3-902457-09-0. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: Highly Reliable Design Based on TSC Circuits. In Počítačové architektury & diagnostika. Prague: CTU, Faculty of Electrical Engineering, Department of Computer Science and Engineering, 2005, vol. 1, p. 101-106. ISBN 80-01-03298-1.
KUBALÍK P. - KUBÁTOVÁ H.: Parity Codes Used for On-line Testing in FPGA. Acta Polytechnica. 2005, vol. 45, no. 6, p. 53-59. ISSN 1210-2709.
KUBÁTOVÁ H.: Modeling by Petri Nets . Acta Polytechnica. 2005, vol. 45, no. 2, p. 5-13. ISSN 1210-2709.
KUBÁTOVÁ H.: Finite State Machine Implementation in FPGAs. In Design of Embedded Control Systems. New York: Springer, 2005, p. 175-184. ISBN 0-387-23630-9.
KUBÁTOVÁ H. - NOVOTNÝ M.: Contemporary Methods of Digital Design Education. In Electronic Circuits and Systems Conference. Bratislava: FEI, Slovak University of Technology, 2005, p. 115-118. [pdf]
MAREK T. - PLUHÁČEK A.: Multiplier Execution Latency Reduction Using Variable Latency Pipeline. In Proceedings of the Work in Progress Session. Linz: Johannes Kepler University, 2005, p. 13-14. ISBN 3-902457-09-0.
NOVÁK O.: Self-test in logic blocks, In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, s. 268. ISBN 963 9364 48 7.
NOVÁK O. - GRAMATOVÁ E. - UBAR R. - PLÍVA Z. - PLESKACZ W. - MOSIN S. - STOPJAKOVÁ V. - HLAWICZKA A. - GARBOLINO T. - GUCZWA K. - FIŠEROVÁ M. - PLEŠTIL A. - KOTÁSEK Z. - DRÁBEK V.: Handbook of Electronic Testing. 1. ed. Praha: Vydavatelství ČVUT, 2005. 405 p. ISBN 80-01-03318-X.
NOVÁK O. - GRAMATOVÁ E. - UBAR R.: IST project REASON - Handbook of Testing Electronic Systems, 2005, In EDCC-5 Suplementary volume. Budapest: Technical University, 2005, s. 15-18.
NOVÁK O. - MADER Z.: SOC Diagnostic System Using the RESPIN Architecture. In Proceedings of the IFIP International Conference on Very Large Scale Integration System-onChip. Perth: Curtin University of Technology, 2005, vol. 1, p. 344-349. ISBN 0-7298-0610-3.
NOVÁK O. - ZAHRÁDKA J.: Test Pattern Compression for Circuits with the RESPIN Architecture. In IEEE European Test Symposium Informal Digest of Papers. Tallinn: Tallinn Technical University, 2005, vol. 1, p. 141-146.
NOVOTNÝ M. - SCHMIDT J.: General Digit-Serial Normal Basis Multiplier. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Sopron: University of Western Hungary, 2005, p. 99-104. ISBN 963-9364-48-7.
PROX J. - DOUŠA J.: SIMNET: Computer Network Simulator. In Proceedings of XXVII International Autumn Colloquium. Ostrava: MARQ, 2005, p. 132-137. ISBN 80-86840-16-6.
SCHMIDT J.: Investigation of Cellular Automata for Diagnostic Purposes. In Proceedings of Workshop 2005. Prague: CTU, 2005, ISBN 80-01-03201-9.
SCHMIDT J. - NOVOTNÝ M.: Scalable Normal Basis Aritmetic Unit for Elliptic Curve Cryptography. Acta Polytechnica. 2005, vol. 45, no. 2, p. 55-60. ISSN 1210-2709.
ŠŤÁVA M. - NOVÁK O.: Zpětné odvození vstupních vektorů kombinačního obvodu ze znalosti výstupních vektorů pomocí HW. In Počítačové architektury & diagnostika. Praha: ČVUT FEL, Katedra počítačů, 2005, díl 1, s. 153-158. ISBN 80-01-03298-1.
ŠŤÁVA M. - NOVÁK O.: How to Use the Reconfiguration at the Backtrace Implemented in an FPGA. In Sborník příspěvků konference Vršov 2005. Brno: VUT v Brně, FEKT, 2005, p. 168-171. ISBN 80-214-3008-7.
ŠŤÁVA M. - NOVÁK O.: Zpětná logická simulace pro odvození vstupních vektorů kombinačního obvodu pomocí HW. In Proceedings of XXVII International Autumn Colloquium. Ostrava: MARQ, 2005, s. 215-220. ISBN 80-86840-16-6.
ULRICH J. - DOUŠA J.: SIMCP_PAR2: Event Oriented Parallel and Pseudo-Parallel Simulator. In Simulation Almanac 2005. Praha: Ediční středisko ČVUT, 2005, p. 132-141. ISBN 80-01-03322-8.

2004

DOBIÁŠ R.: Stanovení spolehlivosti a bezpečnosti pro systémy odolné a bezpečné proti poruše. In Počítačové architektúry a diagnostika. Bratislava: Ústav informatiky SAV, 2004, s. 16-21. ISBN 80-969202-0-0.
DOBIÁŠ R. - GRILLINGER P. - RACEK S.: Using Markov Models for Evaluation of Single Event Upset in TTP/C Systems. In Proceedings of IFAC Workshop on Programmable Devices and Systems. Gliwice: Silesian Technical University, 2004, p. 100-104. ISBN 83-908409-8-7.
DOBIÁŠ R. - KUBÁTOVÁ H.: FPGA Based Design of Raiway's Interlocking Equipment. In EUROMICRO Symposium on Digital System Design. Piscataway: IEEE, 2004, p. 467-473. ISBN 0-7695-2203-3. [pdf]
DOBIÁŠ R. - KUBÁTOVÁ H.: Reliability Characteristic's Computations for Railway Crossing Interlocking Equipment. In Proceedings of Workshop 2004. Prague: CTU, 2004, vol. A, p. 228-229. ISBN 80-01-02945-X.
DOUŠA J. - ULRICH J.: Parallel Strategies and Simulation. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 347-352. ISBN 80-8073-150-0.
DOUŠA J. - VŠETEČKA J.: Parallel and Process Oriented Simulation System. In Proceedings of 38th International Conference MOSIS '04. Ostrava: MARQ, 2004, p. 21-27. ISBN 80-85988-98-4.
FIŠER P. - KUBÁTOVÁ H.: An Efficient Mixed-Mode BIST Technique. In DDECS - Proceedings of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Stará Lesná: Institute of Informatics, Slovak Akademy of Sciences, Bratislava, 2004, p. 227-230. ISBN 80-969117-9-1. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Two-Level Boolean Minimizer BOOM-II. In Boolean Problems - 6th International Workshop. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2004, p. 221-228. ISBN 3-86012-233-9. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Influence of the Test Lengths on Area Overhead in Mixed-Mode BIST. In Proceedings of the 9th Biennial Baltic Electronics Conference. Tallinn: Tallinn Technical University, 2004, p. 201-204. ISBN 9985-59-462-2. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Boolean Minimizer FC-Min: Coverage Finding Process. In EUROMICRO Symposium on Digital System Design. Piscataway: IEEE, 2004, p. 152-159. ISBN 0-7695-2203-3. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Pseudorandom Testability - Study of the Effect of the Generator Type. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 200-205. ISBN 80-8073-150-0. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Survey of the Algorithms in the Column-Matching BIST Method. In 10th IEEE International On-Line Testing Symposium - IOLTS 2004. Piscataway: IEEE, 2004, p. 181. ISBN 0-7695-2180-0. [pdf]
FIŠER P. - KUBÁTOVÁ H.: Single-Level Partitioning Support in BOOM-II. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 149-154. ISBN 83-89712-15-6. [pdf]
KUBALÍK P. - FIŠER P. - KUBÁTOVÁ H.: Minimization of the Hamming Code Generator in Self Checking Circuits. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 161-166. ISBN 83-89712-15-6. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: High Reliable FPGA Based System Design Methodology. In Work in Progress Session of 30th EUROMICRO and DSD 2004. Linz: Universität Linz, 2004, p. 30-31. ISBN 3-902457-05-8. [pdf]
KUBALÍK P. - KUBÁTOVÁ H.: On-line Testing for FPGA. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 194-199. ISBN 80-8073-150-0. [pdf]
KUBÁTOVÁ H.: Direct Implementation of Petri Net Based model in FPGA. In Proceedings of the International Workshop on Discrete-Event System Design - DESDes'04. Zielona Gora: University of Zielona Gora, 2004, p. 31-36. ISBN 83-89712-15-6. [pdf]
KUNEŠ M. - KUBÁTOVÁ H. - DANĚK M.: Partitioning Problem in HW/SW Codesign. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 206-211. ISBN 80-8073-150-0.
MAREK T. - NOVOTNÝ M. - CRHA L.: Design and Implementation of the Memory Scheduler for the PC-Based Router, 2004, In Field Programmable Logic and Applications - FPL2004. Berlin: Springer, 2004, s. 1133-1135. ISBN 3-540-22989-2.
NOVOTNÝ M.: Scalable Normal Basis Multipliers. In Počítačové architektúry a diagnostika. Bratislava: Ústav informatiky SAV, 2004, p. 7-12. ISBN 80-969202-0-0.
NOVOTNÝ M. - SCHMIDT J.: The Finite State Machine in Fairy Tale World. In Workshop 2004. Prague: CTU, 2004, vol. A, p. 310-311. ISBN 80-01-02945-X.
NOVOTNÝ M. - SCHMIDT J.: Optimization of Shifter in Normal Basis Arithmetic Unit. In Workshop 2004. Prague: CTU, 2004, vol. A, p. 326-327. ISBN 80-01-02945-X.
NOVOTNÝ M. - SCHMIDT J.: Cryptographic Hardware Scalable Aritmetic Unit. In Workshop 2004. Prague: CTU, 2004, vol. A, p. 324-325. ISBN 80-01-02945-X.
PLUHÁČEK A.: Korobovův kód a návrh čítačů. In Informatika a informačné technológie 2004. Banská Bystrica: Univerzita Mateja Bela, 2004, s. 136-141. ISBN 80-8083-017-7.
SCHMIDT J. - NOVOTNÝ M.: Scalable Shifter Synthesis for a Finite Field Arithmetic Unit. In DDECS - Proceedings of 7th IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Stará Lesná: Institute of Informatics, Slovak Akademy of Sciences, Bratislava, 2004, p. 195-198. ISBN 80-969117-9-1.
ULRICH J. - DOUŠA J.: Virtual Processor for Event Oriented Optimistic Parallel Simulation. In Proceedings of the Sixth International Scientific Conference Electronic Computers and Informatics ECI 2004. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2004, p. 253-258. ISBN 80-8073-150-0.

2003

BEČVÁŘ M. - PLUHÁČEK A. - DANĚČEK J.: DOP - a CPU Core for Teaching Basics of Computer Architecture, 2003, In Proceedings of the Workshop on Computer Architecture Education (WCAE 2003). New York: ACM, 2003, s. 14-21.
BEČVÁŘ M. - PLUHÁČEK A. - DANĚČEK J.: DOP - A Simple Processor Core for Educational Purposes, 2003, In Programmable Devices and Systems 2003. Oxford: Elsevier Science, 2003, vol. 1, s. 208-213. ISBN 0-08-044130-0.
BEČVÁŘ M.: Optimization of Simple CPU Core for FPGA. In Proceedings of Workshop 2003 (online). Prague: CTU, 2003, vol. A, p. 354-355. ISBN 80-01-02708-2.
DANĚK M. - KUBÁTOVÁ H. - MUZIKÁŘ Z.: Evolutionary Techniques in Physical Design for FPGAs. In Proceedings of Workshop 2003. Prague: CTU, 2003, vol. A, p. 306-307. ISBN 80-01-02708-2.
FIŠER P. - HLAVIČKA J.: BOOM - A Heuristic Boolean Minimizer, 2003, Computing and Informatics. 2003, vol. 22, no. 1, s. 19-51. ISSN 1335-9150.
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: CD-A Based BIST Method, 2003, In ECMS 2003. Liberec: Technical University, 2003, s. 279-283. ISBN 80-7083-708-X. [pdf]
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: Column-Matching BIST Exploiting Test Don't-Cares, 2003, In ETW 2003. Maastricht: IEEE Computer Society TTTC, 2003, s. 215-216. ISBN 0-7695-1908-3. [pdf]
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: Coverage-Directed Assignment Approach to BIST, 2003, In Proceedings of IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems. Poznaň: University of Technology, 2003, s. 87-92. ISBN 83-7143-557-6. [pdf]
FIŠER P. - HLAVIČKA J. - KUBÁTOVÁ H.: FC-Min: A Fast Multi-Output Boolean Minimizer, 2003, In DSD 2003 - EUROMICRO Symposium on Digital System Design. Los Alamitos: IEEE Computer Society Press, 2003, s. 451-454. ISBN 0-7695-2003-0. [pdf]
FIŠER P. - HLAVIČKA J.: A Flexible Minimization and Partitioning Method. In Proceedings of Workshop 2003 (online). Prague: CTU, 2003, vol. A, p. 312-313. ISBN 80-01-02708-2.
KUBALÍK P. - KUBÁTOVÁ H.: Design of Self Checking Circuits Based on FPGA, 2003, In Proceedings of the 15th International Conference on Microelectronics. Cairo: Cairo University, 2003, s. 378-381. ISBN 977-05-2010-1. [pdf]
KUBALÍK P. - BUČEK J.: FPGA Implementation of USB 1.1 Device Core. In Poster 2003. Prague: CTU, Faculty of Electrical Engineering, 2003, p. IC22.
KUBÁTOVÁ H.: Direct Hardware Implementation of Petri Net Based Model, 2003, In Proceedings of the Work in Progress Session of EUROMICRO 2003. Linz: J. Kepler University - FAW, 2003, s. 56-57. ISBN 3-902457-21-X.
KUBÁTOVÁ H.: Petri Net Models in Hardware, 2003, In ECMS 2003. Liberec: Technical University, 2003, s. 158-162. ISBN 80-7083-708-X.
KUBÁTOVÁ H. - HLAVIČKA J., RACEK S., KOLÁŘ J.: Fault Injection for Time Triggered Architecture (FIT). In Proceedings of Workshop 2003. Prague: CTU, 2003, vol. A, p. 352-353. ISBN 80-01-02708-2.
SCHMIDT J. - NOVOTNÝ M.: Normal Basis Multiplication and Inversion Unit for Elliptic Curve Cryptography, 2003, In Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2003, s. 82-85. ISBN 0-7803-8163-7.
SCHMIDT J. - NOVOTNÝ M.: Optimum Shifter Synthesis Using a Genetic Algorithm, 2003, In Recent Trends in Multimedia Information Processing. Praha: Sdělovací technika, 2003, vol. 1, s. 146-149. ISBN 80-86645-05-3.
SCHMIDT J. - NOVOTNÝ M.: Scalable Multiplication and Inversion Unit for ECDSA, 2003, In Programmable Devices and Systems 2003. Oxford: Elsevier Science, 2003, vol. 1, s. 226-231. ISBN 0-08-044130-0.
SCHMIDT J. - NOVOTNÝ M.: Exploration of Design Space in ECDSA. In Proceedings of Workshop 2003. Prague: CTU, 2003, vol. A, p. 318-320. ISBN 80-01-02708-2.

2002

DANĚK M. - MUZIKÁŘ Z.: Integrated Iterative Approach to FPGA Placement. In Field-Programmable Logic and Applications - FPL2002. Berlin: Springer, 2002, p. 253-262. ISBN 3-540-44108-5.
DANĚK M. - MUZIKÁŘ Z.: Integrated Timing-Driven Approach to the FPGA Layout. In The 9th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2002, p. 693-696. ISBN 0-7803-7596-3.
DOUŠA J.: Thread Oriented Discrete Event Simulation System. In Proceedings of the Fifth International Scientific Conference - Electronic Computers and Informatics 2002. Košice: Vienala, 2002, p. 216-220. ISBN 80-7099-879-2.
FIŠER P. - HLAVIČKA J.: A Flexible Minimization and Partitioning Method. In 5th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2002, p. 83-90. ISBN 3-86012-180-4. [pdf]
FIŠER P. - HLAVIČKA J.: A Set of Logic Design Benchmarks. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, p. 324-327. ISBN 80-214-2094-4. [pdf]
FIŠER P. - HLAVIČKA J.: Column-Matching Based BIST Design Method. In ETW'02 - 7th IEEE European Test Workshop. Athens: University of Athens, 2002, p. 15-16. [pdf]
HLAVIČKA J. - FIŠER P.: Minimization and Partitioning Method Reducing Input Sets. In The First IEEE International Workshop on Electronic Design, Test, and Applications 2002. Los Alamitos: IEEE Computer Society Press, 2002, p. 434-436. ISBN 0-7695-1453-7. [pdf]
JÁCHIM M. - JÄGER M. - BEČVÁŘ M.: Elliptic Coprocessor GF(2^162]. In POSTER 2002 - Book of Extended Abstracts. Prague: CTU, Faculty of Electrical Engineering, 2002, p. IC24.
JÁCHIM M. - JÄGER M. - BEČVÁŘ M.: Tuning up the PCI Devices. In POSTER 2002 - Book of Extended Abstracts. Prague: CTU, Faculty of Electrical Engineering, 2002, p. IC25.
KUBÁTOVÁ H. - JELINEK R.: Digital Testing and Reliability Education (DTRE) Computer Tool. In The 9th IEEE International Conference on Electronics, Circuits and Systems. Piscataway: IEEE, 2002, p. 1227-1230. ISBN 0-7803-7596-3.
KUBÁTOVÁ H.: DTRE - Digital Testing and Reliability Education Tool. In Proceedings of the Fifth International Scientific Conference - Electronic Computers and Informatics 2002. Košice: Vienala, 2002, p. 148-153. ISBN 80-7099-879-2.
KUBÁTOVÁ H. - BEČVÁŘ M.: FEL-Code: FSM Internal State Encoding Method. In 5th International Workshop on Boolean Problems. Freiberg: Technische Universität Bergakademie, 2002, p. 109-114. ISBN 3-86012-180-4.
KUBÁTOVÁ H.: How to Obtain Better Implementation of FSM in FPGA. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, p. 332-335. ISBN 80-214-2094-4.
SCHMIDT J. - NOVOTNÝ M. - JÄGER M. - BEČVÁŘ M. - JÁCHIM M.: Comparison of the Polynomial and Optimal Normal Basis ECDSA for GF(2^162). In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop 2002. Brno: University of Technology, 2002, p. 150-157. ISBN 80-214-2094-4.
SCHMIDT J. - NOVOTNÝ M. - JÄGER M. - BEČVÁŘ M. - JÁCHIM M.: Exploration of Design Space in ECDSA. In Field-Programmable Logic and Applications - FPL2002. Berlin: Springer, 2002, p. 1072-1075. ISBN 3-540-44108-5.

2001

BEČVÁŘ M. - JÁCHIM M. - JÄGER M.: Case Study: FPGA Acceleration of CRC Computation. In IFAC Workshop on Programmable Devices and Systems PDS2001. Gliwice: IESUT, 2001, p. 218-223.
BEČVÁŘ M. - SCHMIDT J.: Reconfigurable Acceleration of Intel PC: A Quantitative Analysis. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Gyor: Széchenyi István University of Applied Sciences, 2001, p. 93-96. ISBN 963-7175-16-4.
DANĚČEK J.: Programovací systém MiniJava. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, s. 162-168. ISBN 80-7099-705-2.
ELSHAFEY K. - SCHMIDT J. - HLAVIČKA J.: Design and Analysis of a Suitable Serial Approach to CORDIC Magnitude Processor in an FPGA. In Poster 2001. Prague: CTU, Faculty of Electrical Engineering, 2001, p. IC9.
ELSHAFEY K. - HLAVIČKA J. - SCHMIDT J.: A Comparison of Serial and Parallel Approaches to FPGA Implementations of Arithmetic Functions. In Proceedings of Workshop 2001. Prague: CTU, 2001, vol. A, p. 202-203. ISBN 80-01-02335-4.
FIŠER P. - HLAVIČKA J.: Implicant Expansion Methods Used in the Boom Minimizer. In Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop. Gyor: Széchenyi István University of Applied Sciences, 2001, p. 291-298. ISBN 963-7175-16-4. [pdf]
FIŠER P., HLAVIČKA J., FIŠER P. - HLAVIČKA J.: On the Use of Mutations in Boolean Minimization. In EUROMICRO Symposium on Digital Systems Design. Los Alamitos: IEEE Computer Society Press, 001, p. 300-307. ISBN 0-7695-1239-9. [pdf]
HLAVIČKA J. - FIŠER P.: A Heuristic Method of Two-Level Logic Synthesis. In World Multiconference on Systemics, Cybernetics and Informatics. Orlando: IIIS - International Institute of Informatics and Systemics, 2001, vol. 2, p. 283-288. ISBN 980-07-7552-8. [pdf]
HLAVIČKA J. - FIŠER P.: BOOM - a Heuristic Boolean Minimizer. In IEEE/ACM International Conference on CAD-01. Monterey: IEEE Circuits and Systems Society, 2001, p. 439-442. ISBN 0-7803-7247-6. [pdf]
JÁCHIM M. - SCHMIDT J.: Speeding up the SDRAM Controller Macro-block. In International Conference Applied Electronics 2001. Pilsen: University of West Bohemia, 2001, p. 126-129. ISBN 80-7082-758-0.
KUBÁTOVÁ H.: Hardware Implementation and Simulation of Petri Nets. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, p. 103-106. ISBN 80-7099-705-2.
KUBÁTOVÁ H.: Implementation of the FSM into FPGA. In Proceedings of the International Workshop on Discrete-Event System Design. Zielona Góra: Oficyna Wydawnicza Politechniki Zielonogórskiej, 2001, p. 141-146. ISBN 83-85911-62-6.
KUBÁTOVÁ H.: Optimal Implementation of FSM in FPGA. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, p. 107-110. ISBN 80-7099-705-2.
KUBÁTOVÁ H.: Petri Net Simulation Using FPGA. In Proceedings of XXIIIrd International Autumn Colloquium. Ostrava: MARQ, 2001, p. 129-134. ISBN 80-85988-61-5.
PLUHÁČEK A. - DOUŠA J. - DANĚČEK J. - BEČVÁŘ M.: Návrh procesorů ve výuce. In Proceedings of the Computer Science Education Workshop 2001. Košice: Department of Computers and Informatics of FEI, Technical University Košice, 2001, s. 152-156. ISBN 80-7099-705-2.

2000

BEČVÁŘ M.: Advantage of using FPGA for Implemntation of Interfaces in the VoN Applications, 2000, In Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: POLYGRAFIA SAV, 2000, p. 178-181. ISBN 80-968320-3-4.
FIŠER P. - HLAVIČKA J.: Efficient Minimization Method for Incompletely Defined Boolean Functions, 2000, In 4th International Workshop on Boolean Problems. Freiberg: Freiberg University of Mining and Technology, Institute of Computer Science, 2000, p. 91-98. ISBN 3-86012-124-3. [pdf]
HLAVIČKA J. - FIŠER P.: Algorithm for Minimization of Partial Boolean Functions, 2000, In Proceedings of Design and Diagnostics of Electronic Circuits and Systems Workshop. Bratislava: POLYGRAFIA SAV, 2000, p. 130-133. ISBN 80-968320-3-4.
KOLÁŘ J. - MÜLLER K. - PLUHÁČEK A.: Structured Study and CS&E Curriculum at the Faculty of Electrical Engineering, CTU Prague, 2000, In Proceedings of the Computer Science Education Workshop. Prague: CTU, 2000, p. 38-41. ISBN 80-01-02264-1.
KUBÁTOVÁ H. - ANDRLE J.: Predikce průběhu EKG pomocí neuronové sítě, 2000, In Modelling and Simulation of Systems - Modelling in Manager Work. Ostrava: MARQ, 2000, p. 167-172. ISBN 80-85988-46-1.
KUBÁTOVÁ H., HRDÝ T.: PROKEŠ M., State Encoding of the FSM with the Relation to its Implementation by FPGA, 2000, In Proceedings of the Fourth International Scientific Conference Electronic Computers and Informatics 2000. Košice: TU Košice, FEI, 2000, p. 183-188. ISBN 80-88922-25-9.
NOVÁK O. - HLAVIČKA J.: An Efficient Deterministic Test Pattern Compaction Scheme using Modified IC Scan Chain, 2000, In ETW 2000 - IEEE European Test Workshop. Lisboa: INESC-ID, 2000, p. 305-306.
PLUHÁČEK A.: A Simple Way to Evaluate Logarithms, 2000, In Proceedings of the Fourth International Scientific Conference Electronic Computers and Informatics 2000. Košice: TU Košice, FEI, 2000, p. 62-67. ISBN 80-88922-25-9.

1999

DANĚČEK J. - ROZEHNAL Z.: New Language for Programmable Control Logic. In Proceedings of the 4th International Workshop on ECMS'99. Liberec: Technical University, 1999, p. 80-83. ISBN 80-7083-339-4.
DANĚČEK J. - SLAVÍK P.: Teaching Java at CTU Prague. In Proceedings of Java in Computing Curriculum 3. London: South Bank University, 1999, p. 1-7.
DANĚK M. - MUZIKÁŘ Z.: Global Routing Models. In Field-Programmable Logic and Applications. Berlin: Springer, 1999, p. 391-395. ISBN 3-540-66457-2.
DOUŠA J. - HOLUB A.: Performance Simulation of Local Area Networks. In Proceedings of the First International Conference on Advanced Engineering Design. Prague: CTU, 1999, p. 144-152. ISBN 80-01-02055-X.
KUBÁTOVÁ H.: Hardware Implementation of Petri Nets. In MOSIS'99, Proceedings of the 33rd International Conference "Modelling and Simulation of Systems". Ostrava: MARQ, 1999, p. 87-92. ISBN 80-85988-32-1.
KUBÁTOVÁ H. - RYDLO P.: Model of Computer Network with Router Using Design/CPN. In Proceedings of XXIst International Colloquium ASIS 1999. Ostrava: MARQ, 1999, p. 191-196. ISBN 80-85988-41-0.
PLUHÁČEK A.: Geographic Addressing Using the m-out-of-n Codes. In I & IT - Informatika a informačné technológie. Banská Bystrica: Univerzita Mateja Bela v Banskej Bystrici, Fakulta prírodných vied, 1999, p. 83-88. ISBN 80-8055-335-1.

1998

KUBÁTOVÁ H.: Petri Nets in Hardware Design. In Proceedings of the 32nd International Conference MOSIS98. Ostrava: VSB-TUO, Department of Computer Science of FEI, 1998, p. 249-254. ISBN 80-85988-24-0.
KUBÁTOVÁ H. - RYDLO P.: Design/CPN in System Modelling and Design. In Advanced Simulation of Systems ASIS 1998. Ostrava: VSB-TUO, Department of Computer Science of FEI, 1998, p. 39-44. ISBN 80-85988-26-7.
NOVÁK O. - HLAVIČKA J.: Design of a Cellular Automaton for Efficient Test Pattern Generation. In IEEE European Test Workshop. Barcelona: Publications d'Abast, 1998, p. 30-31.

1997

DANĚČEK J.: Dejte inteligenci svým www stránkám. 1. vyd. Praha: PROFESS, 1997. 154 s. ISBN 80-85235-50-1.
DABROWSKA-WOLAK J. - DRAHOZAL R. - MUZIKÁŘ Z. - SERVÍT M.: Integrated Timing-Driven Layout in an FPGA Environment. In DMMS'97 Proceedings. Budapest: PANEM, 1997, p. 203-212. ISBN 963-545-183-0.

1996

DOUŠA J.: Educational Simulation System. In MOSIS'96. Ostrava: MARQ, 1996, vol. 1, p. 199-204. ISBN 80-85988-02-X.
HLAVIČKA J. - NOVÁK O.: Enhancing Pseudoexhaustive Test Set Quality by Code Bit Inversions. In Proceedings of IEEE European Test Workshop. Montpellier: IEEE Computer Society - TC on Test Technology, 1996, p. 70-74.

1995

DOUŠA J. - BENKOVSKÝ J.: Digital Circuit Simulation in C++. In System Modelling Control. Lodz: Polish Society of Medical Informatics, 1995, p. 235-239. ISBN 83-902115-2-1.
DRÁPAL F. - DANĚČEK J. - PLUHÁČEK A. - SERVÍT M.: Implementation of a General-Purpose Processor Macro. In Proceedings of Workshop on Design Methodologies for Microelectronics. Bratislava: Slovak Academy of Sciences, Institute of Computer Systems, 1995, p. 89-97.
NOVÁK O. - HLAVIČKA J.: Enhancing Fault Coverage of Pseudoexhaustive Test Sets. In Proceedings of 1st IEEE International On-line testing Workshop. Montpellier: IEEE Computer Society - TC on Test Technology, 1995, p. 173-177.
SEVINC S. - BAGDE K. - RICHARDSON D. - RYAN P. - KUBÁTOVÁ H.: Visual and Interactive Modelling of Mine Warfare. In Computer Science. Ostrava: VSB-TUO, 1995, p. 173-178. ISBN 80-901751-7-1.

1994

DANĚČEK J. - PLUHÁČEK A. - DRÁPAL F. - SALČIČ Z. - SERVÍT M.: DOP - A Simple Processor for Custom Computing Machines. Journal of Microcomputer Applications. 1994, vol. 17, no. 11, p. 239-253. ISSN 0745-7138.
DANĚČEK J. - PLUHÁČEK A. - SERVÍT M.: The Architecture of a General-Purpose Processor Cell. In Field-Programmable Logic - Architectures, Synthesis, Applications. Berlin: Springer, 1994, p. 321-325. ISBN 3-540-58419-6.
SERVÍT M. - MUZIKÁŘ Z.: Integrated Layout Synthesis for FPGAS. In Field-Programmable Logic - Architectures, Synthesis, Applications. Berlin: Springer, 1994, p. 23-33. ISBN 3-540-58419-6.

1993

SCHMIDT J.: Generalized Referents: A Neat Interface for the Scruffy Work. In Proceedings of the 1st International Conference on Conceptual Structures. Quebec: Universite Laval, 1993, p. 1-16.