@ARTICLE{4068916, 
author={Cong, J. and Minkovich, K.}, 
journal={Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on}, 
title={Optimality Study of Logic Synthesis for LUT-Based FPGAs}, 
year={2007}, 
month={Feb}, 
volume={26}, 
number={2}, 
pages={230-239}, 
keywords={circuit optimisation;field programmable gate arrays;logic CAD;logic simulation;table lookup;FPGA;LEKO circuits;LEKU circuits;LUT;NP-hard problem;arbitrarily large circuits;area optimization;circuit optimization;circuit synthesis;delay optimization;depth optimization;design automation;field-programmable gate-array;logic mapping;logic optimization;logic synthesis;technology mapping;Added delay;Algorithm design and analysis;Circuit synthesis;Design automation;Field programmable gate arrays;Logic circuits;Logic gates;Network synthesis;Table lookup;Upper bound;Circuit optimization;circuit synthesis;design automation;field-programmable gate arrays (FPGAs);optimization methods}, 
doi={10.1109/TCAD.2006.887922}, 
ISSN={0278-0070},}