@INPROCEEDINGS{100747, 
author={Brglez, F. and Bryan, D. and Kozminski, K.}, 
booktitle={Circuits and Systems, 1989., IEEE International Symposium on}, 
title={Combinational profiles of sequential benchmark circuits}, 
year={1989}, 
month={May}, 
pages={1929-1934 vol.3}, 
keywords={flip-flops;logic testing;sequential circuits;D-type flip-flops;asynchronous behavior;digital sequential circuits;full-scan-mode configuration;gate level;interior faults;partial scan techniques;scan-based test generation;sequential benchmark circuits;sequential test generation;standard functional model;testability profile;Automatic test pattern generation;Benchmark testing;Circuit faults;Circuit synthesis;Circuit testing;Combinational circuits;Computational modeling;Flip-flops;Sequential analysis;Test pattern generators}, 
doi={10.1109/ISCAS.1989.100747},}