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ISCAS'85 and '89 benchmarks

• Primarily for testing
• In formats Bench, BLIF, CIR, Edif, Verilog, ISC, some are collapsed to PLA
• Combinational and sequential circuits, sequential circuits with scan
• ISCAS'85 description
• ISCAS'89 description
• ISCAS'89 description - ISCAS'89 paper
• Detailed description (high-level models) of the benchmarks
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• Origin: CBL
• References:
F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortan," in Proc. of the International Symposium on Circuits and Systems, 1985, pp. 663-698. BibTeX
F. Brglez, D. Bryan, K. Kozminski, "Combinational Profiles of Sequential Benchmark Circuits," in Proc. of the International Symposium of Circuits and Systems, 1989, pp. 1929-1934. BibTeX

ITC'99 benchmarks

• Primarily for testing
• In formats Bench, BLIF, Edif, VHDL
• Combinational and sequential circuits, sequential circuits with scan
• ITC'99 description
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• Origin: ITC'99 Benchmark Homepage
• Reference:
F. Corno, M.S. Reorda, G. Squillero, "RT-level ITC‘99 benchmarks and first ATPG results," in: Proc. of the IEEE Design and Test of Computers (2000), vol. 17, no. 3, pp. 44-53. BibTeX

LGSynth'89 benchmarks

• Primarily for logic synthesis and optimization
• Combinational and sequential circuits, FSMs
• In formats BLIF, Netblif, Verilog, PLA, KISS2, ESP
• Technology libraries provided
• LGSynth'89 benchmarks description
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• Origin: CBL
• Reference:
S. Yang, "Logic Synthesis and Optimization Benchmarks,” Technical Report, MCNC, Dec. 1988, published at 1989 MCNC International Workshop on Logic Synthesis. BibTeX

LGSynth'91 benchmarks

• Primarily for logic synthesis and optimization
• Continuation of LGSynth'89
• Combinational and sequential circuits, FSMs
• In formats BLIF, Slif, Verilog, PLA, KISS2
• Technology libraries provided
• LGSynth'91 benchmarks description
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• Download all - MCNC
• Origin: CBL
• Reference:
S. Yang, "Logic Synthesis and Optimization Benchmarks User Guide Version 3.0,” Technical Report 1991-IWLS-UG-Saeyang, MCNC. BibTeX

IWLS'93 benchmarks

• Primarily for logic synthesis and optimization
• Continuation of LGSynth'91
• Combinational and sequential circuits, FSMs
• In formats BLIF, PLA, KISS2
• Technology library provided
• IWLS'93 benchmarks description
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• Origin: CBL
• Reference:
K. McElvain, "IWLS'93 Benchmark Set: Version 4.0,” Distributed as a part of IWLS'93 benchmark set, May 1993. BibTeX

IWLS 2005 benchmarks

• Compilation of ISCAS, ITC and circuits from Opencores
• In VHDL, Verilog, BLIF
• IWLS 2005 benchmarks description
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• Origin: IWLS
• Reference:
C. Albrecht, "IWLS 2005 Benchmarks,” published at 2005 International Workshop on Logic Synthesis, June 2005. BibTeX

Benchmarks history

LEKO/LEKU benchmarks

• Primarily for testing of LUT mappers
• Artificially constructed combinational circuits with known optimum (LEKO) or upper size bound (LEKU)
• In formats BLIF, VHDL
• LEKO/LEKU benchmarks description
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• Origin: UCLA
• Reference:
J. Cong and K. Minkovich, "Optimality study of logic synthesis for LUT-based FPGAs”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2007, Vol. 26, No. 2, pp. 230–239. BibTeX

Altera Advanced Synthesis Cookbook

• Example designs, as a part of Altera Advanced Synthesis Cookbook
• In Verilog
• Download
• Reference:
"Advanced Synthesis Cookbook”, Altera, MNL-01017-6.0, July 2011. BibTeX

Adders

• Generically constructed 1-17 bit ripple-carry adders
• In formats BLIF, collapsed into PLA
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• Origin: generated by Petr Fišer

EPFL Benchmarks

• Logic optimization benchmarks
• Natively combinational circuits
• In formats AIG, BLIF, Verilog, VHDL
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• Origin: The EPFL Combinational Benchmark Suite