--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2: in std_logic;
    po0,po1,po2: inout std_logic
  );
end top;

architecture top_behav of top is
signal n9,n10: std_logic;
begin
    po0 <= ( not n9 );
    po1 <= ( not n10 );
    po2 <= ( not pi2 );
    n9 <= ( pi0 and pi1 )
      or ( not pi0 and not pi1 );
    n10 <= ( not pi0 and pi1 )
      or ( pi0 and not pi1 )
      or ( pi0 and pi2 )
      or ( pi1 and pi2 )
      or ( not pi0 and not pi2 )
      or ( not pi1 and not pi2 );
end top_behav;
