--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6, CLK: in std_logic;
    po0,po1,po2,po3,po4,po5,po6: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,li0,li1,li2,li3,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    po0 <= ( not n35 );
    po1 <= ( not n36 );
    po3 <= ( not n37 );
    po4 <= ( not n38 );
    po5 <= ( not n39 );
    li0 <= ( not n40 );
    li1 <= ( not n41 );
    li2 <= ( not n42 );
    li3 <= ( not n43 );
    n35 <= ( not n45 and not n49 and not n51 and not n54 and not n58 and not n60 );
    n36 <= ( not n48 and not n52 );
    n37 <= ( not n44 and not n59 );
    n38 <= ( not n53 and not n63 );
    n39 <= ( not n48 and not n61 and not n67 and not n68 and not n69 and not n70 and not n71 and not n72 );
    n40 <= ( pi0 and not n45 and not n49 and not n53 and not n56 and not n61 and not n63 and not n65 and not n70 and not n71 and not n72 );
    n41 <= ( pi0 and not n48 and not n51 and not n52 and not n54 and not n58 and not n60 and not n65 and not n70 and not n71 and not n72 );
    n42 <= ( not n54 and not n55 and not n57 and not n58 and not n60 and not n61 and not n62 );
    n43 <= ( not n48 and not n50 and not n51 and not n53 and not n56 and not n60 and not n61 and not n63 and not n64 and not n65 and not n66 and not n67 and not n68 and not n69 and not n70 and not n71 and not n72 );
    n44 <= ( not pi1 and not pi3 and pi4 and not lo0 and not lo1 and lo2 and not lo3 );
    n45 <= ( pi0 and not pi1 and pi2 and pi3 and not lo0 and not lo1 and lo2 and not lo3 );
    po6 <= ( not pi0 and pi5 and lo0 and lo1 and not lo2 and lo3 );
    po2 <= ( pi0 and not pi6 and lo0 and not lo2 and not lo3 );
    n48 <= ( pi0 and not pi1 and not pi3 and not pi4 and not lo0 and not lo1 and lo2 );
    n49 <= ( pi0 and not pi1 and pi5 and lo0 and lo2 and lo3 );
    n50 <= ( pi2 and pi4 and not lo1 and not lo2 and not lo3 );
    n51 <= ( pi0 and not pi1 and pi3 and not lo0 and not lo1 and lo2 and lo3 );
    n52 <= ( pi0 and not pi1 and not lo0 and lo1 and not lo2 and lo3 );
    n53 <= ( pi0 and pi1 and pi5 and lo0 and not lo2 and lo3 );
    n54 <= ( pi0 and not pi1 and pi2 and not lo1 and not lo2 and not lo3 );
    n55 <= ( pi0 and not pi1 and pi3 and not lo1 and lo2 );
    n56 <= ( not pi5 and lo0 and lo2 and lo3 );
    n57 <= ( pi0 and not pi1 and lo1 and lo2 and lo3 );
    n58 <= ( pi0 and not pi1 and not lo0 and not lo1 and not lo2 and lo3 );
    n59 <= ( pi0 and lo0 and not lo2 and not lo3 );
    n60 <= ( pi0 and not pi1 and pi4 and not lo0 and not lo1 and lo3 );
    n61 <= ( pi0 and not pi1 and not lo0 and lo1 and not lo2 and not lo3 );
    n62 <= ( pi0 and not pi1 and lo0 and lo2 );
    n63 <= ( pi1 and lo0 and not lo1 and not lo2 );
    n64 <= ( not pi0 and not pi5 and lo3 );
    n65 <= ( pi1 and not pi5 and lo1 and lo3 );
    n66 <= ( not pi5 and not lo0 and lo1 );
    n67 <= ( not pi0 and not lo1 );
    n68 <= ( not pi0 and not lo0 );
    n69 <= ( lo1 and lo2 );
    n70 <= ( pi0 and pi1 and not lo3 );
    n71 <= ( pi1 and lo2 );
    n72 <= ( pi1 and not lo0 );
end top_behav;
