--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__cm163a is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15: in std_logic;
    po0,po1,po2,po3,po4: inout std_logic
  );
end LGSynth91__cm163a;

architecture LGSynth91__cm163a_behav of LGSynth91__cm163a is
signal n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36: std_logic;
begin
    po0 <= ( not pi00 and not n27 )
      or ( not n26 and not n27 )
      or ( not pi00 and not n28 )
      or ( not n26 and not n28 );
    po1 <= ( not pi01 and not n29 )
      or ( not n26 and not n29 )
      or ( not pi01 and not n28 )
      or ( not n26 and not n28 );
    po2 <= ( not pi06 and not n30 )
      or ( not n26 and not n30 )
      or ( not pi06 and not n28 )
      or ( not n26 and not n28 );
    po3 <= ( not pi07 and not n31 )
      or ( not n26 and not n31 )
      or ( not pi07 and not n28 )
      or ( not n26 and not n28 );
    po4 <= ( not n32 and pi03 );
    n26 <= ( not pi04 and pi05 );
    n27 <= ( not n33 and pi09 )
      or ( n33 and not pi09 );
    n28 <= ( pi04 and pi05 );
    n29 <= ( n34 and pi11 )
      or ( not n34 and not pi11 );
    n30 <= ( n35 and pi12 )
      or ( not n35 and not pi12 );
    n31 <= ( n36 and pi13 )
      or ( not n36 and not pi13 );
    n32 <= ( not pi14 )
      or ( not pi10 )
      or ( not pi08 )
      or ( not pi15 );
    n33 <= ( not pi02 )
      or ( not pi03 );
    n34 <= ( not pi09 and not n33 );
    n35 <= ( not n33 and not pi09 and not pi11 );
    n36 <= ( not pi12 and not n33 and not pi09 and not pi11 );
end LGSynth91__cm163a_behav;
