--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s298 is 
  Port (
    pi0,pi1,pi2, CLK: in std_logic;
    po0,po1,po2,po3,po4,po5: inout std_logic
  );
end LGSynth91__s298;

architecture LGSynth91__s298_behav of LGSynth91__s298 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,lo12,lo13,li00,li01,li02,li03,li04,li05,li06,li07,li08,li09,li10,li11,li12,li13,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,n108,n109,n110,n111,n112,n113,n114,n115,n116,n117,n118,n119,n120,n121,n122,n123,n124,n125: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    DFF12: DFF port map (li12, CLK, lo12);
    DFF13: DFF port map (li13, CLK, lo13);
    li00 <= ( not pi0 and not lo00 );
    li01 <= ( not pi0 and not n65 and not n66 and not n67 );
    li02 <= ( not pi0 and not n68 and not n69 and not n70 );
    li03 <= ( not n71 and not n72 );
    li04 <= ( not n73 and not n74 and not n75 );
    li05 <= ( not pi0 and not n76 and not n77 );
    li06 <= ( not n78 and not n79 and not n80 and not n81 );
    li07 <= ( not n82 and not n83 and not n84 );
    li08 <= ( not n85 and not n86 );
    li09 <= ( not n87 and not n88 );
    li10 <= ( not n89 and not n90 );
    li11 <= ( not n91 and not n92 );
    li12 <= ( not pi0 and not n93 and not n94 );
    li13 <= ( not pi0 and not n95 and not n96 );
    n65 <= ( lo00 and not lo02 and lo03 );
    n66 <= ( lo00 and lo01 );
    n67 <= ( not lo00 and not lo01 );
    n68 <= ( lo00 and lo01 and lo02 );
    n69 <= ( not lo00 and not lo02 );
    n70 <= ( not lo01 and not lo02 );
    n71 <= ( not lo03 and n101 );
    n72 <= ( pi0 )
      or ( not n113 )
      or ( not n114 );
    n73 <= ( lo00 and not lo01 and not lo02 and n102 );
    n74 <= ( not lo04 and not lo13 and n103 );
    n75 <= ( not n99 and not n100 );
    n76 <= ( lo01 and not lo02 and not lo12 and n104 );
    n77 <= ( not lo05 and n105 );
    n78 <= ( lo04 and not lo06 );
    n79 <= ( not lo03 and not lo04 );
    n80 <= ( not lo02 and not lo03 );
    n81 <= ( not n97 and not n98 );
    n82 <= ( lo03 and not lo07 );
    n83 <= ( lo03 and not lo04 );
    n84 <= ( n81 )
      or ( not n123 )
      or ( not n124 )
      or ( not n125 );
    n85 <= ( lo02 and lo04 and not lo08 );
    n86 <= ( n81 )
      or ( not n115 )
      or ( not n116 )
      or ( not n117 );
    n87 <= ( not lo03 and not n81 and n108 );
    n88 <= ( not n118 )
      or ( not n119 );
    n89 <= ( not n81 and n112 );
    n90 <= ( lo00 and n81 );
    n91 <= ( lo04 and not lo11 );
    n92 <= ( n81 )
      or ( not n120 )
      or ( not n121 )
      or ( not n122 );
    n93 <= ( not pi2 and not lo12 );
    n94 <= ( pi2 and lo12 );
    n95 <= ( not pi1 and not lo13 );
    n96 <= ( pi1 and lo13 );
    n97 <= ( lo01 and not lo02 and not lo12 and n104 );
    n98 <= ( not lo05 and n105 );
    n99 <= ( not pi0 and not lo04 );
    n100 <= ( not pi0 and not lo13 );
    n101 <= ( not lo02 )
      or ( not lo01 )
      or ( not lo00 );
    n102 <= ( lo03 and lo04 );
    n103 <= ( not lo00 )
      or ( lo01 )
      or ( lo02 )
      or ( not lo03 );
    n104 <= ( lo03 and not lo04 );
    n105 <= ( lo01 )
      or ( lo02 )
      or ( not lo12 )
      or ( not n104 );
    n106 <= ( lo02 and lo04 and lo09 );
    n107 <= ( not lo01 and not lo02 and lo04 );
    n108 <= ( not n106 and not n107 );
    n109 <= ( not lo01 )
      or ( lo02 )
      or ( lo03 );
    n110 <= ( not lo02 )
      or ( lo10 );
    n111 <= ( not lo03 )
      or ( lo10 );
    n112 <= ( not n109 )
      or ( not n110 )
      or ( not n111 )
      or ( not lo04 );
    n113 <= ( not lo00 )
      or ( not lo01 )
      or ( not lo02 )
      or ( not lo03 );
    n114 <= ( not lo00 )
      or ( lo01 )
      or ( lo02 );
    n115 <= ( lo01 )
      or ( lo02 )
      or ( lo03 )
      or ( not lo04 );
    n116 <= ( not lo03 )
      or ( lo08 );
    n117 <= ( not lo03 )
      or ( lo04 );
    n118 <= ( not lo03 )
      or ( not lo04 )
      or ( lo09 )
      or ( n81 );
    n119 <= ( not lo00 )
      or ( not n81 );
    n120 <= ( not lo03 )
      or ( lo04 );
    n121 <= ( lo01 )
      or ( lo04 );
    n122 <= ( lo02 )
      or ( lo03 );
    n123 <= ( lo01 )
      or ( lo02 )
      or ( lo03 )
      or ( not lo04 );
    n124 <= ( not lo01 )
      or ( not lo02 )
      or ( lo04 );
    n125 <= ( not lo02 )
      or ( not lo04 )
      or ( lo07 );
    po0 <= ( lo08 );
    po1 <= ( lo10 );
    po2 <= ( lo06 );
    po3 <= ( lo09 );
    po4 <= ( lo11 );
    po5 <= ( lo07 );
end LGSynth91__s298_behav;
