--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gray_to_bin is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7: in std_logic;
    po0,po1,po2,po3,po4,po5,po6: inout std_logic
  );
end Cookbook__gray_to_bin;

architecture Cookbook__gray_to_bin_behav of Cookbook__gray_to_bin is
begin
    po6 <= ( not po5 and pi7 )
      or ( po5 and not pi7 );
    po5 <= ( not po4 and pi6 )
      or ( po4 and not pi6 );
    po4 <= ( not po3 and pi5 )
      or ( po3 and not pi5 );
    po3 <= ( not po2 and pi4 )
      or ( po2 and not pi4 );
    po2 <= ( not po1 and pi3 )
      or ( po1 and not pi3 );
    po1 <= ( not po0 and pi2 )
      or ( po0 and not pi2 );
    po0 <= ( not pi0 and pi1 )
      or ( pi0 and not pi1 );
end Cookbook__gray_to_bin_behav;
