--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end top;

architecture top_behav of top is
signal n12,n14: std_logic;
begin
    po3 <= ( not pi6 and not pi4 and pi5 )
      or ( not pi6 and pi4 and not pi5 )
      or ( pi6 and not pi4 and not pi5 )
      or ( pi6 and pi4 and pi5 );
    n12 <= ( pi6 and pi4 )
      or ( pi6 and pi5 )
      or ( pi4 and pi5 );
    po2 <= ( not n12 and not pi1 and pi3 )
      or ( not n12 and pi1 and not pi3 )
      or ( n12 and not pi1 and not pi3 )
      or ( n12 and pi1 and pi3 );
    n14 <= ( n12 and pi1 )
      or ( n12 and pi3 )
      or ( pi1 and pi3 );
    po1 <= ( not n14 and not pi0 and pi2 )
      or ( not n14 and pi0 and not pi2 )
      or ( n14 and not pi0 and not pi2 )
      or ( n14 and pi0 and pi2 );
    po0 <= ( n14 and pi0 )
      or ( n14 and pi2 )
      or ( pi0 and pi2 );
end top_behav;
