--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__pcler8 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16: inout std_logic
  );
end LGSynth91__pcler8;

architecture LGSynth91__pcler8_behav of LGSynth91__pcler8 is
signal n61,n62,n63,n64,n65,n66,n67: std_logic;
begin
    po00 <= ( pi26 and n61 and n62 );
    po01 <= ( pi00 and pi08 );
    po02 <= ( pi01 and pi08 );
    po03 <= ( pi02 and pi08 );
    po04 <= ( pi03 and pi08 );
    po05 <= ( pi04 and pi08 );
    po06 <= ( pi05 and pi08 );
    po07 <= ( pi06 and pi08 );
    po08 <= ( pi07 and pi08 );
    po09 <= ( po01 )
      or ( pi11 and po00 )
      or ( not pi19 and n62 );
    po10 <= ( po02 )
      or ( po00 and pi12 )
      or ( n62 and not pi19 and pi20 )
      or ( n62 and pi19 and not pi20 );
    po11 <= ( po03 )
      or ( po00 and pi13 )
      or ( n62 and not pi21 and n63 )
      or ( n62 and pi21 and not n63 );
    po12 <= ( po04 )
      or ( po00 and pi14 )
      or ( n62 and not pi22 and n64 )
      or ( n62 and pi22 and not n64 );
    po13 <= ( po05 )
      or ( po00 and pi15 )
      or ( n62 and not pi23 and n65 )
      or ( n62 and pi23 and not n65 );
    po14 <= ( po06 )
      or ( po00 and pi16 )
      or ( n62 and not pi24 and n66 )
      or ( n62 and pi24 and not n66 );
    po15 <= ( po07 )
      or ( po00 and pi17 )
      or ( n62 and not pi25 and n67 )
      or ( n62 and pi25 and not n67 );
    po16 <= ( po08 )
      or ( po00 and pi18 )
      or ( n62 and not pi26 and n61 )
      or ( n62 and pi26 and not n61 );
    n61 <= ( pi25 and n67 );
    n62 <= ( not pi08 and pi09 and not pi10 );
    n63 <= ( pi19 and pi20 );
    n64 <= ( pi21 and n63 );
    n65 <= ( pi22 and n64 );
    n66 <= ( pi23 and n65 );
    n67 <= ( pi24 and n66 );
end LGSynth91__pcler8_behav;
