--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ecc_matrix_32bit is 
  Port (
    pi0,pi1: in std_logic;
    po0,po1: inout std_logic
  );
end Cookbook__ecc_matrix_32bit;

architecture Cookbook__ecc_matrix_32bit_behav of Cookbook__ecc_matrix_32bit is
signal n4,n6: std_logic;
begin
    n4 <= not (( not pi1 and not pi0 ));
    po1 <= not (( not n4 and not pi0 ));
    n6 <= not (( not pi1 and not pi0 ));
    po0 <= ( not n6 and not pi0 );
end Cookbook__ecc_matrix_32bit_behav;
