--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__x2 is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8,pi9: in std_logic;
    po0,po1,po2,po3,po4,po5,po6: inout std_logic
  );
end LGSynth91__x2;

architecture LGSynth91__x2_behav of LGSynth91__x2 is
signal n24,n25,n26,n27,n28: std_logic;
begin
    po0 <= ( n24 )
      or ( n25 )
      or ( n26 )
      or ( n27 )
      or ( not pi8 and not pi9 );
    po1 <= ( n25 )
      or ( n26 )
      or ( n27 )
      or ( pi7 and not pi9 );
    po2 <= ( not pi7 and not pi8 and not pi9 );
    po3 <= ( po2 )
      or ( n24 )
      or ( n26 )
      or ( n27 )
      or ( pi2 )
      or ( pi0 )
      or ( pi1 )
      or ( pi7 and not pi9 );
    po4 <= ( po2 )
      or ( n25 )
      or ( n26 )
      or ( n27 )
      or ( not pi6 );
    po5 <= ( n28 )
      or ( not pi6 )
      or ( not pi8 and not pi9 )
      or ( not pi9 and pi7 and pi3 and not pi4 )
      or ( not pi8 and not pi0 and not pi1 and pi2 and not pi7 )
      or ( pi8 and pi9 and not pi0 and not pi1 and pi2 and pi7 );
    po6 <= ( n28 )
      or ( po2 )
      or ( n24 )
      or ( not pi6 )
      or ( not pi0 and not pi1 and not pi2 and pi7 and pi9 )
      or ( pi7 and not pi9 and pi3 and pi4 and pi8 );
    n24 <= ( pi7 and not pi8 and pi9 );
    n25 <= ( not pi7 and pi8 );
    n26 <= ( pi8 and pi9 );
    n27 <= ( not pi7 and pi9 );
    n28 <= ( pi5 and not pi7 and pi8 and pi9 );
end LGSynth91__x2_behav;
