--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__iter_addsub is 
  Port (
    pi0,pi1,pi2,pi3,pi4, CLK: in std_logic;
    po0: inout std_logic
  );
end Cookbook__iter_addsub;

architecture Cookbook__iter_addsub_behav of Cookbook__iter_addsub is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,n9,n10,n11,n13,n14,n15,n16,n17,li0: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    n9 <= ( not pi2 and pi4 )
      or ( pi2 and not pi4 );
    n10 <= ( not pi3 and n9 )
      or ( pi3 and not n9 );
    n11 <= ( lo0 and not pi1 )
      or ( pi2 and pi1 );
    po0 <= ( not n10 and n11 )
      or ( n10 and not n11 );
    n13 <= ( pi3 and n9 );
    n14 <= ( pi3 and n11 );
    n15 <= not (( not n13 and not n14 ));
    n16 <= ( n9 and n11 );
    n17 <= not (( not n15 and not n16 ));
    li0 <= ( n17 and not pi0 );
end Cookbook__iter_addsub_behav;
