--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misj is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26,pi27,pi28,pi29,pi30,pi31,pi32,pi33,pi34: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11: inout std_logic
  );
end Espresso__misj;

architecture Espresso__misj_behav of Espresso__misj is
begin
    po00 <= ( pi00 and pi01 and pi02 and pi03 );
    po01 <= ( pi05 and pi07 )
      or ( not pi01 and pi07 and pi08 )
      or ( not pi03 and pi07 and pi08 )
      or ( not pi04 and pi07 and pi08 )
      or ( pi07 and pi08 and not pi15 )
      or ( pi07 and pi08 and not pi16 );
    po02 <= ( not pi05 );
    po03 <= ( not pi07 )
      or ( not pi05 and not pi10 )
      or ( not pi05 and not pi11 );
    po04 <= ( not pi07 )
      or ( not pi05 and not pi12 )
      or ( not pi05 and not pi13 )
      or ( not pi05 and not pi14 );
    po05 <= ( not pi17 )
      or ( not pi18 );
    po06 <= ( pi09 )
      or ( pi19 )
      or ( pi20 );
    po07 <= ( not pi15 );
    po08 <= ( not pi06 )
      or ( not pi21 );
    po09 <= ( not pi22 )
      or ( pi23 )
      or ( pi25 )
      or ( not pi27 )
      or ( not pi28 )
      or ( not pi29 )
      or ( not pi30 )
      or ( not pi31 )
      or ( not pi32 )
      or ( not pi33 );
    po10 <= ( not pi22 )
      or ( not pi24 )
      or ( not pi26 )
      or ( not pi27 )
      or ( not pi28 )
      or ( not pi30 )
      or ( not pi31 )
      or ( not pi32 )
      or ( not pi33 )
      or ( not pi34 );
    po11 <= ( not pi01 and pi07 and pi08 )
      or ( not pi03 and pi07 and pi08 )
      or ( not pi04 and pi07 and pi08 )
      or ( pi07 and pi08 and not pi15 )
      or ( pi07 and pi08 and not pi16 );
end Espresso__misj_behav;
