--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part12 is 
  Port (
    pi12,pi28,pi44: in std_logic;
    po12,po28: inout std_logic
  );
end Cookbook__compress_32__part12;

architecture Cookbook__compress_32__part12_behav of Cookbook__compress_32__part12 is
signal n83,n115,n131,n147,n163: std_logic;
begin
    n83 <= ( not pi12 and pi28 )
      or ( pi12 and not pi28 );
    po12 <= ( not n83 and pi44 )
      or ( n83 and not pi44 );
    n115 <= ( pi12 and pi44 );
    n131 <= ( pi12 and pi28 );
    n147 <= not (( not n131 and not n115 ));
    n163 <= ( pi28 and pi44 );
    po28 <= not (( not n147 and not n163 ));
end Cookbook__compress_32__part12_behav;
