--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__i4__part4 is 
  Port (
    pi103,pi117: in std_logic;
    po4: inout std_logic
  );
end IWLS93__i4__part4;

architecture IWLS93__i4__part4_behav of IWLS93__i4__part4 is
begin
    po4 <= ( pi103 and pi117 );
end IWLS93__i4__part4_behav;
