--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__pm1__part2 is 
  Port (
    pi14: in std_logic;
    po04: inout std_logic
  );
end LGSynth91__pm1__part2;

architecture LGSynth91__pm1__part2_behav of LGSynth91__pm1__part2 is
begin
    po04 <= ( not pi14 );
end LGSynth91__pm1__part2_behav;
