--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part243 is 
  Port (
    pi2144, CLK: in std_logic;
    po2035: inout std_logic
  );
end Other__umass_weather__part243;

architecture Other__umass_weather__part243_behav of Other__umass_weather__part243 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4910,lo4982,lo5054,li4910,li4982,li5054: std_logic;
begin
    DFF0: DFF port map (li4910, CLK, lo4910);
    DFF1: DFF port map (li4982, CLK, lo4982);
    DFF2: DFF port map (li5054, CLK, lo5054);
    li4910 <= ( lo4982 );
    li4982 <= ( lo5054 );
    li5054 <= ( pi2144 );
    po2035 <= ( lo4910 );
end Other__umass_weather__part243_behav;
