--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part12 is 
  Port (
    pi3642: in std_logic;
    po3756: inout std_logic
  );
end IWLS2005__DSP__part12;

architecture IWLS2005__DSP__part12_behav of IWLS2005__DSP__part12 is
begin
    po3756 <= ( not pi3642 );
end IWLS2005__DSP__part12_behav;
