--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__i10__part3 is 
  Port (
    pi112: in std_logic;
    po148: inout std_logic
  );
end IWLS93__i10__part3;

architecture IWLS93__i10__part3_behav of IWLS93__i10__part3 is
begin
    po148 <= ( not pi112 );
end IWLS93__i10__part3_behav;
