--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__cc is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14: inout std_logic
  );
end LGSynth91__cc;

architecture LGSynth91__cc_behav of LGSynth91__cc is
signal n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63: std_logic;
begin
    po00 <= ( pi20 and pi11 );
    po01 <= ( pi15 and not pi14 and pi10 and pi08 );
    po02 <= ( pi14 and not n52 )
      or ( not n51 and not n52 );
    po03 <= ( pi15 and not n53 );
    po04 <= ( not pi18 );
    po05 <= ( pi09 and pi08 );
    po06 <= ( not po05 );
    po07 <= ( pi13 and not n54 )
      or ( not n51 and not n54 );
    po08 <= ( pi14 and not n56 )
      or ( not n55 and not n56 );
    po09 <= ( not pi10 and not n58 )
      or ( not pi08 and not n58 )
      or ( not n57 and not n58 );
    po10 <= ( not n51 and not n59 )
      or ( not pi14 and pi16 and not n59 );
    po11 <= ( pi17 and not n60 )
      or ( not n51 and not n60 );
    po12 <= ( pi18 and not n61 )
      or ( not n51 and not n61 );
    po13 <= ( pi19 and not n62 )
      or ( not n51 and not n62 );
    po14 <= ( pi20 and not n63 )
      or ( not n51 and not n63 );
    n51 <= ( pi15 )
      or ( not pi10 )
      or ( not pi08 );
    n52 <= ( not pi12 )
      or ( pi11 );
    n53 <= ( pi14 )
      or ( not pi12 )
      or ( not pi10 )
      or ( not pi08 );
    n54 <= ( not pi12 )
      or ( not pi00 and pi08 and pi10 and not pi15 );
    n55 <= ( not pi15 )
      or ( not pi10 )
      or ( not pi08 );
    n56 <= ( not pi12 )
      or ( pi01 and pi08 and pi10 and not pi15 );
    n57 <= ( pi15 )
      or ( not pi02 );
    n58 <= ( not pi12 )
      or ( not pi08 and not pi15 )
      or ( not pi10 and not pi15 );
    n59 <= ( not pi12 )
      or ( not pi03 and pi08 and pi10 and not pi15 );
    n60 <= ( not pi12 )
      or ( not pi04 and pi08 and pi10 and not pi15 );
    n61 <= ( not pi12 )
      or ( not pi05 and pi08 and pi10 and not pi15 );
    n62 <= ( not pi12 )
      or ( not pi06 and pi08 and pi10 and not pi15 );
    n63 <= ( not pi12 )
      or ( not pi07 and pi08 and pi10 and not pi15 );
end LGSynth91__cc_behav;
