--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_pci__part12 is 
  Port (
    pi248, CLK: in std_logic;
    po329: inout std_logic
  );
end QUIP__oc_pci__part12;

architecture QUIP__oc_pci__part12_behav of QUIP__oc_pci__part12 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo1145,li1145: std_logic;
begin
    DFF0: DFF port map (li1145, CLK, lo1145);
    li1145 <= ( pi248 );
    po329 <= ( lo1145 );
end QUIP__oc_pci__part12_behav;
