--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__newtpla2 is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8,pi9: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end Espresso__newtpla2;

architecture Espresso__newtpla2_behav of Espresso__newtpla2 is
begin
    po0 <= ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 and pi8 )
      or ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 and not pi8 and pi9 );
    po1 <= ( pi3 and not pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 );
    po2 <= ( pi5 and not pi6 and not pi7 )
      or ( pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 );
    po3 <= ( pi6 and not pi7 )
      or ( pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 )
      or ( pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 )
      or ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 and not pi8 and pi9 );
end Espresso__newtpla2_behav;
