--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__dec_67_64__part1 is 
  Port (
    pi02,pi01,pi67: in std_logic;
    po65,po00: inout std_logic
  );
end Cookbook__dec_67_64__part1;

architecture Cookbook__dec_67_64__part1_behav of Cookbook__dec_67_64__part1 is
begin
    po65 <= ( not pi02 and not pi01 )
      or ( pi02 and pi01 );
    po00 <= ( not pi01 and pi67 )
      or ( pi01 and not pi67 );
end Cookbook__dec_67_64__part1_behav;
