--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__cm151a is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11: in std_logic;
    po0,po1: inout std_logic
  );
end LGSynth91__cm151a;

architecture LGSynth91__cm151a_behav of LGSynth91__cm151a is
signal n16,n17,n18,n19,n20,n21,n22: std_logic;
begin
    po0 <= ( not n16 and not pi11 );
    po1 <= ( not po0 );
    n16 <= ( not pi10 and not n21 )
      or ( pi10 and not n22 )
      or ( not n21 and not n22 );
    n17 <= ( not pi00 and not pi01 )
      or ( not pi01 and pi08 )
      or ( not pi00 and not pi08 );
    n18 <= ( not pi02 and not pi03 )
      or ( not pi03 and pi08 )
      or ( not pi02 and not pi08 );
    n19 <= ( not pi04 and not pi05 )
      or ( not pi05 and pi08 )
      or ( not pi04 and not pi08 );
    n20 <= ( not pi06 and not pi07 )
      or ( not pi07 and pi08 )
      or ( not pi06 and not pi08 );
    n21 <= ( not pi09 and not n17 )
      or ( pi09 and not n18 )
      or ( not n17 and not n18 );
    n22 <= ( not pi09 and not n19 )
      or ( pi09 and not n20 )
      or ( not n19 and not n20 );
end LGSynth91__cm151a_behav;
