--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part5 is 
  Port (
    pi16,pi17,pi18,pi19: in std_logic;
    po06: inout std_logic
  );
end Espresso__mish__part5;

architecture Espresso__mish__part5_behav of Espresso__mish__part5 is
begin
    po06 <= ( not pi16 )
      or ( not pi17 )
      or ( not pi18 )
      or ( not pi19 );
end Espresso__mish__part5_behav;
