--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part148 is 
  Port (
    pi0345, CLK: in std_logic;
    po0297: inout std_logic
  );
end Other__umass_weather__part148;

architecture Other__umass_weather__part148_behav of Other__umass_weather__part148 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0399,li0399: std_logic;
begin
    DFF0: DFF port map (li0399, CLK, lo0399);
    li0399 <= ( pi0345 );
    po0297 <= ( lo0399 );
end Other__umass_weather__part148_behav;
