--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part11 is 
  Port (
    pi3641: in std_logic;
    po3751: inout std_logic
  );
end IWLS2005__DSP__part11;

architecture IWLS2005__DSP__part11_behav of IWLS2005__DSP__part11 is
begin
    po3751 <= ( not pi3641 );
end IWLS2005__DSP__part11_behav;
