--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_pci__part2 is 
  Port (
    pi238, CLK: in std_logic;
    po309: inout std_logic
  );
end QUIP__oc_pci__part2;

architecture QUIP__oc_pci__part2_behav of QUIP__oc_pci__part2 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo1123,li1123: std_logic;
begin
    DFF0: DFF port map (li1123, CLK, lo1123);
    li1123 <= ( pi238 );
    po309 <= ( lo1123 );
end QUIP__oc_pci__part2_behav;
