--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__i10__part4 is 
  Port (
    pi153: in std_logic;
    po180: inout std_logic
  );
end IWLS93__i10__part4;

architecture IWLS93__i10__part4_behav of IWLS93__i10__part4 is
begin
    po180 <= ( not pi153 );
end IWLS93__i10__part4_behav;
