--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__nut_000__part1 is 
  Port (
    , CLK: in std_logic;
    po01: inout std_logic
  );
end QUIP__nut_000__part1;

architecture QUIP__nut_000__part1_behav of QUIP__nut_000__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo001,lo060,lo061,lo062,li062,li001,li060,li061: std_logic;
begin
    DFF0: DFF port map (li001, CLK, lo001);
    DFF1: DFF port map (li060, CLK, lo060);
    DFF2: DFF port map (li061, CLK, lo061);
    DFF3: DFF port map (li062, CLK, lo062);
    po01 <= ( lo001 );
    li062 <= ( not lo062 );
    li001 <= ( not lo001 and lo060 and lo061 and lo062 )
      or ( lo001 and not lo060 )
      or ( lo001 and not lo061 )
      or ( lo001 and not lo062 );
    li060 <= ( not lo060 and lo061 and lo062 )
      or ( lo060 and not lo061 )
      or ( lo060 and not lo062 );
    li061 <= ( not lo061 and lo062 )
      or ( lo061 and not lo062 );
end QUIP__nut_000__part1_behav;
