--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__C880__part2 is 
  Port (
    pi35,pi29,pi20,pi47: in std_logic;
    po03,po13: inout std_logic
  );
end IWLS93__C880__part2;

architecture IWLS93__C880__part2_behav of IWLS93__C880__part2 is
signal n296: std_logic;
begin
    po03 <= ( pi35 and not n296 );
    po13 <= ( pi29 and not n296 );
    n296 <= ( not pi20 and not pi47 );
end IWLS93__C880__part2_behav;
