--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__pm1__part3 is 
  Port (
    pi15: in std_logic;
    po09: inout std_logic
  );
end IWLS93__pm1__part3;

architecture IWLS93__pm1__part3_behav of IWLS93__pm1__part3 is
begin
    po09 <= ( not pi15 );
end IWLS93__pm1__part3_behav;
