--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part222 is 
  Port (
    pi2123, CLK: in std_logic;
    po2014: inout std_logic
  );
end Other__umass_weather__part222;

architecture Other__umass_weather__part222_behav of Other__umass_weather__part222 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4889,lo4918,lo4990,li4889,li4918,li4990: std_logic;
begin
    DFF0: DFF port map (li4889, CLK, lo4889);
    DFF1: DFF port map (li4918, CLK, lo4918);
    DFF2: DFF port map (li4990, CLK, lo4990);
    li4889 <= ( lo4918 );
    li4918 <= ( lo4990 );
    li4990 <= ( pi2123 );
    po2014 <= ( lo4889 );
end Other__umass_weather__part222_behav;
