--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part2 is 
  Port (
    pi1879,pi2811: in std_logic;
    po2107,po3699: inout std_logic
  );
end IWLS2005__DSP__part2;

architecture IWLS2005__DSP__part2_behav of IWLS2005__DSP__part2 is
begin
    po2107 <= not (( pi1879 and not pi2811 ));
    po3699 <= ( not pi1879 );
end IWLS2005__DSP__part2_behav;
