--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C7552__part0 is 
  Port (
    pi000,pi086: in std_logic;
    po12: inout std_logic
  );
end LGSynth91__C7552__part0;

architecture LGSynth91__C7552__part0_behav of LGSynth91__C7552__part0 is
begin
    po12 <= ( pi000 and pi086 );
end LGSynth91__C7552__part0_behav;
