--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi38, CLK: in std_logic;
    po123: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo119,lo428,lo531,li428,li119,li531: std_logic;
begin
    DFF0: DFF port map (li119, CLK, lo119);
    DFF1: DFF port map (li428, CLK, lo428);
    DFF2: DFF port map (li531, CLK, lo531);
    li428 <= ( pi38 );
    li119 <= ( lo531 );
    li531 <= ( lo428 );
    po123 <= ( lo119 );
end top_behav;
