--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i10__part2 is 
  Port (
    pi175: in std_logic;
    po135: inout std_logic
  );
end LGSynth91__i10__part2;

architecture LGSynth91__i10__part2_behav of LGSynth91__i10__part2 is
begin
    po135 <= ( not pi175 );
end LGSynth91__i10__part2_behav;
