--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__three_two_comp is 
  Port (
    pi0,pi1,pi2: in std_logic;
    po0,po1: inout std_logic
  );
end Cookbook__three_two_comp;

architecture Cookbook__three_two_comp_behav of Cookbook__three_two_comp is
signal n5,n6,n8,n9: std_logic;
begin
    n5 <= ( not pi2 and pi1 )
      or ( pi2 and not pi1 );
    n6 <= ( not pi2 and not pi1 )
      or ( pi2 and pi1 );
    po1 <= ( n5 and not pi0 )
      or ( n6 and pi0 );
    n8 <= ( pi2 and pi1 );
    n9 <= not (( not pi2 and not pi1 ));
    po0 <= ( n8 and not pi0 )
      or ( n9 and pi0 );
end Cookbook__three_two_comp_behav;
