--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part233 is 
  Port (
    pi2134, CLK: in std_logic;
    po2025: inout std_logic
  );
end Other__umass_weather__part233;

architecture Other__umass_weather__part233_behav of Other__umass_weather__part233 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4900,lo4972,lo5044,li4900,li4972,li5044: std_logic;
begin
    DFF0: DFF port map (li4900, CLK, lo4900);
    DFF1: DFF port map (li4972, CLK, lo4972);
    DFF2: DFF port map (li5044, CLK, lo5044);
    li4900 <= ( lo4972 );
    li4972 <= ( lo5044 );
    li5044 <= ( pi2134 );
    po2025 <= ( lo4900 );
end Other__umass_weather__part233_behav;
