--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part220 is 
  Port (
    pi2121, CLK: in std_logic;
    po2012: inout std_logic
  );
end Other__umass_weather__part220;

architecture Other__umass_weather__part220_behav of Other__umass_weather__part220 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4887,lo4916,lo4988,li4887,li4916,li4988: std_logic;
begin
    DFF0: DFF port map (li4887, CLK, lo4887);
    DFF1: DFF port map (li4916, CLK, lo4916);
    DFF2: DFF port map (li4988, CLK, lo4988);
    li4887 <= ( lo4916 );
    li4916 <= ( lo4988 );
    li4988 <= ( pi2121 );
    po2012 <= ( lo4887 );
end Other__umass_weather__part220_behav;
