--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part0 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07: in std_logic;
    po00: inout std_logic
  );
end Espresso__misg__part0;

architecture Espresso__misg__part0_behav of Espresso__misg__part0 is
begin
    po00 <= ( pi00 and pi01 )
      or ( pi02 and pi03 )
      or ( pi04 and pi05 )
      or ( pi06 and pi07 );
end Espresso__misg__part0_behav;
