--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__ex4__part1 is 
  Port (
    pi01,pi08,pi15,pi25,pi32,pi39,pi49,pi56,pi63: in std_logic;
    po01,po08: inout std_logic
  );
end Espresso__ex4__part1;

architecture Espresso__ex4__part1_behav of Espresso__ex4__part1 is
begin
    po01 <= ( not pi25 and pi32 and not pi39 )
      or ( not pi08 and pi32 and not pi56 )
      or ( pi08 and not pi15 and pi32 and pi39 and not pi49 )
      or ( not pi15 and pi25 and pi32 and pi39 and not pi49 )
      or ( pi08 and not pi15 and pi32 and not pi49 and pi56 )
      or ( not pi15 and pi25 and pi32 and not pi49 and pi56 )
      or ( not pi01 and pi08 and pi25 and pi32 and not pi63 )
      or ( not pi01 and pi25 and pi32 and pi39 and not pi63 )
      or ( not pi01 and pi08 and pi32 and pi56 and not pi63 )
      or ( not pi01 and pi32 and pi39 and pi56 and not pi63 );
    po08 <= ( pi25 and not pi32 and pi39 )
      or ( pi08 and not pi32 and pi56 )
      or ( not pi08 and pi15 and not pi32 and not pi39 and pi49 )
      or ( pi15 and not pi25 and not pi32 and not pi39 and pi49 )
      or ( not pi08 and pi15 and not pi32 and pi49 and not pi56 )
      or ( pi15 and not pi25 and not pi32 and pi49 and not pi56 )
      or ( pi01 and not pi08 and not pi25 and not pi32 and pi63 )
      or ( pi01 and not pi25 and not pi32 and not pi39 and pi63 )
      or ( pi01 and not pi08 and not pi32 and not pi56 and pi63 )
      or ( pi01 and not pi32 and not pi39 and not pi56 and pi63 );
end Espresso__ex4__part1_behav;
