--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part9 is 
  Port (
    pi09,pi25,pi41: in std_logic;
    po09,po25: inout std_logic
  );
end Cookbook__compress_32__part9;

architecture Cookbook__compress_32__part9_behav of Cookbook__compress_32__part9 is
signal n86,n118,n134,n150,n166: std_logic;
begin
    n86 <= ( not pi09 and pi25 )
      or ( pi09 and not pi25 );
    po09 <= ( not n86 and pi41 )
      or ( n86 and not pi41 );
    n118 <= ( pi09 and pi41 );
    n134 <= ( pi09 and pi25 );
    n150 <= not (( not n134 and not n118 ));
    n166 <= ( pi25 and pi41 );
    po25 <= not (( not n150 and not n166 ));
end Cookbook__compress_32__part9_behav;
