--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part5 is 
  Port (
    pi3632,pi3633,pi3515,pi3518: in std_logic;
    po0984,po0985,po1672,po1673: inout std_logic
  );
end IWLS2005__DSP__part5;

architecture IWLS2005__DSP__part5_behav of IWLS2005__DSP__part5 is
signal n35301,n39533: std_logic;
begin
    n35301 <= ( not pi3632 and not pi3633 );
    po0984 <= not (( not pi3515 and not n35301 ));
    po0985 <= not (( not pi3515 and n35301 ));
    n39533 <= ( pi3632 and not pi3633 );
    po1672 <= not (( pi3518 and not n39533 ));
    po1673 <= not (( pi3518 and n39533 ));
end IWLS2005__DSP__part5_behav;
