--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_8__part0 is 
  Port (
    pi14,pi06,pi12,pi04,pi10,pi02,pi00,pi26,pi24,pi22,pi20,pi18,pi16,pi08: in std_logic;
    po24,po22,po20,po18,po16,po14,po12,po10,po08,po06,po04,po02,po00: inout std_logic
  );
end Cookbook__fec_rot_8__part0;

architecture Cookbook__fec_rot_8__part0_behav of Cookbook__fec_rot_8__part0 is
signal n55,n57,n59: std_logic;
begin
    n55 <= ( not pi14 and pi06 )
      or ( pi14 and not pi06 );
    n57 <= ( not pi12 and pi04 )
      or ( pi12 and not pi04 );
    n59 <= ( not pi10 and pi02 )
      or ( pi10 and not pi02 );
    po24 <= ( not pi06 and pi04 )
      or ( pi06 and not pi04 );
    po22 <= ( not pi04 and pi02 )
      or ( pi04 and not pi02 );
    po20 <= ( not pi02 and pi00 )
      or ( pi02 and not pi00 );
    po18 <= ( not pi26 and pi00 )
      or ( pi26 and not pi00 );
    po16 <= ( not pi24 and pi06 )
      or ( pi24 and not pi06 );
    po14 <= ( not pi22 and pi04 )
      or ( pi22 and not pi04 );
    po12 <= ( not pi20 and pi02 )
      or ( pi20 and not pi02 );
    po10 <= ( not pi18 and pi00 )
      or ( pi18 and not pi00 );
    po08 <= ( not pi16 and pi06 )
      or ( pi16 and not pi06 );
    po06 <= ( not n55 and pi04 )
      or ( n55 and not pi04 );
    po04 <= ( not n57 and pi02 )
      or ( n57 and not pi02 );
    po02 <= ( not n59 and pi00 )
      or ( n59 and not pi00 );
    po00 <= ( not pi08 and pi00 )
      or ( pi08 and not pi00 );
end Cookbook__fec_rot_8__part0_behav;
