--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_4__part1 is 
  Port (
    pi07,pi03,pi01,pi15,pi13,pi11,pi09,pi05: in std_logic;
    po13,po11,po09,po07,po05,po03,po01: inout std_logic
  );
end Cookbook__fec_rot_4__part1;

architecture Cookbook__fec_rot_4__part1_behav of Cookbook__fec_rot_4__part1 is
signal n30: std_logic;
begin
    n30 <= ( not pi07 and pi03 )
      or ( pi07 and not pi03 );
    po13 <= ( not pi03 and pi01 )
      or ( pi03 and not pi01 );
    po11 <= ( not pi15 and pi01 )
      or ( pi15 and not pi01 );
    po09 <= ( not pi13 and pi03 )
      or ( pi13 and not pi03 );
    po07 <= ( not pi11 and pi01 )
      or ( pi11 and not pi01 );
    po05 <= ( not pi09 and pi03 )
      or ( pi09 and not pi03 );
    po03 <= ( not n30 and pi01 )
      or ( n30 and not pi01 );
    po01 <= ( not pi05 and pi01 )
      or ( pi05 and not pi01 );
end Cookbook__fec_rot_4__part1_behav;
