--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mult_shift is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8,pi9, CLK: in std_logic;
    : inout std_logic
  );
end Cookbook__mult_shift;

architecture Cookbook__mult_shift_behav of Cookbook__mult_shift is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,lo5,n28,n29,n30,n31,n32,li5,li1,li0,li2,li3,li4: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    DFF5: DFF port map (li5, CLK, lo5);
    n28 <= not (( not pi9 and not pi8 ));
    n29 <= not (( not pi6 and not pi5 ));
    n30 <= not (( not pi7 and not n29 ));
    n31 <= not (( not n28 and not n30 ));
    n32 <= ( n31 and pi3 );
    li5 <= ( lo5 and not pi0 )
      or ( pi2 and pi0 );
    li1 <= ( lo1 and not pi0 )
      or ( pi4 and pi0 );
    li0 <= ( lo0 and not pi0 )
      or ( n32 and pi0 );
    li2 <= ( lo2 and not pi1 )
      or ( lo5 and pi1 );
    li3 <= ( lo3 and not pi1 )
      or ( lo0 and pi1 );
    li4 <= ( lo4 and not pi1 )
      or ( lo1 and pi1 );
end Cookbook__mult_shift_behav;
