--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part14 is 
  Port (
    pi14,pi30,pi46: in std_logic;
    po14,po30: inout std_logic
  );
end Cookbook__compress_32__part14;

architecture Cookbook__compress_32__part14_behav of Cookbook__compress_32__part14 is
signal n81,n113,n129,n145,n161: std_logic;
begin
    n81 <= ( not pi14 and pi30 )
      or ( pi14 and not pi30 );
    po14 <= ( not n81 and pi46 )
      or ( n81 and not pi46 );
    n113 <= ( pi14 and pi46 );
    n129 <= ( pi14 and pi30 );
    n145 <= not (( not n129 and not n113 ));
    n161 <= ( pi30 and pi46 );
    po30 <= not (( not n145 and not n161 ));
end Cookbook__compress_32__part14_behav;
