--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_mux is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11: in std_logic;
    po0,n19,n24,n29,n34,n39,n44,n49_1,n54,n59,n64,n69,n74: inout std_logic
  );
end Cookbook__clock_mux;

architecture Cookbook__clock_mux_behav of Cookbook__clock_mux is
signal n45,n46,n47,n48,n49,n50,n51,n52,n57,n58,n60,n61,n62,n63: std_logic;
begin
    n45 <= not (( not lo07 and not lo10 ));
    n46 <= not (( not lo04 and not n45 ));
    n47 <= not (( not lo07 and not lo10 ));
    n48 <= not (( not lo01 and not n47 ));
    n49 <= not (( not lo01 and not lo04 ));
    n50 <= not (( not n49 and not lo10 ));
    n51 <= not (( not lo01 and not lo04 ));
    n52 <= not (( not n51 and not lo07 ));
    n74 <= ( pi7 and not n46 );
    n29 <= ( pi6 and not n48 );
    n44 <= ( pi5 and not n50 );
    n59 <= ( pi4 and not n52 );
    n57 <= not (( not n60 and not n61 ));
    n58 <= not (( not n62 and not n63 ));
    po0 <= not (( not n57 and not n58 ));
    n60 <= ( pi3 and lo01 );
    n61 <= ( pi2 and lo04 );
    n62 <= ( pi1 and lo07 );
    n63 <= ( pi0 and lo10 );
    n19 <= ( lo11 );
    n24 <= ( lo00 );
    n34 <= ( lo02 );
    n39 <= ( lo03 );
    n49_1 <= ( lo05 );
    n54 <= ( lo06 );
    n64 <= ( lo08 );
    n69 <= ( lo09 );
end Cookbook__clock_mux_behav;
