--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b06_opt is 
  Port (
    pi0,pi1,lo0,lo1,lo2,lo3,lo4,lo5,lo6,lo7,lo8: in std_logic;
    po0,po1,po2,po3,po4,po5,n17,n22,n27,n32,n37_1,n42,n47_1,n52_1,n57_1: inout std_logic
  );
end ITC99__b06_opt;

architecture ITC99__b06_opt_behav of ITC99__b06_opt is
signal n35,n36,n37,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66: std_logic;
begin
    n35 <= not (( lo1 and n62 ));
    n36 <= not (( not n49 and not pi0 ));
    n37 <= ( n65 and n64 );
    n27 <= not (( n37 and n54 ));
    n22 <= not (( n57 and n56 and n47 and n50 ));
    n17 <= not (( n55 and n36 ));
    n37_1 <= not (( n63 and n48 and n35 and n66 ));
    n32 <= not (( n61 and n49 and n60 ));
    n47_1 <= not (( pi0 and n52 and n37 ));
    n42 <= not (( n50 and n51 ));
    n52_1 <= not (( n59 and n58 ));
    n46 <= ( lo0 and lo1 and lo2 );
    n47 <= not (( pi0 and lo1 ));
    n48 <= not (( not lo0 and not lo2 ));
    n49 <= not (( not lo1 and not lo0 and lo2 ));
    n50 <= not (( lo0 and not lo2 and not lo1 and not pi0 ));
    n51 <= not (( lo0 and not n47 ));
    n52 <= not (( lo0 and lo1 ));
    n53 <= not (( not lo1 and not lo2 ));
    n54 <= not (( not pi0 and n53 ));
    n55 <= not (( lo0 and n54 ));
    n56 <= not (( pi0 and not lo0 and lo2 ));
    n57 <= not (( not n48 and lo1 ));
    n58 <= not (( lo1 and not pi0 and not n48 ));
    n59 <= not (( not pi1 and not n46 ));
    n60 <= not (( not n47 and not lo2 ));
    n61 <= not (( lo0 and n54 ));
    n62 <= not (( pi0 and not lo2 ));
    n63 <= not (( lo2 and lo0 ));
    n64 <= not (( not n48 and not lo1 ));
    n65 <= not (( lo2 and lo1 ));
    n66 <= not (( pi0 and not lo1 ));
    n57_1 <= ( n52_1 );
    po0 <= ( lo3 );
    po1 <= ( lo4 );
    po2 <= ( lo5 );
    po3 <= ( lo6 );
    po4 <= ( lo7 );
    po5 <= ( lo8 );
end ITC99__b06_opt_behav;
