--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,lo0,lo1: in std_logic;
    po0,po1,po2,po3,po4,n17,n22_1: inout std_logic
  );
end top;

architecture top_behav of top is
signal n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45: std_logic;
begin
    po0 <= ( not n21 );
    po1 <= ( not n22 );
    po2 <= ( not n23 );
    po3 <= ( not n24 );
    po4 <= ( not n25 );
    n17 <= ( not n26 );
    n22_1 <= ( not n27 );
    n21 <= ( not n30 and not n31 and not n34 and not n37 and not n41 );
    n22 <= ( not n36 and not n38 and not n42 and not n43 and not n44 );
    n23 <= ( not n30 and not n31 and not n35 and not n39 and not n40 );
    n24 <= ( not n28 and not n32 and not n33 and not n36 and not n41 and not n44 and not n45 );
    n25 <= ( not n35 and not n37 and not n42 and not n43 );
    n26 <= ( not n30 and not n34 and not n35 and not n39 and not n40 and not n42 and not n43 and not n44 and not n45 );
    n27 <= ( not n29 and not n34 and not n36 and not n40 and not n45 );
    n28 <= ( not pi0 and not pi1 and pi2 and lo0 );
    n29 <= ( pi0 and not pi2 and not lo0 and not lo1 );
    n30 <= ( pi0 and not pi1 and not pi2 and lo0 and lo1 );
    n31 <= ( not pi0 and not pi1 and pi2 and not lo0 );
    n32 <= ( pi0 and not pi1 and pi2 and not lo1 );
    n33 <= ( pi0 and not pi1 and pi2 and not lo0 );
    n34 <= ( pi1 and not pi2 and not lo0 and lo1 );
    n35 <= ( not pi0 and not pi1 and not pi2 and lo0 );
    n36 <= ( pi0 and pi1 and not pi2 and lo0 );
    n37 <= ( pi1 and pi2 and not lo1 );
    n38 <= ( pi0 and not pi1 and pi2 );
    n39 <= ( pi1 and pi2 and lo1 );
    n40 <= ( pi0 and pi1 and pi2 and not lo1 );
    n41 <= ( not pi0 and not pi2 and not lo0 );
    n42 <= ( pi0 and not pi1 and not pi2 and not lo1 );
    n43 <= ( pi0 and not pi1 and not pi2 and not lo0 );
    n44 <= ( pi0 and pi1 and not pi2 and not lo1 );
    n45 <= ( not pi0 and pi1 and not pi2 );
end top_behav;
