--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__newill is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7: in std_logic;
    po0: inout std_logic
  );
end Espresso__newill;

architecture Espresso__newill_behav of Espresso__newill is
begin
    po0 <= ( pi0 )
      or ( not pi3 and not pi4 and not pi5 and not pi6 and pi7 )
      or ( pi1 and pi2 and not pi3 and not pi5 and pi6 and pi7 )
      or ( pi1 and pi3 and pi4 and not pi5 and pi6 and pi7 )
      or ( pi1 and not pi2 and not pi4 and not pi5 and pi6 and pi7 )
      or ( pi1 and pi2 and pi4 and pi5 and not pi6 and pi7 )
      or ( pi1 and not pi3 and pi4 and pi5 and not pi6 and pi7 )
      or ( pi1 and pi2 and not pi4 and not pi5 and not pi6 and pi7 );
end Espresso__newill_behav;
