--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part684 is 
  Port (
    lo3333: in std_logic;
    n11759: inout std_logic
  );
end Other__sudoku_check__part684;

architecture Other__sudoku_check__part684_behav of Other__sudoku_check__part684 is
begin
    n11759 <= ( lo3333 );
end Other__sudoku_check__part684_behav;
