--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part61 is 
  Port (
    pi0756: in std_logic;
    n24884: inout std_logic
  );
end Other__carpat__part61;

architecture Other__carpat__part61_behav of Other__carpat__part61 is
begin
    n24884 <= ( pi0756 );
end Other__carpat__part61_behav;
