--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part157 is 
  Port (
    lo0037: in std_logic;
    po25: inout std_logic
  );
end IWLS2005__des_perf__part157;

architecture IWLS2005__des_perf__part157_behav of IWLS2005__des_perf__part157 is
begin
    po25 <= ( lo0037 );
end IWLS2005__des_perf__part157_behav;
