--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part543 is 
  Port (
    lo4127: in std_logic;
    n20925: inout std_logic
  );
end IWLS2005__des_perf__part543;

architecture IWLS2005__des_perf__part543_behav of IWLS2005__des_perf__part543 is
begin
    n20925 <= ( lo4127 );
end IWLS2005__des_perf__part543_behav;
