--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2019 is 
  Port (
    lo4520: in std_logic;
    n27186: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2019;

architecture Other__ucsb_152_tap_fir__part2019_behav of Other__ucsb_152_tap_fir__part2019 is
begin
    n27186 <= ( lo4520 );
end Other__ucsb_152_tap_fir__part2019_behav;
