--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1198 is 
  Port (
    lo7445: in std_logic;
    n41404_1: inout std_logic
  );
end Other__carpat__part1198;

architecture Other__carpat__part1198_behav of Other__carpat__part1198 is
begin
    n41404_1 <= ( lo7445 );
end Other__carpat__part1198_behav;
