--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part488 is 
  Port (
    lo05960: in std_logic;
    po1475,po1540,po1832,po1901: inout std_logic
  );
end Other__ray__part488;

architecture Other__ray__part488_behav of Other__ray__part488 is
begin
    po1475 <= ( lo05960 );
    po1540 <= ( lo05960 );
    po1832 <= ( lo05960 );
    po1901 <= ( lo05960 );
end Other__ray__part488_behav;
