--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part830 is 
  Port (
    lo4627: in std_logic;
    n23150: inout std_logic
  );
end IWLS2005__des_perf__part830;

architecture IWLS2005__des_perf__part830_behav of IWLS2005__des_perf__part830 is
begin
    n23150 <= ( lo4627 );
end IWLS2005__des_perf__part830_behav;
