--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part40 is 
  Port (
    lo2167: in std_logic;
    n5319: inout std_logic
  );
end Other__sudoku_check__part40;

architecture Other__sudoku_check__part40_behav of Other__sudoku_check__part40 is
begin
    n5319 <= ( lo2167 );
end Other__sudoku_check__part40_behav;
