--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1261 is 
  Port (
    lo5550: in std_logic;
    n27675_1: inout std_logic
  );
end IWLS2005__des_perf__part1261;

architecture IWLS2005__des_perf__part1261_behav of IWLS2005__des_perf__part1261 is
begin
    n27675_1 <= ( lo5550 );
end IWLS2005__des_perf__part1261_behav;
