--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part1 is 
  Port (
    pi001: in std_logic;
    n2232_1: inout std_logic
  );
end Other__fpu__part1;

architecture Other__fpu__part1_behav of Other__fpu__part1 is
begin
    n2232_1 <= ( pi001 );
end Other__fpu__part1_behav;
