--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1630 is 
  Port (
    lo8422: in std_logic;
    n47009: inout std_logic
  );
end Other__carpat__part1630;

architecture Other__carpat__part1630_behav of Other__carpat__part1630 is
begin
    n47009 <= ( lo8422 );
end Other__carpat__part1630_behav;
