--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2304 is 
  Port (
    lo5088: in std_logic;
    n30006: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2304;

architecture Other__ucsb_152_tap_fir__part2304_behav of Other__ucsb_152_tap_fir__part2304 is
begin
    n30006 <= ( lo5088 );
end Other__ucsb_152_tap_fir__part2304_behav;
