--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part231 is 
  Port (
    lo0300: in std_logic;
    n1799: inout std_logic
  );
end Cookbook__fec_check__part231;

architecture Cookbook__fec_check__part231_behav of Cookbook__fec_check__part231 is
begin
    n1799 <= ( lo0300 );
end Cookbook__fec_check__part231_behav;
