--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s5378__part2 is 
  Port (
    pi33,lo017: in std_logic;
    n258: inout std_logic
  );
end ISCAS__s5378__part2;

architecture ISCAS__s5378__part2_behav of ISCAS__s5378__part2 is
signal n253: std_logic;
begin
    n253 <= ( not pi33 and lo017 );
    n258 <= ( n253 );
end ISCAS__s5378__part2_behav;
