--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1093 is 
  Port (
    lo4462: in std_logic;
    n17799: inout std_logic
  );
end Other__sudoku_check__part1093;

architecture Other__sudoku_check__part1093_behav of Other__sudoku_check__part1093 is
begin
    n17799 <= ( lo4462 );
end Other__sudoku_check__part1093_behav;
