--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part28 is 
  Port (
    lo26: in std_logic;
    po13: inout std_logic
  );
end Cookbook__pipeline_add__part28;

architecture Cookbook__pipeline_add__part28_behav of Cookbook__pipeline_add__part28 is
begin
    po13 <= ( lo26 );
end Cookbook__pipeline_add__part28_behav;
