--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part81 is 
  Port (
    lo2404: in std_logic;
    po191: inout std_logic
  );
end IWLS2005__pci_bridge32__part81;

architecture IWLS2005__pci_bridge32__part81_behav of IWLS2005__pci_bridge32__part81 is
begin
    po191 <= ( lo2404 );
end IWLS2005__pci_bridge32__part81_behav;
