--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2474 is 
  Port (
    lo5460: in std_logic;
    n31806: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2474;

architecture Other__ucsb_152_tap_fir__part2474_behav of Other__ucsb_152_tap_fir__part2474 is
begin
    n31806 <= ( lo5460 );
end Other__ucsb_152_tap_fir__part2474_behav;
