--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part791 is 
  Port (
    lo0860: in std_logic;
    n4599: inout std_logic
  );
end Cookbook__fec_check__part791;

architecture Cookbook__fec_check__part791_behav of Cookbook__fec_check__part791 is
begin
    n4599 <= ( lo0860 );
end Cookbook__fec_check__part791_behav;
