--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part160 is 
  Port (
    lo2809: in std_logic;
    n6519: inout std_logic
  );
end Other__sudoku_check__part160;

architecture Other__sudoku_check__part160_behav of Other__sudoku_check__part160 is
begin
    n6519 <= ( lo2809 );
end Other__sudoku_check__part160_behav;
