--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part343 is 
  Port (
    lo2992: in std_logic;
    n8349: inout std_logic
  );
end Other__sudoku_check__part343;

architecture Other__sudoku_check__part343_behav of Other__sudoku_check__part343 is
begin
    n8349 <= ( lo2992 );
end Other__sudoku_check__part343_behav;
