--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part365 is 
  Port (
    lo05685: in std_logic;
    po6077,po6128,po6383,po6434: inout std_logic
  );
end Other__ray__part365;

architecture Other__ray__part365_behav of Other__ray__part365 is
begin
    po6077 <= ( lo05685 );
    po6128 <= ( lo05685 );
    po6383 <= ( lo05685 );
    po6434 <= ( lo05685 );
end Other__ray__part365_behav;
