--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part33 is 
  Port (
    pi33: in std_logic;
    n544213: inout std_logic
  );
end IWLS2005__leon3mp__part33;

architecture IWLS2005__leon3mp__part33_behav of IWLS2005__leon3mp__part33 is
begin
    n544213 <= ( pi33 );
end IWLS2005__leon3mp__part33_behav;
