--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part177 is 
  Port (
    lo0712: in std_logic;
    n5780: inout std_logic
  );
end Other__fp_operators__part177;

architecture Other__fp_operators__part177_behav of Other__fp_operators__part177 is
begin
    n5780 <= ( lo0712 );
end Other__fp_operators__part177_behav;
