--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part68 is 
  Port (
    lo144: in std_logic;
    po34: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part68;

architecture Cookbook__soft_ecc_ram_32bit__part68_behav of Cookbook__soft_ecc_ram_32bit__part68 is
begin
    po34 <= ( lo144 );
end Cookbook__soft_ecc_ram_32bit__part68_behav;
