--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1023 is 
  Port (
    lo5053: in std_logic;
    n25330: inout std_logic
  );
end IWLS2005__des_perf__part1023;

architecture IWLS2005__des_perf__part1023_behav of IWLS2005__des_perf__part1023 is
begin
    n25330 <= ( lo5053 );
end IWLS2005__des_perf__part1023_behav;
