--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part43 is 
  Port (
    lo42: in std_logic;
    po26: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part43;

architecture Cookbook__x4_decoder_8b10b__part43_behav of Cookbook__x4_decoder_8b10b__part43 is
begin
    po26 <= ( lo42 );
end Cookbook__x4_decoder_8b10b__part43_behav;
