--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part154 is 
  Port (
    lo2803: in std_logic;
    n6459: inout std_logic
  );
end Other__sudoku_check__part154;

architecture Other__sudoku_check__part154_behav of Other__sudoku_check__part154 is
begin
    n6459 <= ( lo2803 );
end Other__sudoku_check__part154_behav;
