--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part906 is 
  Port (
    lo4815: in std_logic;
    n24200: inout std_logic
  );
end IWLS2005__des_perf__part906;

architecture IWLS2005__des_perf__part906_behav of IWLS2005__des_perf__part906 is
begin
    n24200 <= ( lo4815 );
end IWLS2005__des_perf__part906_behav;
