--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1796 is 
  Port (
    lo8891: in std_logic;
    po327: inout std_logic
  );
end Other__carpat__part1796;

architecture Other__carpat__part1796_behav of Other__carpat__part1796 is
begin
    po327 <= ( lo8891 );
end Other__carpat__part1796_behav;
