--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part26 is 
  Port (
    lo064: in std_logic;
    po08: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part26;

architecture Cookbook__soft_ecc_ram_32bit__part26_behav of Cookbook__soft_ecc_ram_32bit__part26 is
begin
    po08 <= ( lo064 );
end Cookbook__soft_ecc_ram_32bit__part26_behav;
