--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part115 is 
  Port (
    lo0711: in std_logic;
    po019: inout std_logic
  );
end IWLS2005__mem_ctrl__part115;

architecture IWLS2005__mem_ctrl__part115_behav of IWLS2005__mem_ctrl__part115 is
begin
    po019 <= ( lo0711 );
end IWLS2005__mem_ctrl__part115_behav;
