--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1236 is 
  Port (
    lo2863: in std_logic;
    n18881: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1236;

architecture Other__ucsb_152_tap_fir__part1236_behav of Other__ucsb_152_tap_fir__part1236 is
begin
    n18881 <= ( lo2863 );
end Other__ucsb_152_tap_fir__part1236_behav;
