--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part35 is 
  Port (
    lo34: in std_logic;
    po34: inout std_logic
  );
end Other__idxlat03n_m12__part35;

architecture Other__idxlat03n_m12__part35_behav of Other__idxlat03n_m12__part35 is
begin
    po34 <= ( lo34 );
end Other__idxlat03n_m12__part35_behav;
