--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part69 is 
  Port (
    lo0138: in std_logic;
    n989: inout std_logic
  );
end Cookbook__fec_check__part69;

architecture Cookbook__fec_check__part69_behav of Cookbook__fec_check__part69 is
begin
    n989 <= ( lo0138 );
end Cookbook__fec_check__part69_behav;
