--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part820 is 
  Port (
    lo6449: in std_logic;
    n30499_1: inout std_logic
  );
end Other__carpat__part820;

architecture Other__carpat__part820_behav of Other__carpat__part820 is
begin
    n30499_1 <= ( lo6449 );
end Other__carpat__part820_behav;
