--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part816 is 
  Port (
    lo0885: in std_logic;
    n4724: inout std_logic
  );
end Cookbook__fec_check__part816;

architecture Cookbook__fec_check__part816_behav of Cookbook__fec_check__part816 is
begin
    n4724 <= ( lo0885 );
end Cookbook__fec_check__part816_behav;
