--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part172 is 
  Port (
    lo0611: in std_logic;
    n4314: inout std_logic
  );
end Cookbook__ucrypt__part172;

architecture Cookbook__ucrypt__part172_behav of Cookbook__ucrypt__part172 is
begin
    n4314 <= ( lo0611 );
end Cookbook__ucrypt__part172_behav;
