--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part215 is 
  Port (
    lo2864: in std_logic;
    n7069: inout std_logic
  );
end Other__sudoku_check__part215;

architecture Other__sudoku_check__part215_behav of Other__sudoku_check__part215 is
begin
    n7069 <= ( lo2864 );
end Other__sudoku_check__part215_behav;
