--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part879 is 
  Port (
    lo07204: in std_logic;
    n50421: inout std_logic
  );
end Other__ray__part879;

architecture Other__ray__part879_behav of Other__ray__part879 is
begin
    n50421 <= ( lo07204 );
end Other__ray__part879_behav;
