--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__rgb_to_hue__part18 is 
  Port (
    lo53: in std_logic;
    po2: inout std_logic
  );
end Cookbook__rgb_to_hue__part18;

architecture Cookbook__rgb_to_hue__part18_behav of Cookbook__rgb_to_hue__part18 is
begin
    po2 <= ( lo53 );
end Cookbook__rgb_to_hue__part18_behav;
