--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1978 is 
  Port (
    lo7005: in std_logic;
    n34685_1: inout std_logic
  );
end IWLS2005__des_perf__part1978;

architecture IWLS2005__des_perf__part1978_behav of IWLS2005__des_perf__part1978 is
begin
    n34685_1 <= ( lo7005 );
end IWLS2005__des_perf__part1978_behav;
