--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense__part1 is 
  Port (
    lo21: in std_logic;
    po28: inout std_logic
  );
end Cookbook__temp_sense__part1;

architecture Cookbook__temp_sense__part1_behav of Cookbook__temp_sense__part1 is
begin
    po28 <= ( lo21 );
end Cookbook__temp_sense__part1_behav;
