--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part300 is 
  Port (
    lo1732: in std_logic;
    n8274_1: inout std_logic
  );
end Other__desperf__part300;

architecture Other__desperf__part300_behav of Other__desperf__part300 is
begin
    n8274_1 <= ( lo1732 );
end Other__desperf__part300_behav;
