--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2035 is 
  Port (
    lo2104: in std_logic;
    n10819: inout std_logic
  );
end Cookbook__fec_check__part2035;

architecture Cookbook__fec_check__part2035_behav of Cookbook__fec_check__part2035 is
begin
    n10819 <= ( lo2104 );
end Cookbook__fec_check__part2035_behav;
