--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1044 is 
  Port (
    lo1113: in std_logic;
    n5864: inout std_logic
  );
end Cookbook__fec_check__part1044;

architecture Cookbook__fec_check__part1044_behav of Cookbook__fec_check__part1044 is
begin
    n5864 <= ( lo1113 );
end Cookbook__fec_check__part1044_behav;
