--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part958 is 
  Port (
    lo4884: in std_logic;
    n24005: inout std_logic
  );
end IWLS2005__des_perf__part958;

architecture IWLS2005__des_perf__part958_behav of IWLS2005__des_perf__part958 is
begin
    n24005 <= ( lo4884 );
end IWLS2005__des_perf__part958_behav;
