--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part648 is 
  Port (
    lo06145: in std_logic;
    po1726,po1762: inout std_logic
  );
end Other__ray__part648;

architecture Other__ray__part648_behav of Other__ray__part648 is
begin
    po1726 <= ( lo06145 );
    po1762 <= ( lo06145 );
end Other__ray__part648_behav;
