--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1277 is 
  Port (
    lo4646: in std_logic;
    n18719: inout std_logic
  );
end Other__sudoku_check__part1277;

architecture Other__sudoku_check__part1277_behav of Other__sudoku_check__part1277 is
begin
    n18719 <= ( lo4646 );
end Other__sudoku_check__part1277_behav;
