--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1490 is 
  Port (
    lo3404: in std_logic;
    n21526: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1490;

architecture Other__ucsb_152_tap_fir__part1490_behav of Other__ucsb_152_tap_fir__part1490 is
begin
    n21526 <= ( lo3404 );
end Other__ucsb_152_tap_fir__part1490_behav;
