--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part381 is 
  Port (
    lo2190: in std_logic;
    n11465: inout std_logic
  );
end IWLS2005__des_perf__part381;

architecture IWLS2005__des_perf__part381_behav of IWLS2005__des_perf__part381 is
begin
    n11465 <= ( lo2190 );
end IWLS2005__des_perf__part381_behav;
