--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2272 is 
  Port (
    lo5023: in std_logic;
    n29696: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2272;

architecture Other__ucsb_152_tap_fir__part2272_behav of Other__ucsb_152_tap_fir__part2272 is
begin
    n29696 <= ( lo5023 );
end Other__ucsb_152_tap_fir__part2272_behav;
