--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2133 is 
  Port (
    lo4739: in std_logic;
    n28196: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2133;

architecture Other__ucsb_152_tap_fir__part2133_behav of Other__ucsb_152_tap_fir__part2133 is
begin
    n28196 <= ( lo4739 );
end Other__ucsb_152_tap_fir__part2133_behav;
