--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1364 is 
  Port (
    lo7814: in std_logic;
    n43949: inout std_logic
  );
end Other__carpat__part1364;

architecture Other__carpat__part1364_behav of Other__carpat__part1364 is
begin
    n43949 <= ( lo7814 );
end Other__carpat__part1364_behav;
