--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part55 is 
  Port (
    lo0123: in std_logic;
    po131: inout std_logic
  );
end Other__mem__part55;

architecture Other__mem__part55_behav of Other__mem__part55 is
begin
    po131 <= ( lo0123 );
end Other__mem__part55_behav;
