--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part147 is 
  Port (
    pi0557: in std_logic;
    n43331_1: inout std_logic
  );
end Other__radar__part147;

architecture Other__radar__part147_behav of Other__radar__part147 is
begin
    n43331_1 <= ( pi0557 );
end Other__radar__part147_behav;
