--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part553 is 
  Port (
    lo3344: in std_logic;
    n15774: inout std_logic
  );
end Other__carpat__part553;

architecture Other__carpat__part553_behav of Other__carpat__part553 is
begin
    n15774 <= ( lo3344 );
end Other__carpat__part553_behav;
