--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part57 is 
  Port (
    lo56: in std_logic;
    po56: inout std_logic
  );
end Other__idxlat00n_m12__part57;

architecture Other__idxlat00n_m12__part57_behav of Other__idxlat00n_m12__part57 is
begin
    po56 <= ( lo56 );
end Other__idxlat00n_m12__part57_behav;
