--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part20 is 
  Port (
    lo058: in std_logic;
    po12: inout std_logic
  );
end Cookbook__fec_gen__part20;

architecture Cookbook__fec_gen__part20_behav of Cookbook__fec_gen__part20 is
begin
    po12 <= ( lo058 );
end Cookbook__fec_gen__part20_behav;
