--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2547 is 
  Port (
    lo5619: in std_logic;
    n32681: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2547;

architecture Other__ucsb_152_tap_fir__part2547_behav of Other__ucsb_152_tap_fir__part2547 is
begin
    n32681 <= ( lo5619 );
end Other__ucsb_152_tap_fir__part2547_behav;
