--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part506 is 
  Port (
    lo2502: in std_logic;
    n14729: inout std_logic
  );
end Other__carpat__part506;

architecture Other__carpat__part506_behav of Other__carpat__part506 is
begin
    n14729 <= ( lo2502 );
end Other__carpat__part506_behav;
