--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part20 is 
  Port (
    lo0018: in std_logic;
    po0022: inout std_logic
  );
end Other__ether__part20;

architecture Other__ether__part20_behav of Other__ether__part20 is
begin
    po0022 <= ( lo0018 );
end Other__ether__part20_behav;
