--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part894 is 
  Port (
    lo0963: in std_logic;
    n5114: inout std_logic
  );
end Cookbook__fec_check__part894;

architecture Cookbook__fec_check__part894_behav of Cookbook__fec_check__part894 is
begin
    n5114 <= ( lo0963 );
end Cookbook__fec_check__part894_behav;
