--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part9 is 
  Port (
    pi009: in std_logic;
    n9694_1: inout std_logic
  );
end Other__desperf__part9;

architecture Other__desperf__part9_behav of Other__desperf__part9 is
begin
    n9694_1 <= ( pi009 );
end Other__desperf__part9_behav;
