--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part63 is 
  Port (
    pi0473: in std_logic;
    n42911_1: inout std_logic
  );
end Other__radar__part63;

architecture Other__radar__part63_behav of Other__radar__part63 is
begin
    n42911_1 <= ( pi0473 );
end Other__radar__part63_behav;
