--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part48 is 
  Port (
    pi048: in std_logic;
    n2467_1: inout std_logic
  );
end Other__fpu__part48;

architecture Other__fpu__part48_behav of Other__fpu__part48 is
begin
    n2467_1 <= ( pi048 );
end Other__fpu__part48_behav;
