--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1543 is 
  Port (
    lo8174: in std_logic;
    n45939_1: inout std_logic
  );
end Other__carpat__part1543;

architecture Other__carpat__part1543_behav of Other__carpat__part1543 is
begin
    n45939_1 <= ( lo8174 );
end Other__carpat__part1543_behav;
