--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part199 is 
  Port (
    lo0397: in std_logic;
    n1434: inout std_logic
  );
end Other__desperf__part199;

architecture Other__desperf__part199_behav of Other__desperf__part199 is
begin
    n1434 <= ( lo0397 );
end Other__desperf__part199_behav;
