--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part173 is 
  Port (
    lo0414: in std_logic;
    n6581: inout std_logic
  );
end Other__ucsb_152_tap_fir__part173;

architecture Other__ucsb_152_tap_fir__part173_behav of Other__ucsb_152_tap_fir__part173 is
begin
    n6581 <= ( lo0414 );
end Other__ucsb_152_tap_fir__part173_behav;
