--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1644 is 
  Port (
    lo6332: in std_logic;
    n31250: inout std_logic
  );
end IWLS2005__des_perf__part1644;

architecture IWLS2005__des_perf__part1644_behav of IWLS2005__des_perf__part1644 is
begin
    n31250 <= ( lo6332 );
end IWLS2005__des_perf__part1644_behav;
