--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part454 is 
  Port (
    lo3103: in std_logic;
    n9459: inout std_logic
  );
end Other__sudoku_check__part454;

architecture Other__sudoku_check__part454_behav of Other__sudoku_check__part454 is
begin
    n9459 <= ( lo3103 );
end Other__sudoku_check__part454_behav;
