--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part3 is 
  Port (
    lo00410: in std_logic;
    po25: inout std_logic
  );
end IWLS2005__vga_lcd__part3;

architecture IWLS2005__vga_lcd__part3_behav of IWLS2005__vga_lcd__part3 is
begin
    po25 <= ( lo00410 );
end IWLS2005__vga_lcd__part3_behav;
