--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part50 is 
  Port (
    lo164: in std_logic;
    po16: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part50;

architecture Cookbook__ycbcr_to_rgb__part50_behav of Cookbook__ycbcr_to_rgb__part50 is
begin
    po16 <= ( lo164 );
end Cookbook__ycbcr_to_rgb__part50_behav;
