--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part8 is 
  Port (
    lo04: in std_logic;
    po05: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part8;

architecture Cookbook__x4_encoder_8b10b__part8_behav of Cookbook__x4_encoder_8b10b__part8 is
begin
    po05 <= ( lo04 );
end Cookbook__x4_encoder_8b10b__part8_behav;
