--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2800 is 
  Port (
    lo8113: in std_logic;
    n40935_1: inout std_logic
  );
end IWLS2005__des_perf__part2800;

architecture IWLS2005__des_perf__part2800_behav of IWLS2005__des_perf__part2800 is
begin
    n40935_1 <= ( lo8113 );
end IWLS2005__des_perf__part2800_behav;
