--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part468 is 
  Port (
    lo05940: in std_logic;
    po1406,po1440: inout std_logic
  );
end Other__ray__part468;

architecture Other__ray__part468_behav of Other__ray__part468 is
begin
    po1406 <= ( lo05940 );
    po1440 <= ( lo05940 );
end Other__ray__part468_behav;
