--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1126 is 
  Port (
    lo4495: in std_logic;
    n17964: inout std_logic
  );
end Other__sudoku_check__part1126;

architecture Other__sudoku_check__part1126_behav of Other__sudoku_check__part1126 is
begin
    n17964 <= ( lo4495 );
end Other__sudoku_check__part1126_behav;
