--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1238 is 
  Port (
    lo4607: in std_logic;
    n18524: inout std_logic
  );
end Other__sudoku_check__part1238;

architecture Other__sudoku_check__part1238_behav of Other__sudoku_check__part1238 is
begin
    n18524 <= ( lo4607 );
end Other__sudoku_check__part1238_behav;
