--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1765 is 
  Port (
    lo1834: in std_logic;
    n9469: inout std_logic
  );
end Cookbook__fec_check__part1765;

architecture Cookbook__fec_check__part1765_behav of Cookbook__fec_check__part1765 is
begin
    n9469 <= ( lo1834 );
end Cookbook__fec_check__part1765_behav;
