--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2319 is 
  Port (
    lo3423,lo3411,lo3787: in std_logic;
    n18914: inout std_logic
  );
end Cookbook__fec_check__part2319;

architecture Cookbook__fec_check__part2319_behav of Cookbook__fec_check__part2319 is
signal n13716: std_logic;
begin
    n13716 <= not (( not lo3423 and not lo3411 ));
    n18914 <= not (( not n13716 and not lo3787 ));
end Cookbook__fec_check__part2319_behav;
