--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2069 is 
  Port (
    lo2138: in std_logic;
    n10989: inout std_logic
  );
end Cookbook__fec_check__part2069;

architecture Cookbook__fec_check__part2069_behav of Cookbook__fec_check__part2069 is
begin
    n10989 <= ( lo2138 );
end Cookbook__fec_check__part2069_behav;
