--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1908 is 
  Port (
    lo1977: in std_logic;
    n10184: inout std_logic
  );
end Cookbook__fec_check__part1908;

architecture Cookbook__fec_check__part1908_behav of Cookbook__fec_check__part1908 is
begin
    n10184 <= ( lo1977 );
end Cookbook__fec_check__part1908_behav;
