--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_8bit__part16 is 
  Port (
    lo40: in std_logic;
    po14: inout std_logic
  );
end Cookbook__soft_ecc_ram_8bit__part16;

architecture Cookbook__soft_ecc_ram_8bit__part16_behav of Cookbook__soft_ecc_ram_8bit__part16 is
begin
    po14 <= ( lo40 );
end Cookbook__soft_ecc_ram_8bit__part16_behav;
