--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1321 is 
  Port (
    lo4690: in std_logic;
    n18939: inout std_logic
  );
end Other__sudoku_check__part1321;

architecture Other__sudoku_check__part1321_behav of Other__sudoku_check__part1321 is
begin
    n18939 <= ( lo4690 );
end Other__sudoku_check__part1321_behav;
