--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part9 is 
  Port (
    pi12: in std_logic;
    n157: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part9;

architecture Cookbook__ycbcr_to_rgb__part9_behav of Cookbook__ycbcr_to_rgb__part9 is
begin
    n157 <= ( pi12 );
end Cookbook__ycbcr_to_rgb__part9_behav;
