--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1339 is 
  Port (
    lo1408: in std_logic;
    n7339: inout std_logic
  );
end Cookbook__fec_check__part1339;

architecture Cookbook__fec_check__part1339_behav of Cookbook__fec_check__part1339 is
begin
    n7339 <= ( lo1408 );
end Cookbook__fec_check__part1339_behav;
