--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part609 is 
  Port (
    lo3258: in std_logic;
    n11009: inout std_logic
  );
end Other__sudoku_check__part609;

architecture Other__sudoku_check__part609_behav of Other__sudoku_check__part609 is
begin
    n11009 <= ( lo3258 );
end Other__sudoku_check__part609_behav;
