--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part95 is 
  Port (
    lo0164: in std_logic;
    n1119: inout std_logic
  );
end Cookbook__fec_check__part95;

architecture Cookbook__fec_check__part95_behav of Cookbook__fec_check__part95 is
begin
    n1119 <= ( lo0164 );
end Cookbook__fec_check__part95_behav;
