--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part355 is 
  Port (
    lo0424: in std_logic;
    n2419: inout std_logic
  );
end Cookbook__fec_check__part355;

architecture Cookbook__fec_check__part355_behav of Cookbook__fec_check__part355 is
begin
    n2419 <= ( lo0424 );
end Cookbook__fec_check__part355_behav;
