--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1802 is 
  Port (
    lo4101: in std_logic;
    n24926: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1802;

architecture Other__ucsb_152_tap_fir__part1802_behav of Other__ucsb_152_tap_fir__part1802 is
begin
    n24926 <= ( lo4101 );
end Other__ucsb_152_tap_fir__part1802_behav;
