--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part142 is 
  Port (
    lo1000: in std_logic;
    po080: inout std_logic
  );
end IWLS2005__mem_ctrl__part142;

architecture IWLS2005__mem_ctrl__part142_behav of IWLS2005__mem_ctrl__part142 is
begin
    po080 <= ( lo1000 );
end IWLS2005__mem_ctrl__part142_behav;
