--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr__part3 is 
  Port (
    lo04: in std_logic;
    n90,po27: inout std_logic
  );
end Cookbook__lfsr__part3;

architecture Cookbook__lfsr__part3_behav of Cookbook__lfsr__part3 is
begin
    n90 <= ( lo04 );
    po27 <= ( lo04 );
end Cookbook__lfsr__part3_behav;
