--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part383 is 
  Port (
    pi1749: in std_logic;
    n48379_1: inout std_logic
  );
end Other__carpat__part383;

architecture Other__carpat__part383_behav of Other__carpat__part383 is
begin
    n48379_1 <= ( pi1749 );
end Other__carpat__part383_behav;
