--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part960 is 
  Port (
    lo4911: in std_logic;
    n24960: inout std_logic
  );
end IWLS2005__des_perf__part960;

architecture IWLS2005__des_perf__part960_behav of IWLS2005__des_perf__part960 is
begin
    n24960 <= ( lo4911 );
end IWLS2005__des_perf__part960_behav;
