--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1972 is 
  Port (
    lo4399: in std_logic;
    n26496: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1972;

architecture Other__ucsb_152_tap_fir__part1972_behav of Other__ucsb_152_tap_fir__part1972 is
begin
    n26496 <= ( lo4399 );
end Other__ucsb_152_tap_fir__part1972_behav;
