--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part706 is 
  Port (
    lo3355: in std_logic;
    n11979: inout std_logic
  );
end Other__sudoku_check__part706;

architecture Other__sudoku_check__part706_behav of Other__sudoku_check__part706 is
begin
    n11979 <= ( lo3355 );
end Other__sudoku_check__part706_behav;
