--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part27 is 
  Port (
    lo1948: in std_logic;
    n5199: inout std_logic
  );
end Other__sudoku_check__part27;

architecture Other__sudoku_check__part27_behav of Other__sudoku_check__part27 is
begin
    n5199 <= ( lo1948 );
end Other__sudoku_check__part27_behav;
