--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1035 is 
  Port (
    lo10770: in std_logic;
    n72191_1: inout std_logic
  );
end Other__ray__part1035;

architecture Other__ray__part1035_behav of Other__ray__part1035 is
begin
    n72191_1 <= ( lo10770 );
end Other__ray__part1035_behav;
