--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part554 is 
  Port (
    lo3345: in std_logic;
    n15779: inout std_logic
  );
end Other__carpat__part554;

architecture Other__carpat__part554_behav of Other__carpat__part554 is
begin
    n15779 <= ( lo3345 );
end Other__carpat__part554_behav;
