--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part206 is 
  Port (
    lo310: in std_logic;
    n1062: inout std_logic
  );
end Other__fpu__part206;

architecture Other__fpu__part206_behav of Other__fpu__part206 is
begin
    n1062 <= ( lo310 );
end Other__fpu__part206_behav;
