--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part85 is 
  Port (
    lo339: in std_logic;
    n1993: inout std_logic
  );
end ISCAS__s13207__part85;

architecture ISCAS__s13207__part85_behav of ISCAS__s13207__part85 is
begin
    n1993 <= ( lo339 );
end ISCAS__s13207__part85_behav;
