--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part21 is 
  Port (
    lo97520: in std_logic;
    n487545_1: inout std_logic
  );
end IWLS2005__netcard__part21;

architecture IWLS2005__netcard__part21_behav of IWLS2005__netcard__part21 is
begin
    n487545_1 <= ( lo97520 );
end IWLS2005__netcard__part21_behav;
