--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part205 is 
  Port (
    lo0733: in std_logic;
    n4774: inout std_logic
  );
end Cookbook__ucrypt__part205;

architecture Cookbook__ucrypt__part205_behav of Cookbook__ucrypt__part205 is
begin
    n4774 <= ( lo0733 );
end Cookbook__ucrypt__part205_behav;
