--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1864 is 
  Port (
    lo6780: in std_logic;
    n33545: inout std_logic
  );
end IWLS2005__des_perf__part1864;

architecture IWLS2005__des_perf__part1864_behav of IWLS2005__des_perf__part1864 is
begin
    n33545 <= ( lo6780 );
end IWLS2005__des_perf__part1864_behav;
