--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1762 is 
  Port (
    lo8833: in std_logic;
    po288: inout std_logic
  );
end Other__carpat__part1762;

architecture Other__carpat__part1762_behav of Other__carpat__part1762 is
begin
    po288 <= ( lo8833 );
end Other__carpat__part1762_behav;
