--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part140 is 
  Port (
    lo0467: in std_logic;
    n3594: inout std_logic
  );
end Cookbook__ucrypt__part140;

architecture Cookbook__ucrypt__part140_behav of Cookbook__ucrypt__part140 is
begin
    n3594 <= ( lo0467 );
end Cookbook__ucrypt__part140_behav;
