--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1573 is 
  Port (
    lo1642: in std_logic;
    n8509: inout std_logic
  );
end Cookbook__fec_check__part1573;

architecture Cookbook__fec_check__part1573_behav of Cookbook__fec_check__part1573 is
begin
    n8509 <= ( lo1642 );
end Cookbook__fec_check__part1573_behav;
