--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part4 is 
  Port (
    lo042: in std_logic;
    po28: inout std_logic
  );
end Cookbook__fec_gen__part4;

architecture Cookbook__fec_gen__part4_behav of Cookbook__fec_gen__part4 is
begin
    po28 <= ( lo042 );
end Cookbook__fec_gen__part4_behav;
