--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part1 is 
  Port (
    pi01: in std_logic;
    n544323: inout std_logic
  );
end IWLS2005__leon3mp__part1;

architecture IWLS2005__leon3mp__part1_behav of IWLS2005__leon3mp__part1 is
begin
    n544323 <= ( pi01 );
end IWLS2005__leon3mp__part1_behav;
