--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part138 is 
  Port (
    lo0488: in std_logic;
    n4860: inout std_logic
  );
end Other__fp_operators__part138;

architecture Other__fp_operators__part138_behav of Other__fp_operators__part138 is
begin
    n4860 <= ( lo0488 );
end Other__fp_operators__part138_behav;
