--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part462 is 
  Port (
    lo05934: in std_logic;
    po1400,po1434: inout std_logic
  );
end Other__ray__part462;

architecture Other__ray__part462_behav of Other__ray__part462 is
begin
    po1400 <= ( lo05934 );
    po1434 <= ( lo05934 );
end Other__ray__part462_behav;
