--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part339 is 
  Port (
    pi1671: in std_logic;
    n47939_1: inout std_logic
  );
end Other__carpat__part339;

architecture Other__carpat__part339_behav of Other__carpat__part339 is
begin
    n47939_1 <= ( pi1671 );
end Other__carpat__part339_behav;
