--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1811 is 
  Port (
    lo9057: in std_logic;
    po442: inout std_logic
  );
end Other__carpat__part1811;

architecture Other__carpat__part1811_behav of Other__carpat__part1811 is
begin
    po442 <= ( lo9057 );
end Other__carpat__part1811_behav;
