--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1516 is 
  Port (
    lo1585: in std_logic;
    n8224: inout std_logic
  );
end Cookbook__fec_check__part1516;

architecture Cookbook__fec_check__part1516_behav of Cookbook__fec_check__part1516 is
begin
    n8224 <= ( lo1585 );
end Cookbook__fec_check__part1516_behav;
