--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1951 is 
  Port (
    lo2020: in std_logic;
    n10399: inout std_logic
  );
end Cookbook__fec_check__part1951;

architecture Cookbook__fec_check__part1951_behav of Cookbook__fec_check__part1951 is
begin
    n10399 <= ( lo2020 );
end Cookbook__fec_check__part1951_behav;
