--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part394 is 
  Port (
    lo0463: in std_logic;
    n2614: inout std_logic
  );
end Cookbook__fec_check__part394;

architecture Cookbook__fec_check__part394_behav of Cookbook__fec_check__part394 is
begin
    n2614 <= ( lo0463 );
end Cookbook__fec_check__part394_behav;
