--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part727 is 
  Port (
    lo4412: in std_logic;
    n22070: inout std_logic
  );
end IWLS2005__des_perf__part727;

architecture IWLS2005__des_perf__part727_behav of IWLS2005__des_perf__part727 is
begin
    n22070 <= ( lo4412 );
end IWLS2005__des_perf__part727_behav;
