--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part789 is 
  Port (
    lo4158: in std_logic;
    n13999: inout std_logic
  );
end Other__sudoku_check__part789;

architecture Other__sudoku_check__part789_behav of Other__sudoku_check__part789 is
begin
    n13999 <= ( lo4158 );
end Other__sudoku_check__part789_behav;
