--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2699 is 
  Port (
    lo8012: in std_logic;
    n39790_1: inout std_logic
  );
end IWLS2005__des_perf__part2699;

architecture IWLS2005__des_perf__part2699_behav of IWLS2005__des_perf__part2699 is
begin
    n39790_1 <= ( lo8012 );
end IWLS2005__des_perf__part2699_behav;
