--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2282 is 
  Port (
    lo5033: in std_logic;
    n29746: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2282;

architecture Other__ucsb_152_tap_fir__part2282_behav of Other__ucsb_152_tap_fir__part2282 is
begin
    n29746 <= ( lo5033 );
end Other__ucsb_152_tap_fir__part2282_behav;
