--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1 is 
  Port (
    pi1157: in std_logic;
    n5511: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1;

architecture Other__ucsb_152_tap_fir__part1_behav of Other__ucsb_152_tap_fir__part1 is
begin
    n5511 <= ( pi1157 );
end Other__ucsb_152_tap_fir__part1_behav;
