--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2037 is 
  Port (
    lo2106: in std_logic;
    n10829: inout std_logic
  );
end Cookbook__fec_check__part2037;

architecture Cookbook__fec_check__part2037_behav of Cookbook__fec_check__part2037 is
begin
    n10829 <= ( lo2106 );
end Cookbook__fec_check__part2037_behav;
