--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part13 is 
  Port (
    lo0004: in std_logic;
    n1279: inout std_logic
  );
end Cookbook__ucrypt__part13;

architecture Cookbook__ucrypt__part13_behav of Cookbook__ucrypt__part13 is
begin
    n1279 <= ( lo0004 );
end Cookbook__ucrypt__part13_behav;
