--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part51 is 
  Port (
    pi051: in std_logic;
    n2482_1: inout std_logic
  );
end Other__fpu__part51;

architecture Other__fpu__part51_behav of Other__fpu__part51 is
begin
    n2482_1 <= ( pi051 );
end Other__fpu__part51_behav;
