--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part58 is 
  Port (
    lo0127: in std_logic;
    n934: inout std_logic
  );
end Cookbook__fec_check__part58;

architecture Cookbook__fec_check__part58_behav of Cookbook__fec_check__part58 is
begin
    n934 <= ( lo0127 );
end Cookbook__fec_check__part58_behav;
