--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1186 is 
  Port (
    lo1255: in std_logic;
    n6574: inout std_logic
  );
end Cookbook__fec_check__part1186;

architecture Cookbook__fec_check__part1186_behav of Cookbook__fec_check__part1186 is
begin
    n6574 <= ( lo1255 );
end Cookbook__fec_check__part1186_behav;
