--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part292 is 
  Port (
    lo03682: in std_logic;
    po6182,po6233,po6488,po6539: inout std_logic
  );
end Other__ray__part292;

architecture Other__ray__part292_behav of Other__ray__part292 is
begin
    po6182 <= ( lo03682 );
    po6233 <= ( lo03682 );
    po6488 <= ( lo03682 );
    po6539 <= ( lo03682 );
end Other__ray__part292_behav;
