--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part8 is 
  Port (
    lo0077: in std_logic;
    n684: inout std_logic
  );
end Cookbook__fec_check__part8;

architecture Cookbook__fec_check__part8_behav of Cookbook__fec_check__part8 is
begin
    n684 <= ( lo0077 );
end Cookbook__fec_check__part8_behav;
