--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1926 is 
  Port (
    lo4309: in std_logic;
    n26131: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1926;

architecture Other__ucsb_152_tap_fir__part1926_behav of Other__ucsb_152_tap_fir__part1926 is
begin
    n26131 <= ( lo4309 );
end Other__ucsb_152_tap_fir__part1926_behav;
