--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part33 is 
  Port (
    pi0361: in std_logic;
    n19569: inout std_logic
  );
end Other__carpat__part33;

architecture Other__carpat__part33_behav of Other__carpat__part33 is
begin
    n19569 <= ( pi0361 );
end Other__carpat__part33_behav;
