--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1572 is 
  Port (
    lo8285: in std_logic;
    n46314_1: inout std_logic
  );
end Other__carpat__part1572;

architecture Other__carpat__part1572_behav of Other__carpat__part1572 is
begin
    n46314_1 <= ( lo8285 );
end Other__carpat__part1572_behav;
