--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part41 is 
  Port (
    lo0445: in std_logic;
    po021: inout std_logic
  );
end IWLS2005__pci_bridge32__part41;

architecture IWLS2005__pci_bridge32__part41_behav of IWLS2005__pci_bridge32__part41 is
begin
    po021 <= ( lo0445 );
end IWLS2005__pci_bridge32__part41_behav;
