--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part141 is 
  Port (
    lo0935: in std_logic;
    n6354_1: inout std_logic
  );
end IWLS93__s38417__part141;

architecture IWLS93__s38417__part141_behav of IWLS93__s38417__part141 is
begin
    n6354_1 <= ( not lo0935 );
end IWLS93__s38417__part141_behav;
