--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part306 is 
  Port (
    lo2955: in std_logic;
    n7979: inout std_logic
  );
end Other__sudoku_check__part306;

architecture Other__sudoku_check__part306_behav of Other__sudoku_check__part306 is
begin
    n7979 <= ( lo2955 );
end Other__sudoku_check__part306_behav;
