--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1376 is 
  Port (
    lo1445: in std_logic;
    n7524: inout std_logic
  );
end Cookbook__fec_check__part1376;

architecture Cookbook__fec_check__part1376_behav of Cookbook__fec_check__part1376 is
begin
    n7524 <= ( lo1445 );
end Cookbook__fec_check__part1376_behav;
