--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3332 is 
  Port (
    lo8738: in std_logic;
    n43520_1: inout std_logic
  );
end IWLS2005__des_perf__part3332;

architecture IWLS2005__des_perf__part3332_behav of IWLS2005__des_perf__part3332 is
begin
    n43520_1 <= ( lo8738 );
end IWLS2005__des_perf__part3332_behav;
