--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part108 is 
  Port (
    lo0350: in std_logic;
    n4365: inout std_logic
  );
end Other__fp_operators__part108;

architecture Other__fp_operators__part108_behav of Other__fp_operators__part108 is
begin
    n4365 <= ( lo0350 );
end Other__fp_operators__part108_behav;
