--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part439 is 
  Port (
    lo3306: in std_logic;
    n16915: inout std_logic
  );
end IWLS2005__des_perf__part439;

architecture IWLS2005__des_perf__part439_behav of IWLS2005__des_perf__part439 is
begin
    n16915 <= ( lo3306 );
end IWLS2005__des_perf__part439_behav;
