--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part820 is 
  Port (
    lo0889: in std_logic;
    n4744: inout std_logic
  );
end Cookbook__fec_check__part820;

architecture Cookbook__fec_check__part820_behav of Cookbook__fec_check__part820 is
begin
    n4744 <= ( lo0889 );
end Cookbook__fec_check__part820_behav;
