--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2089 is 
  Port (
    lo2158: in std_logic;
    n11089: inout std_logic
  );
end Cookbook__fec_check__part2089;

architecture Cookbook__fec_check__part2089_behav of Cookbook__fec_check__part2089 is
begin
    n11089 <= ( lo2158 );
end Cookbook__fec_check__part2089_behav;
