--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1620 is 
  Port (
    lo8412: in std_logic;
    n46959_1: inout std_logic
  );
end Other__carpat__part1620;

architecture Other__carpat__part1620_behav of Other__carpat__part1620 is
begin
    n46959_1 <= ( lo8412 );
end Other__carpat__part1620_behav;
