--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part133 is 
  Port (
    lo2782: in std_logic;
    n6249: inout std_logic
  );
end Other__sudoku_check__part133;

architecture Other__sudoku_check__part133_behav of Other__sudoku_check__part133 is
begin
    n6249 <= ( lo2782 );
end Other__sudoku_check__part133_behav;
