--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part108 is 
  Port (
    lo094: in std_logic;
    po172: inout std_logic
  );
end Cookbook__lc_mult_signed__part108;

architecture Cookbook__lc_mult_signed__part108_behav of Cookbook__lc_mult_signed__part108 is
begin
    po172 <= ( lo094 );
end Cookbook__lc_mult_signed__part108_behav;
