--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1039 is 
  Port (
    lo1108: in std_logic;
    n5839: inout std_logic
  );
end Cookbook__fec_check__part1039;

architecture Cookbook__fec_check__part1039_behav of Cookbook__fec_check__part1039 is
begin
    n5839 <= ( lo1108 );
end Cookbook__fec_check__part1039_behav;
