--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1576 is 
  Port (
    lo1645: in std_logic;
    n8524: inout std_logic
  );
end Cookbook__fec_check__part1576;

architecture Cookbook__fec_check__part1576_behav of Cookbook__fec_check__part1576 is
begin
    n8524 <= ( lo1645 );
end Cookbook__fec_check__part1576_behav;
