--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part36 is 
  Port (
    lo167: in std_logic;
    n969_1: inout std_logic
  );
end ISCAS__s3384__part36;

architecture ISCAS__s3384__part36_behav of ISCAS__s3384__part36 is
begin
    n969_1 <= ( not lo167 );
end ISCAS__s3384__part36_behav;
