--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part66 is 
  Port (
    lo0165: in std_logic;
    n3415: inout std_logic
  );
end Other__fp_operators__part66;

architecture Other__fp_operators__part66_behav of Other__fp_operators__part66 is
begin
    n3415 <= ( lo0165 );
end Other__fp_operators__part66_behav;
