--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part424 is 
  Port (
    lo0493: in std_logic;
    n2764: inout std_logic
  );
end Cookbook__fec_check__part424;

architecture Cookbook__fec_check__part424_behav of Cookbook__fec_check__part424 is
begin
    n2764 <= ( lo0493 );
end Cookbook__fec_check__part424_behav;
