--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part271 is 
  Port (
    lo1357: in std_logic;
    n6239_1: inout std_logic
  );
end Other__desperf__part271;

architecture Other__desperf__part271_behav of Other__desperf__part271 is
begin
    n6239_1 <= ( lo1357 );
end Other__desperf__part271_behav;
