--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2238 is 
  Port (
    lo4959: in std_logic;
    n29381: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2238;

architecture Other__ucsb_152_tap_fir__part2238_behav of Other__ucsb_152_tap_fir__part2238 is
begin
    n29381 <= ( lo4959 );
end Other__ucsb_152_tap_fir__part2238_behav;
