--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part18 is 
  Port (
    pi098: in std_logic;
    n17294_1: inout std_logic
  );
end IWLS2005__pci_bridge32__part18;

architecture IWLS2005__pci_bridge32__part18_behav of IWLS2005__pci_bridge32__part18 is
begin
    n17294_1 <= ( pi098 );
end IWLS2005__pci_bridge32__part18_behav;
