--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part13 is 
  Port (
    lo112: in std_logic;
    n740: inout std_logic
  );
end ISCAS__s15850__part13;

architecture ISCAS__s15850__part13_behav of ISCAS__s15850__part13 is
begin
    n740 <= ( lo112 );
end ISCAS__s15850__part13_behav;
