--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part905 is 
  Port (
    lo0974: in std_logic;
    n5169: inout std_logic
  );
end Cookbook__fec_check__part905;

architecture Cookbook__fec_check__part905_behav of Cookbook__fec_check__part905 is
begin
    n5169 <= ( lo0974 );
end Cookbook__fec_check__part905_behav;
