--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part574 is 
  Port (
    lo4179: in std_logic;
    n21215: inout std_logic
  );
end IWLS2005__des_perf__part574;

architecture IWLS2005__des_perf__part574_behav of IWLS2005__des_perf__part574 is
begin
    n21215 <= ( lo4179 );
end IWLS2005__des_perf__part574_behav;
