--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part41 is 
  Port (
    lo106,lo105: in std_logic;
    n813: inout std_logic
  );
end ISCAS__s13207__part41;

architecture ISCAS__s13207__part41_behav of ISCAS__s13207__part41 is
begin
    n813 <= ( not lo106 and not lo105 );
end ISCAS__s13207__part41_behav;
