--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part32 is 
  Port (
    pi32: in std_logic;
    n544133: inout std_logic
  );
end IWLS2005__leon3mp__part32;

architecture IWLS2005__leon3mp__part32_behav of IWLS2005__leon3mp__part32 is
begin
    n544133 <= ( pi32 );
end IWLS2005__leon3mp__part32_behav;
