--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part73 is 
  Port (
    pi0802: in std_logic;
    n24829: inout std_logic
  );
end Other__carpat__part73;

architecture Other__carpat__part73_behav of Other__carpat__part73 is
begin
    n24829 <= ( pi0802 );
end Other__carpat__part73_behav;
