--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part762 is 
  Port (
    lo0831: in std_logic;
    n4454: inout std_logic
  );
end Cookbook__fec_check__part762;

architecture Cookbook__fec_check__part762_behav of Cookbook__fec_check__part762 is
begin
    n4454 <= ( lo0831 );
end Cookbook__fec_check__part762_behav;
