--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part540 is 
  Port (
    lo1987: in std_logic;
    n11194_1: inout std_logic
  );
end Cookbook__ucrypt__part540;

architecture Cookbook__ucrypt__part540_behav of Cookbook__ucrypt__part540 is
begin
    n11194_1 <= ( lo1987 );
end Cookbook__ucrypt__part540_behav;
