--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part185 is 
  Port (
    lo284: in std_logic;
    n932: inout std_logic
  );
end Other__fpu__part185;

architecture Other__fpu__part185_behav of Other__fpu__part185 is
begin
    n932 <= ( lo284 );
end Other__fpu__part185_behav;
