--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part369 is 
  Port (
    lo0438: in std_logic;
    n2489: inout std_logic
  );
end Cookbook__fec_check__part369;

architecture Cookbook__fec_check__part369_behav of Cookbook__fec_check__part369 is
begin
    n2489 <= ( lo0438 );
end Cookbook__fec_check__part369_behav;
