--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2192 is 
  Port (
    lo2261: in std_logic;
    n11604: inout std_logic
  );
end Cookbook__fec_check__part2192;

architecture Cookbook__fec_check__part2192_behav of Cookbook__fec_check__part2192 is
begin
    n11604 <= ( lo2261 );
end Cookbook__fec_check__part2192_behav;
