--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1202 is 
  Port (
    lo2786: in std_logic;
    n18496: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1202;

architecture Other__ucsb_152_tap_fir__part1202_behav of Other__ucsb_152_tap_fir__part1202 is
begin
    n18496 <= ( lo2786 );
end Other__ucsb_152_tap_fir__part1202_behav;
