--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part184 is 
  Port (
    lo2833: in std_logic;
    n6759: inout std_logic
  );
end Other__sudoku_check__part184;

architecture Other__sudoku_check__part184_behav of Other__sudoku_check__part184 is
begin
    n6759 <= ( lo2833 );
end Other__sudoku_check__part184_behav;
