--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part50 is 
  Port (
    lo48: in std_logic;
    n263: inout std_logic
  );
end Cookbook__pipeline_add_msb__part50;

architecture Cookbook__pipeline_add_msb__part50_behav of Cookbook__pipeline_add_msb__part50 is
begin
    n263 <= ( lo48 );
end Cookbook__pipeline_add_msb__part50_behav;
