--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1603 is 
  Port (
    lo3636: in std_logic;
    n22741: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1603;

architecture Other__ucsb_152_tap_fir__part1603_behav of Other__ucsb_152_tap_fir__part1603 is
begin
    n22741 <= ( lo3636 );
end Other__ucsb_152_tap_fir__part1603_behav;
