--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1452 is 
  Port (
    lo1521: in std_logic;
    n7904: inout std_logic
  );
end Cookbook__fec_check__part1452;

architecture Cookbook__fec_check__part1452_behav of Cookbook__fec_check__part1452 is
begin
    n7904 <= ( lo1521 );
end Cookbook__fec_check__part1452_behav;
