--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part6 is 
  Port (
    pi08: in std_logic;
    n925001: inout std_logic
  );
end IWLS2005__leon3__part6;

architecture IWLS2005__leon3__part6_behav of IWLS2005__leon3__part6 is
begin
    n925001 <= ( pi08 );
end IWLS2005__leon3__part6_behav;
