--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1175 is 
  Port (
    lo7422: in std_logic;
    n41189_1: inout std_logic
  );
end Other__carpat__part1175;

architecture Other__carpat__part1175_behav of Other__carpat__part1175 is
begin
    n41189_1 <= ( lo7422 );
end Other__carpat__part1175_behav;
