--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part494 is 
  Port (
    lo05966: in std_logic;
    po1481,po1546,po1838,po1907: inout std_logic
  );
end Other__ray__part494;

architecture Other__ray__part494_behav of Other__ray__part494 is
begin
    po1481 <= ( lo05966 );
    po1546 <= ( lo05966 );
    po1838 <= ( lo05966 );
    po1907 <= ( lo05966 );
end Other__ray__part494_behav;
