--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part99 is 
  Port (
    lo193: in std_logic;
    po42: inout std_logic
  );
end Cookbook__gearbox_40_67__part99;

architecture Cookbook__gearbox_40_67__part99_behav of Cookbook__gearbox_40_67__part99 is
begin
    po42 <= ( lo193 );
end Cookbook__gearbox_40_67__part99_behav;
