--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part572 is 
  Port (
    lo4177: in std_logic;
    n21260: inout std_logic
  );
end IWLS2005__des_perf__part572;

architecture IWLS2005__des_perf__part572_behav of IWLS2005__des_perf__part572 is
begin
    n21260 <= ( lo4177 );
end IWLS2005__des_perf__part572_behav;
