--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part270 is 
  Port (
    lo455: in std_logic;
    n1577: inout std_logic
  );
end Other__fpu__part270;

architecture Other__fpu__part270_behav of Other__fpu__part270 is
begin
    n1577 <= ( lo455 );
end Other__fpu__part270_behav;
