--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part561 is 
  Port (
    lo3401: in std_logic;
    n16174: inout std_logic
  );
end Other__carpat__part561;

architecture Other__carpat__part561_behav of Other__carpat__part561 is
begin
    n16174 <= ( lo3401 );
end Other__carpat__part561_behav;
