--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part867 is 
  Port (
    lo0936: in std_logic;
    n4979: inout std_logic
  );
end Cookbook__fec_check__part867;

architecture Cookbook__fec_check__part867_behav of Cookbook__fec_check__part867 is
begin
    n4979 <= ( lo0936 );
end Cookbook__fec_check__part867_behav;
