--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part925 is 
  Port (
    lo0994: in std_logic;
    n5269: inout std_logic
  );
end Cookbook__fec_check__part925;

architecture Cookbook__fec_check__part925_behav of Cookbook__fec_check__part925 is
begin
    n5269 <= ( lo0994 );
end Cookbook__fec_check__part925_behav;
