--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part915 is 
  Port (
    lo4284: in std_logic;
    n16909: inout std_logic
  );
end Other__sudoku_check__part915;

architecture Other__sudoku_check__part915_behav of Other__sudoku_check__part915 is
begin
    n16909 <= ( lo4284 );
end Other__sudoku_check__part915_behav;
