--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2542 is 
  Port (
    lo7799: in std_logic;
    n38795_1: inout std_logic
  );
end IWLS2005__des_perf__part2542;

architecture IWLS2005__des_perf__part2542_behav of IWLS2005__des_perf__part2542 is
begin
    n38795_1 <= ( lo7799 );
end IWLS2005__des_perf__part2542_behav;
