--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part157 is 
  Port (
    lo0352: in std_logic;
    n6226: inout std_logic
  );
end Other__ucsb_152_tap_fir__part157;

architecture Other__ucsb_152_tap_fir__part157_behav of Other__ucsb_152_tap_fir__part157 is
begin
    n6226 <= ( lo0352 );
end Other__ucsb_152_tap_fir__part157_behav;
