--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1338 is 
  Port (
    lo1407: in std_logic;
    n7334: inout std_logic
  );
end Cookbook__fec_check__part1338;

architecture Cookbook__fec_check__part1338_behav of Cookbook__fec_check__part1338 is
begin
    n7334 <= ( lo1407 );
end Cookbook__fec_check__part1338_behav;
