--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part10 is 
  Port (
    lo2119: in std_logic;
    n5367: inout std_logic
  );
end Other__top_rs_decode__part10;

architecture Other__top_rs_decode__part10_behav of Other__top_rs_decode__part10 is
begin
    n5367 <= ( lo2119 );
end Other__top_rs_decode__part10_behav;
