--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1275 is 
  Port (
    lo7714: in std_logic;
    n42559_1: inout std_logic
  );
end Other__carpat__part1275;

architecture Other__carpat__part1275_behav of Other__carpat__part1275 is
begin
    n42559_1 <= ( lo7714 );
end Other__carpat__part1275_behav;
