--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part151 is 
  Port (
    lo0031: in std_logic;
    po31: inout std_logic
  );
end Other__desperf__part151;

architecture Other__desperf__part151_behav of Other__desperf__part151 is
begin
    po31 <= ( lo0031 );
end Other__desperf__part151_behav;
