--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1747 is 
  Port (
    lo1816: in std_logic;
    n9379: inout std_logic
  );
end Cookbook__fec_check__part1747;

architecture Cookbook__fec_check__part1747_behav of Cookbook__fec_check__part1747 is
begin
    n9379 <= ( lo1816 );
end Cookbook__fec_check__part1747_behav;
