--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part208 is 
  Port (
    lo0749: in std_logic;
    n4854: inout std_logic
  );
end Cookbook__ucrypt__part208;

architecture Cookbook__ucrypt__part208_behav of Cookbook__ucrypt__part208 is
begin
    n4854 <= ( lo0749 );
end Cookbook__ucrypt__part208_behav;
