--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3014 is 
  Port (
    lo8327: in std_logic;
    n41930_1: inout std_logic
  );
end IWLS2005__des_perf__part3014;

architecture IWLS2005__des_perf__part3014_behav of IWLS2005__des_perf__part3014 is
begin
    n41930_1 <= ( lo8327 );
end IWLS2005__des_perf__part3014_behav;
