--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part364 is 
  Port (
    lo1331: in std_logic;
    n7764_1: inout std_logic
  );
end Cookbook__ucrypt__part364;

architecture Cookbook__ucrypt__part364_behav of Cookbook__ucrypt__part364 is
begin
    n7764_1 <= ( lo1331 );
end Cookbook__ucrypt__part364_behav;
