--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1415 is 
  Port (
    lo7865: in std_logic;
    n44204_1: inout std_logic
  );
end Other__carpat__part1415;

architecture Other__carpat__part1415_behav of Other__carpat__part1415 is
begin
    n44204_1 <= ( lo7865 );
end Other__carpat__part1415_behav;
