--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1169 is 
  Port (
    lo4538: in std_logic;
    n18179: inout std_logic
  );
end Other__sudoku_check__part1169;

architecture Other__sudoku_check__part1169_behav of Other__sudoku_check__part1169 is
begin
    n18179 <= ( lo4538 );
end Other__sudoku_check__part1169_behav;
