--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part567 is 
  Port (
    lo2108: in std_logic;
    n11614_1: inout std_logic
  );
end Cookbook__ucrypt__part567;

architecture Cookbook__ucrypt__part567_behav of Cookbook__ucrypt__part567 is
begin
    n11614_1 <= ( lo2108 );
end Cookbook__ucrypt__part567_behav;
