--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part435 is 
  Port (
    lo0543: in std_logic;
    n7194: inout std_logic
  );
end Other__carpat__part435;

architecture Other__carpat__part435_behav of Other__carpat__part435 is
begin
    n7194 <= ( lo0543 );
end Other__carpat__part435_behav;
