--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2526 is 
  Port (
    lo7782: in std_logic;
    n38675_1: inout std_logic
  );
end IWLS2005__des_perf__part2526;

architecture IWLS2005__des_perf__part2526_behav of IWLS2005__des_perf__part2526 is
begin
    n38675_1 <= ( lo7782 );
end IWLS2005__des_perf__part2526_behav;
