--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1006 is 
  Port (
    lo2365: in std_logic;
    n16351: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1006;

architecture Other__ucsb_152_tap_fir__part1006_behav of Other__ucsb_152_tap_fir__part1006 is
begin
    n16351 <= ( lo2365 );
end Other__ucsb_152_tap_fir__part1006_behav;
