--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part102 is 
  Port (
    pi0512: in std_logic;
    n43106_1: inout std_logic
  );
end Other__radar__part102;

architecture Other__radar__part102_behav of Other__radar__part102 is
begin
    n43106_1 <= ( pi0512 );
end Other__radar__part102_behav;
