--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part32 is 
  Port (
    lo0285: in std_logic;
    n2264: inout std_logic
  );
end LGSynth91__s38417__part32;

architecture LGSynth91__s38417__part32_behav of LGSynth91__s38417__part32 is
begin
    n2264 <= ( not lo0285 );
end LGSynth91__s38417__part32_behav;
