--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1857 is 
  Port (
    lo1926: in std_logic;
    n9929: inout std_logic
  );
end Cookbook__fec_check__part1857;

architecture Cookbook__fec_check__part1857_behav of Cookbook__fec_check__part1857 is
begin
    n9929 <= ( lo1926 );
end Cookbook__fec_check__part1857_behav;
