--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part422 is 
  Port (
    lo1533: in std_logic;
    n8924_1: inout std_logic
  );
end Cookbook__ucrypt__part422;

architecture Cookbook__ucrypt__part422_behav of Cookbook__ucrypt__part422 is
begin
    n8924_1 <= ( lo1533 );
end Cookbook__ucrypt__part422_behav;
