--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part622 is 
  Port (
    lo5010: in std_logic;
    n22194: inout std_logic
  );
end Other__carpat__part622;

architecture Other__carpat__part622_behav of Other__carpat__part622 is
begin
    n22194 <= ( lo5010 );
end Other__carpat__part622_behav;
