--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1024 is 
  Port (
    lo1093: in std_logic;
    n5764: inout std_logic
  );
end Cookbook__fec_check__part1024;

architecture Cookbook__fec_check__part1024_behav of Cookbook__fec_check__part1024 is
begin
    n5764 <= ( lo1093 );
end Cookbook__fec_check__part1024_behav;
