--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part81 is 
  Port (
    lo095: in std_logic;
    n120: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part81;

architecture Cookbook__approx_fp_invsqrt__part81_behav of Cookbook__approx_fp_invsqrt__part81 is
begin
    n120 <= ( lo095 );
end Cookbook__approx_fp_invsqrt__part81_behav;
