--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part172 is 
  Port (
    lo2821: in std_logic;
    n6639: inout std_logic
  );
end Other__sudoku_check__part172;

architecture Other__sudoku_check__part172_behav of Other__sudoku_check__part172 is
begin
    n6639 <= ( lo2821 );
end Other__sudoku_check__part172_behav;
