--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part10 is 
  Port (
    pi1166: in std_logic;
    n5811: inout std_logic
  );
end Other__ucsb_152_tap_fir__part10;

architecture Other__ucsb_152_tap_fir__part10_behav of Other__ucsb_152_tap_fir__part10 is
begin
    n5811 <= ( pi1166 );
end Other__ucsb_152_tap_fir__part10_behav;
