--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part182 is 
  Port (
    lo0062: in std_logic;
    po62: inout std_logic
  );
end Other__desperf__part182;

architecture Other__desperf__part182_behav of Other__desperf__part182 is
begin
    po62 <= ( lo0062 );
end Other__desperf__part182_behav;
