--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part4 is 
  Port (
    pi004: in std_logic;
    n9669_1: inout std_logic
  );
end Other__desperf__part4;

architecture Other__desperf__part4_behav of Other__desperf__part4 is
begin
    n9669_1 <= ( pi004 );
end Other__desperf__part4_behav;
