--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1766 is 
  Port (
    lo6578: in std_logic;
    n33240_1: inout std_logic
  );
end IWLS2005__des_perf__part1766;

architecture IWLS2005__des_perf__part1766_behav of IWLS2005__des_perf__part1766 is
begin
    n33240_1 <= ( lo6578 );
end IWLS2005__des_perf__part1766_behav;
