--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1794 is 
  Port (
    lo1863: in std_logic;
    n9614: inout std_logic
  );
end Cookbook__fec_check__part1794;

architecture Cookbook__fec_check__part1794_behav of Cookbook__fec_check__part1794 is
begin
    n9614 <= ( lo1863 );
end Cookbook__fec_check__part1794_behav;
