--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part890 is 
  Port (
    lo08196: in std_logic;
    n53716_1: inout std_logic
  );
end Other__ray__part890;

architecture Other__ray__part890_behav of Other__ray__part890 is
begin
    n53716_1 <= ( lo08196 );
end Other__ray__part890_behav;
