--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx__part4 is 
  Port (
    pi04: in std_logic;
    n265: inout std_logic
  );
end Cookbook__lane_rx__part4;

architecture Cookbook__lane_rx__part4_behav of Cookbook__lane_rx__part4 is
begin
    n265 <= ( pi04 );
end Cookbook__lane_rx__part4_behav;
