--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3312 is 
  Port (
    lo8694: in std_logic;
    n43480_1: inout std_logic
  );
end IWLS2005__des_perf__part3312;

architecture IWLS2005__des_perf__part3312_behav of IWLS2005__des_perf__part3312 is
begin
    n43480_1 <= ( lo8694 );
end IWLS2005__des_perf__part3312_behav;
