--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1220 is 
  Port (
    lo5430: in std_logic;
    n27330_1: inout std_logic
  );
end IWLS2005__des_perf__part1220;

architecture IWLS2005__des_perf__part1220_behav of IWLS2005__des_perf__part1220 is
begin
    n27330_1 <= ( lo5430 );
end IWLS2005__des_perf__part1220_behav;
