--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part223 is 
  Port (
    lo0116: in std_logic;
    n665: inout std_logic
  );
end IWLS2005__des_perf__part223;

architecture IWLS2005__des_perf__part223_behav of IWLS2005__des_perf__part223 is
begin
    n665 <= ( lo0116 );
end IWLS2005__des_perf__part223_behav;
