--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part3 is 
  Port (
    lo177: in std_logic;
    po045: inout std_logic
  );
end IWLS2005__aes_core__part3;

architecture IWLS2005__aes_core__part3_behav of IWLS2005__aes_core__part3 is
begin
    po045 <= ( lo177 );
end IWLS2005__aes_core__part3_behav;
