--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1585 is 
  Port (
    lo8298: in std_logic;
    n46379_1: inout std_logic
  );
end Other__carpat__part1585;

architecture Other__carpat__part1585_behav of Other__carpat__part1585 is
begin
    n46379_1 <= ( lo8298 );
end Other__carpat__part1585_behav;
