--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part413 is 
  Port (
    lo05885: in std_logic;
    po1302,po1336: inout std_logic
  );
end Other__ray__part413;

architecture Other__ray__part413_behav of Other__ray__part413 is
begin
    po1302 <= ( lo05885 );
    po1336 <= ( lo05885 );
end Other__ray__part413_behav;
