--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1467 is 
  Port (
    lo3381: in std_logic;
    n21411: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1467;

architecture Other__ucsb_152_tap_fir__part1467_behav of Other__ucsb_152_tap_fir__part1467 is
begin
    n21411 <= ( lo3381 );
end Other__ucsb_152_tap_fir__part1467_behav;
