--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1604 is 
  Port (
    lo3638: in std_logic;
    n22746: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1604;

architecture Other__ucsb_152_tap_fir__part1604_behav of Other__ucsb_152_tap_fir__part1604 is
begin
    n22746 <= ( lo3638 );
end Other__ucsb_152_tap_fir__part1604_behav;
