--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part20 is 
  Port (
    pi26: in std_logic;
    n924171: inout std_logic
  );
end IWLS2005__leon3__part20;

architecture IWLS2005__leon3__part20_behav of IWLS2005__leon3__part20 is
begin
    n924171 <= ( pi26 );
end IWLS2005__leon3__part20_behav;
