--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part362 is 
  Port (
    lo3011: in std_logic;
    n8539: inout std_logic
  );
end Other__sudoku_check__part362;

architecture Other__sudoku_check__part362_behav of Other__sudoku_check__part362 is
begin
    n8539 <= ( lo3011 );
end Other__sudoku_check__part362_behav;
