--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part16 is 
  Port (
    lo37: in std_logic;
    po02: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part16;

architecture Cookbook__soft_ecc_ram_16bit__part16_behav of Cookbook__soft_ecc_ram_16bit__part16 is
begin
    po02 <= ( lo37 );
end Cookbook__soft_ecc_ram_16bit__part16_behav;
