--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part946 is 
  Port (
    lo4315: in std_logic;
    n17064: inout std_logic
  );
end Other__sudoku_check__part946;

architecture Other__sudoku_check__part946_behav of Other__sudoku_check__part946 is
begin
    n17064 <= ( lo4315 );
end Other__sudoku_check__part946_behav;
