--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part33 is 
  Port (
    lo45: in std_logic;
    n288: inout std_logic
  );
end Cookbook__mlab_dcfifo__part33;

architecture Cookbook__mlab_dcfifo__part33_behav of Cookbook__mlab_dcfifo__part33 is
begin
    n288 <= ( lo45 );
end Cookbook__mlab_dcfifo__part33_behav;
