--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part60 is 
  Port (
    lo149308: in std_logic;
    n746617: inout std_logic
  );
end IWLS2005__leon2__part60;

architecture IWLS2005__leon2__part60_behav of IWLS2005__leon2__part60 is
begin
    n746617 <= ( lo149308 );
end IWLS2005__leon2__part60_behav;
