--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part120 is 
  Port (
    lo369: in std_logic;
    po096: inout std_logic
  );
end IWLS2005__aes_core__part120;

architecture IWLS2005__aes_core__part120_behav of IWLS2005__aes_core__part120 is
begin
    po096 <= ( lo369 );
end IWLS2005__aes_core__part120_behav;
