--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1790 is 
  Port (
    lo4028: in std_logic;
    n24651: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1790;

architecture Other__ucsb_152_tap_fir__part1790_behav of Other__ucsb_152_tap_fir__part1790 is
begin
    n24651 <= ( lo4028 );
end Other__ucsb_152_tap_fir__part1790_behav;
