--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part169 is 
  Port (
    lo1147: in std_logic;
    n6464: inout std_logic
  );
end IWLS93__s38417__part169;

architecture IWLS93__s38417__part169_behav of IWLS93__s38417__part169 is
begin
    n6464 <= ( lo1147 );
end IWLS93__s38417__part169_behav;
