--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part96 is 
  Port (
    lo2667: in std_logic;
    n5879: inout std_logic
  );
end Other__sudoku_check__part96;

architecture Other__sudoku_check__part96_behav of Other__sudoku_check__part96 is
begin
    n5879 <= ( lo2667 );
end Other__sudoku_check__part96_behav;
