--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1464 is 
  Port (
    lo1533: in std_logic;
    n7964: inout std_logic
  );
end Cookbook__fec_check__part1464;

architecture Cookbook__fec_check__part1464_behav of Cookbook__fec_check__part1464 is
begin
    n7964 <= ( lo1533 );
end Cookbook__fec_check__part1464_behav;
