--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1589 is 
  Port (
    lo3588: in std_logic;
    n22526: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1589;

architecture Other__ucsb_152_tap_fir__part1589_behav of Other__ucsb_152_tap_fir__part1589 is
begin
    n22526 <= ( lo3588 );
end Other__ucsb_152_tap_fir__part1589_behav;
