--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1349 is 
  Port (
    lo4718: in std_logic;
    n19079: inout std_logic
  );
end Other__sudoku_check__part1349;

architecture Other__sudoku_check__part1349_behav of Other__sudoku_check__part1349 is
begin
    n19079 <= ( lo4718 );
end Other__sudoku_check__part1349_behav;
