--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part71 is 
  Port (
    lo0444: in std_logic;
    n3519: inout std_logic
  );
end IWLS93__s38417__part71;

architecture IWLS93__s38417__part71_behav of IWLS93__s38417__part71 is
begin
    n3519 <= ( lo0444 );
end IWLS93__s38417__part71_behav;
