--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__insert_parity__part0 is 
  Port (
    pi08,pi07,pi06,pi05,pi04,pi03,pi01,pi00,pi02: in std_logic;
    po0: inout std_logic
  );
end Cookbook__insert_parity__part0;

architecture Cookbook__insert_parity__part0_behav of Cookbook__insert_parity__part0 is
signal n82,n83,n84,n85,n86,n87,n88: std_logic;
begin
    n82 <= ( not pi08 and pi07 )
      or ( pi08 and not pi07 );
    n83 <= ( not pi06 and pi05 )
      or ( pi06 and not pi05 );
    n84 <= ( not n82 and n83 )
      or ( n82 and not n83 );
    n85 <= ( not pi04 and pi03 )
      or ( pi04 and not pi03 );
    n86 <= ( not pi01 and pi00 )
      or ( pi01 and not pi00 );
    n87 <= ( not pi02 and n86 )
      or ( pi02 and not n86 );
    n88 <= ( not n85 and n87 )
      or ( n85 and not n87 );
    po0 <= ( not n84 and not n88 )
      or ( n84 and n88 );
end Cookbook__insert_parity__part0_behav;
