--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part481 is 
  Port (
    lo3130: in std_logic;
    n9729: inout std_logic
  );
end Other__sudoku_check__part481;

architecture Other__sudoku_check__part481_behav of Other__sudoku_check__part481 is
begin
    n9729 <= ( lo3130 );
end Other__sudoku_check__part481_behav;
