--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s953__part22 is 
  Port (
    lo27: in std_logic;
    po13: inout std_logic
  );
end IWLS93__s953__part22;

architecture IWLS93__s953__part22_behav of IWLS93__s953__part22 is
begin
    po13 <= ( lo27 );
end IWLS93__s953__part22_behav;
