--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1221 is 
  Port (
    lo1290: in std_logic;
    n6749: inout std_logic
  );
end Cookbook__fec_check__part1221;

architecture Cookbook__fec_check__part1221_behav of Cookbook__fec_check__part1221 is
begin
    n6749 <= ( lo1290 );
end Cookbook__fec_check__part1221_behav;
