--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part319 is 
  Port (
    lo2968: in std_logic;
    n8109: inout std_logic
  );
end Other__sudoku_check__part319;

architecture Other__sudoku_check__part319_behav of Other__sudoku_check__part319 is
begin
    n8109 <= ( lo2968 );
end Other__sudoku_check__part319_behav;
