--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part220 is 
  Port (
    lo206: in std_logic;
    po060: inout std_logic
  );
end Cookbook__lc_mult_signed__part220;

architecture Cookbook__lc_mult_signed__part220_behav of Cookbook__lc_mult_signed__part220 is
begin
    po060 <= ( lo206 );
end Cookbook__lc_mult_signed__part220_behav;
