--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part130 is 
  Port (
    lo0253: in std_logic;
    n5711: inout std_logic
  );
end Other__ucsb_152_tap_fir__part130;

architecture Other__ucsb_152_tap_fir__part130_behav of Other__ucsb_152_tap_fir__part130 is
begin
    n5711 <= ( lo0253 );
end Other__ucsb_152_tap_fir__part130_behav;
