--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1936 is 
  Port (
    lo4360: in std_logic;
    n26301: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1936;

architecture Other__ucsb_152_tap_fir__part1936_behav of Other__ucsb_152_tap_fir__part1936 is
begin
    n26301 <= ( lo4360 );
end Other__ucsb_152_tap_fir__part1936_behav;
