--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1284 is 
  Port (
    lo7723: in std_logic;
    n42604_1: inout std_logic
  );
end Other__carpat__part1284;

architecture Other__carpat__part1284_behav of Other__carpat__part1284 is
begin
    n42604_1 <= ( lo7723 );
end Other__carpat__part1284_behav;
