--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part632 is 
  Port (
    lo5020: in std_logic;
    n22244: inout std_logic
  );
end Other__carpat__part632;

architecture Other__carpat__part632_behav of Other__carpat__part632 is
begin
    n22244 <= ( lo5020 );
end Other__carpat__part632_behav;
