--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part8 is 
  Port (
    lo046: in std_logic;
    po26: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part8;

architecture Cookbook__soft_ecc_ram_32bit__part8_behav of Cookbook__soft_ecc_ram_32bit__part8 is
begin
    po26 <= ( lo046 );
end Cookbook__soft_ecc_ram_32bit__part8_behav;
