--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part157 is 
  Port (
    lo254: in std_logic;
    n787: inout std_logic
  );
end Other__fpu__part157;

architecture Other__fpu__part157_behav of Other__fpu__part157 is
begin
    n787 <= ( lo254 );
end Other__fpu__part157_behav;
