--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part11 is 
  Port (
    lo049: in std_logic;
    po21: inout std_logic
  );
end Cookbook__fec_gen__part11;

architecture Cookbook__fec_gen__part11_behav of Cookbook__fec_gen__part11 is
begin
    po21 <= ( lo049 );
end Cookbook__fec_gen__part11_behav;
