--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part58 is 
  Port (
    pi0468: in std_logic;
    n42716_1: inout std_logic
  );
end Other__radar__part58;

architecture Other__radar__part58_behav of Other__radar__part58 is
begin
    n42716_1 <= ( pi0468 );
end Other__radar__part58_behav;
