--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part524 is 
  Port (
    lo3263: in std_logic;
    n15434: inout std_logic
  );
end Other__carpat__part524;

architecture Other__carpat__part524_behav of Other__carpat__part524 is
begin
    n15434 <= ( lo3263 );
end Other__carpat__part524_behav;
