--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part39 is 
  Port (
    pi1131: in std_logic;
    n56171_1: inout std_logic
  );
end Other__ray__part39;

architecture Other__ray__part39_behav of Other__ray__part39 is
begin
    n56171_1 <= ( pi1131 );
end Other__ray__part39_behav;
