--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1144 is 
  Port (
    lo7391: in std_logic;
    n41034_1: inout std_logic
  );
end Other__carpat__part1144;

architecture Other__carpat__part1144_behav of Other__carpat__part1144 is
begin
    n41034_1 <= ( lo7391 );
end Other__carpat__part1144_behav;
