--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part46 is 
  Port (
    pi046: in std_logic;
    n2457_1: inout std_logic
  );
end Other__fpu__part46;

architecture Other__fpu__part46_behav of Other__fpu__part46 is
begin
    n2457_1 <= ( pi046 );
end Other__fpu__part46_behav;
