--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part52 is 
  Port (
    lo2251: in std_logic;
    n5439: inout std_logic
  );
end Other__sudoku_check__part52;

architecture Other__sudoku_check__part52_behav of Other__sudoku_check__part52 is
begin
    n5439 <= ( lo2251 );
end Other__sudoku_check__part52_behav;
