--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part23 is 
  Port (
    lo97556,lo97595: in std_logic;
    n486550,n487915_1: inout std_logic
  );
end IWLS2005__netcard__part23;

architecture IWLS2005__netcard__part23_behav of IWLS2005__netcard__part23 is
begin
    n486550 <= ( not lo97556 and lo97595 );
    n487915_1 <= ( lo97595 );
end IWLS2005__netcard__part23_behav;
