--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1205 is 
  Port (
    lo2789: in std_logic;
    n18511: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1205;

architecture Other__ucsb_152_tap_fir__part1205_behav of Other__ucsb_152_tap_fir__part1205 is
begin
    n18511 <= ( lo2789 );
end Other__ucsb_152_tap_fir__part1205_behav;
