--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part26 is 
  Port (
    lo0017: in std_logic;
    n1344: inout std_logic
  );
end Cookbook__ucrypt__part26;

architecture Cookbook__ucrypt__part26_behav of Cookbook__ucrypt__part26 is
begin
    n1344 <= ( lo0017 );
end Cookbook__ucrypt__part26_behav;
