--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1712 is 
  Port (
    lo6495: in std_logic;
    n32555_1: inout std_logic
  );
end IWLS2005__des_perf__part1712;

architecture IWLS2005__des_perf__part1712_behav of IWLS2005__des_perf__part1712 is
begin
    n32555_1 <= ( lo6495 );
end IWLS2005__des_perf__part1712_behav;
