--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part912 is 
  Port (
    lo4824: in std_logic;
    n24050: inout std_logic
  );
end IWLS2005__des_perf__part912;

architecture IWLS2005__des_perf__part912_behav of IWLS2005__des_perf__part912 is
begin
    n24050 <= ( lo4824 );
end IWLS2005__des_perf__part912_behav;
