--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part40 is 
  Port (
    lo39: in std_logic;
    po39: inout std_logic
  );
end Other__idxlat02n_m12__part40;

architecture Other__idxlat02n_m12__part40_behav of Other__idxlat02n_m12__part40 is
begin
    po39 <= ( lo39 );
end Other__idxlat02n_m12__part40_behav;
