--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part751 is 
  Port (
    lo3400: in std_logic;
    n12429: inout std_logic
  );
end Other__sudoku_check__part751;

architecture Other__sudoku_check__part751_behav of Other__sudoku_check__part751 is
begin
    n12429 <= ( lo3400 );
end Other__sudoku_check__part751_behav;
