--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__spi__part14 is 
  Port (
    lo209: in std_logic;
    po12: inout std_logic
  );
end IWLS2005__spi__part14;

architecture IWLS2005__spi__part14_behav of IWLS2005__spi__part14 is
begin
    po12 <= ( lo209 );
end IWLS2005__spi__part14_behav;
