--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part51 is 
  Port (
    pi051: in std_logic;
    n43975_1: inout std_logic
  );
end IWLS2005__des_perf__part51;

architecture IWLS2005__des_perf__part51_behav of IWLS2005__des_perf__part51 is
begin
    n43975_1 <= ( pi051 );
end IWLS2005__des_perf__part51_behav;
