--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1194 is 
  Port (
    lo5400: in std_logic;
    n27130_1: inout std_logic
  );
end IWLS2005__des_perf__part1194;

architecture IWLS2005__des_perf__part1194_behav of IWLS2005__des_perf__part1194 is
begin
    n27130_1 <= ( lo5400 );
end IWLS2005__des_perf__part1194_behav;
