--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1171 is 
  Port (
    lo5331: in std_logic;
    n26420: inout std_logic
  );
end IWLS2005__des_perf__part1171;

architecture IWLS2005__des_perf__part1171_behav of IWLS2005__des_perf__part1171 is
begin
    n26420 <= ( lo5331 );
end IWLS2005__des_perf__part1171_behav;
