--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_phy__part12 is 
  Port (
    lo51: in std_logic;
    n295,po13: inout std_logic
  );
end IWLS2005__usb_phy__part12;

architecture IWLS2005__usb_phy__part12_behav of IWLS2005__usb_phy__part12 is
begin
    n295 <= ( lo51 );
    po13 <= ( lo51 );
end IWLS2005__usb_phy__part12_behav;
