--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2048 is 
  Port (
    lo4579: in std_logic;
    n27476: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2048;

architecture Other__ucsb_152_tap_fir__part2048_behav of Other__ucsb_152_tap_fir__part2048 is
begin
    n27476 <= ( lo4579 );
end Other__ucsb_152_tap_fir__part2048_behav;
