--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part33 is 
  Port (
    lo0101: in std_logic;
    po109: inout std_logic
  );
end Other__mem__part33;

architecture Other__mem__part33_behav of Other__mem__part33 is
begin
    po109 <= ( lo0101 );
end Other__mem__part33_behav;
