--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part93 is 
  Port (
    lo0651: in std_logic;
    n2494: inout std_logic
  );
end IWLS93__s38417__part93;

architecture IWLS93__s38417__part93_behav of IWLS93__s38417__part93 is
begin
    n2494 <= ( lo0651 );
end IWLS93__s38417__part93_behav;
