--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part655 is 
  Port (
    lo06152: in std_logic;
    po1733,po1769: inout std_logic
  );
end Other__ray__part655;

architecture Other__ray__part655_behav of Other__ray__part655 is
begin
    po1733 <= ( lo06152 );
    po1769 <= ( lo06152 );
end Other__ray__part655_behav;
