--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part287 is 
  Port (
    pi1568: in std_logic;
    n46714_1: inout std_logic
  );
end Other__carpat__part287;

architecture Other__carpat__part287_behav of Other__carpat__part287 is
begin
    n46714_1 <= ( pi1568 );
end Other__carpat__part287_behav;
