--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_22__part24 is 
  Port (
    lo65: in std_logic;
    po03: inout std_logic
  );
end Cookbook__gearbox_20_22__part24;

architecture Cookbook__gearbox_20_22__part24_behav of Cookbook__gearbox_20_22__part24 is
begin
    po03 <= ( lo65 );
end Cookbook__gearbox_20_22__part24_behav;
