--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part232 is 
  Port (
    lo0581: in std_logic;
    n7386: inout std_logic
  );
end Other__ucsb_152_tap_fir__part232;

architecture Other__ucsb_152_tap_fir__part232_behav of Other__ucsb_152_tap_fir__part232 is
begin
    n7386 <= ( lo0581 );
end Other__ucsb_152_tap_fir__part232_behav;
