--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part583 is 
  Port (
    lo06064: in std_logic;
    po1600,po1636: inout std_logic
  );
end Other__ray__part583;

architecture Other__ray__part583_behav of Other__ray__part583 is
begin
    po1600 <= ( lo06064 );
    po1636 <= ( lo06064 );
end Other__ray__part583_behav;
