--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part182 is 
  Port (
    lo281: in std_logic;
    n917: inout std_logic
  );
end Other__fpu__part182;

architecture Other__fpu__part182_behav of Other__fpu__part182 is
begin
    n917 <= ( lo281 );
end Other__fpu__part182_behav;
