--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part5 is 
  Port (
    lo0109: in std_logic;
    n3164: inout std_logic
  );
end Other__sudoku_check__part5;

architecture Other__sudoku_check__part5_behav of Other__sudoku_check__part5 is
begin
    n3164 <= ( lo0109 );
end Other__sudoku_check__part5_behav;
