--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2132 is 
  Port (
    lo7278: in std_logic;
    n36415_1: inout std_logic
  );
end IWLS2005__des_perf__part2132;

architecture IWLS2005__des_perf__part2132_behav of IWLS2005__des_perf__part2132 is
begin
    n36415_1 <= ( lo7278 );
end IWLS2005__des_perf__part2132_behav;
