--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part896 is 
  Port (
    lo6738: in std_logic;
    n33554_1: inout std_logic
  );
end Other__carpat__part896;

architecture Other__carpat__part896_behav of Other__carpat__part896 is
begin
    n33554_1 <= ( lo6738 );
end Other__carpat__part896_behav;
