--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2111 is 
  Port (
    lo4717: in std_logic;
    n28086: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2111;

architecture Other__ucsb_152_tap_fir__part2111_behav of Other__ucsb_152_tap_fir__part2111 is
begin
    n28086 <= ( lo4717 );
end Other__ucsb_152_tap_fir__part2111_behav;
