--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part555 is 
  Port (
    lo0624: in std_logic;
    n3419: inout std_logic
  );
end Cookbook__fec_check__part555;

architecture Cookbook__fec_check__part555_behav of Cookbook__fec_check__part555 is
begin
    n3419 <= ( lo0624 );
end Cookbook__fec_check__part555_behav;
