--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part5 is 
  Port (
    lo70: in std_logic;
    po15: inout std_logic
  );
end Cookbook__gearbox_67_20__part5;

architecture Cookbook__gearbox_67_20__part5_behav of Cookbook__gearbox_67_20__part5 is
begin
    po15 <= ( lo70 );
end Cookbook__gearbox_67_20__part5_behav;
