--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1705 is 
  Port (
    lo8709: in std_logic;
    n49049_1: inout std_logic
  );
end Other__carpat__part1705;

architecture Other__carpat__part1705_behav of Other__carpat__part1705 is
begin
    n49049_1 <= ( lo8709 );
end Other__carpat__part1705_behav;
