--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part69 is 
  Port (
    lo68: in std_logic;
    po68: inout std_logic
  );
end Other__idxlat00n_m12__part69;

architecture Other__idxlat00n_m12__part69_behav of Other__idxlat00n_m12__part69 is
begin
    po68 <= ( lo68 );
end Other__idxlat00n_m12__part69_behav;
