--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1904 is 
  Port (
    lo4284: in std_logic;
    n26001: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1904;

architecture Other__ucsb_152_tap_fir__part1904_behav of Other__ucsb_152_tap_fir__part1904 is
begin
    n26001 <= ( lo4284 );
end Other__ucsb_152_tap_fir__part1904_behav;
