--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1194 is 
  Port (
    lo4563: in std_logic;
    n18304: inout std_logic
  );
end Other__sudoku_check__part1194;

architecture Other__sudoku_check__part1194_behav of Other__sudoku_check__part1194 is
begin
    n18304 <= ( lo4563 );
end Other__sudoku_check__part1194_behav;
