--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part320 is 
  Port (
    lo1095: in std_logic;
    n6734: inout std_logic
  );
end Cookbook__ucrypt__part320;

architecture Cookbook__ucrypt__part320_behav of Cookbook__ucrypt__part320 is
begin
    n6734 <= ( lo1095 );
end Cookbook__ucrypt__part320_behav;
