--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part774 is 
  Port (
    lo5514: in std_logic;
    n25989: inout std_logic
  );
end Other__carpat__part774;

architecture Other__carpat__part774_behav of Other__carpat__part774 is
begin
    n25989 <= ( lo5514 );
end Other__carpat__part774_behav;
