--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3212 is 
  Port (
    lo8550: in std_logic;
    n42825_1: inout std_logic
  );
end IWLS2005__des_perf__part3212;

architecture IWLS2005__des_perf__part3212_behav of IWLS2005__des_perf__part3212 is
begin
    n42825_1 <= ( lo8550 );
end IWLS2005__des_perf__part3212_behav;
