--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part37 is 
  Port (
    pi037: in std_logic;
    n2412_1: inout std_logic
  );
end Other__fpu__part37;

architecture Other__fpu__part37_behav of Other__fpu__part37 is
begin
    n2412_1 <= ( pi037 );
end Other__fpu__part37_behav;
