--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part240 is 
  Port (
    lo0589: in std_logic;
    n7426: inout std_logic
  );
end Other__ucsb_152_tap_fir__part240;

architecture Other__ucsb_152_tap_fir__part240_behav of Other__ucsb_152_tap_fir__part240 is
begin
    n7426 <= ( lo0589 );
end Other__ucsb_152_tap_fir__part240_behav;
