--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part52 is 
  Port (
    lo115: in std_logic;
    po021: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part52;

architecture Cookbook__soft_ecc_ram_64bit__part52_behav of Cookbook__soft_ecc_ram_64bit__part52 is
begin
    po021 <= ( lo115 );
end Cookbook__soft_ecc_ram_64bit__part52_behav;
