--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part387 is 
  Port (
    lo3036: in std_logic;
    n8789: inout std_logic
  );
end Other__sudoku_check__part387;

architecture Other__sudoku_check__part387_behav of Other__sudoku_check__part387 is
begin
    n8789 <= ( lo3036 );
end Other__sudoku_check__part387_behav;
