--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part383 is 
  Port (
    lo2199: in std_logic;
    n11495: inout std_logic
  );
end IWLS2005__des_perf__part383;

architecture IWLS2005__des_perf__part383_behav of IWLS2005__des_perf__part383 is
begin
    n11495 <= ( lo2199 );
end IWLS2005__des_perf__part383_behav;
