--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part374 is 
  Port (
    lo1373: in std_logic;
    n8124_1: inout std_logic
  );
end Cookbook__ucrypt__part374;

architecture Cookbook__ucrypt__part374_behav of Cookbook__ucrypt__part374 is
begin
    n8124_1 <= ( lo1373 );
end Cookbook__ucrypt__part374_behav;
