--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1691 is 
  Port (
    lo1760: in std_logic;
    n9099: inout std_logic
  );
end Cookbook__fec_check__part1691;

architecture Cookbook__fec_check__part1691_behav of Cookbook__fec_check__part1691 is
begin
    n9099 <= ( lo1760 );
end Cookbook__fec_check__part1691_behav;
