--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part598 is 
  Port (
    lo3247: in std_logic;
    n10899: inout std_logic
  );
end Other__sudoku_check__part598;

architecture Other__sudoku_check__part598_behav of Other__sudoku_check__part598 is
begin
    n10899 <= ( lo3247 );
end Other__sudoku_check__part598_behav;
