--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1219 is 
  Port (
    lo2813: in std_logic;
    n18581: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1219;

architecture Other__ucsb_152_tap_fir__part1219_behav of Other__ucsb_152_tap_fir__part1219 is
begin
    n18581 <= ( lo2813 );
end Other__ucsb_152_tap_fir__part1219_behav;
