--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part911 is 
  Port (
    lo4823: in std_logic;
    n24330: inout std_logic
  );
end IWLS2005__des_perf__part911;

architecture IWLS2005__des_perf__part911_behav of IWLS2005__des_perf__part911 is
begin
    n24330 <= ( lo4823 );
end IWLS2005__des_perf__part911_behav;
