--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part131 is 
  Port (
    lo117: in std_logic;
    po149: inout std_logic
  );
end Cookbook__lc_mult_signed__part131;

architecture Cookbook__lc_mult_signed__part131_behav of Cookbook__lc_mult_signed__part131 is
begin
    po149 <= ( lo117 );
end Cookbook__lc_mult_signed__part131_behav;
