--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1852 is 
  Port (
    lo1921: in std_logic;
    n9904: inout std_logic
  );
end Cookbook__fec_check__part1852;

architecture Cookbook__fec_check__part1852_behav of Cookbook__fec_check__part1852 is
begin
    n9904 <= ( lo1921 );
end Cookbook__fec_check__part1852_behav;
