--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part683 is 
  Port (
    lo3332: in std_logic;
    n11749: inout std_logic
  );
end Other__sudoku_check__part683;

architecture Other__sudoku_check__part683_behav of Other__sudoku_check__part683 is
begin
    n11749 <= ( lo3332 );
end Other__sudoku_check__part683_behav;
