--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s5378__part8 is 
  Port (
    lo043: in std_logic;
    n364: inout std_logic
  );
end IWLS93__s5378__part8;

architecture IWLS93__s5378__part8_behav of IWLS93__s5378__part8 is
begin
    n364 <= ( not lo043 );
end IWLS93__s5378__part8_behav;
