--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part135 is 
  Port (
    lo229: in std_logic;
    po06: inout std_logic
  );
end Cookbook__gearbox_40_67__part135;

architecture Cookbook__gearbox_40_67__part135_behav of Cookbook__gearbox_40_67__part135 is
begin
    po06 <= ( lo229 );
end Cookbook__gearbox_40_67__part135_behav;
