--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part199 is 
  Port (
    lo2848: in std_logic;
    n6909: inout std_logic
  );
end Other__sudoku_check__part199;

architecture Other__sudoku_check__part199_behav of Other__sudoku_check__part199 is
begin
    n6909 <= ( lo2848 );
end Other__sudoku_check__part199_behav;
