--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part778 is 
  Port (
    lo4147: in std_logic;
    n13614: inout std_logic
  );
end Other__sudoku_check__part778;

architecture Other__sudoku_check__part778_behav of Other__sudoku_check__part778 is
begin
    n13614 <= ( lo4147 );
end Other__sudoku_check__part778_behav;
