--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part426 is 
  Port (
    lo0524: in std_logic;
    n7059: inout std_logic
  );
end Other__carpat__part426;

architecture Other__carpat__part426_behav of Other__carpat__part426 is
begin
    n7059 <= ( lo0524 );
end Other__carpat__part426_behav;
