--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part229 is 
  Port (
    lo0773: in std_logic;
    n3519: inout std_logic
  );
end Other__desperf__part229;

architecture Other__desperf__part229_behav of Other__desperf__part229 is
begin
    n3519 <= ( lo0773 );
end Other__desperf__part229_behav;
