--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part21 is 
  Port (
    pi0332: in std_logic;
    n19549: inout std_logic
  );
end Other__carpat__part21;

architecture Other__carpat__part21_behav of Other__carpat__part21 is
begin
    n19549 <= ( pi0332 );
end Other__carpat__part21_behav;
