--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part251 is 
  Port (
    lo0320: in std_logic;
    n1899: inout std_logic
  );
end Cookbook__fec_check__part251;

architecture Cookbook__fec_check__part251_behav of Cookbook__fec_check__part251 is
begin
    n1899 <= ( lo0320 );
end Cookbook__fec_check__part251_behav;
