--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part29 is 
  Port (
    lo034: in std_logic;
    n872: inout std_logic
  );
end Cookbook__gearbox_67_40__part29;

architecture Cookbook__gearbox_67_40__part29_behav of Cookbook__gearbox_67_40__part29 is
begin
    n872 <= ( lo034 );
end Cookbook__gearbox_67_40__part29_behav;
