--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2716 is 
  Port (
    lo8029: in std_logic;
    n39650_1: inout std_logic
  );
end IWLS2005__des_perf__part2716;

architecture IWLS2005__des_perf__part2716_behav of IWLS2005__des_perf__part2716 is
begin
    n39650_1 <= ( lo8029 );
end IWLS2005__des_perf__part2716_behav;
