--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part42 is 
  Port (
    lo0075: in std_logic;
    po055: inout std_logic
  );
end Other__fp_operators__part42;

architecture Other__fp_operators__part42_behav of Other__fp_operators__part42 is
begin
    po055 <= ( lo0075 );
end Other__fp_operators__part42_behav;
