--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1165 is 
  Port (
    lo4534: in std_logic;
    n18159: inout std_logic
  );
end Other__sudoku_check__part1165;

architecture Other__sudoku_check__part1165_behav of Other__sudoku_check__part1165 is
begin
    n18159 <= ( lo4534 );
end Other__sudoku_check__part1165_behav;
