--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1199 is 
  Port (
    lo5408: in std_logic;
    n27105_1: inout std_logic
  );
end IWLS2005__des_perf__part1199;

architecture IWLS2005__des_perf__part1199_behav of IWLS2005__des_perf__part1199 is
begin
    n27105_1 <= ( lo5408 );
end IWLS2005__des_perf__part1199_behav;
