--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1747 is 
  Port (
    lo8815: in std_logic;
    po270: inout std_logic
  );
end Other__carpat__part1747;

architecture Other__carpat__part1747_behav of Other__carpat__part1747 is
begin
    po270 <= ( lo8815 );
end Other__carpat__part1747_behav;
