--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part330 is 
  Port (
    lo1198: in std_logic;
    n5820: inout std_logic
  );
end IWLS2005__des_perf__part330;

architecture IWLS2005__des_perf__part330_behav of IWLS2005__des_perf__part330 is
begin
    n5820 <= ( lo1198 );
end IWLS2005__des_perf__part330_behav;
