--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part701 is 
  Port (
    lo5225: in std_logic;
    n25129: inout std_logic
  );
end Other__carpat__part701;

architecture Other__carpat__part701_behav of Other__carpat__part701 is
begin
    n25129 <= ( lo5225 );
end Other__carpat__part701_behav;
