--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part65 is 
  Port (
    lo2396: in std_logic;
    n5569: inout std_logic
  );
end Other__sudoku_check__part65;

architecture Other__sudoku_check__part65_behav of Other__sudoku_check__part65 is
begin
    n5569 <= ( lo2396 );
end Other__sudoku_check__part65_behav;
