--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part47 is 
  Port (
    lo171: in std_logic;
    po34: inout std_logic
  );
end IWLS2005__systemcdes__part47;

architecture IWLS2005__systemcdes__part47_behav of IWLS2005__systemcdes__part47 is
begin
    po34 <= ( lo171 );
end IWLS2005__systemcdes__part47_behav;
