--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part60 is 
  Port (
    pi1155: in std_logic;
    n72281_1: inout std_logic
  );
end Other__ray__part60;

architecture Other__ray__part60_behav of Other__ray__part60 is
begin
    n72281_1 <= ( pi1155 );
end Other__ray__part60_behav;
