--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part126 is 
  Port (
    lo0005: in std_logic;
    po24: inout std_logic
  );
end IWLS2005__des_perf__part126;

architecture IWLS2005__des_perf__part126_behav of IWLS2005__des_perf__part126 is
begin
    po24 <= ( lo0005 );
end IWLS2005__des_perf__part126_behav;
