--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2175 is 
  Port (
    lo7328: in std_logic;
    n36815_1: inout std_logic
  );
end IWLS2005__des_perf__part2175;

architecture IWLS2005__des_perf__part2175_behav of IWLS2005__des_perf__part2175 is
begin
    n36815_1 <= ( lo7328 );
end IWLS2005__des_perf__part2175_behav;
