--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1970 is 
  Port (
    lo4397: in std_logic;
    n26486: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1970;

architecture Other__ucsb_152_tap_fir__part1970_behav of Other__ucsb_152_tap_fir__part1970 is
begin
    n26486 <= ( lo4397 );
end Other__ucsb_152_tap_fir__part1970_behav;
