--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1798 is 
  Port (
    lo6629: in std_logic;
    n33340_1: inout std_logic
  );
end IWLS2005__des_perf__part1798;

architecture IWLS2005__des_perf__part1798_behav of IWLS2005__des_perf__part1798 is
begin
    n33340_1 <= ( lo6629 );
end IWLS2005__des_perf__part1798_behav;
