--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1393 is 
  Port (
    lo7843: in std_logic;
    n44094_1: inout std_logic
  );
end Other__carpat__part1393;

architecture Other__carpat__part1393_behav of Other__carpat__part1393 is
begin
    n44094_1 <= ( lo7843 );
end Other__carpat__part1393_behav;
