--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part99 is 
  Port (
    lo0168: in std_logic;
    n1139: inout std_logic
  );
end Cookbook__fec_check__part99;

architecture Cookbook__fec_check__part99_behav of Cookbook__fec_check__part99 is
begin
    n1139 <= ( lo0168 );
end Cookbook__fec_check__part99_behav;
