--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1086 is 
  Port (
    lo11086: in std_logic;
    n73921_1: inout std_logic
  );
end Other__ray__part1086;

architecture Other__ray__part1086_behav of Other__ray__part1086 is
begin
    n73921_1 <= ( lo11086 );
end Other__ray__part1086_behav;
