--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part473 is 
  Port (
    lo1610: in std_logic;
    n10159: inout std_logic
  );
end Other__carpat__part473;

architecture Other__carpat__part473_behav of Other__carpat__part473 is
begin
    n10159 <= ( lo1610 );
end Other__carpat__part473_behav;
