--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1284 is 
  Port (
    lo5589: in std_logic;
    n27895: inout std_logic
  );
end IWLS2005__des_perf__part1284;

architecture IWLS2005__des_perf__part1284_behav of IWLS2005__des_perf__part1284 is
begin
    n27895 <= ( lo5589 );
end IWLS2005__des_perf__part1284_behav;
