--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part217 is 
  Port (
    lo0286: in std_logic;
    n1729: inout std_logic
  );
end Cookbook__fec_check__part217;

architecture Cookbook__fec_check__part217_behav of Cookbook__fec_check__part217 is
begin
    n1729 <= ( lo0286 );
end Cookbook__fec_check__part217_behav;
