--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part277 is 
  Port (
    lo03652: in std_logic;
    po6152,po6219,po6458,po6525: inout std_logic
  );
end Other__ray__part277;

architecture Other__ray__part277_behav of Other__ray__part277 is
begin
    po6152 <= ( lo03652 );
    po6219 <= ( lo03652 );
    po6458 <= ( lo03652 );
    po6525 <= ( lo03652 );
end Other__ray__part277_behav;
