--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part774 is 
  Port (
    lo4511: in std_logic;
    n22485: inout std_logic
  );
end IWLS2005__des_perf__part774;

architecture IWLS2005__des_perf__part774_behav of IWLS2005__des_perf__part774 is
begin
    n22485 <= ( lo4511 );
end IWLS2005__des_perf__part774_behav;
