--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1376 is 
  Port (
    lo4745: in std_logic;
    n19214_1: inout std_logic
  );
end Other__sudoku_check__part1376;

architecture Other__sudoku_check__part1376_behav of Other__sudoku_check__part1376 is
begin
    n19214_1 <= ( lo4745 );
end Other__sudoku_check__part1376_behav;
