--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_40__part1 is 
  Port (
    lo006: in std_logic;
    po42: inout std_logic
  );
end Cookbook__gearbox_66_40__part1;

architecture Cookbook__gearbox_66_40__part1_behav of Cookbook__gearbox_66_40__part1 is
begin
    po42 <= ( lo006 );
end Cookbook__gearbox_66_40__part1_behav;
