--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1278 is 
  Port (
    lo4647: in std_logic;
    n18724: inout std_logic
  );
end Other__sudoku_check__part1278;

architecture Other__sudoku_check__part1278_behav of Other__sudoku_check__part1278 is
begin
    n18724 <= ( lo4647 );
end Other__sudoku_check__part1278_behav;
