--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part10 is 
  Port (
    pi48: in std_logic;
    po01: inout std_logic
  );
end Espresso__misg__part10;

architecture Espresso__misg__part10_behav of Espresso__misg__part10 is
begin
    po01 <= ( not pi48 );
end Espresso__misg__part10_behav;
