--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1504 is 
  Port (
    lo1573: in std_logic;
    n8164: inout std_logic
  );
end Cookbook__fec_check__part1504;

architecture Cookbook__fec_check__part1504_behav of Cookbook__fec_check__part1504 is
begin
    n8164 <= ( lo1573 );
end Cookbook__fec_check__part1504_behav;
