--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part21 is 
  Port (
    lo33: in std_logic;
    n168: inout std_logic
  );
end Cookbook__mlab_dcfifo__part21;

architecture Cookbook__mlab_dcfifo__part21_behav of Cookbook__mlab_dcfifo__part21 is
begin
    n168 <= ( lo33 );
end Cookbook__mlab_dcfifo__part21_behav;
