--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part149 is 
  Port (
    lo135: in std_logic;
    po131: inout std_logic
  );
end Cookbook__lc_mult_signed__part149;

architecture Cookbook__lc_mult_signed__part149_behav of Cookbook__lc_mult_signed__part149 is
begin
    po131 <= ( lo135 );
end Cookbook__lc_mult_signed__part149_behav;
