--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part1 is 
  Port (
    lo020: in std_logic;
    n275,n565,n1570: inout std_logic
  );
end ISCAS__s15850__part1;

architecture ISCAS__s15850__part1_behav of ISCAS__s15850__part1 is
begin
    n275 <= ( lo020 );
    n565 <= ( lo020 );
    n1570 <= ( lo020 );
end ISCAS__s15850__part1_behav;
