--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part626 is 
  Port (
    lo4272: in std_logic;
    n21700: inout std_logic
  );
end IWLS2005__des_perf__part626;

architecture IWLS2005__des_perf__part626_behav of IWLS2005__des_perf__part626 is
begin
    n21700 <= ( lo4272 );
end IWLS2005__des_perf__part626_behav;
