--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2018 is 
  Port (
    lo2087: in std_logic;
    n10734: inout std_logic
  );
end Cookbook__fec_check__part2018;

architecture Cookbook__fec_check__part2018_behav of Cookbook__fec_check__part2018 is
begin
    n10734 <= ( lo2087 );
end Cookbook__fec_check__part2018_behav;
