--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part48 is 
  Port (
    lo15854: in std_logic;
    po87: inout std_logic
  );
end IWLS2005__vga_lcd__part48;

architecture IWLS2005__vga_lcd__part48_behav of IWLS2005__vga_lcd__part48 is
begin
    po87 <= ( lo15854 );
end IWLS2005__vga_lcd__part48_behav;
