--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1465 is 
  Port (
    lo1534: in std_logic;
    n7969: inout std_logic
  );
end Cookbook__fec_check__part1465;

architecture Cookbook__fec_check__part1465_behav of Cookbook__fec_check__part1465 is
begin
    n7969 <= ( lo1534 );
end Cookbook__fec_check__part1465_behav;
