--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1369 is 
  Port (
    lo3138: in std_logic;
    n20276: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1369;

architecture Other__ucsb_152_tap_fir__part1369_behav of Other__ucsb_152_tap_fir__part1369 is
begin
    n20276 <= ( lo3138 );
end Other__ucsb_152_tap_fir__part1369_behav;
