--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part147 is 
  Port (
    lo030: in std_logic;
    po030: inout std_logic
  );
end Other__fpu__part147;

architecture Other__fpu__part147_behav of Other__fpu__part147 is
begin
    po030 <= ( lo030 );
end Other__fpu__part147_behav;
