--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1314 is 
  Port (
    lo1383: in std_logic;
    n7214: inout std_logic
  );
end Cookbook__fec_check__part1314;

architecture Cookbook__fec_check__part1314_behav of Cookbook__fec_check__part1314 is
begin
    n7214 <= ( lo1383 );
end Cookbook__fec_check__part1314_behav;
