--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2141 is 
  Port (
    lo2210: in std_logic;
    n11349: inout std_logic
  );
end Cookbook__fec_check__part2141;

architecture Cookbook__fec_check__part2141_behav of Cookbook__fec_check__part2141 is
begin
    n11349 <= ( lo2210 );
end Cookbook__fec_check__part2141_behav;
