--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part87 is 
  Port (
    lo213: in std_logic;
    po125: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part87;

architecture Cookbook__soft_ecc_ram_64bit__part87_behav of Cookbook__soft_ecc_ram_64bit__part87 is
begin
    po125 <= ( lo213 );
end Cookbook__soft_ecc_ram_64bit__part87_behav;
