--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part188 is 
  Port (
    lo174: in std_logic;
    po092: inout std_logic
  );
end Cookbook__lc_mult_signed__part188;

architecture Cookbook__lc_mult_signed__part188_behav of Cookbook__lc_mult_signed__part188 is
begin
    po092 <= ( lo174 );
end Cookbook__lc_mult_signed__part188_behav;
