--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2037 is 
  Port (
    lo4538: in std_logic;
    n27276: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2037;

architecture Other__ucsb_152_tap_fir__part2037_behav of Other__ucsb_152_tap_fir__part2037 is
begin
    n27276 <= ( lo4538 );
end Other__ucsb_152_tap_fir__part2037_behav;
