--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3235 is 
  Port (
    lo8578: in std_logic;
    n43205_1: inout std_logic
  );
end IWLS2005__des_perf__part3235;

architecture IWLS2005__des_perf__part3235_behav of IWLS2005__des_perf__part3235 is
begin
    n43205_1 <= ( lo8578 );
end IWLS2005__des_perf__part3235_behav;
