--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part751 is 
  Port (
    lo5485: in std_logic;
    n25874: inout std_logic
  );
end Other__carpat__part751;

architecture Other__carpat__part751_behav of Other__carpat__part751 is
begin
    n25874 <= ( lo5485 );
end Other__carpat__part751_behav;
