--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part69 is 
  Port (
    lo0423: in std_logic;
    n2739: inout std_logic
  );
end IWLS93__s38417__part69;

architecture IWLS93__s38417__part69_behav of IWLS93__s38417__part69 is
begin
    n2739 <= ( lo0423 );
end IWLS93__s38417__part69_behav;
