--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part434 is 
  Port (
    lo0503: in std_logic;
    n2814: inout std_logic
  );
end Cookbook__fec_check__part434;

architecture Cookbook__fec_check__part434_behav of Cookbook__fec_check__part434 is
begin
    n2814 <= ( lo0503 );
end Cookbook__fec_check__part434_behav;
