--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part600 is 
  Port (
    lo4210: in std_logic;
    n21220: inout std_logic
  );
end IWLS2005__des_perf__part600;

architecture IWLS2005__des_perf__part600_behav of IWLS2005__des_perf__part600 is
begin
    n21220 <= ( lo4210 );
end IWLS2005__des_perf__part600_behav;
