--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part988 is 
  Port (
    lo4951: in std_logic;
    n24905: inout std_logic
  );
end IWLS2005__des_perf__part988;

architecture IWLS2005__des_perf__part988_behav of IWLS2005__des_perf__part988 is
begin
    n24905 <= ( lo4951 );
end IWLS2005__des_perf__part988_behav;
