--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1002 is 
  Port (
    lo1071: in std_logic;
    n5654: inout std_logic
  );
end Cookbook__fec_check__part1002;

architecture Cookbook__fec_check__part1002_behav of Cookbook__fec_check__part1002 is
begin
    n5654 <= ( lo1071 );
end Cookbook__fec_check__part1002_behav;
