--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part762 is 
  Port (
    lo5497: in std_logic;
    n25929: inout std_logic
  );
end Other__carpat__part762;

architecture Other__carpat__part762_behav of Other__carpat__part762 is
begin
    n25929 <= ( lo5497 );
end Other__carpat__part762_behav;
