--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part237 is 
  Port (
    lo0993: in std_logic;
    n5545: inout std_logic
  );
end IWLS2005__des_perf__part237;

architecture IWLS2005__des_perf__part237_behav of IWLS2005__des_perf__part237 is
begin
    n5545 <= ( lo0993 );
end IWLS2005__des_perf__part237_behav;
