--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part115 is 
  Port (
    lo0184: in std_logic;
    n1219: inout std_logic
  );
end Cookbook__fec_check__part115;

architecture Cookbook__fec_check__part115_behav of Cookbook__fec_check__part115 is
begin
    n1219 <= ( lo0184 );
end Cookbook__fec_check__part115_behav;
