--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part77 is 
  Port (
    lo529: in std_logic;
    n2823: inout std_logic
  );
end Cookbook__lane_tx__part77;

architecture Cookbook__lane_tx__part77_behav of Cookbook__lane_tx__part77 is
begin
    n2823 <= ( lo529 );
end Cookbook__lane_tx__part77_behav;
