--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part203 is 
  Port (
    lo0816: in std_logic;
    n6240: inout std_logic
  );
end Other__fp_operators__part203;

architecture Other__fp_operators__part203_behav of Other__fp_operators__part203 is
begin
    n6240 <= ( lo0816 );
end Other__fp_operators__part203_behav;
