--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part539 is 
  Port (
    lo3188: in std_logic;
    n10309: inout std_logic
  );
end Other__sudoku_check__part539;

architecture Other__sudoku_check__part539_behav of Other__sudoku_check__part539 is
begin
    n10309 <= ( lo3188 );
end Other__sudoku_check__part539_behav;
