--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part185 is 
  Port (
    pi1209: in std_logic;
    n33209_1: inout std_logic
  );
end Other__carpat__part185;

architecture Other__carpat__part185_behav of Other__carpat__part185 is
begin
    n33209_1 <= ( pi1209 );
end Other__carpat__part185_behav;
