--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2011 is 
  Port (
    lo2080: in std_logic;
    n10699: inout std_logic
  );
end Cookbook__fec_check__part2011;

architecture Cookbook__fec_check__part2011_behav of Cookbook__fec_check__part2011 is
begin
    n10699 <= ( lo2080 );
end Cookbook__fec_check__part2011_behav;
