--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1459 is 
  Port (
    lo5938: in std_logic;
    n29920_1: inout std_logic
  );
end IWLS2005__des_perf__part1459;

architecture IWLS2005__des_perf__part1459_behav of IWLS2005__des_perf__part1459 is
begin
    n29920_1 <= ( lo5938 );
end IWLS2005__des_perf__part1459_behav;
