--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part35 is 
  Port (
    lo034: in std_logic;
    n480: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part35;

architecture Cookbook__approx_fp_invsqrt__part35_behav of Cookbook__approx_fp_invsqrt__part35 is
begin
    n480 <= ( lo034 );
end Cookbook__approx_fp_invsqrt__part35_behav;
