--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part9 is 
  Port (
    pi09: in std_logic;
    n123: inout std_logic
  );
end Cookbook__pipeline_add_msb__part9;

architecture Cookbook__pipeline_add_msb__part9_behav of Cookbook__pipeline_add_msb__part9 is
begin
    n123 <= ( pi09 );
end Cookbook__pipeline_add_msb__part9_behav;
