--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part7 is 
  Port (
    lo2116: in std_logic;
    n5352: inout std_logic
  );
end Other__top_rs_decode__part7;

architecture Other__top_rs_decode__part7_behav of Other__top_rs_decode__part7 is
begin
    n5352 <= ( lo2116 );
end Other__top_rs_decode__part7_behav;
