--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part143 is 
  Port (
    lo0324: in std_logic;
    n6101: inout std_logic
  );
end Other__ucsb_152_tap_fir__part143;

architecture Other__ucsb_152_tap_fir__part143_behav of Other__ucsb_152_tap_fir__part143 is
begin
    n6101 <= ( lo0324 );
end Other__ucsb_152_tap_fir__part143_behav;
