--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part109 is 
  Port (
    lo0178: in std_logic;
    n1189: inout std_logic
  );
end Cookbook__fec_check__part109;

architecture Cookbook__fec_check__part109_behav of Cookbook__fec_check__part109 is
begin
    n1189 <= ( lo0178 );
end Cookbook__fec_check__part109_behav;
