--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2320 is 
  Port (
    lo3412,lo3786: in std_logic;
    n18909: inout std_logic
  );
end Cookbook__fec_check__part2320;

architecture Cookbook__fec_check__part2320_behav of Cookbook__fec_check__part2320 is
begin
    n18909 <= not (( not lo3412 and not lo3786 ));
end Cookbook__fec_check__part2320_behav;
