--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part120 is 
  Port (
    lo0455: in std_logic;
    n4655: inout std_logic
  );
end Other__fp_operators__part120;

architecture Other__fp_operators__part120_behav of Other__fp_operators__part120 is
begin
    n4655 <= ( lo0455 );
end Other__fp_operators__part120_behav;
