--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part111 is 
  Port (
    lo0180: in std_logic;
    n1199: inout std_logic
  );
end Cookbook__fec_check__part111;

architecture Cookbook__fec_check__part111_behav of Cookbook__fec_check__part111 is
begin
    n1199 <= ( lo0180 );
end Cookbook__fec_check__part111_behav;
