--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part28 is 
  Port (
    lo120: in std_logic;
    po05: inout std_logic
  );
end IWLS2005__systemcdes__part28;

architecture IWLS2005__systemcdes__part28_behav of IWLS2005__systemcdes__part28 is
begin
    po05 <= ( lo120 );
end IWLS2005__systemcdes__part28_behav;
