--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1673 is 
  Port (
    lo8618: in std_logic;
    n48589_1: inout std_logic
  );
end Other__carpat__part1673;

architecture Other__carpat__part1673_behav of Other__carpat__part1673 is
begin
    n48589_1 <= ( lo8618 );
end Other__carpat__part1673_behav;
