--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part151 is 
  Port (
    lo0541: in std_logic;
    n5215: inout std_logic
  );
end Other__fp_operators__part151;

architecture Other__fp_operators__part151_behav of Other__fp_operators__part151 is
begin
    n5215 <= ( lo0541 );
end Other__fp_operators__part151_behav;
