--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part17 is 
  Port (
    lo16: in std_logic;
    po16: inout std_logic
  );
end Other__idxlat02n_m12__part17;

architecture Other__idxlat02n_m12__part17_behav of Other__idxlat02n_m12__part17 is
begin
    po16 <= ( lo16 );
end Other__idxlat02n_m12__part17_behav;
