--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2864 is 
  Port (
    lo8177: in std_logic;
    n41300_1: inout std_logic
  );
end IWLS2005__des_perf__part2864;

architecture IWLS2005__des_perf__part2864_behav of IWLS2005__des_perf__part2864 is
begin
    n41300_1 <= ( lo8177 );
end IWLS2005__des_perf__part2864_behav;
