--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part947 is 
  Port (
    lo4316: in std_logic;
    n17069: inout std_logic
  );
end Other__sudoku_check__part947;

architecture Other__sudoku_check__part947_behav of Other__sudoku_check__part947 is
begin
    n17069 <= ( lo4316 );
end Other__sudoku_check__part947_behav;
