--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part999 is 
  Port (
    lo4962: in std_logic;
    n24820: inout std_logic
  );
end IWLS2005__des_perf__part999;

architecture IWLS2005__des_perf__part999_behav of IWLS2005__des_perf__part999 is
begin
    n24820 <= ( lo4962 );
end IWLS2005__des_perf__part999_behav;
