--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1519 is 
  Port (
    lo5685,lo5686,lo5687,lo5688: in std_logic;
    n27249_1,n29354_1,n29539_1,n29719,n29899_1,n30079,n30259,n30439,n30619: inout std_logic
  );
end Other__sudoku_check__part1519;

architecture Other__sudoku_check__part1519_behav of Other__sudoku_check__part1519 is
begin
    n27249_1 <= ( lo5685 and not lo5686 and not lo5687 and not lo5688 );
    n29354_1 <= ( lo5685 and not lo5686 and not lo5687 and lo5688 );
    n29539_1 <= ( not lo5685 and not lo5686 and not lo5687 and lo5688 );
    n29719 <= ( lo5685 and lo5686 and lo5687 and not lo5688 );
    n29899_1 <= ( not lo5685 and lo5686 and lo5687 and not lo5688 );
    n30079 <= ( lo5685 and not lo5686 and lo5687 and not lo5688 );
    n30259 <= ( not lo5685 and not lo5686 and lo5687 and not lo5688 );
    n30439 <= ( lo5685 and lo5686 and not lo5687 and not lo5688 );
    n30619 <= ( not lo5685 and lo5686 and not lo5687 and not lo5688 );
end Other__sudoku_check__part1519_behav;
