--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2312 is 
  Port (
    lo5104: in std_logic;
    n30046: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2312;

architecture Other__ucsb_152_tap_fir__part2312_behav of Other__ucsb_152_tap_fir__part2312 is
begin
    n30046 <= ( lo5104 );
end Other__ucsb_152_tap_fir__part2312_behav;
