--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part661 is 
  Port (
    lo4307: in std_logic;
    n21445: inout std_logic
  );
end IWLS2005__des_perf__part661;

architecture IWLS2005__des_perf__part661_behav of IWLS2005__des_perf__part661 is
begin
    n21445 <= ( lo4307 );
end IWLS2005__des_perf__part661_behav;
