--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1554 is 
  Port (
    lo8185: in std_logic;
    n45994_1: inout std_logic
  );
end Other__carpat__part1554;

architecture Other__carpat__part1554_behav of Other__carpat__part1554 is
begin
    n45994_1 <= ( lo8185 );
end Other__carpat__part1554_behav;
