--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1522 is 
  Port (
    lo1591: in std_logic;
    n8254: inout std_logic
  );
end Cookbook__fec_check__part1522;

architecture Cookbook__fec_check__part1522_behav of Cookbook__fec_check__part1522 is
begin
    n8254 <= ( lo1591 );
end Cookbook__fec_check__part1522_behav;
