--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1103 is 
  Port (
    lo5180: in std_logic;
    n26120: inout std_logic
  );
end IWLS2005__des_perf__part1103;

architecture IWLS2005__des_perf__part1103_behav of IWLS2005__des_perf__part1103 is
begin
    n26120 <= ( lo5180 );
end IWLS2005__des_perf__part1103_behav;
