--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part34 is 
  Port (
    lo00303: in std_logic;
    po017: inout std_logic
  );
end IWLS2005__ethernet__part34;

architecture IWLS2005__ethernet__part34_behav of IWLS2005__ethernet__part34 is
begin
    po017 <= ( lo00303 );
end IWLS2005__ethernet__part34_behav;
