--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part121 is 
  Port (
    lo3271: in std_logic;
    n16834: inout std_logic
  );
end IWLS2005__pci_bridge32__part121;

architecture IWLS2005__pci_bridge32__part121_behav of IWLS2005__pci_bridge32__part121 is
begin
    n16834 <= ( lo3271 );
end IWLS2005__pci_bridge32__part121_behav;
