--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part67 is 
  Port (
    pi067: in std_logic;
    n9984_1: inout std_logic
  );
end Other__desperf__part67;

architecture Other__desperf__part67_behav of Other__desperf__part67 is
begin
    n9984_1 <= ( pi067 );
end Other__desperf__part67_behav;
