--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1664 is 
  Port (
    lo3784: in std_logic;
    n23496: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1664;

architecture Other__ucsb_152_tap_fir__part1664_behav of Other__ucsb_152_tap_fir__part1664 is
begin
    n23496 <= ( lo3784 );
end Other__ucsb_152_tap_fir__part1664_behav;
