--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part807 is 
  Port (
    lo0876: in std_logic;
    n4679: inout std_logic
  );
end Cookbook__fec_check__part807;

architecture Cookbook__fec_check__part807_behav of Cookbook__fec_check__part807 is
begin
    n4679 <= ( lo0876 );
end Cookbook__fec_check__part807_behav;
