--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2160 is 
  Port (
    lo4795: in std_logic;
    n28561: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2160;

architecture Other__ucsb_152_tap_fir__part2160_behav of Other__ucsb_152_tap_fir__part2160 is
begin
    n28561 <= ( lo4795 );
end Other__ucsb_152_tap_fir__part2160_behav;
