--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part786 is 
  Port (
    lo06513: in std_logic;
    n48891_1: inout std_logic
  );
end Other__ray__part786;

architecture Other__ray__part786_behav of Other__ray__part786 is
begin
    n48891_1 <= ( lo06513 );
end Other__ray__part786_behav;
