--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part493 is 
  Port (
    lo2055: in std_logic;
    n14099: inout std_logic
  );
end Other__carpat__part493;

architecture Other__carpat__part493_behav of Other__carpat__part493 is
begin
    n14099 <= ( lo2055 );
end Other__carpat__part493_behav;
