--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part981 is 
  Port (
    lo1050: in std_logic;
    n5549: inout std_logic
  );
end Cookbook__fec_check__part981;

architecture Cookbook__fec_check__part981_behav of Cookbook__fec_check__part981 is
begin
    n5549 <= ( lo1050 );
end Cookbook__fec_check__part981_behav;
