--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part266 is 
  Port (
    lo1051: in std_logic;
    n5780: inout std_logic
  );
end IWLS2005__des_perf__part266;

architecture IWLS2005__des_perf__part266_behav of IWLS2005__des_perf__part266 is
begin
    n5780 <= ( lo1051 );
end IWLS2005__des_perf__part266_behav;
