--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1498 is 
  Port (
    lo8129: in std_logic;
    n44694_1: inout std_logic
  );
end Other__carpat__part1498;

architecture Other__carpat__part1498_behav of Other__carpat__part1498 is
begin
    n44694_1 <= ( lo8129 );
end Other__carpat__part1498_behav;
