--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part747 is 
  Port (
    lo4471: in std_logic;
    n22655: inout std_logic
  );
end IWLS2005__des_perf__part747;

architecture IWLS2005__des_perf__part747_behav of IWLS2005__des_perf__part747 is
begin
    n22655 <= ( lo4471 );
end IWLS2005__des_perf__part747_behav;
