--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1735 is 
  Port (
    lo6519: in std_logic;
    n32350: inout std_logic
  );
end IWLS2005__des_perf__part1735;

architecture IWLS2005__des_perf__part1735_behav of IWLS2005__des_perf__part1735 is
begin
    n32350 <= ( lo6519 );
end IWLS2005__des_perf__part1735_behav;
