--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part610 is 
  Port (
    lo3259: in std_logic;
    n11019: inout std_logic
  );
end Other__sudoku_check__part610;

architecture Other__sudoku_check__part610_behav of Other__sudoku_check__part610 is
begin
    n11019 <= ( lo3259 );
end Other__sudoku_check__part610_behav;
