--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1862 is 
  Port (
    lo9135: in std_logic;
    po499: inout std_logic
  );
end Other__carpat__part1862;

architecture Other__carpat__part1862_behav of Other__carpat__part1862 is
begin
    po499 <= ( lo9135 );
end Other__carpat__part1862_behav;
