--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1813 is 
  Port (
    lo1882: in std_logic;
    n9709: inout std_logic
  );
end Cookbook__fec_check__part1813;

architecture Cookbook__fec_check__part1813_behav of Cookbook__fec_check__part1813 is
begin
    n9709 <= ( lo1882 );
end Cookbook__fec_check__part1813_behav;
