--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part24 is 
  Port (
    lo023: in std_logic;
    n425_1: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part24;

architecture Cookbook__approx_fp_invsqrt__part24_behav of Cookbook__approx_fp_invsqrt__part24 is
begin
    n425_1 <= ( lo023 );
end Cookbook__approx_fp_invsqrt__part24_behav;
