--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part24 is 
  Port (
    lo116,lo117,lo108,lo109,lo110,lo111,lo112,lo113,lo114,lo115,lo118: in std_logic;
    n802_1,n807_1,n812_1,n817_1,n822,n827_1,n832,n837: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part24;

architecture Cookbook__ycbcr_to_rgb__part24_behav of Cookbook__ycbcr_to_rgb__part24 is
signal n1206,n1207,n1208,n1209,n1210,n1211,n1212,n1213,n1214: std_logic;
begin
    n1206 <= not (( not lo116 and not lo117 ));
    n1207 <= not (( not lo108 and not n1206 ));
    n1208 <= not (( not lo109 and not n1206 ));
    n1209 <= not (( not lo110 and not n1206 ));
    n1210 <= not (( not lo111 and not n1206 ));
    n1211 <= not (( not lo112 and not n1206 ));
    n1212 <= not (( not lo113 and not n1206 ));
    n1213 <= not (( not lo114 and not n1206 ));
    n1214 <= not (( not lo115 and not n1206 ));
    n802_1 <= ( n1207 and not lo118 );
    n807_1 <= ( n1208 and not lo118 );
    n812_1 <= ( n1209 and not lo118 );
    n817_1 <= ( n1210 and not lo118 );
    n822 <= ( n1211 and not lo118 );
    n827_1 <= ( n1212 and not lo118 );
    n832 <= ( n1213 and not lo118 );
    n837 <= ( n1214 and not lo118 );
end Cookbook__ycbcr_to_rgb__part24_behav;
