--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part732 is 
  Port (
    lo0801: in std_logic;
    n4304: inout std_logic
  );
end Cookbook__fec_check__part732;

architecture Cookbook__fec_check__part732_behav of Cookbook__fec_check__part732 is
begin
    n4304 <= ( lo0801 );
end Cookbook__fec_check__part732_behav;
