--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part387 is 
  Port (
    lo0456: in std_logic;
    n2579: inout std_logic
  );
end Cookbook__fec_check__part387;

architecture Cookbook__fec_check__part387_behav of Cookbook__fec_check__part387 is
begin
    n2579 <= ( lo0456 );
end Cookbook__fec_check__part387_behav;
