--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part714 is 
  Port (
    lo4399: in std_logic;
    n22180: inout std_logic
  );
end IWLS2005__des_perf__part714;

architecture IWLS2005__des_perf__part714_behav of IWLS2005__des_perf__part714 is
begin
    n22180 <= ( lo4399 );
end IWLS2005__des_perf__part714_behav;
