--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1003 is 
  Port (
    lo4966: in std_logic;
    n24950: inout std_logic
  );
end IWLS2005__des_perf__part1003;

architecture IWLS2005__des_perf__part1003_behav of IWLS2005__des_perf__part1003 is
begin
    n24950 <= ( lo4966 );
end IWLS2005__des_perf__part1003_behav;
