--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1401 is 
  Port (
    lo3229: in std_logic;
    n20721: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1401;

architecture Other__ucsb_152_tap_fir__part1401_behav of Other__ucsb_152_tap_fir__part1401 is
begin
    n20721 <= ( lo3229 );
end Other__ucsb_152_tap_fir__part1401_behav;
