--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1192 is 
  Port (
    lo5389: in std_logic;
    n27250_1: inout std_logic
  );
end IWLS2005__des_perf__part1192;

architecture IWLS2005__des_perf__part1192_behav of IWLS2005__des_perf__part1192 is
begin
    n27250_1 <= ( lo5389 );
end IWLS2005__des_perf__part1192_behav;
