--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part567 is 
  Port (
    lo0636: in std_logic;
    n3479: inout std_logic
  );
end Cookbook__fec_check__part567;

architecture Cookbook__fec_check__part567_behav of Cookbook__fec_check__part567 is
begin
    n3479 <= ( lo0636 );
end Cookbook__fec_check__part567_behav;
