--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part124 is 
  Port (
    lo0917: in std_logic;
    n4859: inout std_logic
  );
end LGSynth91__s38417__part124;

architecture LGSynth91__s38417__part124_behav of LGSynth91__s38417__part124 is
begin
    n4859 <= ( lo0917 );
end LGSynth91__s38417__part124_behav;
