--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part192 is 
  Port (
    lo03232: in std_logic;
    n34036: inout std_logic
  );
end Other__ray__part192;

architecture Other__ray__part192_behav of Other__ray__part192 is
begin
    n34036 <= ( lo03232 );
end Other__ray__part192_behav;
