--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part340 is 
  Port (
    lo1606,lo1605: in std_logic;
    n6860_1,n11400_1,n11405_1,n6855_1,po657,po658: inout std_logic
  );
end Other__fp_operators__part340;

architecture Other__fp_operators__part340_behav of Other__fp_operators__part340 is
signal n25743,n25744,n37138,n37139: std_logic;
begin
    n6860_1 <= ( not lo1606 );
    n25743 <= ( not lo1605 and lo1606 );
    n25744 <= not (( not n37139 and not n25743 ));
    n11400_1 <= ( not lo1605 and not n25744 );
    n11405_1 <= ( not n25744 and n37138 );
    n37138 <= ( not lo1606 and lo1605 )
      or ( lo1606 and not lo1605 );
    n37139 <= ( lo1606 and lo1605 );
    n6855_1 <= ( lo1605 );
    po657 <= ( lo1605 );
    po658 <= ( lo1606 );
end Other__fp_operators__part340_behav;
