--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part32 is 
  Port (
    lo243: in std_logic;
    po020: inout std_logic
  );
end IWLS2005__aes_core__part32;

architecture IWLS2005__aes_core__part32_behav of IWLS2005__aes_core__part32 is
begin
    po020 <= ( lo243 );
end IWLS2005__aes_core__part32_behav;
