--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part272 is 
  Port (
    lo1098: in std_logic;
    n6000: inout std_logic
  );
end IWLS2005__des_perf__part272;

architecture IWLS2005__des_perf__part272_behav of IWLS2005__des_perf__part272 is
begin
    n6000 <= ( lo1098 );
end IWLS2005__des_perf__part272_behav;
