--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part294 is 
  Port (
    lo1069: in std_logic;
    n6604: inout std_logic
  );
end Cookbook__ucrypt__part294;

architecture Cookbook__ucrypt__part294_behav of Cookbook__ucrypt__part294 is
begin
    n6604 <= ( lo1069 );
end Cookbook__ucrypt__part294_behav;
