--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part901 is 
  Port (
    lo09287: in std_logic;
    n59536_1: inout std_logic
  );
end Other__ray__part901;

architecture Other__ray__part901_behav of Other__ray__part901 is
begin
    n59536_1 <= ( lo09287 );
end Other__ray__part901_behav;
