--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part430 is 
  Port (
    lo2297: in std_logic;
    n10990: inout std_logic
  );
end IWLS2005__des_perf__part430;

architecture IWLS2005__des_perf__part430_behav of IWLS2005__des_perf__part430 is
begin
    n10990 <= ( not lo2297 );
end IWLS2005__des_perf__part430_behav;
