--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part124 is 
  Port (
    lo007: in std_logic;
    po007: inout std_logic
  );
end Other__fpu__part124;

architecture Other__fpu__part124_behav of Other__fpu__part124 is
begin
    po007 <= ( lo007 );
end Other__fpu__part124_behav;
