--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2425 is 
  Port (
    lo5340: in std_logic;
    n31286_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2425;

architecture Other__ucsb_152_tap_fir__part2425_behav of Other__ucsb_152_tap_fir__part2425 is
begin
    n31286_1 <= ( lo5340 );
end Other__ucsb_152_tap_fir__part2425_behav;
