--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part626 is 
  Port (
    lo06107: in std_logic;
    n38481: inout std_logic
  );
end Other__ray__part626;

architecture Other__ray__part626_behav of Other__ray__part626 is
begin
    n38481 <= ( lo06107 );
end Other__ray__part626_behav;
