--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part98 is 
  Port (
    pi0508: in std_logic;
    n43086_1: inout std_logic
  );
end Other__radar__part98;

architecture Other__radar__part98_behav of Other__radar__part98 is
begin
    n43086_1 <= ( pi0508 );
end Other__radar__part98_behav;
