--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part156 is 
  Port (
    lo0546: in std_logic;
    n5240: inout std_logic
  );
end Other__fp_operators__part156;

architecture Other__fp_operators__part156_behav of Other__fp_operators__part156 is
begin
    n5240 <= ( lo0546 );
end Other__fp_operators__part156_behav;
