--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part16 is 
  Port (
    lo81: in std_logic;
    po04: inout std_logic
  );
end Cookbook__gearbox_67_20__part16;

architecture Cookbook__gearbox_67_20__part16_behav of Cookbook__gearbox_67_20__part16 is
begin
    po04 <= ( lo81 );
end Cookbook__gearbox_67_20__part16_behav;
