--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part186 is 
  Port (
    lo172: in std_logic;
    po094: inout std_logic
  );
end Cookbook__lc_mult_signed__part186;

architecture Cookbook__lc_mult_signed__part186_behav of Cookbook__lc_mult_signed__part186 is
begin
    po094 <= ( lo172 );
end Cookbook__lc_mult_signed__part186_behav;
