--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1170 is 
  Port (
    lo4539: in std_logic;
    n18184: inout std_logic
  );
end Other__sudoku_check__part1170;

architecture Other__sudoku_check__part1170_behav of Other__sudoku_check__part1170 is
begin
    n18184 <= ( lo4539 );
end Other__sudoku_check__part1170_behav;
