--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part12 is 
  Port (
    pi742,pi743: in std_logic;
    po041: inout std_logic
  );
end Other__fp_operators__part12;

architecture Other__fp_operators__part12_behav of Other__fp_operators__part12 is
begin
    po041 <= ( not pi742 and pi743 )
      or ( pi742 and not pi743 );
end Other__fp_operators__part12_behav;
