--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2059 is 
  Port (
    lo4590: in std_logic;
    n27531: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2059;

architecture Other__ucsb_152_tap_fir__part2059_behav of Other__ucsb_152_tap_fir__part2059 is
begin
    n27531 <= ( lo4590 );
end Other__ucsb_152_tap_fir__part2059_behav;
