--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1599 is 
  Port (
    lo8312: in std_logic;
    n46449_1: inout std_logic
  );
end Other__carpat__part1599;

architecture Other__carpat__part1599_behav of Other__carpat__part1599 is
begin
    n46449_1 <= ( lo8312 );
end Other__carpat__part1599_behav;
