--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1578 is 
  Port (
    lo1647: in std_logic;
    n8534: inout std_logic
  );
end Cookbook__fec_check__part1578;

architecture Cookbook__fec_check__part1578_behav of Cookbook__fec_check__part1578 is
begin
    n8534 <= ( lo1647 );
end Cookbook__fec_check__part1578_behav;
