--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part306 is 
  Port (
    lo03696: in std_logic;
    po6247,po6314,po6553,po6620: inout std_logic
  );
end Other__ray__part306;

architecture Other__ray__part306_behav of Other__ray__part306 is
begin
    po6247 <= ( lo03696 );
    po6314 <= ( lo03696 );
    po6553 <= ( lo03696 );
    po6620 <= ( lo03696 );
end Other__ray__part306_behav;
