--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part13 is 
  Port (
    lo34: in std_logic;
    po05: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part13;

architecture Cookbook__soft_ecc_ram_16bit__part13_behav of Cookbook__soft_ecc_ram_16bit__part13 is
begin
    po05 <= ( lo34 );
end Cookbook__soft_ecc_ram_16bit__part13_behav;
