--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1290 is 
  Port (
    lo5595: in std_logic;
    n27615_1: inout std_logic
  );
end IWLS2005__des_perf__part1290;

architecture IWLS2005__des_perf__part1290_behav of IWLS2005__des_perf__part1290 is
begin
    n27615_1 <= ( lo5595 );
end IWLS2005__des_perf__part1290_behav;
