--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part15 is 
  Port (
    lo462: in std_logic;
    po09: inout std_logic
  );
end Cookbook__lane_tx__part15;

architecture Cookbook__lane_tx__part15_behav of Cookbook__lane_tx__part15 is
begin
    po09 <= ( lo462 );
end Cookbook__lane_tx__part15_behav;
