--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part569 is 
  Port (
    lo4173: in std_logic;
    n21030: inout std_logic
  );
end IWLS2005__des_perf__part569;

architecture IWLS2005__des_perf__part569_behav of IWLS2005__des_perf__part569 is
begin
    n21030 <= ( lo4173 );
end IWLS2005__des_perf__part569_behav;
