--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part78 is 
  Port (
    lo312: in std_logic;
    po071: inout std_logic
  );
end IWLS2005__aes_core__part78;

architecture IWLS2005__aes_core__part78_behav of IWLS2005__aes_core__part78 is
begin
    po071 <= ( lo312 );
end IWLS2005__aes_core__part78_behav;
