--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part31 is 
  Port (
    lo111: in std_logic;
    n359: inout std_logic
  );
end ISCAS__s3384__part31;

architecture ISCAS__s3384__part31_behav of ISCAS__s3384__part31 is
begin
    n359 <= ( not lo111 );
end ISCAS__s3384__part31_behav;
