--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1094 is 
  Port (
    lo4463: in std_logic;
    n17804: inout std_logic
  );
end Other__sudoku_check__part1094;

architecture Other__sudoku_check__part1094_behav of Other__sudoku_check__part1094 is
begin
    n17804 <= ( lo4463 );
end Other__sudoku_check__part1094_behav;
