--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part245 is 
  Port (
    lo1010: in std_logic;
    n4654: inout std_logic
  );
end Other__desperf__part245;

architecture Other__desperf__part245_behav of Other__desperf__part245 is
begin
    n4654 <= ( lo1010 );
end Other__desperf__part245_behav;
