--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part42 is 
  Port (
    lo0186: in std_logic;
    n2162: inout std_logic
  );
end Other__cfft__part42;

architecture Other__cfft__part42_behav of Other__cfft__part42 is
begin
    n2162 <= ( not lo0186 );
end Other__cfft__part42_behav;
