--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part655 is 
  Port (
    lo0724: in std_logic;
    n3919: inout std_logic
  );
end Cookbook__fec_check__part655;

architecture Cookbook__fec_check__part655_behav of Cookbook__fec_check__part655 is
begin
    n3919 <= ( lo0724 );
end Cookbook__fec_check__part655_behav;
