--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part5 is 
  Port (
    pi097: in std_logic;
    n9074: inout std_logic
  );
end IWLS2005__usb_funct__part5;

architecture IWLS2005__usb_funct__part5_behav of IWLS2005__usb_funct__part5 is
begin
    n9074 <= ( pi097 );
end IWLS2005__usb_funct__part5_behav;
