--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part233 is 
  Port (
    lo219: in std_logic;
    po047: inout std_logic
  );
end Cookbook__lc_mult_signed__part233;

architecture Cookbook__lc_mult_signed__part233_behav of Cookbook__lc_mult_signed__part233 is
begin
    po047 <= ( lo219 );
end Cookbook__lc_mult_signed__part233_behav;
