--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part123 is 
  Port (
    lo0002: in std_logic;
    po36: inout std_logic
  );
end IWLS2005__des_perf__part123;

architecture IWLS2005__des_perf__part123_behav of IWLS2005__des_perf__part123 is
begin
    po36 <= ( lo0002 );
end IWLS2005__des_perf__part123_behav;
