--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__adder_tree_node__part11 is 
  Port (
    lo09: in std_logic;
    po07: inout std_logic
  );
end Cookbook__adder_tree_node__part11;

architecture Cookbook__adder_tree_node__part11_behav of Cookbook__adder_tree_node__part11 is
begin
    po07 <= ( lo09 );
end Cookbook__adder_tree_node__part11_behav;
