--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1936 is 
  Port (
    lo6957: in std_logic;
    n34930_1: inout std_logic
  );
end IWLS2005__des_perf__part1936;

architecture IWLS2005__des_perf__part1936_behav of IWLS2005__des_perf__part1936 is
begin
    n34930_1 <= ( lo6957 );
end IWLS2005__des_perf__part1936_behav;
