--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1115 is 
  Port (
    lo1184: in std_logic;
    n6219: inout std_logic
  );
end Cookbook__fec_check__part1115;

architecture Cookbook__fec_check__part1115_behav of Cookbook__fec_check__part1115 is
begin
    n6219 <= ( lo1184 );
end Cookbook__fec_check__part1115_behav;
