--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1205 is 
  Port (
    lo5415: in std_logic;
    n27095_1: inout std_logic
  );
end IWLS2005__des_perf__part1205;

architecture IWLS2005__des_perf__part1205_behav of IWLS2005__des_perf__part1205 is
begin
    n27095_1 <= ( lo5415 );
end IWLS2005__des_perf__part1205_behav;
