--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part76 is 
  Port (
    lo73: in std_logic;
    po11: inout std_logic
  );
end Cookbook__approx_fp_div__part76;

architecture Cookbook__approx_fp_div__part76_behav of Cookbook__approx_fp_div__part76 is
begin
    po11 <= ( lo73 );
end Cookbook__approx_fp_div__part76_behav;
