--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part610 is 
  Port (
    lo06091: in std_logic;
    n38401: inout std_logic
  );
end Other__ray__part610;

architecture Other__ray__part610_behav of Other__ray__part610 is
begin
    n38401 <= ( lo06091 );
end Other__ray__part610_behav;
