--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part33 is 
  Port (
    lo0133: in std_logic;
    po393: inout std_logic
  );
end Other__cfft__part33;

architecture Other__cfft__part33_behav of Other__cfft__part33 is
begin
    po393 <= ( lo0133 );
end Other__cfft__part33_behav;
