--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part848 is 
  Port (
    lo0917: in std_logic;
    n4884: inout std_logic
  );
end Cookbook__fec_check__part848;

architecture Cookbook__fec_check__part848_behav of Cookbook__fec_check__part848 is
begin
    n4884 <= ( lo0917 );
end Cookbook__fec_check__part848_behav;
