--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1435 is 
  Port (
    lo4804: in std_logic;
    n19509_1: inout std_logic
  );
end Other__sudoku_check__part1435;

architecture Other__sudoku_check__part1435_behav of Other__sudoku_check__part1435 is
begin
    n19509_1 <= ( lo4804 );
end Other__sudoku_check__part1435_behav;
