--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1624 is 
  Port (
    lo1693: in std_logic;
    n8764: inout std_logic
  );
end Cookbook__fec_check__part1624;

architecture Cookbook__fec_check__part1624_behav of Cookbook__fec_check__part1624 is
begin
    n8764 <= ( lo1693 );
end Cookbook__fec_check__part1624_behav;
