--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity EPFL__mem_ctrl__part1 is 
  Port (
    pi0956: in std_logic;
    po014: inout std_logic
  );
end EPFL__mem_ctrl__part1;

architecture EPFL__mem_ctrl__part1_behav of EPFL__mem_ctrl__part1 is
begin
    po014 <= ( not pi0956 );
end EPFL__mem_ctrl__part1_behav;
