--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3173 is 
  Port (
    lo8496: in std_logic;
    n42980_1: inout std_logic
  );
end IWLS2005__des_perf__part3173;

architecture IWLS2005__des_perf__part3173_behav of IWLS2005__des_perf__part3173 is
begin
    n42980_1 <= ( lo8496 );
end IWLS2005__des_perf__part3173_behav;
