--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part507 is 
  Port (
    lo05979: in std_logic;
    po1494,po1528: inout std_logic
  );
end Other__ray__part507;

architecture Other__ray__part507_behav of Other__ray__part507 is
begin
    po1494 <= ( lo05979 );
    po1528 <= ( lo05979 );
end Other__ray__part507_behav;
