--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1528 is 
  Port (
    lo5721,lo5722,lo5723,lo5724: in std_logic;
    n27294_1,n27369_1,n27374_1,n27379_1,n27384_1,n27389_1,n27394_1,n27399_1,n27404_1: inout std_logic
  );
end Other__sudoku_check__part1528;

architecture Other__sudoku_check__part1528_behav of Other__sudoku_check__part1528 is
begin
    n27294_1 <= ( lo5721 and not lo5722 and not lo5723 and not lo5724 );
    n27369_1 <= ( lo5721 and not lo5722 and not lo5723 and lo5724 );
    n27374_1 <= ( not lo5721 and not lo5722 and not lo5723 and lo5724 );
    n27379_1 <= ( lo5721 and lo5722 and lo5723 and not lo5724 );
    n27384_1 <= ( not lo5721 and lo5722 and lo5723 and not lo5724 );
    n27389_1 <= ( lo5721 and not lo5722 and lo5723 and not lo5724 );
    n27394_1 <= ( not lo5721 and not lo5722 and lo5723 and not lo5724 );
    n27399_1 <= ( lo5721 and lo5722 and not lo5723 and not lo5724 );
    n27404_1 <= ( not lo5721 and lo5722 and not lo5723 and not lo5724 );
end Other__sudoku_check__part1528_behav;
