--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part885 is 
  Port (
    lo6721: in std_logic;
    n32784_1: inout std_logic
  );
end Other__carpat__part885;

architecture Other__carpat__part885_behav of Other__carpat__part885 is
begin
    n32784_1 <= ( lo6721 );
end Other__carpat__part885_behav;
