--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2153 is 
  Port (
    lo4788: in std_logic;
    n28526: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2153;

architecture Other__ucsb_152_tap_fir__part2153_behav of Other__ucsb_152_tap_fir__part2153 is
begin
    n28526 <= ( lo4788 );
end Other__ucsb_152_tap_fir__part2153_behav;
