--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part396 is 
  Port (
    lo1395: in std_logic;
    n8234_1: inout std_logic
  );
end Cookbook__ucrypt__part396;

architecture Cookbook__ucrypt__part396_behav of Cookbook__ucrypt__part396 is
begin
    n8234_1 <= ( lo1395 );
end Cookbook__ucrypt__part396_behav;
