--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part32 is 
  Port (
    lo0023: in std_logic;
    n1374: inout std_logic
  );
end Cookbook__ucrypt__part32;

architecture Cookbook__ucrypt__part32_behav of Cookbook__ucrypt__part32 is
begin
    n1374 <= ( lo0023 );
end Cookbook__ucrypt__part32_behav;
