--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part208 is 
  Port (
    lo2857: in std_logic;
    n6999: inout std_logic
  );
end Other__sudoku_check__part208;

architecture Other__sudoku_check__part208_behav of Other__sudoku_check__part208 is
begin
    n6999 <= ( lo2857 );
end Other__sudoku_check__part208_behav;
