--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part202 is 
  Port (
    lo0499: in std_logic;
    n7071: inout std_logic
  );
end Other__ucsb_152_tap_fir__part202;

architecture Other__ucsb_152_tap_fir__part202_behav of Other__ucsb_152_tap_fir__part202 is
begin
    n7071 <= ( lo0499 );
end Other__ucsb_152_tap_fir__part202_behav;
