--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part310 is 
  Port (
    lo1172: in std_logic;
    n6330: inout std_logic
  );
end IWLS2005__des_perf__part310;

architecture IWLS2005__des_perf__part310_behav of IWLS2005__des_perf__part310 is
begin
    n6330 <= ( lo1172 );
end IWLS2005__des_perf__part310_behav;
