--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1533 is 
  Port (
    lo8164: in std_logic;
    n45889_1: inout std_logic
  );
end Other__carpat__part1533;

architecture Other__carpat__part1533_behav of Other__carpat__part1533 is
begin
    n45889_1 <= ( lo8164 );
end Other__carpat__part1533_behav;
