--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part920 is 
  Port (
    lo0989: in std_logic;
    n5244: inout std_logic
  );
end Cookbook__fec_check__part920;

architecture Cookbook__fec_check__part920_behav of Cookbook__fec_check__part920 is
begin
    n5244 <= ( lo0989 );
end Cookbook__fec_check__part920_behav;
