--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part80 is 
  Port (
    lo0661: in std_logic;
    n4269: inout std_logic
  );
end ISCAS__s38417__part80;

architecture ISCAS__s38417__part80_behav of ISCAS__s38417__part80 is
begin
    n4269 <= ( not lo0661 );
end ISCAS__s38417__part80_behav;
