--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part52 is 
  Port (
    pi052: in std_logic;
    n9909_1: inout std_logic
  );
end Other__desperf__part52;

architecture Other__desperf__part52_behav of Other__desperf__part52 is
begin
    n9909_1 <= ( pi052 );
end Other__desperf__part52_behav;
