--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part23 is 
  Port (
    lo1944: in std_logic;
    n5139: inout std_logic
  );
end Other__sudoku_check__part23;

architecture Other__sudoku_check__part23_behav of Other__sudoku_check__part23 is
begin
    n5139 <= ( lo1944 );
end Other__sudoku_check__part23_behav;
