--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1088 is 
  Port (
    lo5164: in std_logic;
    n26100: inout std_logic
  );
end IWLS2005__des_perf__part1088;

architecture IWLS2005__des_perf__part1088_behav of IWLS2005__des_perf__part1088 is
begin
    n26100 <= ( lo5164 );
end IWLS2005__des_perf__part1088_behav;
