--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2597 is 
  Port (
    lo7854: in std_logic;
    n39110: inout std_logic
  );
end IWLS2005__des_perf__part2597;

architecture IWLS2005__des_perf__part2597_behav of IWLS2005__des_perf__part2597 is
begin
    n39110 <= ( lo7854 );
end IWLS2005__des_perf__part2597_behav;
