--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part243 is 
  Port (
    lo1193: in std_logic;
    n7445_1: inout std_logic
  );
end Other__fp_operators__part243;

architecture Other__fp_operators__part243_behav of Other__fp_operators__part243 is
begin
    n7445_1 <= ( lo1193 );
end Other__fp_operators__part243_behav;
