--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part180 is 
  Port (
    lo0426: in std_logic;
    n6621: inout std_logic
  );
end Other__ucsb_152_tap_fir__part180;

architecture Other__ucsb_152_tap_fir__part180_behav of Other__ucsb_152_tap_fir__part180 is
begin
    n6621 <= ( lo0426 );
end Other__ucsb_152_tap_fir__part180_behav;
