--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part420 is 
  Port (
    lo0306,lo0307,lo0310,lo0311,lo0312,lo0313,lo0314,lo0315,lo0316,lo0324: in std_logic;
    n6609: inout std_logic
  );
end Other__carpat__part420;

architecture Other__carpat__part420_behav of Other__carpat__part420 is
signal n6559,n6569,n6574,n6579,n6584,n6589,n6594,n6599: std_logic;
begin
    n6559 <= ( not lo0306 and lo0307 )
      or ( lo0306 and not lo0307 );
    n6569 <= ( not n6559 and lo0310 )
      or ( n6559 and not lo0310 );
    n6574 <= ( not n6569 and lo0311 )
      or ( n6569 and not lo0311 );
    n6579 <= ( not n6574 and lo0312 )
      or ( n6574 and not lo0312 );
    n6584 <= ( not n6579 and lo0313 )
      or ( n6579 and not lo0313 );
    n6589 <= ( not n6584 and lo0314 )
      or ( n6584 and not lo0314 );
    n6594 <= ( not n6589 and lo0315 )
      or ( n6589 and not lo0315 );
    n6599 <= ( not n6594 and lo0316 )
      or ( n6594 and not lo0316 );
    n6609 <= ( not n6599 and lo0324 )
      or ( n6599 and not lo0324 );
end Other__carpat__part420_behav;
