--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part30 is 
  Port (
    lo97627: in std_logic;
    n488100_1: inout std_logic
  );
end IWLS2005__netcard__part30;

architecture IWLS2005__netcard__part30_behav of IWLS2005__netcard__part30 is
begin
    n488100_1 <= ( lo97627 );
end IWLS2005__netcard__part30_behav;
