--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part635 is 
  Port (
    lo06132: in std_logic;
    po1698,po1793: inout std_logic
  );
end Other__ray__part635;

architecture Other__ray__part635_behav of Other__ray__part635 is
begin
    po1698 <= ( lo06132 );
    po1793 <= ( lo06132 );
end Other__ray__part635_behav;
