--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part78 is 
  Port (
    lo0599: in std_logic;
    n3824: inout std_logic
  );
end LGSynth91__s38417__part78;

architecture LGSynth91__s38417__part78_behav of LGSynth91__s38417__part78 is
begin
    n3824 <= ( not lo0599 );
end LGSynth91__s38417__part78_behav;
