--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part491 is 
  Port (
    lo05963: in std_logic;
    po1478,po1543,po1835,po1904: inout std_logic
  );
end Other__ray__part491;

architecture Other__ray__part491_behav of Other__ray__part491 is
begin
    po1478 <= ( lo05963 );
    po1543 <= ( lo05963 );
    po1835 <= ( lo05963 );
    po1904 <= ( lo05963 );
end Other__ray__part491_behav;
