--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part16 is 
  Port (
    pi19: in std_logic;
    n117: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part16;

architecture Cookbook__ycbcr_to_rgb__part16_behav of Cookbook__ycbcr_to_rgb__part16 is
begin
    n117 <= ( pi19 );
end Cookbook__ycbcr_to_rgb__part16_behav;
