--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part290 is 
  Port (
    lo2939: in std_logic;
    n7819: inout std_logic
  );
end Other__sudoku_check__part290;

architecture Other__sudoku_check__part290_behav of Other__sudoku_check__part290 is
begin
    n7819 <= ( lo2939 );
end Other__sudoku_check__part290_behav;
