--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2444 is 
  Port (
    lo5384: in std_logic;
    n31516: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2444;

architecture Other__ucsb_152_tap_fir__part2444_behav of Other__ucsb_152_tap_fir__part2444 is
begin
    n31516 <= ( lo5384 );
end Other__ucsb_152_tap_fir__part2444_behav;
