--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1185 is 
  Port (
    lo4554: in std_logic;
    n18259: inout std_logic
  );
end Other__sudoku_check__part1185;

architecture Other__sudoku_check__part1185_behav of Other__sudoku_check__part1185 is
begin
    n18259 <= ( lo4554 );
end Other__sudoku_check__part1185_behav;
