--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1138 is 
  Port (
    lo5295: in std_logic;
    n26605_1: inout std_logic
  );
end IWLS2005__des_perf__part1138;

architecture IWLS2005__des_perf__part1138_behav of IWLS2005__des_perf__part1138 is
begin
    n26605_1 <= ( lo5295 );
end IWLS2005__des_perf__part1138_behav;
