--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx__part12 is 
  Port (
    pi12: in std_logic;
    n225: inout std_logic
  );
end Cookbook__lane_rx__part12;

architecture Cookbook__lane_rx__part12_behav of Cookbook__lane_rx__part12 is
begin
    n225 <= ( pi12 );
end Cookbook__lane_rx__part12_behav;
