--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2181 is 
  Port (
    lo2250: in std_logic;
    n11549: inout std_logic
  );
end Cookbook__fec_check__part2181;

architecture Cookbook__fec_check__part2181_behav of Cookbook__fec_check__part2181 is
begin
    n11549 <= ( lo2250 );
end Cookbook__fec_check__part2181_behav;
