--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part36 is 
  Port (
    lo00833: in std_logic;
    n4408: inout std_logic
  );
end IWLS2005__ethernet__part36;

architecture IWLS2005__ethernet__part36_behav of IWLS2005__ethernet__part36 is
begin
    n4408 <= ( lo00833 );
end IWLS2005__ethernet__part36_behav;
