--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2688 is 
  Port (
    lo8001: in std_logic;
    n39740_1: inout std_logic
  );
end IWLS2005__des_perf__part2688;

architecture IWLS2005__des_perf__part2688_behav of IWLS2005__des_perf__part2688 is
begin
    n39740_1 <= ( lo8001 );
end IWLS2005__des_perf__part2688_behav;
