--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1863 is 
  Port (
    lo6779: in std_logic;
    n33490: inout std_logic
  );
end IWLS2005__des_perf__part1863;

architecture IWLS2005__des_perf__part1863_behav of IWLS2005__des_perf__part1863 is
begin
    n33490 <= ( lo6779 );
end IWLS2005__des_perf__part1863_behav;
