--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part826 is 
  Port (
    lo6455: in std_logic;
    n30529_1: inout std_logic
  );
end Other__carpat__part826;

architecture Other__carpat__part826_behav of Other__carpat__part826 is
begin
    n30529_1 <= ( lo6455 );
end Other__carpat__part826_behav;
