--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1256 is 
  Port (
    lo7695: in std_logic;
    n42464_1: inout std_logic
  );
end Other__carpat__part1256;

architecture Other__carpat__part1256_behav of Other__carpat__part1256 is
begin
    n42464_1 <= ( lo7695 );
end Other__carpat__part1256_behav;
