--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1628 is 
  Port (
    lo8420: in std_logic;
    n46999_1: inout std_logic
  );
end Other__carpat__part1628;

architecture Other__carpat__part1628_behav of Other__carpat__part1628 is
begin
    n46999_1 <= ( lo8420 );
end Other__carpat__part1628_behav;
