--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part15 is 
  Port (
    pi15: in std_logic;
    n156: inout std_logic
  );
end Cookbook__approx_fp_div__part15;

architecture Cookbook__approx_fp_div__part15_behav of Cookbook__approx_fp_div__part15 is
begin
    n156 <= ( pi15 );
end Cookbook__approx_fp_div__part15_behav;
