--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part112 is 
  Port (
    lo098: in std_logic;
    po168: inout std_logic
  );
end Cookbook__lc_mult_signed__part112;

architecture Cookbook__lc_mult_signed__part112_behav of Cookbook__lc_mult_signed__part112 is
begin
    po168 <= ( lo098 );
end Cookbook__lc_mult_signed__part112_behav;
