--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ternary_sum_nine__part12 is 
  Port (
    lo38: in std_logic;
    po03: inout std_logic
  );
end Cookbook__ternary_sum_nine__part12;

architecture Cookbook__ternary_sum_nine__part12_behav of Cookbook__ternary_sum_nine__part12 is
begin
    po03 <= ( lo38 );
end Cookbook__ternary_sum_nine__part12_behav;
