--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part118 is 
  Port (
    pi173: in std_logic;
    n43935: inout std_logic
  );
end IWLS2005__des_perf__part118;

architecture IWLS2005__des_perf__part118_behav of IWLS2005__des_perf__part118 is
begin
    n43935 <= ( pi173 );
end IWLS2005__des_perf__part118_behav;
