--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part510 is 
  Port (
    lo3159: in std_logic;
    n10019: inout std_logic
  );
end Other__sudoku_check__part510;

architecture Other__sudoku_check__part510_behav of Other__sudoku_check__part510 is
begin
    n10019 <= ( lo3159 );
end Other__sudoku_check__part510_behav;
