--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1468 is 
  Port (
    lo1537: in std_logic;
    n7984: inout std_logic
  );
end Cookbook__fec_check__part1468;

architecture Cookbook__fec_check__part1468_behav of Cookbook__fec_check__part1468 is
begin
    n7984 <= ( lo1537 );
end Cookbook__fec_check__part1468_behav;
