--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part108 is 
  Port (
    lo0323: in std_logic;
    n2874: inout std_logic
  );
end Cookbook__ucrypt__part108;

architecture Cookbook__ucrypt__part108_behav of Cookbook__ucrypt__part108 is
begin
    n2874 <= ( lo0323 );
end Cookbook__ucrypt__part108_behav;
