--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part34 is 
  Port (
    pi34: in std_logic;
    n544208: inout std_logic
  );
end IWLS2005__leon3mp__part34;

architecture IWLS2005__leon3mp__part34_behav of IWLS2005__leon3mp__part34 is
begin
    n544208 <= ( pi34 );
end IWLS2005__leon3mp__part34_behav;
