--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s953__part3 is 
  Port (
    lo08: in std_logic;
    po20: inout std_logic
  );
end ISCAS__s953__part3;

architecture ISCAS__s953__part3_behav of ISCAS__s953__part3 is
begin
    po20 <= ( lo08 );
end ISCAS__s953__part3_behav;
