--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__display_char__part10 is 
  Port (
    pi45: in std_logic;
    n255: inout std_logic
  );
end Cookbook__display_char__part10;

architecture Cookbook__display_char__part10_behav of Cookbook__display_char__part10 is
begin
    n255 <= ( pi45 );
end Cookbook__display_char__part10_behav;
