--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2066 is 
  Port (
    lo4597: in std_logic;
    n27566: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2066;

architecture Other__ucsb_152_tap_fir__part2066_behav of Other__ucsb_152_tap_fir__part2066 is
begin
    n27566 <= ( lo4597 );
end Other__ucsb_152_tap_fir__part2066_behav;
