--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part937 is 
  Port (
    lo10516: in std_logic;
    n68946_1: inout std_logic
  );
end Other__ray__part937;

architecture Other__ray__part937_behav of Other__ray__part937 is
begin
    n68946_1 <= ( lo10516 );
end Other__ray__part937_behav;
