--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part973 is 
  Port (
    lo4342: in std_logic;
    n17199: inout std_logic
  );
end Other__sudoku_check__part973;

architecture Other__sudoku_check__part973_behav of Other__sudoku_check__part973 is
begin
    n17199 <= ( lo4342 );
end Other__sudoku_check__part973_behav;
