--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s967__part8 is 
  Port (
    lo13: in std_logic;
    po07: inout std_logic
  );
end ISCAS__s967__part8;

architecture ISCAS__s967__part8_behav of ISCAS__s967__part8 is
begin
    po07 <= ( lo13 );
end ISCAS__s967__part8_behav;
