--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part83 is 
  Port (
    lo0609: in std_logic;
    n3319: inout std_logic
  );
end LGSynth91__s38417__part83;

architecture LGSynth91__s38417__part83_behav of LGSynth91__s38417__part83 is
begin
    n3319 <= ( lo0609 );
end LGSynth91__s38417__part83_behav;
