--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part38 is 
  Port (
    lo280: in std_logic;
    n1580: inout std_logic
  );
end ISCAS__s15850__part38;

architecture ISCAS__s15850__part38_behav of ISCAS__s15850__part38 is
begin
    n1580 <= ( lo280 );
end ISCAS__s15850__part38_behav;
