--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part31 is 
  Port (
    lo00282: in std_logic;
    po018: inout std_logic
  );
end IWLS2005__ethernet__part31;

architecture IWLS2005__ethernet__part31_behav of IWLS2005__ethernet__part31 is
begin
    po018 <= ( lo00282 );
end IWLS2005__ethernet__part31_behav;
