--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr__part12 is 
  Port (
    lo18: in std_logic;
    n160,po13: inout std_logic
  );
end Cookbook__lfsr__part12;

architecture Cookbook__lfsr__part12_behav of Cookbook__lfsr__part12 is
begin
    n160 <= ( lo18 );
    po13 <= ( lo18 );
end Cookbook__lfsr__part12_behav;
