--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part22 is 
  Port (
    lo00,lo01,lo03,lo04,lo02: in std_logic;
    n284_1: inout std_logic
  );
end Cookbook__pipe_equal__part22;

architecture Cookbook__pipe_equal__part22_behav of Cookbook__pipe_equal__part22 is
signal n336,n337,n338: std_logic;
begin
    n336 <= ( lo00 and lo01 );
    n337 <= ( lo03 and lo04 );
    n338 <= ( lo02 and n337 );
    n284_1 <= ( n336 and n338 );
end Cookbook__pipe_equal__part22_behav;
