--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1212 is 
  Port (
    lo5422: in std_logic;
    n27185_1: inout std_logic
  );
end IWLS2005__des_perf__part1212;

architecture IWLS2005__des_perf__part1212_behav of IWLS2005__des_perf__part1212 is
begin
    n27185_1 <= ( lo5422 );
end IWLS2005__des_perf__part1212_behav;
