--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part779 is 
  Port (
    lo4516: in std_logic;
    n22465: inout std_logic
  );
end IWLS2005__des_perf__part779;

architecture IWLS2005__des_perf__part779_behav of IWLS2005__des_perf__part779 is
begin
    n22465 <= ( lo4516 );
end IWLS2005__des_perf__part779_behav;
