--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part280 is 
  Port (
    lo1121: in std_logic;
    n6095: inout std_logic
  );
end IWLS2005__des_perf__part280;

architecture IWLS2005__des_perf__part280_behav of IWLS2005__des_perf__part280 is
begin
    n6095 <= ( lo1121 );
end IWLS2005__des_perf__part280_behav;
