--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1068 is 
  Port (
    lo5109: in std_logic;
    n25425: inout std_logic
  );
end IWLS2005__des_perf__part1068;

architecture IWLS2005__des_perf__part1068_behav of IWLS2005__des_perf__part1068 is
begin
    n25425 <= ( lo5109 );
end IWLS2005__des_perf__part1068_behav;
