--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part437 is 
  Port (
    lo0506: in std_logic;
    n2829: inout std_logic
  );
end Cookbook__fec_check__part437;

architecture Cookbook__fec_check__part437_behav of Cookbook__fec_check__part437 is
begin
    n2829 <= ( lo0506 );
end Cookbook__fec_check__part437_behav;
