--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1383 is 
  Port (
    lo3181: in std_logic;
    n20491: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1383;

architecture Other__ucsb_152_tap_fir__part1383_behav of Other__ucsb_152_tap_fir__part1383 is
begin
    n20491 <= ( lo3181 );
end Other__ucsb_152_tap_fir__part1383_behav;
