--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1085 is 
  Port (
    lo2539: in std_logic;
    n17256: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1085;

architecture Other__ucsb_152_tap_fir__part1085_behav of Other__ucsb_152_tap_fir__part1085 is
begin
    n17256 <= ( lo2539 );
end Other__ucsb_152_tap_fir__part1085_behav;
