--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part426 is 
  Port (
    lo1537: in std_logic;
    n8944_1: inout std_logic
  );
end Cookbook__ucrypt__part426;

architecture Cookbook__ucrypt__part426_behav of Cookbook__ucrypt__part426 is
begin
    n8944_1 <= ( lo1537 );
end Cookbook__ucrypt__part426_behav;
