--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part557 is 
  Port (
    lo3206: in std_logic;
    n10489: inout std_logic
  );
end Other__sudoku_check__part557;

architecture Other__sudoku_check__part557_behav of Other__sudoku_check__part557 is
begin
    n10489 <= ( lo3206 );
end Other__sudoku_check__part557_behav;
