--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1177 is 
  Port (
    lo1246: in std_logic;
    n6529: inout std_logic
  );
end Cookbook__fec_check__part1177;

architecture Cookbook__fec_check__part1177_behav of Cookbook__fec_check__part1177 is
begin
    n6529 <= ( lo1246 );
end Cookbook__fec_check__part1177_behav;
