--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2415 is 
  Port (
    lo5328: in std_logic;
    n31231_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2415;

architecture Other__ucsb_152_tap_fir__part2415_behav of Other__ucsb_152_tap_fir__part2415 is
begin
    n31231_1 <= ( lo5328 );
end Other__ucsb_152_tap_fir__part2415_behav;
