--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2134 is 
  Port (
    lo4740: in std_logic;
    n28201: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2134;

architecture Other__ucsb_152_tap_fir__part2134_behav of Other__ucsb_152_tap_fir__part2134 is
begin
    n28201 <= ( lo4740 );
end Other__ucsb_152_tap_fir__part2134_behav;
