--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part268 is 
  Port (
    lo1294: in std_logic;
    n6074: inout std_logic
  );
end Other__desperf__part268;

architecture Other__desperf__part268_behav of Other__desperf__part268 is
begin
    n6074 <= ( lo1294 );
end Other__desperf__part268_behav;
