--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1413 is 
  Port (
    lo7863: in std_logic;
    n44194: inout std_logic
  );
end Other__carpat__part1413;

architecture Other__carpat__part1413_behav of Other__carpat__part1413 is
begin
    n44194 <= ( lo7863 );
end Other__carpat__part1413_behav;
