--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1705 is 
  Port (
    lo3855: in std_logic;
    n23856: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1705;

architecture Other__ucsb_152_tap_fir__part1705_behav of Other__ucsb_152_tap_fir__part1705 is
begin
    n23856 <= ( lo3855 );
end Other__ucsb_152_tap_fir__part1705_behav;
