--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part145 is 
  Port (
    lo0214: in std_logic;
    n1369: inout std_logic
  );
end Cookbook__fec_check__part145;

architecture Cookbook__fec_check__part145_behav of Cookbook__fec_check__part145 is
begin
    n1369 <= ( lo0214 );
end Cookbook__fec_check__part145_behav;
