--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1326 is 
  Port (
    lo7771: in std_logic;
    n43674_1: inout std_logic
  );
end Other__carpat__part1326;

architecture Other__carpat__part1326_behav of Other__carpat__part1326 is
begin
    n43674_1 <= ( lo7771 );
end Other__carpat__part1326_behav;
