--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1051 is 
  Port (
    lo2472: in std_logic;
    n16951: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1051;

architecture Other__ucsb_152_tap_fir__part1051_behav of Other__ucsb_152_tap_fir__part1051 is
begin
    n16951 <= ( lo2472 );
end Other__ucsb_152_tap_fir__part1051_behav;
