--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part160 is 
  Port (
    lo0040: in std_logic;
    po40: inout std_logic
  );
end Other__desperf__part160;

architecture Other__desperf__part160_behav of Other__desperf__part160 is
begin
    po40 <= ( lo0040 );
end Other__desperf__part160_behav;
