--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1786 is 
  Port (
    lo8881: in std_logic;
    po316: inout std_logic
  );
end Other__carpat__part1786;

architecture Other__carpat__part1786_behav of Other__carpat__part1786 is
begin
    po316 <= ( lo8881 );
end Other__carpat__part1786_behav;
