--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1022 is 
  Port (
    lo1091: in std_logic;
    n5754: inout std_logic
  );
end Cookbook__fec_check__part1022;

architecture Cookbook__fec_check__part1022_behav of Cookbook__fec_check__part1022 is
begin
    n5754 <= ( lo1091 );
end Cookbook__fec_check__part1022_behav;
