--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2177 is 
  Port (
    lo4815: in std_logic;
    n28661: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2177;

architecture Other__ucsb_152_tap_fir__part2177_behav of Other__ucsb_152_tap_fir__part2177 is
begin
    n28661 <= ( lo4815 );
end Other__ucsb_152_tap_fir__part2177_behav;
