--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part283 is 
  Port (
    lo2932: in std_logic;
    n7749: inout std_logic
  );
end Other__sudoku_check__part283;

architecture Other__sudoku_check__part283_behav of Other__sudoku_check__part283 is
begin
    n7749 <= ( lo2932 );
end Other__sudoku_check__part283_behav;
