--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part255 is 
  Port (
    pi1512: in std_logic;
    n44359_1: inout std_logic
  );
end Other__carpat__part255;

architecture Other__carpat__part255_behav of Other__carpat__part255 is
begin
    n44359_1 <= ( pi1512 );
end Other__carpat__part255_behav;
