--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part173 is 
  Port (
    lo272: in std_logic;
    n872: inout std_logic
  );
end Other__fpu__part173;

architecture Other__fpu__part173_behav of Other__fpu__part173 is
begin
    n872 <= ( lo272 );
end Other__fpu__part173_behav;
