--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1812 is 
  Port (
    lo4111: in std_logic;
    n25001: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1812;

architecture Other__ucsb_152_tap_fir__part1812_behav of Other__ucsb_152_tap_fir__part1812 is
begin
    n25001 <= ( lo4111 );
end Other__ucsb_152_tap_fir__part1812_behav;
