--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1254 is 
  Port (
    lo4623: in std_logic;
    n18604: inout std_logic
  );
end Other__sudoku_check__part1254;

architecture Other__sudoku_check__part1254_behav of Other__sudoku_check__part1254 is
begin
    n18604 <= ( lo4623 );
end Other__sudoku_check__part1254_behav;
