--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part81 is 
  Port (
    lo533: in std_logic;
    n2843: inout std_logic
  );
end Cookbook__lane_tx__part81;

architecture Cookbook__lane_tx__part81_behav of Cookbook__lane_tx__part81 is
begin
    n2843 <= ( lo533 );
end Cookbook__lane_tx__part81_behav;
