--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part394 is 
  Port (
    lo0008: in std_logic;
    po008: inout std_logic
  );
end Other__carpat__part394;

architecture Other__carpat__part394_behav of Other__carpat__part394 is
begin
    po008 <= ( lo0008 );
end Other__carpat__part394_behav;
