--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part157 is 
  Port (
    lo143: in std_logic;
    po123: inout std_logic
  );
end Cookbook__lc_mult_signed__part157;

architecture Cookbook__lc_mult_signed__part157_behav of Cookbook__lc_mult_signed__part157 is
begin
    po123 <= ( lo143 );
end Cookbook__lc_mult_signed__part157_behav;
