--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part618 is 
  Port (
    lo0687: in std_logic;
    n3734: inout std_logic
  );
end Cookbook__fec_check__part618;

architecture Cookbook__fec_check__part618_behav of Cookbook__fec_check__part618 is
begin
    n3734 <= ( lo0687 );
end Cookbook__fec_check__part618_behav;
