--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1264 is 
  Port (
    lo5553: in std_logic;
    n27915_1: inout std_logic
  );
end IWLS2005__des_perf__part1264;

architecture IWLS2005__des_perf__part1264_behav of IWLS2005__des_perf__part1264 is
begin
    n27915_1 <= ( lo5553 );
end IWLS2005__des_perf__part1264_behav;
