--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1215 is 
  Port (
    lo7631: in std_logic;
    n42044_1: inout std_logic
  );
end Other__carpat__part1215;

architecture Other__carpat__part1215_behav of Other__carpat__part1215 is
begin
    n42044_1 <= ( lo7631 );
end Other__carpat__part1215_behav;
