--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part72 is 
  Port (
    lo0141: in std_logic;
    n1004: inout std_logic
  );
end Cookbook__fec_check__part72;

architecture Cookbook__fec_check__part72_behav of Cookbook__fec_check__part72 is
begin
    n1004 <= ( lo0141 );
end Cookbook__fec_check__part72_behav;
