--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part131 is 
  Port (
    lo3319: in std_logic;
    n16939: inout std_logic
  );
end IWLS2005__pci_bridge32__part131;

architecture IWLS2005__pci_bridge32__part131_behav of IWLS2005__pci_bridge32__part131 is
begin
    n16939 <= ( lo3319 );
end IWLS2005__pci_bridge32__part131_behav;
