--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part822 is 
  Port (
    lo0891: in std_logic;
    n4754: inout std_logic
  );
end Cookbook__fec_check__part822;

architecture Cookbook__fec_check__part822_behav of Cookbook__fec_check__part822 is
begin
    n4754 <= ( lo0891 );
end Cookbook__fec_check__part822_behav;
