--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1201 is 
  Port (
    lo1270: in std_logic;
    n6649: inout std_logic
  );
end Cookbook__fec_check__part1201;

architecture Cookbook__fec_check__part1201_behav of Cookbook__fec_check__part1201 is
begin
    n6649 <= ( lo1270 );
end Cookbook__fec_check__part1201_behav;
