--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1642 is 
  Port (
    lo8434: in std_logic;
    n47069_1: inout std_logic
  );
end Other__carpat__part1642;

architecture Other__carpat__part1642_behav of Other__carpat__part1642 is
begin
    n47069_1 <= ( lo8434 );
end Other__carpat__part1642_behav;
