--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part13 is 
  Port (
    pi013: in std_logic;
    n44195_1: inout std_logic
  );
end IWLS2005__des_perf__part13;

architecture IWLS2005__des_perf__part13_behav of IWLS2005__des_perf__part13 is
begin
    n44195_1 <= ( pi013 );
end IWLS2005__des_perf__part13_behav;
