--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1614 is 
  Port (
    lo3658: in std_logic;
    n22796: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1614;

architecture Other__ucsb_152_tap_fir__part1614_behav of Other__ucsb_152_tap_fir__part1614 is
begin
    n22796 <= ( lo3658 );
end Other__ucsb_152_tap_fir__part1614_behav;
