--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part747 is 
  Port (
    lo0816: in std_logic;
    n4379: inout std_logic
  );
end Cookbook__fec_check__part747;

architecture Cookbook__fec_check__part747_behav of Cookbook__fec_check__part747 is
begin
    n4379 <= ( lo0816 );
end Cookbook__fec_check__part747_behav;
