--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part281 is 
  Port (
    lo1490: in std_logic;
    n7054_1: inout std_logic
  );
end Other__desperf__part281;

architecture Other__desperf__part281_behav of Other__desperf__part281 is
begin
    n7054_1 <= ( lo1490 );
end Other__desperf__part281_behav;
