--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part420 is 
  Port (
    lo2279: in std_logic;
    n11195: inout std_logic
  );
end IWLS2005__des_perf__part420;

architecture IWLS2005__des_perf__part420_behav of IWLS2005__des_perf__part420 is
begin
    n11195 <= ( lo2279 );
end IWLS2005__des_perf__part420_behav;
