--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part116 is 
  Port (
    lo0331: in std_logic;
    n2914: inout std_logic
  );
end Cookbook__ucrypt__part116;

architecture Cookbook__ucrypt__part116_behav of Cookbook__ucrypt__part116 is
begin
    n2914 <= ( lo0331 );
end Cookbook__ucrypt__part116_behav;
