--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1080 is 
  Port (
    lo1149: in std_logic;
    n6044: inout std_logic
  );
end Cookbook__fec_check__part1080;

architecture Cookbook__fec_check__part1080_behav of Cookbook__fec_check__part1080 is
begin
    n6044 <= ( lo1149 );
end Cookbook__fec_check__part1080_behav;
