--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part74 is 
  Port (
    lo251: in std_logic;
    n1553: inout std_logic
  );
end ISCAS__s13207__part74;

architecture ISCAS__s13207__part74_behav of ISCAS__s13207__part74 is
begin
    n1553 <= ( lo251 );
end ISCAS__s13207__part74_behav;
