--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1816 is 
  Port (
    lo1885: in std_logic;
    n9724: inout std_logic
  );
end Cookbook__fec_check__part1816;

architecture Cookbook__fec_check__part1816_behav of Cookbook__fec_check__part1816 is
begin
    n9724 <= ( lo1885 );
end Cookbook__fec_check__part1816_behav;
