--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1015 is 
  Port (
    lo1084: in std_logic;
    n5719: inout std_logic
  );
end Cookbook__fec_check__part1015;

architecture Cookbook__fec_check__part1015_behav of Cookbook__fec_check__part1015 is
begin
    n5719 <= ( lo1084 );
end Cookbook__fec_check__part1015_behav;
