--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part29 is 
  Port (
    lo00278: in std_logic;
    po022: inout std_logic
  );
end IWLS2005__ethernet__part29;

architecture IWLS2005__ethernet__part29_behav of IWLS2005__ethernet__part29 is
begin
    po022 <= ( lo00278 );
end IWLS2005__ethernet__part29_behav;
