--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part563 is 
  Port (
    lo2088: in std_logic;
    n11534_1: inout std_logic
  );
end Cookbook__ucrypt__part563;

architecture Cookbook__ucrypt__part563_behav of Cookbook__ucrypt__part563 is
begin
    n11534_1 <= ( lo2088 );
end Cookbook__ucrypt__part563_behav;
