--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part575 is 
  Port (
    lo3521: in std_logic;
    n16764: inout std_logic
  );
end Other__carpat__part575;

architecture Other__carpat__part575_behav of Other__carpat__part575 is
begin
    n16764 <= ( lo3521 );
end Other__carpat__part575_behav;
