--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part56 is 
  Port (
    lo0331: in std_logic;
    n1929: inout std_logic
  );
end LGSynth91__s38417__part56;

architecture LGSynth91__s38417__part56_behav of LGSynth91__s38417__part56 is
begin
    n1929 <= ( lo0331 );
end LGSynth91__s38417__part56_behav;
