--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part244 is 
  Port (
    lo0593: in std_logic;
    n7446: inout std_logic
  );
end Other__ucsb_152_tap_fir__part244;

architecture Other__ucsb_152_tap_fir__part244_behav of Other__ucsb_152_tap_fir__part244 is
begin
    n7446 <= ( lo0593 );
end Other__ucsb_152_tap_fir__part244_behav;
