--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part346 is 
  Port (
    pi1678: in std_logic;
    n47974_1: inout std_logic
  );
end Other__carpat__part346;

architecture Other__carpat__part346_behav of Other__carpat__part346 is
begin
    n47974_1 <= ( pi1678 );
end Other__carpat__part346_behav;
