--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part863 is 
  Port (
    lo06622: in std_logic;
    n49446: inout std_logic
  );
end Other__ray__part863;

architecture Other__ray__part863_behav of Other__ray__part863 is
begin
    n49446 <= ( lo06622 );
end Other__ray__part863_behav;
