--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part835 is 
  Port (
    lo06594: in std_logic;
    n49306_1: inout std_logic
  );
end Other__ray__part835;

architecture Other__ray__part835_behav of Other__ray__part835 is
begin
    n49306_1 <= ( lo06594 );
end Other__ray__part835_behav;
