--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__min_max__part1 is 
  Port (
    lo00: in std_logic;
    po15: inout std_logic
  );
end Cookbook__min_max__part1;

architecture Cookbook__min_max__part1_behav of Cookbook__min_max__part1 is
begin
    po15 <= ( lo00 );
end Cookbook__min_max__part1_behav;
