--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part47 is 
  Port (
    lo46: in std_logic;
    po46: inout std_logic
  );
end Other__idxlat03n_m12__part47;

architecture Other__idxlat03n_m12__part47_behav of Other__idxlat03n_m12__part47 is
begin
    po46 <= ( lo46 );
end Other__idxlat03n_m12__part47_behav;
