--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part175 is 
  Port (
    lo0055: in std_logic;
    po55: inout std_logic
  );
end Other__desperf__part175;

architecture Other__desperf__part175_behav of Other__desperf__part175 is
begin
    po55 <= ( lo0055 );
end Other__desperf__part175_behav;
