--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part100 is 
  Port (
    lo0671: in std_logic;
    po005: inout std_logic
  );
end IWLS2005__mem_ctrl__part100;

architecture IWLS2005__mem_ctrl__part100_behav of IWLS2005__mem_ctrl__part100 is
begin
    po005 <= ( lo0671 );
end IWLS2005__mem_ctrl__part100_behav;
