--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part268 is 
  Port (
    lo1053: in std_logic;
    n5815: inout std_logic
  );
end IWLS2005__des_perf__part268;

architecture IWLS2005__des_perf__part268_behav of IWLS2005__des_perf__part268 is
begin
    n5815 <= ( lo1053 );
end IWLS2005__des_perf__part268_behav;
