--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1203 is 
  Port (
    lo4572: in std_logic;
    n18349: inout std_logic
  );
end Other__sudoku_check__part1203;

architecture Other__sudoku_check__part1203_behav of Other__sudoku_check__part1203 is
begin
    n18349 <= ( lo4572 );
end Other__sudoku_check__part1203_behav;
