--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part606 is 
  Port (
    lo06087: in std_logic;
    n38381: inout std_logic
  );
end Other__ray__part606;

architecture Other__ray__part606_behav of Other__ray__part606 is
begin
    n38381 <= ( lo06087 );
end Other__ray__part606_behav;
