--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part568 is 
  Port (
    lo4172: in std_logic;
    n21040: inout std_logic
  );
end IWLS2005__des_perf__part568;

architecture IWLS2005__des_perf__part568_behav of IWLS2005__des_perf__part568 is
begin
    n21040 <= ( lo4172 );
end IWLS2005__des_perf__part568_behav;
