--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2452 is 
  Port (
    lo5392: in std_logic;
    n31561_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2452;

architecture Other__ucsb_152_tap_fir__part2452_behav of Other__ucsb_152_tap_fir__part2452 is
begin
    n31561_1 <= ( lo5392 );
end Other__ucsb_152_tap_fir__part2452_behav;
