--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ac97_ctrl__part16 is 
  Port (
    pi18: in std_logic;
    n11073_1: inout std_logic
  );
end IWLS2005__ac97_ctrl__part16;

architecture IWLS2005__ac97_ctrl__part16_behav of IWLS2005__ac97_ctrl__part16 is
begin
    n11073_1 <= ( pi18 );
end IWLS2005__ac97_ctrl__part16_behav;
