--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part455 is 
  Port (
    lo3104: in std_logic;
    n9469: inout std_logic
  );
end Other__sudoku_check__part455;

architecture Other__sudoku_check__part455_behav of Other__sudoku_check__part455 is
begin
    n9469 <= ( lo3104 );
end Other__sudoku_check__part455_behav;
