--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part281 is 
  Port (
    lo0350: in std_logic;
    n2049: inout std_logic
  );
end Cookbook__fec_check__part281;

architecture Cookbook__fec_check__part281_behav of Cookbook__fec_check__part281 is
begin
    n2049 <= ( lo0350 );
end Cookbook__fec_check__part281_behav;
