--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part155 is 
  Port (
    lo1027: in std_logic;
    n4959_1: inout std_logic
  );
end IWLS93__s38417__part155;

architecture IWLS93__s38417__part155_behav of IWLS93__s38417__part155 is
begin
    n4959_1 <= ( lo1027 );
end IWLS93__s38417__part155_behav;
