--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part299 is 
  Port (
    lo2948: in std_logic;
    n7909: inout std_logic
  );
end Other__sudoku_check__part299;

architecture Other__sudoku_check__part299_behav of Other__sudoku_check__part299 is
begin
    n7909 <= ( lo2948 );
end Other__sudoku_check__part299_behav;
