--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part976 is 
  Port (
    lo4939: in std_logic;
    n24680: inout std_logic
  );
end IWLS2005__des_perf__part976;

architecture IWLS2005__des_perf__part976_behav of IWLS2005__des_perf__part976 is
begin
    n24680 <= ( lo4939 );
end IWLS2005__des_perf__part976_behav;
