--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part6 is 
  Port (
    lo0460: in std_logic;
    n3249: inout std_logic
  );
end Other__sudoku_check__part6;

architecture Other__sudoku_check__part6_behav of Other__sudoku_check__part6 is
begin
    n3249 <= ( lo0460 );
end Other__sudoku_check__part6_behav;
