--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part399 is 
  Port (
    lo2237: in std_logic;
    n11590: inout std_logic
  );
end IWLS2005__des_perf__part399;

architecture IWLS2005__des_perf__part399_behav of IWLS2005__des_perf__part399 is
begin
    n11590 <= ( lo2237 );
end IWLS2005__des_perf__part399_behav;
