--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1726 is 
  Port (
    lo8766: in std_logic;
    po225: inout std_logic
  );
end Other__carpat__part1726;

architecture Other__carpat__part1726_behav of Other__carpat__part1726 is
begin
    po225 <= ( lo8766 );
end Other__carpat__part1726_behav;
