--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part499 is 
  Port (
    lo3148: in std_logic;
    n9909: inout std_logic
  );
end Other__sudoku_check__part499;

architecture Other__sudoku_check__part499_behav of Other__sudoku_check__part499 is
begin
    n9909 <= ( lo3148 );
end Other__sudoku_check__part499_behav;
