--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2272 is 
  Port (
    lo2372: in std_logic;
    n12159: inout std_logic
  );
end Cookbook__fec_check__part2272;

architecture Cookbook__fec_check__part2272_behav of Cookbook__fec_check__part2272 is
begin
    n12159 <= ( lo2372 );
end Cookbook__fec_check__part2272_behav;
