--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2065 is 
  Port (
    lo4596: in std_logic;
    n27561: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2065;

architecture Other__ucsb_152_tap_fir__part2065_behav of Other__ucsb_152_tap_fir__part2065 is
begin
    n27561 <= ( lo4596 );
end Other__ucsb_152_tap_fir__part2065_behav;
