--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part214 is 
  Port (
    lo0103: in std_logic;
    n620: inout std_logic
  );
end IWLS2005__des_perf__part214;

architecture IWLS2005__des_perf__part214_behav of IWLS2005__des_perf__part214 is
begin
    n620 <= ( lo0103 );
end IWLS2005__des_perf__part214_behav;
