--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2148 is 
  Port (
    lo2217: in std_logic;
    n11384: inout std_logic
  );
end Cookbook__fec_check__part2148;

architecture Cookbook__fec_check__part2148_behav of Cookbook__fec_check__part2148 is
begin
    n11384 <= ( lo2217 );
end Cookbook__fec_check__part2148_behav;
