--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part638 is 
  Port (
    lo4284: in std_logic;
    n21680: inout std_logic
  );
end IWLS2005__des_perf__part638;

architecture IWLS2005__des_perf__part638_behav of IWLS2005__des_perf__part638 is
begin
    n21680 <= ( lo4284 );
end IWLS2005__des_perf__part638_behav;
