--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part44 is 
  Port (
    lo0002: in std_logic;
    po123: inout std_logic
  );
end IWLS2005__mem_ctrl__part44;

architecture IWLS2005__mem_ctrl__part44_behav of IWLS2005__mem_ctrl__part44 is
begin
    po123 <= ( lo0002 );
end IWLS2005__mem_ctrl__part44_behav;
