--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part414 is 
  Port (
    lo3063: in std_logic;
    n9059: inout std_logic
  );
end Other__sudoku_check__part414;

architecture Other__sudoku_check__part414_behav of Other__sudoku_check__part414 is
begin
    n9059 <= ( lo3063 );
end Other__sudoku_check__part414_behav;
