--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part819 is 
  Port (
    lo4612: in std_logic;
    n22920: inout std_logic
  );
end IWLS2005__des_perf__part819;

architecture IWLS2005__des_perf__part819_behav of IWLS2005__des_perf__part819 is
begin
    n22920 <= ( lo4612 );
end IWLS2005__des_perf__part819_behav;
