--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part159 is 
  Port (
    lo256: in std_logic;
    n797: inout std_logic
  );
end Other__fpu__part159;

architecture Other__fpu__part159_behav of Other__fpu__part159 is
begin
    n797 <= ( lo256 );
end Other__fpu__part159_behav;
