--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2086 is 
  Port (
    lo4646: in std_logic;
    n27816: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2086;

architecture Other__ucsb_152_tap_fir__part2086_behav of Other__ucsb_152_tap_fir__part2086 is
begin
    n27816 <= ( lo4646 );
end Other__ucsb_152_tap_fir__part2086_behav;
