--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1933 is 
  Port (
    lo2002: in std_logic;
    n10309: inout std_logic
  );
end Cookbook__fec_check__part1933;

architecture Cookbook__fec_check__part1933_behav of Cookbook__fec_check__part1933 is
begin
    n10309 <= ( lo2002 );
end Cookbook__fec_check__part1933_behav;
