--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part596 is 
  Port (
    lo4206: in std_logic;
    n21235: inout std_logic
  );
end IWLS2005__des_perf__part596;

architecture IWLS2005__des_perf__part596_behav of IWLS2005__des_perf__part596 is
begin
    n21235 <= ( lo4206 );
end IWLS2005__des_perf__part596_behav;
