--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part816 is 
  Port (
    lo6429: in std_logic;
    n30409: inout std_logic
  );
end Other__carpat__part816;

architecture Other__carpat__part816_behav of Other__carpat__part816 is
begin
    n30409 <= ( lo6429 );
end Other__carpat__part816_behav;
