--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_22__part26 is 
  Port (
    lo67: in std_logic;
    po01: inout std_logic
  );
end Cookbook__gearbox_20_22__part26;

architecture Cookbook__gearbox_20_22__part26_behav of Cookbook__gearbox_20_22__part26 is
begin
    po01 <= ( lo67 );
end Cookbook__gearbox_20_22__part26_behav;
