--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1445 is 
  Port (
    lo1514: in std_logic;
    n7869: inout std_logic
  );
end Cookbook__fec_check__part1445;

architecture Cookbook__fec_check__part1445_behav of Cookbook__fec_check__part1445 is
begin
    n7869 <= ( lo1514 );
end Cookbook__fec_check__part1445_behav;
