--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1087 is 
  Port (
    lo4456: in std_logic;
    n17769: inout std_logic
  );
end Other__sudoku_check__part1087;

architecture Other__sudoku_check__part1087_behav of Other__sudoku_check__part1087 is
begin
    n17769 <= ( lo4456 );
end Other__sudoku_check__part1087_behav;
