--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part150 is 
  Port (
    lo0219: in std_logic;
    n1394: inout std_logic
  );
end Cookbook__fec_check__part150;

architecture Cookbook__fec_check__part150_behav of Cookbook__fec_check__part150 is
begin
    n1394 <= ( lo0219 );
end Cookbook__fec_check__part150_behav;
