--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part314 is 
  Port (
    lo1089: in std_logic;
    n6704: inout std_logic
  );
end Cookbook__ucrypt__part314;

architecture Cookbook__ucrypt__part314_behav of Cookbook__ucrypt__part314 is
begin
    n6704 <= ( lo1089 );
end Cookbook__ucrypt__part314_behav;
