--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part189 is 
  Port (
    lo175: in std_logic;
    po091: inout std_logic
  );
end Cookbook__lc_mult_signed__part189;

architecture Cookbook__lc_mult_signed__part189_behav of Cookbook__lc_mult_signed__part189 is
begin
    po091 <= ( lo175 );
end Cookbook__lc_mult_signed__part189_behav;
