--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part25 is 
  Port (
    lo088: in std_logic;
    po048: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part25;

architecture Cookbook__soft_ecc_ram_64bit__part25_behav of Cookbook__soft_ecc_ram_64bit__part25 is
begin
    po048 <= ( lo088 );
end Cookbook__soft_ecc_ram_64bit__part25_behav;
