--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1545 is 
  Port (
    lo5789,lo5790,lo5791,lo5792: in std_logic;
    n27539_1,n29439_1,n29624_1,n29804,n29984_1,n30164,n30344,n30524,n30704: inout std_logic
  );
end Other__sudoku_check__part1545;

architecture Other__sudoku_check__part1545_behav of Other__sudoku_check__part1545 is
begin
    n27539_1 <= ( lo5789 and not lo5790 and not lo5791 and not lo5792 );
    n29439_1 <= ( lo5789 and not lo5790 and not lo5791 and lo5792 );
    n29624_1 <= ( not lo5789 and not lo5790 and not lo5791 and lo5792 );
    n29804 <= ( lo5789 and lo5790 and lo5791 and not lo5792 );
    n29984_1 <= ( not lo5789 and lo5790 and lo5791 and not lo5792 );
    n30164 <= ( lo5789 and not lo5790 and lo5791 and not lo5792 );
    n30344 <= ( not lo5789 and not lo5790 and lo5791 and not lo5792 );
    n30524 <= ( lo5789 and lo5790 and not lo5791 and not lo5792 );
    n30704 <= ( not lo5789 and lo5790 and not lo5791 and not lo5792 );
end Other__sudoku_check__part1545_behav;
