--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part464 is 
  Port (
    lo0533: in std_logic;
    n2964: inout std_logic
  );
end Cookbook__fec_check__part464;

architecture Cookbook__fec_check__part464_behav of Cookbook__fec_check__part464 is
begin
    n2964 <= ( lo0533 );
end Cookbook__fec_check__part464_behav;
