--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1541 is 
  Port (
    lo1610: in std_logic;
    n8349: inout std_logic
  );
end Cookbook__fec_check__part1541;

architecture Cookbook__fec_check__part1541_behav of Cookbook__fec_check__part1541 is
begin
    n8349 <= ( lo1610 );
end Cookbook__fec_check__part1541_behav;
