--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part414 is 
  Port (
    lo05886: in std_logic;
    po1303,po1337: inout std_logic
  );
end Other__ray__part414;

architecture Other__ray__part414_behav of Other__ray__part414 is
begin
    po1303 <= ( lo05886 );
    po1337 <= ( lo05886 );
end Other__ray__part414_behav;
