--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1034 is 
  Port (
    lo4403: in std_logic;
    n17504: inout std_logic
  );
end Other__sudoku_check__part1034;

architecture Other__sudoku_check__part1034_behav of Other__sudoku_check__part1034 is
begin
    n17504 <= ( lo4403 );
end Other__sudoku_check__part1034_behav;
