--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part601 is 
  Port (
    lo0670: in std_logic;
    n3649: inout std_logic
  );
end Cookbook__fec_check__part601;

architecture Cookbook__fec_check__part601_behav of Cookbook__fec_check__part601 is
begin
    n3649 <= ( lo0670 );
end Cookbook__fec_check__part601_behav;
