--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1387 is 
  Port (
    lo7837: in std_logic;
    n44064_1: inout std_logic
  );
end Other__carpat__part1387;

architecture Other__carpat__part1387_behav of Other__carpat__part1387 is
begin
    n44064_1 <= ( lo7837 );
end Other__carpat__part1387_behav;
