--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1201 is 
  Port (
    lo5410: in std_logic;
    n27050_1: inout std_logic
  );
end IWLS2005__des_perf__part1201;

architecture IWLS2005__des_perf__part1201_behav of IWLS2005__des_perf__part1201 is
begin
    n27050_1 <= ( lo5410 );
end IWLS2005__des_perf__part1201_behav;
