--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1148 is 
  Port (
    lo4517: in std_logic;
    n18074: inout std_logic
  );
end Other__sudoku_check__part1148;

architecture Other__sudoku_check__part1148_behav of Other__sudoku_check__part1148 is
begin
    n18074 <= ( lo4517 );
end Other__sudoku_check__part1148_behav;
