--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part25 is 
  Port (
    pi25: in std_logic;
    n544108: inout std_logic
  );
end IWLS2005__leon3mp__part25;

architecture IWLS2005__leon3mp__part25_behav of IWLS2005__leon3mp__part25 is
begin
    n544108 <= ( pi25 );
end IWLS2005__leon3mp__part25_behav;
