--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1004 is 
  Port (
    lo2361: in std_logic;
    n16341: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1004;

architecture Other__ucsb_152_tap_fir__part1004_behav of Other__ucsb_152_tap_fir__part1004 is
begin
    n16341 <= ( lo2361 );
end Other__ucsb_152_tap_fir__part1004_behav;
