--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1182 is 
  Port (
    lo4551: in std_logic;
    n18244: inout std_logic
  );
end Other__sudoku_check__part1182;

architecture Other__sudoku_check__part1182_behav of Other__sudoku_check__part1182 is
begin
    n18244 <= ( lo4551 );
end Other__sudoku_check__part1182_behav;
