--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1619 is 
  Port (
    lo6288: in std_logic;
    n31240: inout std_logic
  );
end IWLS2005__des_perf__part1619;

architecture IWLS2005__des_perf__part1619_behav of IWLS2005__des_perf__part1619 is
begin
    n31240 <= ( lo6288 );
end IWLS2005__des_perf__part1619_behav;
