--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1103 is 
  Port (
    lo2557: in std_logic;
    n17346: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1103;

architecture Other__ucsb_152_tap_fir__part1103_behav of Other__ucsb_152_tap_fir__part1103 is
begin
    n17346 <= ( lo2557 );
end Other__ucsb_152_tap_fir__part1103_behav;
