--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1315 is 
  Port (
    lo3035: in std_logic;
    n19671: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1315;

architecture Other__ucsb_152_tap_fir__part1315_behav of Other__ucsb_152_tap_fir__part1315 is
begin
    n19671 <= ( lo3035 );
end Other__ucsb_152_tap_fir__part1315_behav;
