--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part898 is 
  Port (
    lo4267: in std_logic;
    n16824: inout std_logic
  );
end Other__sudoku_check__part898;

architecture Other__sudoku_check__part898_behav of Other__sudoku_check__part898 is
begin
    n16824 <= ( lo4267 );
end Other__sudoku_check__part898_behav;
