--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part7 is 
  Port (
    lo72: in std_logic;
    po13: inout std_logic
  );
end Cookbook__gearbox_67_20__part7;

architecture Cookbook__gearbox_67_20__part7_behav of Cookbook__gearbox_67_20__part7 is
begin
    po13 <= ( lo72 );
end Cookbook__gearbox_67_20__part7_behav;
