--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part177 is 
  Port (
    lo276: in std_logic;
    n892: inout std_logic
  );
end Other__fpu__part177;

architecture Other__fpu__part177_behav of Other__fpu__part177 is
begin
    n892 <= ( lo276 );
end Other__fpu__part177_behav;
