--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part420 is 
  Port (
    lo0489: in std_logic;
    n2744: inout std_logic
  );
end Cookbook__fec_check__part420;

architecture Cookbook__fec_check__part420_behav of Cookbook__fec_check__part420 is
begin
    n2744 <= ( lo0489 );
end Cookbook__fec_check__part420_behav;
