--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1175 is 
  Port (
    lo1244: in std_logic;
    n6519: inout std_logic
  );
end Cookbook__fec_check__part1175;

architecture Cookbook__fec_check__part1175_behav of Cookbook__fec_check__part1175 is
begin
    n6519 <= ( lo1244 );
end Cookbook__fec_check__part1175_behav;
