--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part9 is 
  Port (
    pi56: in std_logic;
    n488250_1,n488265_1: inout std_logic
  );
end IWLS2005__netcard__part9;

architecture IWLS2005__netcard__part9_behav of IWLS2005__netcard__part9 is
begin
    n488250_1 <= ( pi56 );
    n488265_1 <= ( pi56 );
end IWLS2005__netcard__part9_behav;
