--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part408 is 
  Port (
    lo3057: in std_logic;
    n8999: inout std_logic
  );
end Other__sudoku_check__part408;

architecture Other__sudoku_check__part408_behav of Other__sudoku_check__part408 is
begin
    n8999 <= ( lo3057 );
end Other__sudoku_check__part408_behav;
