--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part99 is 
  Port (
    lo3234: in std_logic;
    n16639: inout std_logic
  );
end IWLS2005__pci_bridge32__part99;

architecture IWLS2005__pci_bridge32__part99_behav of IWLS2005__pci_bridge32__part99 is
begin
    n16639 <= ( lo3234 );
end IWLS2005__pci_bridge32__part99_behav;
