--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part314 is 
  Port (
    lo2963: in std_logic;
    n8059: inout std_logic
  );
end Other__sudoku_check__part314;

architecture Other__sudoku_check__part314_behav of Other__sudoku_check__part314 is
begin
    n8059 <= ( lo2963 );
end Other__sudoku_check__part314_behav;
