--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part256 is 
  Port (
    lo1133: in std_logic;
    n5299: inout std_logic
  );
end Other__desperf__part256;

architecture Other__desperf__part256_behav of Other__desperf__part256 is
begin
    n5299 <= ( lo1133 );
end Other__desperf__part256_behav;
