--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part14 is 
  Port (
    pi014: in std_logic;
    n9719_1: inout std_logic
  );
end Other__desperf__part14;

architecture Other__desperf__part14_behav of Other__desperf__part14 is
begin
    n9719_1 <= ( pi014 );
end Other__desperf__part14_behav;
