--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part158 is 
  Port (
    lo0548: in std_logic;
    n5250: inout std_logic
  );
end Other__fp_operators__part158;

architecture Other__fp_operators__part158_behav of Other__fp_operators__part158 is
begin
    n5250 <= ( lo0548 );
end Other__fp_operators__part158_behav;
