--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part21 is 
  Port (
    lo468: in std_logic;
    po03: inout std_logic
  );
end Cookbook__lane_tx__part21;

architecture Cookbook__lane_tx__part21_behav of Cookbook__lane_tx__part21 is
begin
    po03 <= ( lo468 );
end Cookbook__lane_tx__part21_behav;
