--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part900 is 
  Port (
    lo09286: in std_logic;
    n59531: inout std_logic
  );
end Other__ray__part900;

architecture Other__ray__part900_behav of Other__ray__part900 is
begin
    n59531 <= ( lo09286 );
end Other__ray__part900_behav;
