--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part436 is 
  Port (
    lo0505: in std_logic;
    n2824: inout std_logic
  );
end Cookbook__fec_check__part436;

architecture Cookbook__fec_check__part436_behav of Cookbook__fec_check__part436 is
begin
    n2824 <= ( lo0505 );
end Cookbook__fec_check__part436_behav;
