--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1625 is 
  Port (
    lo1694: in std_logic;
    n8769: inout std_logic
  );
end Cookbook__fec_check__part1625;

architecture Cookbook__fec_check__part1625_behav of Cookbook__fec_check__part1625 is
begin
    n8769 <= ( lo1694 );
end Cookbook__fec_check__part1625_behav;
