--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part73 is 
  Port (
    lo307: in std_logic;
    po039: inout std_logic
  );
end IWLS2005__aes_core__part73;

architecture IWLS2005__aes_core__part73_behav of IWLS2005__aes_core__part73 is
begin
    po039 <= ( lo307 );
end IWLS2005__aes_core__part73_behav;
