--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part244 is 
  Port (
    lo230: in std_logic;
    po036: inout std_logic
  );
end Cookbook__lc_mult_signed__part244;

architecture Cookbook__lc_mult_signed__part244_behav of Cookbook__lc_mult_signed__part244 is
begin
    po036 <= ( lo230 );
end Cookbook__lc_mult_signed__part244_behav;
