--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part984 is 
  Port (
    lo7039: in std_logic;
    n37294: inout std_logic
  );
end Other__carpat__part984;

architecture Other__carpat__part984_behav of Other__carpat__part984 is
begin
    n37294 <= ( lo7039 );
end Other__carpat__part984_behav;
