--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1041 is 
  Port (
    lo2434: in std_logic;
    n16751: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1041;

architecture Other__ucsb_152_tap_fir__part1041_behav of Other__ucsb_152_tap_fir__part1041 is
begin
    n16751 <= ( lo2434 );
end Other__ucsb_152_tap_fir__part1041_behav;
