--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part53 is 
  Port (
    lo00928: in std_logic;
    po081: inout std_logic
  );
end IWLS2005__ethernet__part53;

architecture IWLS2005__ethernet__part53_behav of IWLS2005__ethernet__part53 is
begin
    po081 <= ( lo00928 );
end IWLS2005__ethernet__part53_behav;
