--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1599 is 
  Port (
    lo3622: in std_logic;
    n22691: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1599;

architecture Other__ucsb_152_tap_fir__part1599_behav of Other__ucsb_152_tap_fir__part1599 is
begin
    n22691 <= ( lo3622 );
end Other__ucsb_152_tap_fir__part1599_behav;
