--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part585 is 
  Port (
    lo3234: in std_logic;
    n10769: inout std_logic
  );
end Other__sudoku_check__part585;

architecture Other__sudoku_check__part585_behav of Other__sudoku_check__part585 is
begin
    n10769 <= ( lo3234 );
end Other__sudoku_check__part585_behav;
