--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part205 is 
  Port (
    lo0908: in std_logic;
    n6325: inout std_logic
  );
end Other__fp_operators__part205;

architecture Other__fp_operators__part205_behav of Other__fp_operators__part205 is
begin
    n6325 <= ( lo0908 );
end Other__fp_operators__part205_behav;
