--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part297 is 
  Port (
    lo1149: in std_logic;
    n6125: inout std_logic
  );
end IWLS2005__des_perf__part297;

architecture IWLS2005__des_perf__part297_behav of IWLS2005__des_perf__part297 is
begin
    n6125 <= ( lo1149 );
end IWLS2005__des_perf__part297_behav;
