--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part27 is 
  Port (
    lo032: in std_logic;
    n862: inout std_logic
  );
end Cookbook__gearbox_67_40__part27;

architecture Cookbook__gearbox_67_40__part27_behav of Cookbook__gearbox_67_40__part27 is
begin
    n862 <= ( lo032 );
end Cookbook__gearbox_67_40__part27_behav;
