--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1039 is 
  Port (
    lo4408: in std_logic;
    n17529: inout std_logic
  );
end Other__sudoku_check__part1039;

architecture Other__sudoku_check__part1039_behav of Other__sudoku_check__part1039 is
begin
    n17529 <= ( lo4408 );
end Other__sudoku_check__part1039_behav;
