--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part153 is 
  Port (
    lo036: in std_logic;
    po039: inout std_logic
  );
end Other__fpu__part153;

architecture Other__fpu__part153_behav of Other__fpu__part153 is
begin
    po039 <= ( lo036 );
end Other__fpu__part153_behav;
