--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part889 is 
  Port (
    lo6725: in std_logic;
    n32869_1: inout std_logic
  );
end Other__carpat__part889;

architecture Other__carpat__part889_behav of Other__carpat__part889 is
begin
    n32869_1 <= ( lo6725 );
end Other__carpat__part889_behav;
