--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part59 is 
  Port (
    pi0754: in std_logic;
    n24874: inout std_logic
  );
end Other__carpat__part59;

architecture Other__carpat__part59_behav of Other__carpat__part59 is
begin
    n24874 <= ( pi0754 );
end Other__carpat__part59_behav;
