--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s400__part3 is 
  Port (
    lo03: in std_logic;
    po0: inout std_logic
  );
end IWLS93__s400__part3;

architecture IWLS93__s400__part3_behav of IWLS93__s400__part3 is
begin
    po0 <= ( lo03 );
end IWLS93__s400__part3_behav;
