--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1264 is 
  Port (
    lo4633: in std_logic;
    n18654: inout std_logic
  );
end Other__sudoku_check__part1264;

architecture Other__sudoku_check__part1264_behav of Other__sudoku_check__part1264 is
begin
    n18654 <= ( lo4633 );
end Other__sudoku_check__part1264_behav;
