--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__c7552__part0 is 
  Port (
    pi086,pi000: in std_logic;
    po12: inout std_logic
  );
end ISCAS__c7552__part0;

architecture ISCAS__c7552__part0_behav of ISCAS__c7552__part0 is
begin
    po12 <= ( pi086 and pi000 );
end ISCAS__c7552__part0_behav;
