--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part54 is 
  Port (
    lo51: in std_logic;
    n511: inout std_logic
  );
end Cookbook__approx_fp_div__part54;

architecture Cookbook__approx_fp_div__part54_behav of Cookbook__approx_fp_div__part54 is
begin
    n511 <= ( lo51 );
end Cookbook__approx_fp_div__part54_behav;
