--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1004 is 
  Port (
    lo7089: in std_logic;
    n37619_1: inout std_logic
  );
end Other__carpat__part1004;

architecture Other__carpat__part1004_behav of Other__carpat__part1004 is
begin
    n37619_1 <= ( lo7089 );
end Other__carpat__part1004_behav;
