--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part189 is 
  Port (
    lo2838: in std_logic;
    n6809: inout std_logic
  );
end Other__sudoku_check__part189;

architecture Other__sudoku_check__part189_behav of Other__sudoku_check__part189 is
begin
    n6809 <= ( lo2838 );
end Other__sudoku_check__part189_behav;
