--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2152 is 
  Port (
    lo2221: in std_logic;
    n11404: inout std_logic
  );
end Cookbook__fec_check__part2152;

architecture Cookbook__fec_check__part2152_behav of Cookbook__fec_check__part2152 is
begin
    n11404 <= ( lo2221 );
end Cookbook__fec_check__part2152_behav;
