--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1006 is 
  Port (
    lo10725: in std_logic;
    n71756_1: inout std_logic
  );
end Other__ray__part1006;

architecture Other__ray__part1006_behav of Other__ray__part1006 is
begin
    n71756_1 <= ( lo10725 );
end Other__ray__part1006_behav;
