--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part242 is 
  Port (
    lo03520: in std_logic;
    n34886: inout std_logic
  );
end Other__ray__part242;

architecture Other__ray__part242_behav of Other__ray__part242 is
begin
    n34886 <= ( lo03520 );
end Other__ray__part242_behav;
