--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part724 is 
  Port (
    lo5450: in std_logic;
    n25739: inout std_logic
  );
end Other__carpat__part724;

architecture Other__carpat__part724_behav of Other__carpat__part724 is
begin
    n25739 <= ( lo5450 );
end Other__carpat__part724_behav;
