--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2315 is 
  Port (
    lo5109: in std_logic;
    n30061: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2315;

architecture Other__ucsb_152_tap_fir__part2315_behav of Other__ucsb_152_tap_fir__part2315 is
begin
    n30061 <= ( lo5109 );
end Other__ucsb_152_tap_fir__part2315_behav;
