--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part805 is 
  Port (
    lo4578: in std_logic;
    n23055: inout std_logic
  );
end IWLS2005__des_perf__part805;

architecture IWLS2005__des_perf__part805_behav of IWLS2005__des_perf__part805 is
begin
    n23055 <= ( lo4578 );
end IWLS2005__des_perf__part805_behav;
