--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part670 is 
  Port (
    lo3319: in std_logic;
    n11619: inout std_logic
  );
end Other__sudoku_check__part670;

architecture Other__sudoku_check__part670_behav of Other__sudoku_check__part670 is
begin
    n11619 <= ( lo3319 );
end Other__sudoku_check__part670_behav;
