--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part133 is 
  Port (
    lo0935: in std_logic;
    n4949_1: inout std_logic
  );
end LGSynth91__s38417__part133;

architecture LGSynth91__s38417__part133_behav of LGSynth91__s38417__part133 is
begin
    n4949_1 <= ( lo0935 );
end LGSynth91__s38417__part133_behav;
