--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part163 is 
  Port (
    lo0361: in std_logic;
    n6256: inout std_logic
  );
end Other__ucsb_152_tap_fir__part163;

architecture Other__ucsb_152_tap_fir__part163_behav of Other__ucsb_152_tap_fir__part163 is
begin
    n6256 <= ( lo0361 );
end Other__ucsb_152_tap_fir__part163_behav;
