--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1411 is 
  Port (
    lo7861: in std_logic;
    n44184_1: inout std_logic
  );
end Other__carpat__part1411;

architecture Other__carpat__part1411_behav of Other__carpat__part1411 is
begin
    n44184_1 <= ( lo7861 );
end Other__carpat__part1411_behav;
