--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3010 is 
  Port (
    lo8323: in std_logic;
    n42010_1: inout std_logic
  );
end IWLS2005__des_perf__part3010;

architecture IWLS2005__des_perf__part3010_behav of IWLS2005__des_perf__part3010 is
begin
    n42010_1 <= ( lo8323 );
end IWLS2005__des_perf__part3010_behav;
