--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part10 is 
  Port (
    pi1102: in std_logic;
    n51221_1: inout std_logic
  );
end Other__ray__part10;

architecture Other__ray__part10_behav of Other__ray__part10 is
begin
    n51221_1 <= ( pi1102 );
end Other__ray__part10_behav;
