--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part170 is 
  Port (
    lo1161: in std_logic;
    n2049: inout std_logic
  );
end IWLS93__s38417__part170;

architecture IWLS93__s38417__part170_behav of IWLS93__s38417__part170 is
begin
    n2049 <= ( not lo1161 );
end IWLS93__s38417__part170_behav;
