--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__apex5__part1 is 
  Port (
    : in std_logic;
    po04,po30,po36: inout std_logic
  );
end IWLS93__apex5__part1;

architecture IWLS93__apex5__part1_behav of IWLS93__apex5__part1 is
signal n203: std_logic;
begin
    n203 <= '0';
    po04 <= ( n203 );
    po30 <= ( n203 );
    po36 <= ( n203 );
end IWLS93__apex5__part1_behav;
