--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part999 is 
  Port (
    lo4368: in std_logic;
    n17329: inout std_logic
  );
end Other__sudoku_check__part999;

architecture Other__sudoku_check__part999_behav of Other__sudoku_check__part999 is
begin
    n17329 <= ( lo4368 );
end Other__sudoku_check__part999_behav;
