--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part54 is 
  Port (
    lo78: in std_logic;
    po02: inout std_logic
  );
end Cookbook__mlab_dcfifo__part54;

architecture Cookbook__mlab_dcfifo__part54_behav of Cookbook__mlab_dcfifo__part54 is
begin
    po02 <= ( lo78 );
end Cookbook__mlab_dcfifo__part54_behav;
