--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1156 is 
  Port (
    lo1225: in std_logic;
    n6424: inout std_logic
  );
end Cookbook__fec_check__part1156;

architecture Cookbook__fec_check__part1156_behav of Cookbook__fec_check__part1156 is
begin
    n6424 <= ( lo1225 );
end Cookbook__fec_check__part1156_behav;
