--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part106 is 
  Port (
    lo0175: in std_logic;
    n1174: inout std_logic
  );
end Cookbook__fec_check__part106;

architecture Cookbook__fec_check__part106_behav of Cookbook__fec_check__part106 is
begin
    n1174 <= ( lo0175 );
end Cookbook__fec_check__part106_behav;
