--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part472 is 
  Port (
    lo1695: in std_logic;
    n9734_1: inout std_logic
  );
end Cookbook__ucrypt__part472;

architecture Cookbook__ucrypt__part472_behav of Cookbook__ucrypt__part472 is
begin
    n9734_1 <= ( lo1695 );
end Cookbook__ucrypt__part472_behav;
