--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part668 is 
  Port (
    lo5189: in std_logic;
    n24964: inout std_logic
  );
end Other__carpat__part668;

architecture Other__carpat__part668_behav of Other__carpat__part668 is
begin
    n24964 <= ( lo5189 );
end Other__carpat__part668_behav;
