--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1471 is 
  Port (
    lo8102: in std_logic;
    n44559_1: inout std_logic
  );
end Other__carpat__part1471;

architecture Other__carpat__part1471_behav of Other__carpat__part1471 is
begin
    n44559_1 <= ( lo8102 );
end Other__carpat__part1471_behav;
