--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part376 is 
  Port (
    lo05696: in std_logic;
    n36276: inout std_logic
  );
end Other__ray__part376;

architecture Other__ray__part376_behav of Other__ray__part376 is
begin
    n36276 <= ( lo05696 );
end Other__ray__part376_behav;
