--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part144 is 
  Port (
    lo130: in std_logic;
    po136: inout std_logic
  );
end Cookbook__lc_mult_signed__part144;

architecture Cookbook__lc_mult_signed__part144_behav of Cookbook__lc_mult_signed__part144 is
begin
    po136 <= ( lo130 );
end Cookbook__lc_mult_signed__part144_behav;
