--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2366 is 
  Port (
    lo7569: in std_logic;
    n37775_1: inout std_logic
  );
end IWLS2005__des_perf__part2366;

architecture IWLS2005__des_perf__part2366_behav of IWLS2005__des_perf__part2366 is
begin
    n37775_1 <= ( lo7569 );
end IWLS2005__des_perf__part2366_behav;
