--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1688 is 
  Port (
    lo3808: in std_logic;
    n23616: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1688;

architecture Other__ucsb_152_tap_fir__part1688_behav of Other__ucsb_152_tap_fir__part1688 is
begin
    n23616 <= ( lo3808 );
end Other__ucsb_152_tap_fir__part1688_behav;
