--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part129 is 
  Port (
    lo0198: in std_logic;
    n1289: inout std_logic
  );
end Cookbook__fec_check__part129;

architecture Cookbook__fec_check__part129_behav of Cookbook__fec_check__part129 is
begin
    n1289 <= ( lo0198 );
end Cookbook__fec_check__part129_behav;
