--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part65 is 
  Port (
    lo62: in std_logic;
    po22: inout std_logic
  );
end Cookbook__approx_fp_div__part65;

architecture Cookbook__approx_fp_div__part65_behav of Cookbook__approx_fp_div__part65 is
begin
    po22 <= ( lo62 );
end Cookbook__approx_fp_div__part65_behav;
