--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part231 is 
  Port (
    lo335: in std_logic;
    n1187: inout std_logic
  );
end Other__fpu__part231;

architecture Other__fpu__part231_behav of Other__fpu__part231 is
begin
    n1187 <= ( lo335 );
end Other__fpu__part231_behav;
