--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part603 is 
  Port (
    lo3252: in std_logic;
    n10949: inout std_logic
  );
end Other__sudoku_check__part603;

architecture Other__sudoku_check__part603_behav of Other__sudoku_check__part603 is
begin
    n10949 <= ( lo3252 );
end Other__sudoku_check__part603_behav;
