--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part14 is 
  Port (
    pi1106: in std_logic;
    n51241_1: inout std_logic
  );
end Other__ray__part14;

architecture Other__ray__part14_behav of Other__ray__part14 is
begin
    n51241_1 <= ( pi1106 );
end Other__ray__part14_behav;
