--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part60 is 
  Port (
    lo512: in std_logic;
    n2738_1: inout std_logic
  );
end Cookbook__lane_tx__part60;

architecture Cookbook__lane_tx__part60_behav of Cookbook__lane_tx__part60 is
begin
    n2738_1 <= ( lo512 );
end Cookbook__lane_tx__part60_behav;
