--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part896 is 
  Port (
    lo0965: in std_logic;
    n5124: inout std_logic
  );
end Cookbook__fec_check__part896;

architecture Cookbook__fec_check__part896_behav of Cookbook__fec_check__part896 is
begin
    n5124 <= ( lo0965 );
end Cookbook__fec_check__part896_behav;
