--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_1 is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end Cookbook__fec_rot_1;

architecture Cookbook__fec_rot_1_behav of Cookbook__fec_rot_1 is
begin
    po3 <= ( not pi4 and pi0 )
      or ( pi4 and not pi0 );
    po2 <= ( not pi3 and pi0 )
      or ( pi3 and not pi0 );
    po1 <= ( not pi2 and pi0 )
      or ( pi2 and not pi0 );
    po0 <= ( not pi1 and pi0 )
      or ( pi1 and not pi0 );
end Cookbook__fec_rot_1_behav;
