--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1565 is 
  Port (
    lo1634: in std_logic;
    n8469: inout std_logic
  );
end Cookbook__fec_check__part1565;

architecture Cookbook__fec_check__part1565_behav of Cookbook__fec_check__part1565 is
begin
    n8469 <= ( lo1634 );
end Cookbook__fec_check__part1565_behav;
