--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part777 is 
  Port (
    lo4514: in std_logic;
    n22665: inout std_logic
  );
end IWLS2005__des_perf__part777;

architecture IWLS2005__des_perf__part777_behav of IWLS2005__des_perf__part777 is
begin
    n22665 <= ( lo4514 );
end IWLS2005__des_perf__part777_behav;
