--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1126 is 
  Port (
    lo1195: in std_logic;
    n6274: inout std_logic
  );
end Cookbook__fec_check__part1126;

architecture Cookbook__fec_check__part1126_behav of Cookbook__fec_check__part1126 is
begin
    n6274 <= ( lo1195 );
end Cookbook__fec_check__part1126_behav;
