--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2109 is 
  Port (
    lo2178: in std_logic;
    n11189: inout std_logic
  );
end Cookbook__fec_check__part2109;

architecture Cookbook__fec_check__part2109_behav of Cookbook__fec_check__part2109 is
begin
    n11189 <= ( lo2178 );
end Cookbook__fec_check__part2109_behav;
