--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1283 is 
  Port (
    lo1352: in std_logic;
    n7059: inout std_logic
  );
end Cookbook__fec_check__part1283;

architecture Cookbook__fec_check__part1283_behav of Cookbook__fec_check__part1283 is
begin
    n7059 <= ( lo1352 );
end Cookbook__fec_check__part1283_behav;
