--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part970 is 
  Port (
    lo4933: in std_logic;
    n24865: inout std_logic
  );
end IWLS2005__des_perf__part970;

architecture IWLS2005__des_perf__part970_behav of IWLS2005__des_perf__part970 is
begin
    n24865 <= ( lo4933 );
end IWLS2005__des_perf__part970_behav;
