--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1532 is 
  Port (
    lo3474: in std_logic;
    n21956: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1532;

architecture Other__ucsb_152_tap_fir__part1532_behav of Other__ucsb_152_tap_fir__part1532 is
begin
    n21956 <= ( lo3474 );
end Other__ucsb_152_tap_fir__part1532_behav;
