--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1681 is 
  Port (
    lo1750: in std_logic;
    n9049: inout std_logic
  );
end Cookbook__fec_check__part1681;

architecture Cookbook__fec_check__part1681_behav of Cookbook__fec_check__part1681 is
begin
    n9049 <= ( lo1750 );
end Cookbook__fec_check__part1681_behav;
