--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part541 is 
  Port (
    lo06016: in std_logic;
    n36856: inout std_logic
  );
end Other__ray__part541;

architecture Other__ray__part541_behav of Other__ray__part541 is
begin
    n36856 <= ( lo06016 );
end Other__ray__part541_behav;
