--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1486 is 
  Port (
    lo8117: in std_logic;
    n44634_1: inout std_logic
  );
end Other__carpat__part1486;

architecture Other__carpat__part1486_behav of Other__carpat__part1486 is
begin
    n44634_1 <= ( lo8117 );
end Other__carpat__part1486_behav;
