--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1700 is 
  Port (
    lo1769: in std_logic;
    n9144: inout std_logic
  );
end Cookbook__fec_check__part1700;

architecture Cookbook__fec_check__part1700_behav of Cookbook__fec_check__part1700 is
begin
    n9144 <= ( lo1769 );
end Cookbook__fec_check__part1700_behav;
