--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part421 is 
  Port (
    lo05893: in std_logic;
    po1310,po1359,po1617,po1679: inout std_logic
  );
end Other__ray__part421;

architecture Other__ray__part421_behav of Other__ray__part421 is
begin
    po1310 <= ( lo05893 );
    po1359 <= ( lo05893 );
    po1617 <= ( lo05893 );
    po1679 <= ( lo05893 );
end Other__ray__part421_behav;
