--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part436 is 
  Port (
    lo1547: in std_logic;
    n8994_1: inout std_logic
  );
end Cookbook__ucrypt__part436;

architecture Cookbook__ucrypt__part436_behav of Cookbook__ucrypt__part436 is
begin
    n8994_1 <= ( lo1547 );
end Cookbook__ucrypt__part436_behav;
