--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part104 is 
  Port (
    lo0173: in std_logic;
    n1164: inout std_logic
  );
end Cookbook__fec_check__part104;

architecture Cookbook__fec_check__part104_behav of Cookbook__fec_check__part104 is
begin
    n1164 <= ( lo0173 );
end Cookbook__fec_check__part104_behav;
