--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2479 is 
  Port (
    lo5465: in std_logic;
    n31831: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2479;

architecture Other__ucsb_152_tap_fir__part2479_behav of Other__ucsb_152_tap_fir__part2479 is
begin
    n31831 <= ( lo5465 );
end Other__ucsb_152_tap_fir__part2479_behav;
