--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part31 is 
  Port (
    lo29: in std_logic;
    po10: inout std_logic
  );
end Cookbook__pipeline_add__part31;

architecture Cookbook__pipeline_add__part31_behav of Cookbook__pipeline_add__part31 is
begin
    po10 <= ( lo29 );
end Cookbook__pipeline_add__part31_behav;
