--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part6 is 
  Port (
    lo05: in std_logic;
    po05: inout std_logic
  );
end Other__idxlat02n_m12__part6;

architecture Other__idxlat02n_m12__part6_behav of Other__idxlat02n_m12__part6 is
begin
    po05 <= ( lo05 );
end Other__idxlat02n_m12__part6_behav;
