--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part44 is 
  Port (
    lo107: in std_logic;
    po029: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part44;

architecture Cookbook__soft_ecc_ram_64bit__part44_behav of Cookbook__soft_ecc_ram_64bit__part44 is
begin
    po029 <= ( lo107 );
end Cookbook__soft_ecc_ram_64bit__part44_behav;
