--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2006 is 
  Port (
    lo2075: in std_logic;
    n10674: inout std_logic
  );
end Cookbook__fec_check__part2006;

architecture Cookbook__fec_check__part2006_behav of Cookbook__fec_check__part2006 is
begin
    n10674 <= ( lo2075 );
end Cookbook__fec_check__part2006_behav;
