--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part816 is 
  Port (
    lo06575: in std_logic;
    n49211_1: inout std_logic
  );
end Other__ray__part816;

architecture Other__ray__part816_behav of Other__ray__part816 is
begin
    n49211_1 <= ( lo06575 );
end Other__ray__part816_behav;
