--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2614 is 
  Port (
    lo7874: in std_logic;
    n39455_1: inout std_logic
  );
end IWLS2005__des_perf__part2614;

architecture IWLS2005__des_perf__part2614_behav of IWLS2005__des_perf__part2614 is
begin
    n39455_1 <= ( lo7874 );
end IWLS2005__des_perf__part2614_behav;
