--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part40 is 
  Port (
    pi040: in std_logic;
    n9849_1: inout std_logic
  );
end Other__desperf__part40;

architecture Other__desperf__part40_behav of Other__desperf__part40 is
begin
    n9849_1 <= ( pi040 );
end Other__desperf__part40_behav;
