--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part596 is 
  Port (
    lo4251: in std_logic;
    n21719: inout std_logic
  );
end Other__carpat__part596;

architecture Other__carpat__part596_behav of Other__carpat__part596 is
begin
    n21719 <= ( lo4251 );
end Other__carpat__part596_behav;
