--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part435 is 
  Port (
    lo3084: in std_logic;
    n9269: inout std_logic
  );
end Other__sudoku_check__part435;

architecture Other__sudoku_check__part435_behav of Other__sudoku_check__part435 is
begin
    n9269 <= ( lo3084 );
end Other__sudoku_check__part435_behav;
