--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part126 is 
  Port (
    lo0962: in std_logic;
    n5294_1: inout std_logic
  );
end IWLS2005__mem_ctrl__part126;

architecture IWLS2005__mem_ctrl__part126_behav of IWLS2005__mem_ctrl__part126 is
begin
    n5294_1 <= ( lo0962 );
end IWLS2005__mem_ctrl__part126_behav;
