--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part33 is 
  Port (
    lo00302: in std_logic;
    po016: inout std_logic
  );
end IWLS2005__ethernet__part33;

architecture IWLS2005__ethernet__part33_behav of IWLS2005__ethernet__part33 is
begin
    po016 <= ( lo00302 );
end IWLS2005__ethernet__part33_behav;
