--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part547 is 
  Port (
    lo4131: in std_logic;
    n20765: inout std_logic
  );
end IWLS2005__des_perf__part547;

architecture IWLS2005__des_perf__part547_behav of IWLS2005__des_perf__part547 is
begin
    n20765 <= ( lo4131 );
end IWLS2005__des_perf__part547_behav;
