--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part226 is 
  Port (
    lo330: in std_logic;
    n1162: inout std_logic
  );
end Other__fpu__part226;

architecture Other__fpu__part226_behav of Other__fpu__part226 is
begin
    n1162 <= ( lo330 );
end Other__fpu__part226_behav;
