--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part28 is 
  Port (
    lo027: in std_logic;
    n445: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part28;

architecture Cookbook__approx_fp_invsqrt__part28_behav of Cookbook__approx_fp_invsqrt__part28 is
begin
    n445 <= ( lo027 );
end Cookbook__approx_fp_invsqrt__part28_behav;
