--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1575 is 
  Port (
    lo1644: in std_logic;
    n8519: inout std_logic
  );
end Cookbook__fec_check__part1575;

architecture Cookbook__fec_check__part1575_behav of Cookbook__fec_check__part1575 is
begin
    n8519 <= ( lo1644 );
end Cookbook__fec_check__part1575_behav;
