--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part289 is 
  Port (
    lo1137: in std_logic;
    n6165: inout std_logic
  );
end IWLS2005__des_perf__part289;

architecture IWLS2005__des_perf__part289_behav of IWLS2005__des_perf__part289 is
begin
    n6165 <= ( lo1137 );
end IWLS2005__des_perf__part289_behav;
