--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part315 is 
  Port (
    pi1613: in std_logic;
    n47379_1: inout std_logic
  );
end Other__carpat__part315;

architecture Other__carpat__part315_behav of Other__carpat__part315 is
begin
    n47379_1 <= ( pi1613 );
end Other__carpat__part315_behav;
