--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part616 is 
  Port (
    lo06097: in std_logic;
    n38431: inout std_logic
  );
end Other__ray__part616;

architecture Other__ray__part616_behav of Other__ray__part616 is
begin
    n38431 <= ( lo06097 );
end Other__ray__part616_behav;
