--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part71 is 
  Port (
    lo147: in std_logic;
    po69: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part71;

architecture Cookbook__soft_ecc_ram_32bit__part71_behav of Cookbook__soft_ecc_ram_32bit__part71 is
begin
    po69 <= ( lo147 );
end Cookbook__soft_ecc_ram_32bit__part71_behav;
