--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1162 is 
  Port (
    lo1231: in std_logic;
    n6454: inout std_logic
  );
end Cookbook__fec_check__part1162;

architecture Cookbook__fec_check__part1162_behav of Cookbook__fec_check__part1162 is
begin
    n6454 <= ( lo1231 );
end Cookbook__fec_check__part1162_behav;
