--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part312 is 
  Port (
    lo1492: in std_logic;
    n10475_1: inout std_logic
  );
end Other__fp_operators__part312;

architecture Other__fp_operators__part312_behav of Other__fp_operators__part312 is
begin
    n10475_1 <= ( lo1492 );
end Other__fp_operators__part312_behav;
