--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part163 is 
  Port (
    pi1089: in std_logic;
    n31894: inout std_logic
  );
end Other__carpat__part163;

architecture Other__carpat__part163_behav of Other__carpat__part163 is
begin
    n31894 <= ( pi1089 );
end Other__carpat__part163_behav;
