--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__encoder_8b10b__part1 is 
  Port (
    lo01: in std_logic;
    po00: inout std_logic
  );
end Cookbook__encoder_8b10b__part1;

architecture Cookbook__encoder_8b10b__part1_behav of Cookbook__encoder_8b10b__part1 is
begin
    po00 <= ( lo01 );
end Cookbook__encoder_8b10b__part1_behav;
