--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part480 is 
  Port (
    lo4031: in std_logic;
    n20510: inout std_logic
  );
end IWLS2005__des_perf__part480;

architecture IWLS2005__des_perf__part480_behav of IWLS2005__des_perf__part480 is
begin
    n20510 <= ( lo4031 );
end IWLS2005__des_perf__part480_behav;
