--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1409 is 
  Port (
    lo7859: in std_logic;
    n44174_1: inout std_logic
  );
end Other__carpat__part1409;

architecture Other__carpat__part1409_behav of Other__carpat__part1409 is
begin
    n44174_1 <= ( lo7859 );
end Other__carpat__part1409_behav;
