--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part196 is 
  Port (
    lo0462: in std_logic;
    n6761: inout std_logic
  );
end Other__ucsb_152_tap_fir__part196;

architecture Other__ucsb_152_tap_fir__part196_behav of Other__ucsb_152_tap_fir__part196 is
begin
    n6761 <= ( lo0462 );
end Other__ucsb_152_tap_fir__part196_behav;
