--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1004 is 
  Port (
    lo1073: in std_logic;
    n5664: inout std_logic
  );
end Cookbook__fec_check__part1004;

architecture Cookbook__fec_check__part1004_behav of Cookbook__fec_check__part1004 is
begin
    n5664 <= ( lo1073 );
end Cookbook__fec_check__part1004_behav;
