--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part393 is 
  Port (
    lo3042: in std_logic;
    n8849: inout std_logic
  );
end Other__sudoku_check__part393;

architecture Other__sudoku_check__part393_behav of Other__sudoku_check__part393 is
begin
    n8849 <= ( lo3042 );
end Other__sudoku_check__part393_behav;
