--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1715 is 
  Port (
    lo3865: in std_logic;
    n23906: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1715;

architecture Other__ucsb_152_tap_fir__part1715_behav of Other__ucsb_152_tap_fir__part1715 is
begin
    n23906 <= ( lo3865 );
end Other__ucsb_152_tap_fir__part1715_behav;
