--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part573 is 
  Port (
    lo3519: in std_logic;
    n16754: inout std_logic
  );
end Other__carpat__part573;

architecture Other__carpat__part573_behav of Other__carpat__part573 is
begin
    n16754 <= ( lo3519 );
end Other__carpat__part573_behav;
