--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part698 is 
  Port (
    lo0767: in std_logic;
    n4134: inout std_logic
  );
end Cookbook__fec_check__part698;

architecture Cookbook__fec_check__part698_behav of Cookbook__fec_check__part698 is
begin
    n4134 <= ( lo0767 );
end Cookbook__fec_check__part698_behav;
