--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2615 is 
  Port (
    lo7876: in std_logic;
    n39565_1: inout std_logic
  );
end IWLS2005__des_perf__part2615;

architecture IWLS2005__des_perf__part2615_behav of IWLS2005__des_perf__part2615 is
begin
    n39565_1 <= ( lo7876 );
end IWLS2005__des_perf__part2615_behav;
