--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1051 is 
  Port (
    lo1120: in std_logic;
    n5899: inout std_logic
  );
end Cookbook__fec_check__part1051;

architecture Cookbook__fec_check__part1051_behav of Cookbook__fec_check__part1051 is
begin
    n5899 <= ( lo1120 );
end Cookbook__fec_check__part1051_behav;
