--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part127 is 
  Port (
    lo0833: in std_logic;
    n694: inout std_logic
  );
end IWLS93__s38417__part127;

architecture IWLS93__s38417__part127_behav of IWLS93__s38417__part127 is
begin
    n694 <= ( lo0833 );
end IWLS93__s38417__part127_behav;
