--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part147 is 
  Port (
    lo0332: in std_logic;
    n6126: inout std_logic
  );
end Other__ucsb_152_tap_fir__part147;

architecture Other__ucsb_152_tap_fir__part147_behav of Other__ucsb_152_tap_fir__part147 is
begin
    n6126 <= ( lo0332 );
end Other__ucsb_152_tap_fir__part147_behav;
