--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part259 is 
  Port (
    lo0328: in std_logic;
    n1939: inout std_logic
  );
end Cookbook__fec_check__part259;

architecture Cookbook__fec_check__part259_behav of Cookbook__fec_check__part259 is
begin
    n1939 <= ( lo0328 );
end Cookbook__fec_check__part259_behav;
