--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part177 is 
  Port (
    lo1389: in std_logic;
    n7219_1: inout std_logic
  );
end ISCAS__s38417__part177;

architecture ISCAS__s38417__part177_behav of ISCAS__s38417__part177 is
begin
    n7219_1 <= ( lo1389 );
end ISCAS__s38417__part177_behav;
