--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1691 is 
  Port (
    lo3839: in std_logic;
    n23776: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1691;

architecture Other__ucsb_152_tap_fir__part1691_behav of Other__ucsb_152_tap_fir__part1691 is
begin
    n23776 <= ( lo3839 );
end Other__ucsb_152_tap_fir__part1691_behav;
