--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2060 is 
  Port (
    lo2129: in std_logic;
    n10944: inout std_logic
  );
end Cookbook__fec_check__part2060;

architecture Cookbook__fec_check__part2060_behav of Cookbook__fec_check__part2060 is
begin
    n10944 <= ( lo2129 );
end Cookbook__fec_check__part2060_behav;
