--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2110 is 
  Port (
    lo2179: in std_logic;
    n11194: inout std_logic
  );
end Cookbook__fec_check__part2110;

architecture Cookbook__fec_check__part2110_behav of Cookbook__fec_check__part2110 is
begin
    n11194 <= ( lo2179 );
end Cookbook__fec_check__part2110_behav;
