--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part128 is 
  Port (
    lo184932: in std_logic;
    n924551: inout std_logic
  );
end IWLS2005__leon3__part128;

architecture IWLS2005__leon3__part128_behav of IWLS2005__leon3__part128 is
begin
    n924551 <= ( lo184932 );
end IWLS2005__leon3__part128_behav;
