--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1078 is 
  Port (
    lo1147: in std_logic;
    n6034: inout std_logic
  );
end Cookbook__fec_check__part1078;

architecture Cookbook__fec_check__part1078_behav of Cookbook__fec_check__part1078 is
begin
    n6034 <= ( lo1147 );
end Cookbook__fec_check__part1078_behav;
