--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part52 is 
  Port (
    lo00927: in std_logic;
    po082: inout std_logic
  );
end IWLS2005__ethernet__part52;

architecture IWLS2005__ethernet__part52_behav of IWLS2005__ethernet__part52 is
begin
    po082 <= ( lo00927 );
end IWLS2005__ethernet__part52_behav;
