--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part40 is 
  Port (
    lo0297: in std_logic;
    n1759: inout std_logic
  );
end LGSynth91__s38417__part40;

architecture LGSynth91__s38417__part40_behav of LGSynth91__s38417__part40 is
begin
    n1759 <= ( lo0297 );
end LGSynth91__s38417__part40_behav;
