--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ac97_ctrl__part25 is 
  Port (
    pi27: in std_logic;
    n11083: inout std_logic
  );
end IWLS2005__ac97_ctrl__part25;

architecture IWLS2005__ac97_ctrl__part25_behav of IWLS2005__ac97_ctrl__part25 is
begin
    n11083 <= ( pi27 );
end IWLS2005__ac97_ctrl__part25_behav;
