--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part349 is 
  Port (
    pi1681: in std_logic;
    n47989_1: inout std_logic
  );
end Other__carpat__part349;

architecture Other__carpat__part349_behav of Other__carpat__part349 is
begin
    n47989_1 <= ( pi1681 );
end Other__carpat__part349_behav;
