--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part902 is 
  Port (
    lo0971: in std_logic;
    n5154: inout std_logic
  );
end Cookbook__fec_check__part902;

architecture Cookbook__fec_check__part902_behav of Cookbook__fec_check__part902 is
begin
    n5154 <= ( lo0971 );
end Cookbook__fec_check__part902_behav;
