--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part17 is 
  Port (
    lo464: in std_logic;
    po07: inout std_logic
  );
end Cookbook__lane_tx__part17;

architecture Cookbook__lane_tx__part17_behav of Cookbook__lane_tx__part17 is
begin
    po07 <= ( lo464 );
end Cookbook__lane_tx__part17_behav;
