--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part245 is 
  Port (
    lo0594: in std_logic;
    n7451: inout std_logic
  );
end Other__ucsb_152_tap_fir__part245;

architecture Other__ucsb_152_tap_fir__part245_behav of Other__ucsb_152_tap_fir__part245 is
begin
    n7451 <= ( lo0594 );
end Other__ucsb_152_tap_fir__part245_behav;
