--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part84 is 
  Port (
    pi084: in std_logic;
    n10069_1: inout std_logic
  );
end Other__desperf__part84;

architecture Other__desperf__part84_behav of Other__desperf__part84 is
begin
    n10069_1 <= ( pi084 );
end Other__desperf__part84_behav;
