--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part531 is 
  Port (
    lo4114: in std_logic;
    n20760: inout std_logic
  );
end IWLS2005__des_perf__part531;

architecture IWLS2005__des_perf__part531_behav of IWLS2005__des_perf__part531 is
begin
    n20760 <= ( lo4114 );
end IWLS2005__des_perf__part531_behav;
