--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1091 is 
  Port (
    lo4460: in std_logic;
    n17789: inout std_logic
  );
end Other__sudoku_check__part1091;

architecture Other__sudoku_check__part1091_behav of Other__sudoku_check__part1091 is
begin
    n17789 <= ( lo4460 );
end Other__sudoku_check__part1091_behav;
