--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part142 is 
  Port (
    lo0211: in std_logic;
    n1354: inout std_logic
  );
end Cookbook__fec_check__part142;

architecture Cookbook__fec_check__part142_behav of Cookbook__fec_check__part142 is
begin
    n1354 <= ( lo0211 );
end Cookbook__fec_check__part142_behav;
