--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2784 is 
  Port (
    lo8097: in std_logic;
    n40995_1: inout std_logic
  );
end IWLS2005__des_perf__part2784;

architecture IWLS2005__des_perf__part2784_behav of IWLS2005__des_perf__part2784 is
begin
    n40995_1 <= ( lo8097 );
end IWLS2005__des_perf__part2784_behav;
