--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part118 is 
  Port (
    lo0229: in std_logic;
    n5606: inout std_logic
  );
end Other__ucsb_152_tap_fir__part118;

architecture Other__ucsb_152_tap_fir__part118_behav of Other__ucsb_152_tap_fir__part118 is
begin
    n5606 <= ( lo0229 );
end Other__ucsb_152_tap_fir__part118_behav;
