--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part599 is 
  Port (
    lo0668: in std_logic;
    n3639: inout std_logic
  );
end Cookbook__fec_check__part599;

architecture Cookbook__fec_check__part599_behav of Cookbook__fec_check__part599 is
begin
    n3639 <= ( lo0668 );
end Cookbook__fec_check__part599_behav;
