--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part369 is 
  Port (
    pi1735: in std_logic;
    n48309_1: inout std_logic
  );
end Other__carpat__part369;

architecture Other__carpat__part369_behav of Other__carpat__part369 is
begin
    n48309_1 <= ( pi1735 );
end Other__carpat__part369_behav;
