--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part36 is 
  Port (
    pi102: in std_logic;
    n5884_1: inout std_logic
  );
end IWLS2005__mem_ctrl__part36;

architecture IWLS2005__mem_ctrl__part36_behav of IWLS2005__mem_ctrl__part36 is
begin
    n5884_1 <= ( pi102 );
end IWLS2005__mem_ctrl__part36_behav;
