--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part17 is 
  Port (
    lo13: in std_logic;
    po16: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part17;

architecture Cookbook__x4_encoder_8b10b__part17_behav of Cookbook__x4_encoder_8b10b__part17 is
begin
    po16 <= ( lo13 );
end Cookbook__x4_encoder_8b10b__part17_behav;
