--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part10 is 
  Port (
    pi010: in std_logic;
    n9699_1: inout std_logic
  );
end Other__desperf__part10;

architecture Other__desperf__part10_behav of Other__desperf__part10 is
begin
    n9699_1 <= ( pi010 );
end Other__desperf__part10_behav;
