--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part498 is 
  Port (
    lo1833: in std_logic;
    n10424_1: inout std_logic
  );
end Cookbook__ucrypt__part498;

architecture Cookbook__ucrypt__part498_behav of Cookbook__ucrypt__part498 is
begin
    n10424_1 <= ( lo1833 );
end Cookbook__ucrypt__part498_behav;
