--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part416 is 
  Port (
    lo0124: in std_logic;
    po095: inout std_logic
  );
end Other__carpat__part416;

architecture Other__carpat__part416_behav of Other__carpat__part416 is
begin
    po095 <= ( lo0124 );
end Other__carpat__part416_behav;
