--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part36 is 
  Port (
    lo33: in std_logic;
    n306: inout std_logic
  );
end Cookbook__approx_fp_div__part36;

architecture Cookbook__approx_fp_div__part36_behav of Cookbook__approx_fp_div__part36 is
begin
    n306 <= ( lo33 );
end Cookbook__approx_fp_div__part36_behav;
