--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part42 is 
  Port (
    lo0110: in std_logic;
    po118: inout std_logic
  );
end Other__mem__part42;

architecture Other__mem__part42_behav of Other__mem__part42 is
begin
    po118 <= ( lo0110 );
end Other__mem__part42_behav;
