--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1173 is 
  Port (
    lo4542: in std_logic;
    n18199: inout std_logic
  );
end Other__sudoku_check__part1173;

architecture Other__sudoku_check__part1173_behav of Other__sudoku_check__part1173 is
begin
    n18199 <= ( lo4542 );
end Other__sudoku_check__part1173_behav;
