--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1417 is 
  Port (
    lo5873: in std_logic;
    n29250_1: inout std_logic
  );
end IWLS2005__des_perf__part1417;

architecture IWLS2005__des_perf__part1417_behav of IWLS2005__des_perf__part1417 is
begin
    n29250_1 <= ( lo5873 );
end IWLS2005__des_perf__part1417_behav;
