--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s1196__part1 is 
  Port (
    lo12: in std_logic;
    po13: inout std_logic
  );
end IWLS93__s1196__part1;

architecture IWLS93__s1196__part1_behav of IWLS93__s1196__part1 is
begin
    po13 <= ( not lo12 );
end IWLS93__s1196__part1_behav;
