--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part59 is 
  Port (
    lo0127: in std_logic;
    po135: inout std_logic
  );
end Other__mem__part59;

architecture Other__mem__part59_behav of Other__mem__part59 is
begin
    po135 <= ( lo0127 );
end Other__mem__part59_behav;
