--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1399 is 
  Port (
    lo1468: in std_logic;
    n7639: inout std_logic
  );
end Cookbook__fec_check__part1399;

architecture Cookbook__fec_check__part1399_behav of Cookbook__fec_check__part1399 is
begin
    n7639 <= ( lo1468 );
end Cookbook__fec_check__part1399_behav;
