--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part206 is 
  Port (
    lo0513: in std_logic;
    n2024: inout std_logic
  );
end Other__desperf__part206;

architecture Other__desperf__part206_behav of Other__desperf__part206 is
begin
    n2024 <= ( lo0513 );
end Other__desperf__part206_behav;
