--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2123 is 
  Port (
    lo2192: in std_logic;
    n11259: inout std_logic
  );
end Cookbook__fec_check__part2123;

architecture Cookbook__fec_check__part2123_behav of Cookbook__fec_check__part2123 is
begin
    n11259 <= ( lo2192 );
end Cookbook__fec_check__part2123_behav;
