--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2101 is 
  Port (
    lo4661: in std_logic;
    n27891: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2101;

architecture Other__ucsb_152_tap_fir__part2101_behav of Other__ucsb_152_tap_fir__part2101 is
begin
    n27891 <= ( lo4661 );
end Other__ucsb_152_tap_fir__part2101_behav;
