--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part546 is 
  Port (
    lo06021: in std_logic;
    n36881: inout std_logic
  );
end Other__ray__part546;

architecture Other__ray__part546_behav of Other__ray__part546 is
begin
    n36881 <= ( lo06021 );
end Other__ray__part546_behav;
