--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part123 is 
  Port (
    pi0978: in std_logic;
    n31904: inout std_logic
  );
end Other__carpat__part123;

architecture Other__carpat__part123_behav of Other__carpat__part123 is
begin
    n31904 <= ( pi0978 );
end Other__carpat__part123_behav;
