--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1419 is 
  Port (
    lo4788: in std_logic;
    n19429_1: inout std_logic
  );
end Other__sudoku_check__part1419;

architecture Other__sudoku_check__part1419_behav of Other__sudoku_check__part1419 is
begin
    n19429_1 <= ( lo4788 );
end Other__sudoku_check__part1419_behav;
