--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1544 is 
  Port (
    lo1613: in std_logic;
    n8364: inout std_logic
  );
end Cookbook__fec_check__part1544;

architecture Cookbook__fec_check__part1544_behav of Cookbook__fec_check__part1544 is
begin
    n8364 <= ( lo1613 );
end Cookbook__fec_check__part1544_behav;
