--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part126 is 
  Port (
    pi0536: in std_logic;
    n43226_1: inout std_logic
  );
end Other__radar__part126;

architecture Other__radar__part126_behav of Other__radar__part126 is
begin
    n43226_1 <= ( pi0536 );
end Other__radar__part126_behav;
