--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1393 is 
  Port (
    lo3191: in std_logic;
    n20541: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1393;

architecture Other__ucsb_152_tap_fir__part1393_behav of Other__ucsb_152_tap_fir__part1393 is
begin
    n20541 <= ( lo3191 );
end Other__ucsb_152_tap_fir__part1393_behav;
