--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part136 is 
  Port (
    lo019: in std_logic;
    po019: inout std_logic
  );
end Other__fpu__part136;

architecture Other__fpu__part136_behav of Other__fpu__part136 is
begin
    po019 <= ( lo019 );
end Other__fpu__part136_behav;
