--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part67 is 
  Port (
    lo0405: in std_logic;
    n3704: inout std_logic
  );
end IWLS93__s38417__part67;

architecture IWLS93__s38417__part67_behav of IWLS93__s38417__part67 is
begin
    n3704 <= ( not lo0405 );
end IWLS93__s38417__part67_behav;
