--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part452 is 
  Port (
    lo0819: in std_logic;
    n9534: inout std_logic
  );
end Other__carpat__part452;

architecture Other__carpat__part452_behav of Other__carpat__part452 is
begin
    n9534 <= ( lo0819 );
end Other__carpat__part452_behav;
