--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part183 is 
  Port (
    lo169: in std_logic;
    po097: inout std_logic
  );
end Cookbook__lc_mult_signed__part183;

architecture Cookbook__lc_mult_signed__part183_behav of Cookbook__lc_mult_signed__part183 is
begin
    po097 <= ( lo169 );
end Cookbook__lc_mult_signed__part183_behav;
