--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part951 is 
  Port (
    lo4320: in std_logic;
    n17089: inout std_logic
  );
end Other__sudoku_check__part951;

architecture Other__sudoku_check__part951_behav of Other__sudoku_check__part951 is
begin
    n17089 <= ( lo4320 );
end Other__sudoku_check__part951_behav;
