--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1804 is 
  Port (
    lo8899: in std_logic;
    po335: inout std_logic
  );
end Other__carpat__part1804;

architecture Other__carpat__part1804_behav of Other__carpat__part1804 is
begin
    po335 <= ( lo8899 );
end Other__carpat__part1804_behav;
