--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part99 is 
  Port (
    pi0934: in std_logic;
    n31329_1: inout std_logic
  );
end Other__carpat__part99;

architecture Other__carpat__part99_behav of Other__carpat__part99 is
begin
    n31329_1 <= ( pi0934 );
end Other__carpat__part99_behav;
