--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part251 is 
  Port (
    lo1260: in std_logic;
    n8700_1: inout std_logic
  );
end Other__fp_operators__part251;

architecture Other__fp_operators__part251_behav of Other__fp_operators__part251 is
begin
    n8700_1 <= ( lo1260 );
end Other__fp_operators__part251_behav;
