--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part159 is 
  Port (
    pi1085: in std_logic;
    n31764_1: inout std_logic
  );
end Other__carpat__part159;

architecture Other__carpat__part159_behav of Other__carpat__part159 is
begin
    n31764_1 <= ( pi1085 );
end Other__carpat__part159_behav;
