--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2568 is 
  Port (
    lo7825: in std_logic;
    n39210_1: inout std_logic
  );
end IWLS2005__des_perf__part2568;

architecture IWLS2005__des_perf__part2568_behav of IWLS2005__des_perf__part2568 is
begin
    n39210_1 <= ( lo7825 );
end IWLS2005__des_perf__part2568_behav;
