--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part27 is 
  Port (
    pi0338: in std_logic;
    n19639: inout std_logic
  );
end Other__carpat__part27;

architecture Other__carpat__part27_behav of Other__carpat__part27 is
begin
    n19639 <= ( pi0338 );
end Other__carpat__part27_behav;
