--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1528 is 
  Port (
    lo8159: in std_logic;
    n45864_1: inout std_logic
  );
end Other__carpat__part1528;

architecture Other__carpat__part1528_behav of Other__carpat__part1528 is
begin
    n45864_1 <= ( lo8159 );
end Other__carpat__part1528_behav;
