--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2031 is 
  Port (
    lo2100: in std_logic;
    n10799: inout std_logic
  );
end Cookbook__fec_check__part2031;

architecture Cookbook__fec_check__part2031_behav of Cookbook__fec_check__part2031 is
begin
    n10799 <= ( lo2100 );
end Cookbook__fec_check__part2031_behav;
