--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1152 is 
  Port (
    lo5310: in std_logic;
    n26375: inout std_logic
  );
end IWLS2005__des_perf__part1152;

architecture IWLS2005__des_perf__part1152_behav of IWLS2005__des_perf__part1152 is
begin
    n26375 <= ( lo5310 );
end IWLS2005__des_perf__part1152_behav;
