--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part13 is 
  Port (
    pi039,pi103,pi038,pi102,pi037,pi101: in std_logic;
    n329_1: inout std_logic
  );
end Cookbook__pipe_equal__part13;

architecture Cookbook__pipe_equal__part13_behav of Cookbook__pipe_equal__part13 is
signal n253,n254,n255,n256: std_logic;
begin
    n253 <= ( not pi039 and pi103 )
      or ( pi039 and not pi103 );
    n254 <= ( not pi038 and pi102 )
      or ( pi038 and not pi102 );
    n255 <= ( not pi037 and pi101 )
      or ( pi037 and not pi101 );
    n256 <= not (( not n254 and not n255 ));
    n329_1 <= ( not n253 and not n256 );
end Cookbook__pipe_equal__part13_behav;
