--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part316 is 
  Port (
    lo0385: in std_logic;
    n2224: inout std_logic
  );
end Cookbook__fec_check__part316;

architecture Cookbook__fec_check__part316_behav of Cookbook__fec_check__part316 is
begin
    n2224 <= ( lo0385 );
end Cookbook__fec_check__part316_behav;
