--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part836 is 
  Port (
    lo6465: in std_logic;
    n30579_1: inout std_logic
  );
end Other__carpat__part836;

architecture Other__carpat__part836_behav of Other__carpat__part836 is
begin
    n30579_1 <= ( lo6465 );
end Other__carpat__part836_behav;
