--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part199 is 
  Port (
    lo185: in std_logic;
    po081: inout std_logic
  );
end Cookbook__lc_mult_signed__part199;

architecture Cookbook__lc_mult_signed__part199_behav of Cookbook__lc_mult_signed__part199 is
begin
    po081 <= ( lo185 );
end Cookbook__lc_mult_signed__part199_behav;
