--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part183 is 
  Port (
    lo0063: in std_logic;
    po63: inout std_logic
  );
end Other__desperf__part183;

architecture Other__desperf__part183_behav of Other__desperf__part183 is
begin
    po63 <= ( lo0063 );
end Other__desperf__part183_behav;
