--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1116 is 
  Port (
    lo4485: in std_logic;
    n17914: inout std_logic
  );
end Other__sudoku_check__part1116;

architecture Other__sudoku_check__part1116_behav of Other__sudoku_check__part1116 is
begin
    n17914 <= ( lo4485 );
end Other__sudoku_check__part1116_behav;
