--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part86 is 
  Port (
    lo100: in std_logic;
    n145: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part86;

architecture Cookbook__approx_fp_invsqrt__part86_behav of Cookbook__approx_fp_invsqrt__part86 is
begin
    n145 <= ( lo100 );
end Cookbook__approx_fp_invsqrt__part86_behav;
