--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1224 is 
  Port (
    lo1293: in std_logic;
    n6764: inout std_logic
  );
end Cookbook__fec_check__part1224;

architecture Cookbook__fec_check__part1224_behav of Cookbook__fec_check__part1224 is
begin
    n6764 <= ( lo1293 );
end Cookbook__fec_check__part1224_behav;
