--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part24 is 
  Port (
    lo0277: in std_logic;
    n2244: inout std_logic
  );
end LGSynth91__s38417__part24;

architecture LGSynth91__s38417__part24_behav of LGSynth91__s38417__part24 is
begin
    n2244 <= ( not lo0277 );
end LGSynth91__s38417__part24_behav;
