--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2173 is 
  Port (
    lo2242: in std_logic;
    n11509: inout std_logic
  );
end Cookbook__fec_check__part2173;

architecture Cookbook__fec_check__part2173_behav of Cookbook__fec_check__part2173 is
begin
    n11509 <= ( lo2242 );
end Cookbook__fec_check__part2173_behav;
