--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part40 is 
  Port (
    lo39: in std_logic;
    po29: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part40;

architecture Cookbook__x4_decoder_8b10b__part40_behav of Cookbook__x4_decoder_8b10b__part40 is
begin
    po29 <= ( lo39 );
end Cookbook__x4_decoder_8b10b__part40_behav;
