--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part293 is 
  Port (
    lo1425: in std_logic;
    n10050_1: inout std_logic
  );
end Other__fp_operators__part293;

architecture Other__fp_operators__part293_behav of Other__fp_operators__part293 is
begin
    n10050_1 <= ( lo1425 );
end Other__fp_operators__part293_behav;
