--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part120 is 
  Port (
    lo246: in std_logic;
    po092: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part120;

architecture Cookbook__soft_ecc_ram_64bit__part120_behav of Cookbook__soft_ecc_ram_64bit__part120 is
begin
    po092 <= ( lo246 );
end Cookbook__soft_ecc_ram_64bit__part120_behav;
