--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part209 is 
  Port (
    pi1269: in std_logic;
    n33339_1: inout std_logic
  );
end Other__carpat__part209;

architecture Other__carpat__part209_behav of Other__carpat__part209 is
begin
    n33339_1 <= ( pi1269 );
end Other__carpat__part209_behav;
