--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2024 is 
  Port (
    lo2093: in std_logic;
    n10764: inout std_logic
  );
end Cookbook__fec_check__part2024;

architecture Cookbook__fec_check__part2024_behav of Cookbook__fec_check__part2024 is
begin
    n10764 <= ( lo2093 );
end Cookbook__fec_check__part2024_behav;
