--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part130 is 
  Port (
    lo224: in std_logic;
    po11: inout std_logic
  );
end Cookbook__gearbox_40_67__part130;

architecture Cookbook__gearbox_40_67__part130_behav of Cookbook__gearbox_40_67__part130 is
begin
    po11 <= ( lo224 );
end Cookbook__gearbox_40_67__part130_behav;
