--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2259 is 
  Port (
    lo7451: in std_logic;
    n36985_1: inout std_logic
  );
end IWLS2005__des_perf__part2259;

architecture IWLS2005__des_perf__part2259_behav of IWLS2005__des_perf__part2259 is
begin
    n36985_1 <= ( lo7451 );
end IWLS2005__des_perf__part2259_behav;
