--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s6669__part25 is 
  Port (
    lo227: in std_logic;
    n607: inout std_logic
  );
end ISCAS__s6669__part25;

architecture ISCAS__s6669__part25_behav of ISCAS__s6669__part25 is
begin
    n607 <= ( not lo227 );
end ISCAS__s6669__part25_behav;
