--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1538 is 
  Port (
    lo1607: in std_logic;
    n8334: inout std_logic
  );
end Cookbook__fec_check__part1538;

architecture Cookbook__fec_check__part1538_behav of Cookbook__fec_check__part1538 is
begin
    n8334 <= ( lo1607 );
end Cookbook__fec_check__part1538_behav;
