--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part621 is 
  Port (
    lo5009: in std_logic;
    n22189: inout std_logic
  );
end Other__carpat__part621;

architecture Other__carpat__part621_behav of Other__carpat__part621 is
begin
    n22189 <= ( lo5009 );
end Other__carpat__part621_behav;
