--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part312 is 
  Port (
    lo03702: in std_logic;
    po6253,po6320,po6559,po6626: inout std_logic
  );
end Other__ray__part312;

architecture Other__ray__part312_behav of Other__ray__part312 is
begin
    po6253 <= ( lo03702 );
    po6320 <= ( lo03702 );
    po6559 <= ( lo03702 );
    po6626 <= ( lo03702 );
end Other__ray__part312_behav;
