--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1118 is 
  Port (
    lo7364: in std_logic;
    n40894_1: inout std_logic
  );
end Other__carpat__part1118;

architecture Other__carpat__part1118_behav of Other__carpat__part1118 is
begin
    n40894_1 <= ( lo7364 );
end Other__carpat__part1118_behav;
