--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1335 is 
  Port (
    lo3055: in std_logic;
    n19771: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1335;

architecture Other__ucsb_152_tap_fir__part1335_behav of Other__ucsb_152_tap_fir__part1335 is
begin
    n19771 <= ( lo3055 );
end Other__ucsb_152_tap_fir__part1335_behav;
