--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part839 is 
  Port (
    lo06598: in std_logic;
    n49326_1: inout std_logic
  );
end Other__ray__part839;

architecture Other__ray__part839_behav of Other__ray__part839 is
begin
    n49326_1 <= ( lo06598 );
end Other__ray__part839_behav;
