--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1668 is 
  Port (
    lo6373: in std_logic;
    n32065_1: inout std_logic
  );
end IWLS2005__des_perf__part1668;

architecture IWLS2005__des_perf__part1668_behav of IWLS2005__des_perf__part1668 is
begin
    n32065_1 <= ( lo6373 );
end IWLS2005__des_perf__part1668_behav;
