--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part560 is 
  Port (
    lo3209: in std_logic;
    n10519: inout std_logic
  );
end Other__sudoku_check__part560;

architecture Other__sudoku_check__part560_behav of Other__sudoku_check__part560 is
begin
    n10519 <= ( lo3209 );
end Other__sudoku_check__part560_behav;
