--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part193 is 
  Port (
    lo1463: in std_logic;
    po074: inout std_logic
  );
end LGSynth91__s38417__part193;

architecture LGSynth91__s38417__part193_behav of LGSynth91__s38417__part193 is
begin
    po074 <= ( lo1463 );
end LGSynth91__s38417__part193_behav;
