--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part80 is 
  Port (
    lo094: in std_logic;
    n115: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part80;

architecture Cookbook__approx_fp_invsqrt__part80_behav of Cookbook__approx_fp_invsqrt__part80 is
begin
    n115 <= ( lo094 );
end Cookbook__approx_fp_invsqrt__part80_behav;
