--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part17 is 
  Port (
    lo0008: in std_logic;
    n1299: inout std_logic
  );
end Cookbook__ucrypt__part17;

architecture Cookbook__ucrypt__part17_behav of Cookbook__ucrypt__part17 is
begin
    n1299 <= ( lo0008 );
end Cookbook__ucrypt__part17_behav;
