--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part102 is 
  Port (
    lo0344: in std_logic;
    n4190: inout std_logic
  );
end Other__fp_operators__part102;

architecture Other__fp_operators__part102_behav of Other__fp_operators__part102 is
begin
    n4190 <= ( lo0344 );
end Other__fp_operators__part102_behav;
