--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1358 is 
  Port (
    lo7808: in std_logic;
    n43919_1: inout std_logic
  );
end Other__carpat__part1358;

architecture Other__carpat__part1358_behav of Other__carpat__part1358 is
begin
    n43919_1 <= ( lo7808 );
end Other__carpat__part1358_behav;
