--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part472 is 
  Port (
    lo0541: in std_logic;
    n3004: inout std_logic
  );
end Cookbook__fec_check__part472;

architecture Cookbook__fec_check__part472_behav of Cookbook__fec_check__part472 is
begin
    n3004 <= ( lo0541 );
end Cookbook__fec_check__part472_behav;
