--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx__part14 is 
  Port (
    pi14: in std_logic;
    n215: inout std_logic
  );
end Cookbook__lane_rx__part14;

architecture Cookbook__lane_rx__part14_behav of Cookbook__lane_rx__part14 is
begin
    n215 <= ( pi14 );
end Cookbook__lane_rx__part14_behav;
