--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part69 is 
  Port (
    pi069: in std_logic;
    n9994_1: inout std_logic
  );
end Other__desperf__part69;

architecture Other__desperf__part69_behav of Other__desperf__part69 is
begin
    n9994_1 <= ( pi069 );
end Other__desperf__part69_behav;
