--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part270 is 
  Port (
    lo1089: in std_logic;
    n5955: inout std_logic
  );
end IWLS2005__des_perf__part270;

architecture IWLS2005__des_perf__part270_behav of IWLS2005__des_perf__part270 is
begin
    n5955 <= ( lo1089 );
end IWLS2005__des_perf__part270_behav;
