--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part46 is 
  Port (
    lo45: in std_logic;
    po45: inout std_logic
  );
end Other__idxlat01n_m12__part46;

architecture Other__idxlat01n_m12__part46_behav of Other__idxlat01n_m12__part46 is
begin
    po45 <= ( lo45 );
end Other__idxlat01n_m12__part46_behav;
