--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part22 is 
  Port (
    pi22: in std_logic;
    n1619: inout std_logic
  );
end Cookbook__gearbox_40_67__part22;

architecture Cookbook__gearbox_40_67__part22_behav of Cookbook__gearbox_40_67__part22 is
begin
    n1619 <= ( pi22 );
end Cookbook__gearbox_40_67__part22_behav;
