--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part264 is 
  Port (
    lo1049: in std_logic;
    n5765: inout std_logic
  );
end IWLS2005__des_perf__part264;

architecture IWLS2005__des_perf__part264_behav of IWLS2005__des_perf__part264 is
begin
    n5765 <= ( lo1049 );
end IWLS2005__des_perf__part264_behav;
