--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part744 is 
  Port (
    lo0813: in std_logic;
    n4364: inout std_logic
  );
end Cookbook__fec_check__part744;

architecture Cookbook__fec_check__part744_behav of Cookbook__fec_check__part744 is
begin
    n4364 <= ( lo0813 );
end Cookbook__fec_check__part744_behav;
