--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx_crc__part1 is 
  Port (
    lo000: in std_logic;
    n197: inout std_logic
  );
end Cookbook__lane_tx_crc__part1;

architecture Cookbook__lane_tx_crc__part1_behav of Cookbook__lane_tx_crc__part1 is
begin
    n197 <= ( lo000 );
end Cookbook__lane_tx_crc__part1_behav;
