--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part30 is 
  Port (
    pi030: in std_logic;
    n44235_1: inout std_logic
  );
end IWLS2005__des_perf__part30;

architecture IWLS2005__des_perf__part30_behav of IWLS2005__des_perf__part30 is
begin
    n44235_1 <= ( pi030 );
end IWLS2005__des_perf__part30_behav;
