--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1471 is 
  Port (
    lo3385: in std_logic;
    n21431: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1471;

architecture Other__ucsb_152_tap_fir__part1471_behav of Other__ucsb_152_tap_fir__part1471 is
begin
    n21431 <= ( lo3385 );
end Other__ucsb_152_tap_fir__part1471_behav;
