--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1757 is 
  Port (
    lo8828: in std_logic;
    po283: inout std_logic
  );
end Other__carpat__part1757;

architecture Other__carpat__part1757_behav of Other__carpat__part1757 is
begin
    po283 <= ( lo8828 );
end Other__carpat__part1757_behav;
