--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part58 is 
  Port (
    lo57: in std_logic;
    po57: inout std_logic
  );
end Other__idxlat10n_m12__part58;

architecture Other__idxlat10n_m12__part58_behav of Other__idxlat10n_m12__part58 is
begin
    po57 <= ( lo57 );
end Other__idxlat10n_m12__part58_behav;
