--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part307 is 
  Port (
    lo03697: in std_logic;
    po6248,po6315,po6554,po6621: inout std_logic
  );
end Other__ray__part307;

architecture Other__ray__part307_behav of Other__ray__part307 is
begin
    po6248 <= ( lo03697 );
    po6315 <= ( lo03697 );
    po6554 <= ( lo03697 );
    po6621 <= ( lo03697 );
end Other__ray__part307_behav;
