--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2137 is 
  Port (
    lo4743: in std_logic;
    n28216: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2137;

architecture Other__ucsb_152_tap_fir__part2137_behav of Other__ucsb_152_tap_fir__part2137 is
begin
    n28216 <= ( lo4743 );
end Other__ucsb_152_tap_fir__part2137_behav;
