--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part135 is 
  Port (
    lo121: in std_logic;
    po145: inout std_logic
  );
end Cookbook__lc_mult_signed__part135;

architecture Cookbook__lc_mult_signed__part135_behav of Cookbook__lc_mult_signed__part135 is
begin
    po145 <= ( lo121 );
end Cookbook__lc_mult_signed__part135_behav;
