--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part83 is 
  Port (
    lo258,lo259,lo271,lo250,lo254,lo251,lo255,lo252,lo256,lo253,lo257,lo260,lo262,lo261,lo263: in std_logic;
    n1537_1,n1542,n1547_1,n1552_1,n1557,n1562_1,n1567_1: inout std_logic
  );
end Cookbook__gearbox_67_40__part83;

architecture Cookbook__gearbox_67_40__part83_behav of Cookbook__gearbox_67_40__part83 is
begin
    n1537_1 <= ( lo258 and not lo271 )
      or ( lo259 and lo271 );
    n1542 <= ( lo250 and not lo271 )
      or ( lo254 and lo271 );
    n1547_1 <= ( lo251 and not lo271 )
      or ( lo255 and lo271 );
    n1552_1 <= ( lo252 and not lo271 )
      or ( lo256 and lo271 );
    n1557 <= ( lo253 and not lo271 )
      or ( lo257 and lo271 );
    n1562_1 <= ( lo260 and not lo271 )
      or ( lo262 and lo271 );
    n1567_1 <= ( lo261 and not lo271 )
      or ( lo263 and lo271 );
end Cookbook__gearbox_67_40__part83_behav;
