--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part249 is 
  Port (
    lo235: in std_logic;
    po031: inout std_logic
  );
end Cookbook__lc_mult_signed__part249;

architecture Cookbook__lc_mult_signed__part249_behav of Cookbook__lc_mult_signed__part249 is
begin
    po031 <= ( lo235 );
end Cookbook__lc_mult_signed__part249_behav;
