--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1235 is 
  Port (
    lo2862: in std_logic;
    n18876: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1235;

architecture Other__ucsb_152_tap_fir__part1235_behav of Other__ucsb_152_tap_fir__part1235 is
begin
    n18876 <= ( lo2862 );
end Other__ucsb_152_tap_fir__part1235_behav;
