--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part54 is 
  Port (
    lo282: in std_logic;
    po054: inout std_logic
  );
end IWLS2005__aes_core__part54;

architecture IWLS2005__aes_core__part54_behav of IWLS2005__aes_core__part54 is
begin
    po054 <= ( lo282 );
end IWLS2005__aes_core__part54_behav;
