--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1348 is 
  Port (
    lo3116: in std_logic;
    n20096: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1348;

architecture Other__ucsb_152_tap_fir__part1348_behav of Other__ucsb_152_tap_fir__part1348 is
begin
    n20096 <= ( lo3116 );
end Other__ucsb_152_tap_fir__part1348_behav;
