--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i10__part1 is 
  Port (
    pi032: in std_logic;
    po039: inout std_logic
  );
end LGSynth91__i10__part1;

architecture LGSynth91__i10__part1_behav of LGSynth91__i10__part1 is
begin
    po039 <= ( not pi032 );
end LGSynth91__i10__part1_behav;
