--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part31 is 
  Port (
    pi31: in std_logic;
    n544143: inout std_logic
  );
end IWLS2005__leon3mp__part31;

architecture IWLS2005__leon3mp__part31_behav of IWLS2005__leon3mp__part31 is
begin
    n544143 <= ( pi31 );
end IWLS2005__leon3mp__part31_behav;
