--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part71 is 
  Port (
    lo305: in std_logic;
    po002: inout std_logic
  );
end IWLS2005__aes_core__part71;

architecture IWLS2005__aes_core__part71_behav of IWLS2005__aes_core__part71 is
begin
    po002 <= ( lo305 );
end IWLS2005__aes_core__part71_behav;
