--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1398 is 
  Port (
    lo7848: in std_logic;
    n44119_1: inout std_logic
  );
end Other__carpat__part1398;

architecture Other__carpat__part1398_behav of Other__carpat__part1398 is
begin
    n44119_1 <= ( lo7848 );
end Other__carpat__part1398_behav;
