--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3233 is 
  Port (
    lo8576: in std_logic;
    n43235_1: inout std_logic
  );
end IWLS2005__des_perf__part3233;

architecture IWLS2005__des_perf__part3233_behav of IWLS2005__des_perf__part3233 is
begin
    n43235_1 <= ( lo8576 );
end IWLS2005__des_perf__part3233_behav;
