--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2541 is 
  Port (
    lo5588: in std_logic;
    n32526: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2541;

architecture Other__ucsb_152_tap_fir__part2541_behav of Other__ucsb_152_tap_fir__part2541 is
begin
    n32526 <= ( lo5588 );
end Other__ucsb_152_tap_fir__part2541_behav;
