--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part804 is 
  Port (
    lo0873: in std_logic;
    n4664: inout std_logic
  );
end Cookbook__fec_check__part804;

architecture Cookbook__fec_check__part804_behav of Cookbook__fec_check__part804 is
begin
    n4664 <= ( lo0873 );
end Cookbook__fec_check__part804_behav;
