--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part125 is 
  Port (
    lo0005: in std_logic;
    po05: inout std_logic
  );
end Other__desperf__part125;

architecture Other__desperf__part125_behav of Other__desperf__part125 is
begin
    po05 <= ( lo0005 );
end Other__desperf__part125_behav;
