--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1913 is 
  Port (
    lo4296: in std_logic;
    n26066: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1913;

architecture Other__ucsb_152_tap_fir__part1913_behav of Other__ucsb_152_tap_fir__part1913 is
begin
    n26066 <= ( lo4296 );
end Other__ucsb_152_tap_fir__part1913_behav;
