--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part25 is 
  Port (
    lo23: in std_logic;
    po16: inout std_logic
  );
end Cookbook__pipeline_add__part25;

architecture Cookbook__pipeline_add__part25_behav of Cookbook__pipeline_add__part25 is
begin
    po16 <= ( lo23 );
end Cookbook__pipeline_add__part25_behav;
