--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part198 is 
  Port (
    lo0637: in std_logic;
    n4444: inout std_logic
  );
end Cookbook__ucrypt__part198;

architecture Cookbook__ucrypt__part198_behav of Cookbook__ucrypt__part198 is
begin
    n4444 <= ( lo0637 );
end Cookbook__ucrypt__part198_behav;
