--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part197 is 
  Port (
    lo0636: in std_logic;
    n4439: inout std_logic
  );
end Cookbook__ucrypt__part197;

architecture Cookbook__ucrypt__part197_behav of Cookbook__ucrypt__part197 is
begin
    n4439 <= ( lo0636 );
end Cookbook__ucrypt__part197_behav;
