--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part644 is 
  Port (
    lo06141: in std_logic;
    po1707,po1802: inout std_logic
  );
end Other__ray__part644;

architecture Other__ray__part644_behav of Other__ray__part644 is
begin
    po1707 <= ( lo06141 );
    po1802 <= ( lo06141 );
end Other__ray__part644_behav;
