--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1789 is 
  Port (
    lo1858: in std_logic;
    n9589: inout std_logic
  );
end Cookbook__fec_check__part1789;

architecture Cookbook__fec_check__part1789_behav of Cookbook__fec_check__part1789 is
begin
    n9589 <= ( lo1858 );
end Cookbook__fec_check__part1789_behav;
