--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part282 is 
  Port (
    pi1539: in std_logic;
    n44904_1: inout std_logic
  );
end Other__carpat__part282;

architecture Other__carpat__part282_behav of Other__carpat__part282 is
begin
    n44904_1 <= ( pi1539 );
end Other__carpat__part282_behav;
