--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr__part8 is 
  Port (
    lo14: in std_logic;
    n140,po17: inout std_logic
  );
end Cookbook__lfsr__part8;

architecture Cookbook__lfsr__part8_behav of Cookbook__lfsr__part8 is
begin
    n140 <= ( lo14 );
    po17 <= ( lo14 );
end Cookbook__lfsr__part8_behav;
