--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part109 is 
  Port (
    lo0351: in std_logic;
    n4370: inout std_logic
  );
end Other__fp_operators__part109;

architecture Other__fp_operators__part109_behav of Other__fp_operators__part109 is
begin
    n4370 <= ( lo0351 );
end Other__fp_operators__part109_behav;
