--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part9 is 
  Port (
    lo0078: in std_logic;
    n689: inout std_logic
  );
end Cookbook__fec_check__part9;

architecture Cookbook__fec_check__part9_behav of Cookbook__fec_check__part9 is
begin
    n689 <= ( lo0078 );
end Cookbook__fec_check__part9_behav;
