--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part341 is 
  Port (
    lo05646: in std_logic;
    po6038,po6105,po6344,po6411: inout std_logic
  );
end Other__ray__part341;

architecture Other__ray__part341_behav of Other__ray__part341 is
begin
    po6038 <= ( lo05646 );
    po6105 <= ( lo05646 );
    po6344 <= ( lo05646 );
    po6411 <= ( lo05646 );
end Other__ray__part341_behav;
