--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part100 is 
  Port (
    lo337: in std_logic;
    po035: inout std_logic
  );
end IWLS2005__aes_core__part100;

architecture IWLS2005__aes_core__part100_behav of IWLS2005__aes_core__part100 is
begin
    po035 <= ( lo337 );
end IWLS2005__aes_core__part100_behav;
