--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1010 is 
  Port (
    lo2373: in std_logic;
    n16371: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1010;

architecture Other__ucsb_152_tap_fir__part1010_behav of Other__ucsb_152_tap_fir__part1010 is
begin
    n16371 <= ( lo2373 );
end Other__ucsb_152_tap_fir__part1010_behav;
