--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part43 is 
  Port (
    lo61: in std_logic;
    n368_1: inout std_logic
  );
end Cookbook__mlab_dcfifo__part43;

architecture Cookbook__mlab_dcfifo__part43_behav of Cookbook__mlab_dcfifo__part43 is
begin
    n368_1 <= ( lo61 );
end Cookbook__mlab_dcfifo__part43_behav;
