--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part9 is 
  Port (
    lo05: in std_logic;
    po04: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part9;

architecture Cookbook__x4_encoder_8b10b__part9_behav of Cookbook__x4_encoder_8b10b__part9 is
begin
    po04 <= ( lo05 );
end Cookbook__x4_encoder_8b10b__part9_behav;
