--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part467 is 
  Port (
    lo1690: in std_logic;
    n9709_1: inout std_logic
  );
end Cookbook__ucrypt__part467;

architecture Cookbook__ucrypt__part467_behav of Cookbook__ucrypt__part467 is
begin
    n9709_1 <= ( lo1690 );
end Cookbook__ucrypt__part467_behav;
