--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1378 is 
  Port (
    lo1447: in std_logic;
    n7534: inout std_logic
  );
end Cookbook__fec_check__part1378;

architecture Cookbook__fec_check__part1378_behav of Cookbook__fec_check__part1378 is
begin
    n7534 <= ( lo1447 );
end Cookbook__fec_check__part1378_behav;
