--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part457 is 
  Port (
    lo0526: in std_logic;
    n2929: inout std_logic
  );
end Cookbook__fec_check__part457;

architecture Cookbook__fec_check__part457_behav of Cookbook__fec_check__part457 is
begin
    n2929 <= ( lo0526 );
end Cookbook__fec_check__part457_behav;
