--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1074 is 
  Port (
    lo1143: in std_logic;
    n6014: inout std_logic
  );
end Cookbook__fec_check__part1074;

architecture Cookbook__fec_check__part1074_behav of Cookbook__fec_check__part1074 is
begin
    n6014 <= ( lo1143 );
end Cookbook__fec_check__part1074_behav;
