--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1551 is 
  Port (
    lo6139: in std_logic;
    n31065_1: inout std_logic
  );
end IWLS2005__des_perf__part1551;

architecture IWLS2005__des_perf__part1551_behav of IWLS2005__des_perf__part1551 is
begin
    n31065_1 <= ( lo6139 );
end IWLS2005__des_perf__part1551_behav;
