--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part575 is 
  Port (
    lo3224: in std_logic;
    n10669: inout std_logic
  );
end Other__sudoku_check__part575;

architecture Other__sudoku_check__part575_behav of Other__sudoku_check__part575 is
begin
    n10669 <= ( lo3224 );
end Other__sudoku_check__part575_behav;
