--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part185 is 
  Port (
    lo0782: in std_logic;
    n6040: inout std_logic
  );
end Other__fp_operators__part185;

architecture Other__fp_operators__part185_behav of Other__fp_operators__part185 is
begin
    n6040 <= ( lo0782 );
end Other__fp_operators__part185_behav;
