--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part145 is 
  Port (
    lo0024: in std_logic;
    po34: inout std_logic
  );
end IWLS2005__des_perf__part145;

architecture IWLS2005__des_perf__part145_behav of IWLS2005__des_perf__part145 is
begin
    po34 <= ( lo0024 );
end IWLS2005__des_perf__part145_behav;
