--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part132 is 
  Port (
    lo184938: in std_logic;
    n924616: inout std_logic
  );
end IWLS2005__leon3__part132;

architecture IWLS2005__leon3__part132_behav of IWLS2005__leon3__part132 is
begin
    n924616 <= ( lo184938 );
end IWLS2005__leon3__part132_behav;
