--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part736 is 
  Port (
    lo3385: in std_logic;
    n12279: inout std_logic
  );
end Other__sudoku_check__part736;

architecture Other__sudoku_check__part736_behav of Other__sudoku_check__part736 is
begin
    n12279 <= ( lo3385 );
end Other__sudoku_check__part736_behav;
