--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2115 is 
  Port (
    lo2184: in std_logic;
    n11219: inout std_logic
  );
end Cookbook__fec_check__part2115;

architecture Cookbook__fec_check__part2115_behav of Cookbook__fec_check__part2115 is
begin
    n11219 <= ( lo2184 );
end Cookbook__fec_check__part2115_behav;
