--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part38 is 
  Port (
    lo37: in std_logic;
    po31: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part38;

architecture Cookbook__x4_decoder_8b10b__part38_behav of Cookbook__x4_decoder_8b10b__part38 is
begin
    po31 <= ( lo37 );
end Cookbook__x4_decoder_8b10b__part38_behav;
