--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1920 is 
  Port (
    lo4303: in std_logic;
    n26101: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1920;

architecture Other__ucsb_152_tap_fir__part1920_behav of Other__ucsb_152_tap_fir__part1920 is
begin
    n26101 <= ( lo4303 );
end Other__ucsb_152_tap_fir__part1920_behav;
