--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2191 is 
  Port (
    lo7354: in std_logic;
    n36620_1: inout std_logic
  );
end IWLS2005__des_perf__part2191;

architecture IWLS2005__des_perf__part2191_behav of IWLS2005__des_perf__part2191 is
begin
    n36620_1 <= ( lo7354 );
end IWLS2005__des_perf__part2191_behav;
