--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part659 is 
  Port (
    lo4305: in std_logic;
    n21500: inout std_logic
  );
end IWLS2005__des_perf__part659;

architecture IWLS2005__des_perf__part659_behav of IWLS2005__des_perf__part659 is
begin
    n21500 <= ( lo4305 );
end IWLS2005__des_perf__part659_behav;
