--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part55 is 
  Port (
    lo507: in std_logic;
    n2713_1: inout std_logic
  );
end Cookbook__lane_tx__part55;

architecture Cookbook__lane_tx__part55_behav of Cookbook__lane_tx__part55 is
begin
    n2713_1 <= ( lo507 );
end Cookbook__lane_tx__part55_behav;
