--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part210 is 
  Port (
    lo0279: in std_logic;
    n1694: inout std_logic
  );
end Cookbook__fec_check__part210;

architecture Cookbook__fec_check__part210_behav of Cookbook__fec_check__part210 is
begin
    n1694 <= ( lo0279 );
end Cookbook__fec_check__part210_behav;
