--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part129 is 
  Port (
    lo0985: in std_logic;
    po139: inout std_logic
  );
end IWLS2005__mem_ctrl__part129;

architecture IWLS2005__mem_ctrl__part129_behav of IWLS2005__mem_ctrl__part129 is
begin
    po139 <= ( lo0985 );
end IWLS2005__mem_ctrl__part129_behav;
