--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx_crc__part3 is 
  Port (
    lo035: in std_logic;
    n315: inout std_logic
  );
end Cookbook__lane_rx_crc__part3;

architecture Cookbook__lane_rx_crc__part3_behav of Cookbook__lane_rx_crc__part3 is
begin
    n315 <= ( lo035 );
end Cookbook__lane_rx_crc__part3_behav;
