--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part175 is 
  Port (
    lo0416: in std_logic;
    n6596: inout std_logic
  );
end Other__ucsb_152_tap_fir__part175;

architecture Other__ucsb_152_tap_fir__part175_behav of Other__ucsb_152_tap_fir__part175 is
begin
    n6596 <= ( lo0416 );
end Other__ucsb_152_tap_fir__part175_behav;
