--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part956 is 
  Port (
    lo1025: in std_logic;
    n5424: inout std_logic
  );
end Cookbook__fec_check__part956;

architecture Cookbook__fec_check__part956_behav of Cookbook__fec_check__part956 is
begin
    n5424 <= ( lo1025 );
end Cookbook__fec_check__part956_behav;
