--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part36 is 
  Port (
    lo2125: in std_logic;
    n5279: inout std_logic
  );
end Other__sudoku_check__part36;

architecture Other__sudoku_check__part36_behav of Other__sudoku_check__part36 is
begin
    n5279 <= ( lo2125 );
end Other__sudoku_check__part36_behav;
