--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1016 is 
  Port (
    lo4385: in std_logic;
    n17414: inout std_logic
  );
end Other__sudoku_check__part1016;

architecture Other__sudoku_check__part1016_behav of Other__sudoku_check__part1016 is
begin
    n17414 <= ( lo4385 );
end Other__sudoku_check__part1016_behav;
