--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part717 is 
  Port (
    lo5249: in std_logic;
    n25209: inout std_logic
  );
end Other__carpat__part717;

architecture Other__carpat__part717_behav of Other__carpat__part717 is
begin
    n25209 <= ( lo5249 );
end Other__carpat__part717_behav;
