--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2228 is 
  Port (
    lo4920: in std_logic;
    n29186: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2228;

architecture Other__ucsb_152_tap_fir__part2228_behav of Other__ucsb_152_tap_fir__part2228 is
begin
    n29186 <= ( lo4920 );
end Other__ucsb_152_tap_fir__part2228_behav;
