--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part21 is 
  Port (
    lo0015: in std_logic;
    n834: inout std_logic
  );
end IWLS93__s38417__part21;

architecture IWLS93__s38417__part21_behav of IWLS93__s38417__part21 is
begin
    n834 <= ( lo0015 );
end IWLS93__s38417__part21_behav;
