--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part162 is 
  Port (
    pi1088: in std_logic;
    n31864: inout std_logic
  );
end Other__carpat__part162;

architecture Other__carpat__part162_behav of Other__carpat__part162 is
begin
    n31864 <= ( pi1088 );
end Other__carpat__part162_behav;
