--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part278 is 
  Port (
    lo466: in std_logic;
    n1617: inout std_logic
  );
end Other__fpu__part278;

architecture Other__fpu__part278_behav of Other__fpu__part278 is
begin
    n1617 <= ( lo466 );
end Other__fpu__part278_behav;
