--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1425 is 
  Port (
    lo1494: in std_logic;
    n7769: inout std_logic
  );
end Cookbook__fec_check__part1425;

architecture Cookbook__fec_check__part1425_behav of Cookbook__fec_check__part1425 is
begin
    n7769 <= ( lo1494 );
end Cookbook__fec_check__part1425_behav;
