--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part951 is 
  Port (
    lo10532: in std_logic;
    po0971: inout std_logic
  );
end Other__ray__part951;

architecture Other__ray__part951_behav of Other__ray__part951 is
begin
    po0971 <= ( lo10532 );
end Other__ray__part951_behav;
