--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part846 is 
  Port (
    lo06605: in std_logic;
    n49361_1: inout std_logic
  );
end Other__ray__part846;

architecture Other__ray__part846_behav of Other__ray__part846 is
begin
    n49361_1 <= ( lo06605 );
end Other__ray__part846_behav;
