--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part175 is 
  Port (
    lo274: in std_logic;
    n882: inout std_logic
  );
end Other__fpu__part175;

architecture Other__fpu__part175_behav of Other__fpu__part175 is
begin
    n882 <= ( lo274 );
end Other__fpu__part175_behav;
