--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1762 is 
  Port (
    lo1831: in std_logic;
    n9454: inout std_logic
  );
end Cookbook__fec_check__part1762;

architecture Cookbook__fec_check__part1762_behav of Cookbook__fec_check__part1762 is
begin
    n9454 <= ( lo1831 );
end Cookbook__fec_check__part1762_behav;
