--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part62 is 
  Port (
    pi062: in std_logic;
    n9959_1: inout std_logic
  );
end Other__desperf__part62;

architecture Other__desperf__part62_behav of Other__desperf__part62 is
begin
    n9959_1 <= ( pi062 );
end Other__desperf__part62_behav;
