--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part52 is 
  Port (
    lo066: in std_logic;
    po27: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part52;

architecture Cookbook__approx_fp_invsqrt__part52_behav of Cookbook__approx_fp_invsqrt__part52 is
begin
    po27 <= ( lo066 );
end Cookbook__approx_fp_invsqrt__part52_behav;
