--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1508 is 
  Port (
    lo5641,lo5642,lo5643,lo5644: in std_logic;
    n27159_1,n29224,n29229,n29234,n29239,n29244,n29249,n29254_1,n29259_1: inout std_logic
  );
end Other__sudoku_check__part1508;

architecture Other__sudoku_check__part1508_behav of Other__sudoku_check__part1508 is
begin
    n27159_1 <= ( lo5641 and not lo5642 and not lo5643 and not lo5644 );
    n29224 <= ( lo5641 and not lo5642 and not lo5643 and lo5644 );
    n29229 <= ( not lo5641 and not lo5642 and not lo5643 and lo5644 );
    n29234 <= ( lo5641 and lo5642 and lo5643 and not lo5644 );
    n29239 <= ( not lo5641 and lo5642 and lo5643 and not lo5644 );
    n29244 <= ( lo5641 and not lo5642 and lo5643 and not lo5644 );
    n29249 <= ( not lo5641 and not lo5642 and lo5643 and not lo5644 );
    n29254_1 <= ( lo5641 and lo5642 and not lo5643 and not lo5644 );
    n29259_1 <= ( not lo5641 and lo5642 and not lo5643 and not lo5644 );
end Other__sudoku_check__part1508_behav;
