--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2802 is 
  Port (
    lo8115: in std_logic;
    n40800_1: inout std_logic
  );
end IWLS2005__des_perf__part2802;

architecture IWLS2005__des_perf__part2802_behav of IWLS2005__des_perf__part2802 is
begin
    n40800_1 <= ( lo8115 );
end IWLS2005__des_perf__part2802_behav;
