--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part356 is 
  Port (
    lo2118: in std_logic;
    n11055: inout std_logic
  );
end IWLS2005__des_perf__part356;

architecture IWLS2005__des_perf__part356_behav of IWLS2005__des_perf__part356 is
begin
    n11055 <= ( lo2118 );
end IWLS2005__des_perf__part356_behav;
