--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part212 is 
  Port (
    lo03259: in std_logic;
    n34071: inout std_logic
  );
end Other__ray__part212;

architecture Other__ray__part212_behav of Other__ray__part212 is
begin
    n34071 <= ( lo03259 );
end Other__ray__part212_behav;
