--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part39 is 
  Port (
    lo0292: in std_logic;
    n1734: inout std_logic
  );
end LGSynth91__s38417__part39;

architecture LGSynth91__s38417__part39_behav of LGSynth91__s38417__part39 is
begin
    n1734 <= ( lo0292 );
end LGSynth91__s38417__part39_behav;
