--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part145 is 
  Port (
    lo1071: in std_logic;
    n5629_1: inout std_logic
  );
end ISCAS__s38417__part145;

architecture ISCAS__s38417__part145_behav of ISCAS__s38417__part145 is
begin
    n5629_1 <= ( lo1071 );
end ISCAS__s38417__part145_behav;
