--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2284 is 
  Port (
    lo7483: in std_logic;
    n37320_1: inout std_logic
  );
end IWLS2005__des_perf__part2284;

architecture IWLS2005__des_perf__part2284_behav of IWLS2005__des_perf__part2284 is
begin
    n37320_1 <= ( lo7483 );
end IWLS2005__des_perf__part2284_behav;
