--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1023 is 
  Port (
    lo4392: in std_logic;
    n17449: inout std_logic
  );
end Other__sudoku_check__part1023;

architecture Other__sudoku_check__part1023_behav of Other__sudoku_check__part1023 is
begin
    n17449 <= ( lo4392 );
end Other__sudoku_check__part1023_behav;
