--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part127 is 
  Port (
    lo113: in std_logic;
    po153: inout std_logic
  );
end Cookbook__lc_mult_signed__part127;

architecture Cookbook__lc_mult_signed__part127_behav of Cookbook__lc_mult_signed__part127 is
begin
    po153 <= ( lo113 );
end Cookbook__lc_mult_signed__part127_behav;
