--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2902 is 
  Port (
    lo8215: in std_logic;
    n41515_1: inout std_logic
  );
end IWLS2005__des_perf__part2902;

architecture IWLS2005__des_perf__part2902_behav of IWLS2005__des_perf__part2902 is
begin
    n41515_1 <= ( lo8215 );
end IWLS2005__des_perf__part2902_behav;
