--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part444 is 
  Port (
    lo1635: in std_logic;
    n9284_1: inout std_logic
  );
end Cookbook__ucrypt__part444;

architecture Cookbook__ucrypt__part444_behav of Cookbook__ucrypt__part444 is
begin
    n9284_1 <= ( lo1635 );
end Cookbook__ucrypt__part444_behav;
