--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part518 is 
  Port (
    lo05990: in std_logic;
    po1505,po1539: inout std_logic
  );
end Other__ray__part518;

architecture Other__ray__part518_behav of Other__ray__part518 is
begin
    po1505 <= ( lo05990 );
    po1539 <= ( lo05990 );
end Other__ray__part518_behav;
