--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part637 is 
  Port (
    lo4283: in std_logic;
    n21415: inout std_logic
  );
end IWLS2005__des_perf__part637;

architecture IWLS2005__des_perf__part637_behav of IWLS2005__des_perf__part637 is
begin
    n21415 <= ( lo4283 );
end IWLS2005__des_perf__part637_behav;
