--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part764 is 
  Port (
    lo06444: in std_logic;
    n48481: inout std_logic
  );
end Other__ray__part764;

architecture Other__ray__part764_behav of Other__ray__part764 is
begin
    n48481 <= ( lo06444 );
end Other__ray__part764_behav;
