--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part81 is 
  Port (
    lo248: in std_logic;
    po02: inout std_logic
  );
end Cookbook__gearbox_67_40__part81;

architecture Cookbook__gearbox_67_40__part81_behav of Cookbook__gearbox_67_40__part81 is
begin
    po02 <= ( lo248 );
end Cookbook__gearbox_67_40__part81_behav;
