--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part196 is 
  Port (
    lo0793: in std_logic;
    n6105: inout std_logic
  );
end Other__fp_operators__part196;

architecture Other__fp_operators__part196_behav of Other__fp_operators__part196 is
begin
    n6105 <= ( lo0793 );
end Other__fp_operators__part196_behav;
