--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1980 is 
  Port (
    lo7008: in std_logic;
    n34905_1: inout std_logic
  );
end IWLS2005__des_perf__part1980;

architecture IWLS2005__des_perf__part1980_behav of IWLS2005__des_perf__part1980 is
begin
    n34905_1 <= ( lo7008 );
end IWLS2005__des_perf__part1980_behav;
