--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part122 is 
  Port (
    lo005: in std_logic;
    po005: inout std_logic
  );
end Other__fpu__part122;

architecture Other__fpu__part122_behav of Other__fpu__part122 is
begin
    po005 <= ( lo005 );
end Other__fpu__part122_behav;
