--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part16 is 
  Port (
    pi16: in std_logic;
    n1649: inout std_logic
  );
end Cookbook__gearbox_40_67__part16;

architecture Cookbook__gearbox_40_67__part16_behav of Cookbook__gearbox_40_67__part16 is
begin
    n1649 <= ( pi16 );
end Cookbook__gearbox_40_67__part16_behav;
