--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1297 is 
  Port (
    lo1366: in std_logic;
    n7129: inout std_logic
  );
end Cookbook__fec_check__part1297;

architecture Cookbook__fec_check__part1297_behav of Cookbook__fec_check__part1297 is
begin
    n7129 <= ( lo1366 );
end Cookbook__fec_check__part1297_behav;
