--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2077 is 
  Port (
    lo2146: in std_logic;
    n11029: inout std_logic
  );
end Cookbook__fec_check__part2077;

architecture Cookbook__fec_check__part2077_behav of Cookbook__fec_check__part2077 is
begin
    n11029 <= ( lo2146 );
end Cookbook__fec_check__part2077_behav;
