--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part550 is 
  Port (
    lo06025: in std_logic;
    n36901: inout std_logic
  );
end Other__ray__part550;

architecture Other__ray__part550_behav of Other__ray__part550 is
begin
    n36901 <= ( lo06025 );
end Other__ray__part550_behav;
