--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part32 is 
  Port (
    lo0132: in std_logic;
    po371: inout std_logic
  );
end Other__cfft__part32;

architecture Other__cfft__part32_behav of Other__cfft__part32 is
begin
    po371 <= ( lo0132 );
end Other__cfft__part32_behav;
