--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part47 is 
  Port (
    lo033: in std_logic;
    po233: inout std_logic
  );
end Cookbook__lc_mult_signed__part47;

architecture Cookbook__lc_mult_signed__part47_behav of Cookbook__lc_mult_signed__part47 is
begin
    po233 <= ( lo033 );
end Cookbook__lc_mult_signed__part47_behav;
