--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part252 is 
  Port (
    lo1125: in std_logic;
    n5164: inout std_logic
  );
end Other__desperf__part252;

architecture Other__desperf__part252_behav of Other__desperf__part252 is
begin
    n5164 <= ( lo1125 );
end Other__desperf__part252_behav;
