--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part59 is 
  Port (
    lo58: in std_logic;
    po58: inout std_logic
  );
end Other__idxlat00n_m12__part59;

architecture Other__idxlat00n_m12__part59_behav of Other__idxlat00n_m12__part59 is
begin
    po58 <= ( lo58 );
end Other__idxlat00n_m12__part59_behav;
