--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part492 is 
  Port (
    lo1827: in std_logic;
    n10394_1: inout std_logic
  );
end Cookbook__ucrypt__part492;

architecture Cookbook__ucrypt__part492_behav of Cookbook__ucrypt__part492 is
begin
    n10394_1 <= ( lo1827 );
end Cookbook__ucrypt__part492_behav;
