--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part580 is 
  Port (
    lo3229: in std_logic;
    n10719: inout std_logic
  );
end Other__sudoku_check__part580;

architecture Other__sudoku_check__part580_behav of Other__sudoku_check__part580 is
begin
    n10719 <= ( lo3229 );
end Other__sudoku_check__part580_behav;
