--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1096 is 
  Port (
    lo4465: in std_logic;
    n17814: inout std_logic
  );
end Other__sudoku_check__part1096;

architecture Other__sudoku_check__part1096_behav of Other__sudoku_check__part1096 is
begin
    n17814 <= ( lo4465 );
end Other__sudoku_check__part1096_behav;
