--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_20__part39 is 
  Port (
    lo113: in std_logic;
    po02: inout std_logic
  );
end Cookbook__gearbox_66_20__part39;

architecture Cookbook__gearbox_66_20__part39_behav of Cookbook__gearbox_66_20__part39 is
begin
    po02 <= ( lo113 );
end Cookbook__gearbox_66_20__part39_behav;
