--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part217 is 
  Port (
    lo203: in std_logic;
    po063: inout std_logic
  );
end Cookbook__lc_mult_signed__part217;

architecture Cookbook__lc_mult_signed__part217_behav of Cookbook__lc_mult_signed__part217 is
begin
    po063 <= ( lo203 );
end Cookbook__lc_mult_signed__part217_behav;
