--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part32 is 
  Port (
    lo29: in std_logic;
    n286: inout std_logic
  );
end Cookbook__approx_fp_div__part32;

architecture Cookbook__approx_fp_div__part32_behav of Cookbook__approx_fp_div__part32 is
begin
    n286 <= ( lo29 );
end Cookbook__approx_fp_div__part32_behav;
