--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1124 is 
  Port (
    lo4493: in std_logic;
    n17954: inout std_logic
  );
end Other__sudoku_check__part1124;

architecture Other__sudoku_check__part1124_behav of Other__sudoku_check__part1124 is
begin
    n17954 <= ( lo4493 );
end Other__sudoku_check__part1124_behav;
