--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1092 is 
  Port (
    lo4461: in std_logic;
    n17794: inout std_logic
  );
end Other__sudoku_check__part1092;

architecture Other__sudoku_check__part1092_behav of Other__sudoku_check__part1092 is
begin
    n17794 <= ( lo4461 );
end Other__sudoku_check__part1092_behav;
