--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__prolog__part1 is 
  Port (
    pi16: in std_logic;
    n465: inout std_logic
  );
end ISCAS__prolog__part1;

architecture ISCAS__prolog__part1_behav of ISCAS__prolog__part1 is
begin
    n465 <= ( pi16 );
end ISCAS__prolog__part1_behav;
