--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__eightbyeight_sad__part25 is 
  Port (
    lo332: in std_logic;
    po03: inout std_logic
  );
end Cookbook__eightbyeight_sad__part25;

architecture Cookbook__eightbyeight_sad__part25_behav of Cookbook__eightbyeight_sad__part25 is
begin
    po03 <= ( lo332 );
end Cookbook__eightbyeight_sad__part25_behav;
