--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part936 is 
  Port (
    lo10515: in std_logic;
    n68941_1: inout std_logic
  );
end Other__ray__part936;

architecture Other__ray__part936_behav of Other__ray__part936 is
begin
    n68941_1 <= ( lo10515 );
end Other__ray__part936_behav;
