--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part140 is 
  Port (
    lo126: in std_logic;
    po140: inout std_logic
  );
end Cookbook__lc_mult_signed__part140;

architecture Cookbook__lc_mult_signed__part140_behav of Cookbook__lc_mult_signed__part140 is
begin
    po140 <= ( lo126 );
end Cookbook__lc_mult_signed__part140_behav;
