--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part255 is 
  Port (
    lo1273: in std_logic;
    n8920_1: inout std_logic
  );
end Other__fp_operators__part255;

architecture Other__fp_operators__part255_behav of Other__fp_operators__part255 is
begin
    n8920_1 <= ( lo1273 );
end Other__fp_operators__part255_behav;
