--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1714 is 
  Port (
    lo8740: in std_logic;
    po192: inout std_logic
  );
end Other__carpat__part1714;

architecture Other__carpat__part1714_behav of Other__carpat__part1714 is
begin
    po192 <= ( lo8740 );
end Other__carpat__part1714_behav;
