--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part23 is 
  Port (
    lo061: in std_logic;
    po11: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part23;

architecture Cookbook__soft_ecc_ram_32bit__part23_behav of Cookbook__soft_ecc_ram_32bit__part23 is
begin
    po11 <= ( lo061 );
end Cookbook__soft_ecc_ram_32bit__part23_behav;
