--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1467 is 
  Port (
    lo4836: in std_logic;
    n19669_1: inout std_logic
  );
end Other__sudoku_check__part1467;

architecture Other__sudoku_check__part1467_behav of Other__sudoku_check__part1467 is
begin
    n19669_1 <= ( lo4836 );
end Other__sudoku_check__part1467_behav;
