--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part75 is 
  Port (
    lo2466: in std_logic;
    n5669: inout std_logic
  );
end Other__sudoku_check__part75;

architecture Other__sudoku_check__part75_behav of Other__sudoku_check__part75 is
begin
    n5669 <= ( lo2466 );
end Other__sudoku_check__part75_behav;
