--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part81 is 
  Port (
    lo78: in std_logic;
    po06: inout std_logic
  );
end Cookbook__approx_fp_div__part81;

architecture Cookbook__approx_fp_div__part81_behav of Cookbook__approx_fp_div__part81 is
begin
    po06 <= ( lo78 );
end Cookbook__approx_fp_div__part81_behav;
