--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part784 is 
  Port (
    lo4523: in std_logic;
    n22470: inout std_logic
  );
end IWLS2005__des_perf__part784;

architecture IWLS2005__des_perf__part784_behav of IWLS2005__des_perf__part784 is
begin
    n22470 <= ( lo4523 );
end IWLS2005__des_perf__part784_behav;
