--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1323 is 
  Port (
    lo7768: in std_logic;
    n43659_1: inout std_logic
  );
end Other__carpat__part1323;

architecture Other__carpat__part1323_behav of Other__carpat__part1323 is
begin
    n43659_1 <= ( lo7768 );
end Other__carpat__part1323_behav;
