--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1043 is 
  Port (
    lo5075: in std_logic;
    n25215: inout std_logic
  );
end IWLS2005__des_perf__part1043;

architecture IWLS2005__des_perf__part1043_behav of IWLS2005__des_perf__part1043 is
begin
    n25215 <= ( lo5075 );
end IWLS2005__des_perf__part1043_behav;
