--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part10 is 
  Port (
    lo0008: in std_logic;
    po0008: inout std_logic
  );
end Other__ether__part10;

architecture Other__ether__part10_behav of Other__ether__part10 is
begin
    po0008 <= ( lo0008 );
end Other__ether__part10_behav;
