--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part16 is 
  Port (
    lo15: in std_logic;
    po13: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part16;

architecture Cookbook__x4_decoder_8b10b__part16_behav of Cookbook__x4_decoder_8b10b__part16 is
begin
    po13 <= ( lo15 );
end Cookbook__x4_decoder_8b10b__part16_behav;
