--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part962 is 
  Port (
    lo6807: in std_logic;
    n34379_1: inout std_logic
  );
end Other__carpat__part962;

architecture Other__carpat__part962_behav of Other__carpat__part962 is
begin
    n34379_1 <= ( lo6807 );
end Other__carpat__part962_behav;
