--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1643 is 
  Port (
    lo1712: in std_logic;
    n8859: inout std_logic
  );
end Cookbook__fec_check__part1643;

architecture Cookbook__fec_check__part1643_behav of Cookbook__fec_check__part1643 is
begin
    n8859 <= ( lo1712 );
end Cookbook__fec_check__part1643_behav;
