--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part36 is 
  Port (
    lo78: in std_logic;
    po18: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part36;

architecture Cookbook__soft_ecc_ram_16bit__part36_behav of Cookbook__soft_ecc_ram_16bit__part36 is
begin
    po18 <= ( lo78 );
end Cookbook__soft_ecc_ram_16bit__part36_behav;
