--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part84 is 
  Port (
    lo1758: in std_logic;
    po072: inout std_logic
  );
end Other__mem__part84;

architecture Other__mem__part84_behav of Other__mem__part84 is
begin
    po072 <= ( lo1758 );
end Other__mem__part84_behav;
