--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part306 is 
  Port (
    lo1812: in std_logic;
    n8534_1: inout std_logic
  );
end Other__desperf__part306;

architecture Other__desperf__part306_behav of Other__desperf__part306 is
begin
    n8534_1 <= ( lo1812 );
end Other__desperf__part306_behav;
