--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part396 is 
  Port (
    lo2232: in std_logic;
    n11615: inout std_logic
  );
end IWLS2005__des_perf__part396;

architecture IWLS2005__des_perf__part396_behav of IWLS2005__des_perf__part396 is
begin
    n11615 <= ( lo2232 );
end IWLS2005__des_perf__part396_behav;
