--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part41 is 
  Port (
    lo0746: in std_logic;
    n4893: inout std_logic
  );
end Other__ether__part41;

architecture Other__ether__part41_behav of Other__ether__part41 is
begin
    n4893 <= ( lo0746 );
end Other__ether__part41_behav;
