--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part674 is 
  Port (
    lo4323: in std_logic;
    n21705: inout std_logic
  );
end IWLS2005__des_perf__part674;

architecture IWLS2005__des_perf__part674_behav of IWLS2005__des_perf__part674 is
begin
    n21705 <= ( lo4323 );
end IWLS2005__des_perf__part674_behav;
