--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part604 is 
  Port (
    lo3253: in std_logic;
    n10959: inout std_logic
  );
end Other__sudoku_check__part604;

architecture Other__sudoku_check__part604_behav of Other__sudoku_check__part604 is
begin
    n10959 <= ( lo3253 );
end Other__sudoku_check__part604_behav;
