--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1499 is 
  Port (
    lo3413: in std_logic;
    n21571: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1499;

architecture Other__ucsb_152_tap_fir__part1499_behav of Other__ucsb_152_tap_fir__part1499 is
begin
    n21571 <= ( lo3413 );
end Other__ucsb_152_tap_fir__part1499_behav;
