--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part8 is 
  Port (
    pi08: in std_logic;
    n128: inout std_logic
  );
end Cookbook__pipeline_add_msb__part8;

architecture Cookbook__pipeline_add_msb__part8_behav of Cookbook__pipeline_add_msb__part8 is
begin
    n128 <= ( pi08 );
end Cookbook__pipeline_add_msb__part8_behav;
