--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10: inout std_logic
  );
end top;

architecture top_behav of top is
signal n33,n35,n37,n39,n41,n43,n45,n47,n49: std_logic;
begin
    po10 <= ( not pi20 and not pi09 and pi19 )
      or ( not pi20 and pi09 and not pi19 )
      or ( pi20 and not pi09 and not pi19 )
      or ( pi20 and pi09 and pi19 );
    n33 <= ( pi20 and pi09 )
      or ( pi20 and pi19 )
      or ( pi09 and pi19 );
    po09 <= ( not n33 and not pi08 and pi18 )
      or ( not n33 and pi08 and not pi18 )
      or ( n33 and not pi08 and not pi18 )
      or ( n33 and pi08 and pi18 );
    n35 <= ( n33 and pi08 )
      or ( n33 and pi18 )
      or ( pi08 and pi18 );
    po08 <= ( not n35 and not pi07 and pi17 )
      or ( not n35 and pi07 and not pi17 )
      or ( n35 and not pi07 and not pi17 )
      or ( n35 and pi07 and pi17 );
    n37 <= ( n35 and pi07 )
      or ( n35 and pi17 )
      or ( pi07 and pi17 );
    po07 <= ( not n37 and not pi06 and pi16 )
      or ( not n37 and pi06 and not pi16 )
      or ( n37 and not pi06 and not pi16 )
      or ( n37 and pi06 and pi16 );
    n39 <= ( n37 and pi06 )
      or ( n37 and pi16 )
      or ( pi06 and pi16 );
    po06 <= ( not n39 and not pi05 and pi15 )
      or ( not n39 and pi05 and not pi15 )
      or ( n39 and not pi05 and not pi15 )
      or ( n39 and pi05 and pi15 );
    n41 <= ( n39 and pi05 )
      or ( n39 and pi15 )
      or ( pi05 and pi15 );
    po05 <= ( not n41 and not pi04 and pi14 )
      or ( not n41 and pi04 and not pi14 )
      or ( n41 and not pi04 and not pi14 )
      or ( n41 and pi04 and pi14 );
    n43 <= ( n41 and pi04 )
      or ( n41 and pi14 )
      or ( pi04 and pi14 );
    po04 <= ( not n43 and not pi03 and pi13 )
      or ( not n43 and pi03 and not pi13 )
      or ( n43 and not pi03 and not pi13 )
      or ( n43 and pi03 and pi13 );
    n45 <= ( n43 and pi03 )
      or ( n43 and pi13 )
      or ( pi03 and pi13 );
    po03 <= ( not n45 and not pi02 and pi12 )
      or ( not n45 and pi02 and not pi12 )
      or ( n45 and not pi02 and not pi12 )
      or ( n45 and pi02 and pi12 );
    n47 <= ( n45 and pi02 )
      or ( n45 and pi12 )
      or ( pi02 and pi12 );
    po02 <= ( not n47 and not pi01 and pi11 )
      or ( not n47 and pi01 and not pi11 )
      or ( n47 and not pi01 and not pi11 )
      or ( n47 and pi01 and pi11 );
    n49 <= ( n47 and pi01 )
      or ( n47 and pi11 )
      or ( pi01 and pi11 );
    po01 <= ( not n49 and not pi00 and pi10 )
      or ( not n49 and pi00 and not pi10 )
      or ( n49 and not pi00 and not pi10 )
      or ( n49 and pi00 and pi10 );
    po00 <= ( n49 and pi00 )
      or ( n49 and pi10 )
      or ( pi00 and pi10 );
end top_behav;
