--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part4 is 
  Port (
    lo9443,lo9442: in std_logic;
    n5246,n51941,n51946: inout std_logic
  );
end Other__ucsb_152_tap_fir__part4;

architecture Other__ucsb_152_tap_fir__part4_behav of Other__ucsb_152_tap_fir__part4 is
signal n30872,n30873,n57041,n57042: std_logic;
begin
    n5246 <= ( not lo9443 );
    n30872 <= ( not lo9442 and lo9443 );
    n30873 <= not (( not n57042 and not n30872 ));
    n51941 <= ( not lo9442 and not n30873 );
    n51946 <= ( not n30873 and n57041 );
    n57041 <= ( not lo9443 and lo9442 )
      or ( lo9443 and not lo9442 );
    n57042 <= ( lo9443 and lo9442 );
end Other__ucsb_152_tap_fir__part4_behav;
