--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part117 is 
  Port (
    lo7384,lo7385: in std_logic;
    n40994_1,n40999_1,n41014_1: inout std_logic
  );
end Other__carpat__part117;

architecture Other__carpat__part117_behav of Other__carpat__part117 is
signal n97881,n97882: std_logic;
begin
    n97881 <= ( not lo7384 and not lo7385 );
    n97882 <= ( not lo7384 and lo7385 )
      or ( lo7384 and not lo7385 );
    n40994_1 <= ( not n97881 and not n97882 );
    n40999_1 <= ( lo7384 and not lo7385 );
    n41014_1 <= not (( not lo7384 and not lo7385 ));
end Other__carpat__part117_behav;
