--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__cmb is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end IWLS93__cmb;

architecture IWLS93__cmb_behav of IWLS93__cmb is
signal n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46: std_logic;
begin
    po0 <= ( pi10 and pi11 and pi12 and not n29 );
    po1 <= ( pi00 )
      or ( not n26 );
    po2 <= ( not pi15 )
      or ( not n26 );
    po3 <= ( not pi00 and not pi14 and not pi15 and not n27 );
    n24 <= ( pi06 and pi07 and pi08 and pi09 );
    n25 <= ( pi03 and pi04 and pi05 );
    n26 <= ( n34 )
      or ( n30 )
      or ( n32 )
      or ( n42 );
    n27 <= ( pi05 )
      or ( pi06 )
      or ( not n37 )
      or ( not n39 );
    n28 <= ( n36 )
      or ( n40 )
      or ( n41 )
      or ( not n46 );
    n29 <= ( not pi01 )
      or ( not pi02 )
      or ( not n24 )
      or ( not n25 );
    n30 <= ( pi05 and pi06 and not pi08 and not n28 );
    n31 <= ( not pi13 and pi14 );
    n32 <= ( pi05 and not pi07 and not pi08 and not n28 );
    n33 <= ( not pi12 and pi13 );
    n34 <= ( not pi06 and not pi07 and not pi08 and not n28 );
    n35 <= ( not pi00 and pi05 );
    n36 <= ( not pi10 and pi11 );
    n37 <= ( not pi07 and not pi08 and not pi09 );
    n38 <= ( not pi14 and pi15 );
    n39 <= ( not pi10 and not pi11 and not pi12 and not pi13 );
    n40 <= ( not pi08 and pi09 );
    n41 <= ( not pi09 and pi10 );
    n42 <= ( pi05 and pi06 and pi07 and not n28 );
    n43 <= ( n35 )
      or ( n31 )
      or ( n38 )
      or ( n33 );
    n44 <= ( pi11 and not n43 );
    n45 <= ( not pi12 and not n43 );
    n46 <= ( n44 )
      or ( n45 );
end IWLS93__cmb_behav;
