--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part91 is 
  Port (
    lo5901,lo5902,lo5903,lo5904: in std_logic;
    n27999_1,n28004_1,n28009_1,n28014_1,n28019_1,n28024_1,n28029_1,n28034_1,n28039_1: inout std_logic
  );
end Other__sudoku_check__part91;

architecture Other__sudoku_check__part91_behav of Other__sudoku_check__part91 is
begin
    n27999_1 <= ( lo5901 and not lo5902 and not lo5903 and lo5904 );
    n28004_1 <= ( not lo5901 and not lo5902 and not lo5903 and lo5904 );
    n28009_1 <= ( lo5901 and lo5902 and lo5903 and not lo5904 );
    n28014_1 <= ( not lo5901 and lo5902 and lo5903 and not lo5904 );
    n28019_1 <= ( lo5901 and not lo5902 and lo5903 and not lo5904 );
    n28024_1 <= ( not lo5901 and not lo5902 and lo5903 and not lo5904 );
    n28029_1 <= ( lo5901 and lo5902 and not lo5903 and not lo5904 );
    n28034_1 <= ( not lo5901 and lo5902 and not lo5903 and not lo5904 );
    n28039_1 <= ( lo5901 and not lo5902 and not lo5903 and not lo5904 );
end Other__sudoku_check__part91_behav;
