--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part13 is 
  Port (
    pi13,pi29,pi45: in std_logic;
    po13,po29: inout std_logic
  );
end Cookbook__compress_32__part13;

architecture Cookbook__compress_32__part13_behav of Cookbook__compress_32__part13 is
signal n82,n114,n130,n146,n162: std_logic;
begin
    n82 <= ( not pi13 and pi29 )
      or ( pi13 and not pi29 );
    po13 <= ( not n82 and pi45 )
      or ( n82 and not pi45 );
    n114 <= ( pi13 and pi45 );
    n130 <= ( pi13 and pi29 );
    n146 <= not (( not n130 and not n114 ));
    n162 <= ( pi29 and pi45 );
    po29 <= not (( not n146 and not n162 ));
end Cookbook__compress_32__part13_behav;
