--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part18 is 
  Port (
    lo04242,lo04243,lo04244,lo04241,lo04245: in std_logic;
    n27621,n27631,n27616,n27626,n27636: inout std_logic
  );
end QUIP__uoft_raytracer__part18;

architecture QUIP__uoft_raytracer__part18_behav of QUIP__uoft_raytracer__part18 is
signal n53092,n53093,n77404,n77405: std_logic;
begin
    n53092 <= ( lo04242 and not lo04243 and not lo04244 );
    n53093 <= ( lo04241 and lo04245 and n53092 )
      or ( lo04245 and n77405 );
    n27621 <= ( not lo04242 and lo04241 and not n53093 )
      or ( lo04242 and not lo04241 and not n53093 );
    n27631 <= ( not lo04244 and n77404 and not n53093 )
      or ( lo04244 and not n77404 and not n53093 );
    n77404 <= ( lo04242 and lo04241 and lo04243 );
    n77405 <= ( lo04242 and lo04241 and lo04243 and lo04244 );
    n27616 <= ( not lo04241 and not lo04245 )
      or ( not lo04241 and not n77405 );
    n27626 <= ( not lo04242 and lo04243 and not n53093 )
      or ( lo04242 and lo04241 and not lo04243 and not n53093 )
      or ( not lo04241 and lo04243 and not n53093 );
    n27636 <= ( not lo04241 and lo04245 and not n77405 )
      or ( not lo04245 and n77405 )
      or ( lo04245 and not n77405 and not n53092 );
end QUIP__uoft_raytracer__part18_behav;
