--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part42 is 
  Port (
    lo5705,lo5706,lo5707,lo5708: in std_logic;
    n27274_1,n29474,n29659_1,n29839_1,n30019_1,n30199,n30379,n30559,n30739: inout std_logic
  );
end Other__sudoku_check__part42;

architecture Other__sudoku_check__part42_behav of Other__sudoku_check__part42 is
begin
    n27274_1 <= ( lo5705 and not lo5706 and not lo5707 and not lo5708 );
    n29474 <= ( lo5705 and not lo5706 and not lo5707 and lo5708 );
    n29659_1 <= ( not lo5705 and not lo5706 and not lo5707 and lo5708 );
    n29839_1 <= ( lo5705 and lo5706 and lo5707 and not lo5708 );
    n30019_1 <= ( not lo5705 and lo5706 and lo5707 and not lo5708 );
    n30199 <= ( lo5705 and not lo5706 and lo5707 and not lo5708 );
    n30379 <= ( not lo5705 and not lo5706 and lo5707 and not lo5708 );
    n30559 <= ( lo5705 and lo5706 and not lo5707 and not lo5708 );
    n30739 <= ( not lo5705 and lo5706 and not lo5707 and not lo5708 );
end Other__sudoku_check__part42_behav;
