--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part79 is 
  Port (
    lo5853,lo5854,lo5855,lo5856: in std_logic;
    n27859_1,n29364,n29549,n29729,n29909_1,n30089,n30269,n30449,n30629: inout std_logic
  );
end Other__sudoku_check__part79;

architecture Other__sudoku_check__part79_behav of Other__sudoku_check__part79 is
begin
    n27859_1 <= ( lo5853 and not lo5854 and not lo5855 and not lo5856 );
    n29364 <= ( lo5853 and not lo5854 and not lo5855 and lo5856 );
    n29549 <= ( not lo5853 and not lo5854 and not lo5855 and lo5856 );
    n29729 <= ( lo5853 and lo5854 and lo5855 and not lo5856 );
    n29909_1 <= ( not lo5853 and lo5854 and lo5855 and not lo5856 );
    n30089 <= ( lo5853 and not lo5854 and lo5855 and not lo5856 );
    n30269 <= ( not lo5853 and not lo5854 and lo5855 and not lo5856 );
    n30449 <= ( lo5853 and lo5854 and not lo5855 and not lo5856 );
    n30629 <= ( not lo5853 and lo5854 and not lo5855 and not lo5856 );
end Other__sudoku_check__part79_behav;
