--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_oc8051__part3 is 
  Port (
    lo648,lo647,lo649,lo650: in std_logic;
    n3915_1,n2425,n3910,n3920_1,n3925_1: inout std_logic
  );
end QUIP__oc_oc8051__part3;

architecture QUIP__oc_oc8051__part3_behav of QUIP__oc_oc8051__part3 is
begin
    n3915_1 <= ( not lo648 );
    n2425 <= ( lo647 and lo648 and lo649 and not lo650 );
    n3910 <= ( not lo647 and lo648 )
      or ( lo647 and not lo648 );
    n3920_1 <= ( lo650 and not lo649 and lo647 and lo648 )
      or ( lo649 and not lo647 )
      or ( lo649 and not lo648 );
    n3925_1 <= ( not lo650 and not lo649 and lo647 and lo648 )
      or ( lo650 and not lo647 )
      or ( lo650 and not lo648 );
end QUIP__oc_oc8051__part3_behav;
