--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part88 is 
  Port (
    lo5889,lo5890,lo5891,lo5892: in std_logic;
    n27984_1,n28259_1,n28264_1,n28269_1,n28274_1,n28279_1,n28284_1,n28289_1,n28294_1: inout std_logic
  );
end Other__sudoku_check__part88;

architecture Other__sudoku_check__part88_behav of Other__sudoku_check__part88 is
begin
    n27984_1 <= ( lo5889 and not lo5890 and not lo5891 and not lo5892 );
    n28259_1 <= ( lo5889 and not lo5890 and not lo5891 and lo5892 );
    n28264_1 <= ( not lo5889 and not lo5890 and not lo5891 and lo5892 );
    n28269_1 <= ( lo5889 and lo5890 and lo5891 and not lo5892 );
    n28274_1 <= ( not lo5889 and lo5890 and lo5891 and not lo5892 );
    n28279_1 <= ( lo5889 and not lo5890 and lo5891 and not lo5892 );
    n28284_1 <= ( not lo5889 and not lo5890 and lo5891 and not lo5892 );
    n28289_1 <= ( lo5889 and lo5890 and not lo5891 and not lo5892 );
    n28294_1 <= ( not lo5889 and lo5890 and not lo5891 and not lo5892 );
end Other__sudoku_check__part88_behav;
