--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr is 
  Port (
    lo00,lo01,lo06,lo07,lo08,lo09,lo10,lo31: in std_logic;
    n65,n70,n75,n100,n105,n110,n115,n120: inout std_logic
  );
end Cookbook__lfsr;

architecture Cookbook__lfsr_behav of Cookbook__lfsr is
begin
    n70 <= ( not lo00 and lo31 )
      or ( lo00 and not lo31 );
    n75 <= ( not lo01 and lo31 )
      or ( lo01 and not lo31 );
    n100 <= ( not lo06 and lo31 )
      or ( lo06 and not lo31 );
    n105 <= ( not lo07 and lo31 )
      or ( lo07 and not lo31 );
    n110 <= ( not lo08 and lo31 )
      or ( lo08 and not lo31 );
    n115 <= ( not lo09 and lo31 )
      or ( lo09 and not lo31 );
    n120 <= ( not lo10 and lo31 )
      or ( lo10 and not lo31 );
    n65 <= ( not lo31 );
end Cookbook__lfsr_behav;
