--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part69 is 
  Port (
    lo5813,lo5814,lo5815,lo5816: in std_logic;
    n27649_1,n29429,n29614_1,n29794,n29974_1,n30154,n30334,n30514,n30694: inout std_logic
  );
end Other__sudoku_check__part69;

architecture Other__sudoku_check__part69_behav of Other__sudoku_check__part69 is
begin
    n27649_1 <= ( lo5813 and not lo5814 and not lo5815 and not lo5816 );
    n29429 <= ( lo5813 and not lo5814 and not lo5815 and lo5816 );
    n29614_1 <= ( not lo5813 and not lo5814 and not lo5815 and lo5816 );
    n29794 <= ( lo5813 and lo5814 and lo5815 and not lo5816 );
    n29974_1 <= ( not lo5813 and lo5814 and lo5815 and not lo5816 );
    n30154 <= ( lo5813 and not lo5814 and lo5815 and not lo5816 );
    n30334 <= ( not lo5813 and not lo5814 and lo5815 and not lo5816 );
    n30514 <= ( lo5813 and lo5814 and not lo5815 and not lo5816 );
    n30694 <= ( not lo5813 and lo5814 and not lo5815 and not lo5816 );
end Other__sudoku_check__part69_behav;
