--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part15 is 
  Port (
    pi15,pi31,pi47: in std_logic;
    po15,po31: inout std_logic
  );
end Cookbook__compress_32__part15;

architecture Cookbook__compress_32__part15_behav of Cookbook__compress_32__part15 is
signal n80,n112,n128,n144,n160: std_logic;
begin
    n80 <= ( not pi15 and pi31 )
      or ( pi15 and not pi31 );
    po15 <= ( not n80 and pi47 )
      or ( n80 and not pi47 );
    n112 <= ( pi15 and pi47 );
    n128 <= ( pi15 and pi31 );
    n144 <= not (( not n128 and not n112 ));
    n160 <= ( pi31 and pi47 );
    po31 <= not (( not n144 and not n160 ));
end Cookbook__compress_32__part15_behav;
