--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part0 is 
  Port (
    pi00,pi16,pi32: in std_logic;
    po00,po16: inout std_logic
  );
end Cookbook__compress_32__part0;

architecture Cookbook__compress_32__part0_behav of Cookbook__compress_32__part0 is
signal n95,n127,n143,n159,n175: std_logic;
begin
    n95 <= ( not pi00 and pi16 )
      or ( pi00 and not pi16 );
    po00 <= ( not n95 and pi32 )
      or ( n95 and not pi32 );
    n127 <= ( pi00 and pi32 );
    n143 <= ( pi00 and pi16 );
    n159 <= not (( not n143 and not n127 ));
    n175 <= ( pi16 and pi32 );
    po16 <= not (( not n159 and not n175 ));
end Cookbook__compress_32__part0_behav;
