--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__con1 is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6: in std_logic;
    po0,po1: inout std_logic
  );
end IWLS93__con1;

architecture IWLS93__con1_behav of IWLS93__con1 is
signal n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22: std_logic;
begin
    po0 <= ( n22 )
      or ( n14 );
    po1 <= ( n15 )
      or ( n16 );
    n11 <= ( not pi1 and not pi2 and pi3 );
    n12 <= ( pi2 and pi3 and pi4 );
    n13 <= ( pi1 and not pi4 and pi6 );
    n14 <= ( n11 )
      or ( n12 )
      or ( n13 );
    n15 <= ( n17 )
      or ( n18 );
    n16 <= ( n19 )
      or ( n20 )
      or ( n21 );
    n17 <= ( not pi0 and not pi1 );
    n18 <= ( not pi0 and pi4 );
    n19 <= ( pi0 and pi1 and not pi4 );
    n20 <= ( not pi4 and not pi5 );
    n21 <= ( not pi1 and not pi3 and pi4 );
    n22 <= ( pi0 and pi1 );
end IWLS93__con1_behav;
