--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part16 is 
  Port (
    pi048,pi112,pi047,pi111,pi046,pi110: in std_logic;
    n314_1: inout std_logic
  );
end Cookbook__pipe_equal__part16;

architecture Cookbook__pipe_equal__part16_behav of Cookbook__pipe_equal__part16 is
signal n238,n239,n240,n241: std_logic;
begin
    n238 <= ( not pi048 and pi112 )
      or ( pi048 and not pi112 );
    n239 <= ( not pi047 and pi111 )
      or ( pi047 and not pi111 );
    n240 <= ( not pi046 and pi110 )
      or ( pi046 and not pi110 );
    n241 <= not (( not n239 and not n240 ));
    n314_1 <= ( not n238 and not n241 );
end Cookbook__pipe_equal__part16_behav;
