--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part15 is 
  Port (
    pi1814,pi1815,pi1816: in std_logic;
    n21781,n21786,n21791: inout std_logic
  );
end Other__umass_weather__part15;

architecture Other__umass_weather__part15_behav of Other__umass_weather__part15 is
signal n34898: std_logic;
begin
    n21781 <= ( not pi1814 );
    n21786 <= ( not pi1814 and not pi1815 )
      or ( pi1814 and pi1815 );
    n34898 <= not (( not pi1814 and not pi1815 ));
    n21791 <= ( not pi1816 and not n34898 )
      or ( pi1816 and n34898 );
end Other__umass_weather__part15_behav;
