--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part36 is 
  Port (
    lo5681,lo5682,lo5683,lo5684: in std_logic;
    n27244_1,n27769_1,n27774_1,n27779_1,n27784_1,n27789_1,n27794_1,n27799_1,n27804_1: inout std_logic
  );
end Other__sudoku_check__part36;

architecture Other__sudoku_check__part36_behav of Other__sudoku_check__part36 is
begin
    n27244_1 <= ( lo5681 and not lo5682 and not lo5683 and not lo5684 );
    n27769_1 <= ( lo5681 and not lo5682 and not lo5683 and lo5684 );
    n27774_1 <= ( not lo5681 and not lo5682 and not lo5683 and lo5684 );
    n27779_1 <= ( lo5681 and lo5682 and lo5683 and not lo5684 );
    n27784_1 <= ( not lo5681 and lo5682 and lo5683 and not lo5684 );
    n27789_1 <= ( lo5681 and not lo5682 and lo5683 and not lo5684 );
    n27794_1 <= ( not lo5681 and not lo5682 and lo5683 and not lo5684 );
    n27799_1 <= ( lo5681 and lo5682 and not lo5683 and not lo5684 );
    n27804_1 <= ( not lo5681 and lo5682 and not lo5683 and not lo5684 );
end Other__sudoku_check__part36_behav;
