--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part30 is 
  Port (
    lo5657,lo5658,lo5659,lo5660: in std_logic;
    n27179_1,n28824_1,n28829_1,n28834,n28839_1,n28844_1,n28849_1,n28854_1,n28859_1: inout std_logic
  );
end Other__sudoku_check__part30;

architecture Other__sudoku_check__part30_behav of Other__sudoku_check__part30 is
begin
    n27179_1 <= ( lo5657 and not lo5658 and not lo5659 and not lo5660 );
    n28824_1 <= ( lo5657 and not lo5658 and not lo5659 and lo5660 );
    n28829_1 <= ( not lo5657 and not lo5658 and not lo5659 and lo5660 );
    n28834 <= ( lo5657 and lo5658 and lo5659 and not lo5660 );
    n28839_1 <= ( not lo5657 and lo5658 and lo5659 and not lo5660 );
    n28844_1 <= ( lo5657 and not lo5658 and lo5659 and not lo5660 );
    n28849_1 <= ( not lo5657 and not lo5658 and lo5659 and not lo5660 );
    n28854_1 <= ( lo5657 and lo5658 and not lo5659 and not lo5660 );
    n28859_1 <= ( not lo5657 and lo5658 and not lo5659 and not lo5660 );
end Other__sudoku_check__part30_behav;
