--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part0 is 
  Port (
    lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo16,lo17,lo08,lo09,lo10,lo11,lo12,lo13,lo14,lo15: in std_logic;
    n33,n38,n43,n48,n53,n58,n63,n68,n73,n78,n83,n88,n93,n98,n103,n108,n113,n118: inout std_logic
  );
end Cookbook__temp_sense_s5__part0;

architecture Cookbook__temp_sense_s5__part0_behav of Cookbook__temp_sense_s5__part0 is
signal n250,n252,n254,n256,n258,n260,n262,n263,n264,n265,n266,n267,n268,n269: std_logic;
begin
    n33 <= ( not lo00 );
    n38 <= ( not lo00 and lo01 )
      or ( lo00 and not lo01 );
    n250 <= ( lo00 and lo01 );
    n43 <= ( not n250 and lo02 )
      or ( n250 and not lo02 );
    n252 <= ( n250 and lo02 );
    n48 <= ( not n252 and lo03 )
      or ( n252 and not lo03 );
    n254 <= ( n252 and lo03 );
    n53 <= ( not n254 and lo04 )
      or ( n254 and not lo04 );
    n256 <= ( n254 and lo04 );
    n58 <= ( not n256 and lo05 )
      or ( n256 and not lo05 );
    n258 <= ( n256 and lo05 );
    n63 <= ( not n258 and lo06 )
      or ( n258 and not lo06 );
    n260 <= ( n258 and lo06 );
    n68 <= ( not n260 and lo07 )
      or ( n260 and not lo07 );
    n262 <= ( lo00 and lo01 );
    n263 <= ( lo02 and lo03 );
    n264 <= ( n262 and n263 );
    n265 <= ( lo04 and lo05 );
    n266 <= ( lo06 and lo07 );
    n267 <= ( n265 and n266 );
    n268 <= ( n264 and n267 );
    n269 <= ( not lo16 and lo17 )
      or ( lo16 and not lo17 );
    n73 <= not (( not lo08 and not n268 ));
    n78 <= ( lo09 and not n268 );
    n83 <= not (( not lo10 and not n268 ));
    n88 <= ( lo11 and not n268 );
    n93 <= ( lo12 and not n268 );
    n98 <= ( lo13 and not n268 );
    n103 <= ( lo14 and not n268 );
    n108 <= not (( not lo15 and not n268 ));
    n113 <= ( not lo16 and n268 )
      or ( lo16 and not n268 );
    n118 <= ( lo17 and not n268 )
      or ( n269 and n268 );
end Cookbook__temp_sense_s5__part0_behav;
