--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b01 is 
  Port (
    pi0,pi1,lo1,lo2,lo3: in std_logic;
    n9,n14,n19,n24,n29_1: inout std_logic
  );
end ITC99__b01;

architecture ITC99__b01_behav of ITC99__b01 is
signal n22,n23,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48: std_logic;
begin
    n9 <= ( lo2 and not lo1 and lo3 );
    n24 <= not (( n44 and n43 and n42 and n41 ));
    n19 <= not (( n34 and n32 and n33 ));
    n22 <= not (( not pi1 and not pi0 ));
    n23 <= not (( lo2 and not lo3 ));
    n29_1 <= not (( n48 and n47 ));
    n14 <= not (( n36 and n35 ));
    n26 <= not (( n46 and n45 ));
    n27 <= not (( pi0 and pi1 ));
    n28 <= not (( lo1 and n23 ));
    n29 <= not (( not n22 and not lo3 ));
    n30 <= not (( n27 and n23 ));
    n31 <= not (( lo1 and n27 ));
    n32 <= not (( lo3 and not lo2 and n27 ));
    n33 <= not (( not n23 and n31 ));
    n34 <= not (( n38 and n37 and lo1 ));
    n35 <= not (( n30 and not lo1 ));
    n36 <= not (( n29 and not lo2 and lo1 ));
    n37 <= not (( lo2 and not n22 ));
    n38 <= not (( n22 and not lo3 ));
    n39 <= not (( lo3 and n27 ));
    n40 <= not (( not n27 and not lo3 ));
    n41 <= not (( n40 and n39 and not lo2 and not lo1 ));
    n42 <= not (( n23 and n22 and lo1 ));
    n43 <= not (( n9 and n27 ));
    n44 <= not (( not n27 and not n23 ));
    n45 <= not (( pi0 and not pi1 ));
    n46 <= not (( pi1 and not pi0 ));
    n47 <= not (( not n28 and not n26 ));
    n48 <= not (( n26 and n28 ));
end ITC99__b01_behav;
