--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part76 is 
  Port (
    lo5841,lo5842,lo5843,lo5844: in std_logic;
    n27764_1,n29299,n29484_1,n29664_1,n29844,n30024_1,n30204,n30384,n30564: inout std_logic
  );
end Other__sudoku_check__part76;

architecture Other__sudoku_check__part76_behav of Other__sudoku_check__part76 is
begin
    n27764_1 <= ( lo5841 and not lo5842 and not lo5843 and not lo5844 );
    n29299 <= ( lo5841 and not lo5842 and not lo5843 and lo5844 );
    n29484_1 <= ( not lo5841 and not lo5842 and not lo5843 and lo5844 );
    n29664_1 <= ( lo5841 and lo5842 and lo5843 and not lo5844 );
    n29844 <= ( not lo5841 and lo5842 and lo5843 and not lo5844 );
    n30024_1 <= ( lo5841 and not lo5842 and lo5843 and not lo5844 );
    n30204 <= ( not lo5841 and not lo5842 and lo5843 and not lo5844 );
    n30384 <= ( lo5841 and lo5842 and not lo5843 and not lo5844 );
    n30564 <= ( not lo5841 and lo5842 and not lo5843 and not lo5844 );
end Other__sudoku_check__part76_behav;
