--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part92 is 
  Port (
    lo5905,lo5906,lo5907,lo5908: in std_logic;
    n28124_1,n28379_1,n28384_1,n28389_1,n28394_1,n28399_1,n28404_1,n28409_1,n28414_1: inout std_logic
  );
end Other__sudoku_check__part92;

architecture Other__sudoku_check__part92_behav of Other__sudoku_check__part92 is
begin
    n28124_1 <= ( lo5905 and not lo5906 and not lo5907 and not lo5908 );
    n28379_1 <= ( lo5905 and not lo5906 and not lo5907 and lo5908 );
    n28384_1 <= ( not lo5905 and not lo5906 and not lo5907 and lo5908 );
    n28389_1 <= ( lo5905 and lo5906 and lo5907 and not lo5908 );
    n28394_1 <= ( not lo5905 and lo5906 and lo5907 and not lo5908 );
    n28399_1 <= ( lo5905 and not lo5906 and lo5907 and not lo5908 );
    n28404_1 <= ( not lo5905 and not lo5906 and lo5907 and not lo5908 );
    n28409_1 <= ( lo5905 and lo5906 and not lo5907 and not lo5908 );
    n28414_1 <= ( not lo5905 and lo5906 and not lo5907 and not lo5908 );
end Other__sudoku_check__part92_behav;
