--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part62 is 
  Port (
    lo3720,lo3708,lo3684,lo3672,lo3696,lo3648,lo3636,lo3660,lo3612,lo3600,lo3624: in std_logic;
    n19049: inout std_logic
  );
end Cookbook__fec_check__part62;

architecture Cookbook__fec_check__part62_behav of Cookbook__fec_check__part62 is
signal n13482,n13483,n13484,n13485,n13486,n13487,n13488,n13489,n13490: std_logic;
begin
    n13482 <= not (( not lo3720 and not lo3708 ));
    n13483 <= not (( not lo3684 and not lo3672 ));
    n13484 <= not (( not lo3696 and not n13483 ));
    n13485 <= not (( not n13482 and not n13484 ));
    n13486 <= not (( not lo3648 and not lo3636 ));
    n13487 <= not (( not lo3660 and not n13486 ));
    n13488 <= not (( not lo3612 and not lo3600 ));
    n13489 <= not (( not lo3624 and not n13488 ));
    n13490 <= not (( not n13487 and not n13489 ));
    n19049 <= not (( not n13485 and not n13490 ));
end Cookbook__fec_check__part62_behav;
