--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part49 is 
  Port (
    lo3577,lo3565,lo3541,lo3529,lo3553,lo3505,lo3493,lo3517,lo3469,lo3457,lo3481: in std_logic;
    n18984: inout std_logic
  );
end Cookbook__fec_check__part49;

architecture Cookbook__fec_check__part49_behav of Cookbook__fec_check__part49 is
signal n13612,n13613,n13614,n13615,n13616,n13617,n13618,n13619,n13620: std_logic;
begin
    n13612 <= not (( not lo3577 and not lo3565 ));
    n13613 <= not (( not lo3541 and not lo3529 ));
    n13614 <= not (( not lo3553 and not n13613 ));
    n13615 <= not (( not n13612 and not n13614 ));
    n13616 <= not (( not lo3505 and not lo3493 ));
    n13617 <= not (( not lo3517 and not n13616 ));
    n13618 <= not (( not lo3469 and not lo3457 ));
    n13619 <= not (( not lo3481 and not n13618 ));
    n13620 <= not (( not n13617 and not n13619 ));
    n18984 <= not (( not n13615 and not n13620 ));
end Cookbook__fec_check__part49_behav;
