--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misj__part4 is 
  Port (
    pi22,pi23,pi25,pi27,pi28,pi29,pi30,pi31,pi32,pi33,pi24,pi26,pi34: in std_logic;
    po09,po10: inout std_logic
  );
end Espresso__misj__part4;

architecture Espresso__misj__part4_behav of Espresso__misj__part4 is
begin
    po09 <= ( not pi22 )
      or ( pi23 )
      or ( pi25 )
      or ( not pi27 )
      or ( not pi28 )
      or ( not pi29 )
      or ( not pi30 )
      or ( not pi31 )
      or ( not pi32 )
      or ( not pi33 );
    po10 <= ( not pi22 )
      or ( not pi24 )
      or ( not pi26 )
      or ( not pi27 )
      or ( not pi28 )
      or ( not pi30 )
      or ( not pi31 )
      or ( not pi32 )
      or ( not pi33 )
      or ( not pi34 );
end Espresso__misj__part4_behav;
