--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part52 is 
  Port (
    lo3610,lo3598,lo3574,lo3562,lo3586,lo3538,lo3526,lo3550,lo3502,lo3490,lo3514: in std_logic;
    n18999: inout std_logic
  );
end Cookbook__fec_check__part52;

architecture Cookbook__fec_check__part52_behav of Cookbook__fec_check__part52 is
signal n13582,n13583,n13584,n13585,n13586,n13587,n13588,n13589,n13590: std_logic;
begin
    n13582 <= not (( not lo3610 and not lo3598 ));
    n13583 <= not (( not lo3574 and not lo3562 ));
    n13584 <= not (( not lo3586 and not n13583 ));
    n13585 <= not (( not n13582 and not n13584 ));
    n13586 <= not (( not lo3538 and not lo3526 ));
    n13587 <= not (( not lo3550 and not n13586 ));
    n13588 <= not (( not lo3502 and not lo3490 ));
    n13589 <= not (( not lo3514 and not n13588 ));
    n13590 <= not (( not n13587 and not n13589 ));
    n18999 <= not (( not n13585 and not n13590 ));
end Cookbook__fec_check__part52_behav;
