--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0, CLK: in std_logic;
    po0,po1,po2: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,li0,li1,li2,li3,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n39,n40,n41,n42,n43,n44,n45,n46: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    po0 <= ( not n22 );
    po2 <= ( not n23 );
    li0 <= ( not n24 );
    li1 <= ( not n25 );
    li2 <= ( not n26 );
    li3 <= ( not n27 );
    n22 <= ( not n28 and not n37 );
    n23 <= ( not n31 and not n36 );
    n24 <= ( not n29 and not n30 and not n39 and not n40 and not n44 );
    n25 <= ( not n29 and not n33 and not n34 and not n39 and not n40 and not n42 );
    n26 <= ( not n35 and not n41 and not n43 and not n46 );
    n27 <= ( not n30 and not n32 and not n33 and not n35 and not n36 and not n45 and not n46 );
    n28 <= ( not pi0 and lo0 and not lo1 and lo3 );
    n29 <= ( pi0 and lo0 and lo1 and not lo2 and not lo3 );
    n30 <= ( not pi0 and not lo0 and lo1 and not lo2 and not lo3 );
    n31 <= ( pi0 and lo0 and not lo1 and not lo2 );
    n32 <= ( pi0 and not lo0 and lo1 and lo3 );
    n33 <= ( not pi0 and not lo1 and lo2 and lo3 );
    n34 <= ( pi0 and not lo0 and not lo1 and not lo3 );
    n35 <= ( not pi0 and lo0 and lo2 and not lo3 );
    n36 <= ( not lo0 and not lo1 and lo2 and not lo3 );
    n37 <= ( lo0 and not lo1 and lo2 );
    po1 <= ( lo1 and lo2 and not lo3 );
    n39 <= ( pi0 and not lo1 and lo2 and not lo3 );
    n40 <= ( pi0 and not lo0 and lo1 and lo2 );
    n41 <= ( not pi0 and not lo0 and not lo2 );
    n42 <= ( pi0 and lo2 and lo3 );
    n43 <= ( not lo0 and not lo2 and not lo3 );
    n44 <= ( pi0 and not lo0 and not lo2 );
    n45 <= ( not lo0 and lo1 and lo2 );
    n46 <= ( pi0 and lo0 and not lo2 );
end top_behav;
