--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4, CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,li0,li1,li2,li3,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n63,n64,n65,n67,n68: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    po01 <= ( not n41 );
    po02 <= ( not n42 );
    po04 <= ( not n43 );
    po05 <= ( not n44 );
    po06 <= ( not n45 );
    po13 <= ( not n46 );
    li0 <= ( not n47 );
    li1 <= ( not n48 );
    li2 <= ( not n49 );
    li3 <= ( not n50 );
    n41 <= ( pi0 and not n60 and not n61 and not n63 and not n64 and not po10 and not n67 );
    n42 <= ( pi0 and not n58 and not n59 and not n60 and not n61 and not po12 and not po10 and not n67 and not n68 );
    n43 <= ( not n61 and not n63 );
    n44 <= ( not n61 and not n63 );
    n45 <= ( pi0 and not n58 and not n60 and not n64 and not n65 and not po10 and not n67 and not n68 );
    n46 <= ( not n58 and not po12 );
    n47 <= ( not n52 and not n53 and not n63 and not po10 and not n67 and not n68 );
    n48 <= ( pi0 and not n52 and not n54 and not n57 and not n58 and not po12 and not n63 and not n65 );
    n49 <= ( pi0 and not n56 and not n59 and not n61 and not n63 and not po10 and not n68 );
    n50 <= ( not n51 and not n53 and not n54 and not n55 and not n59 and not n61 and not n63 and not n67 and not n68 );
    n51 <= ( pi0 and not pi2 and pi3 and not pi4 and lo0 and not lo1 );
    n52 <= ( pi0 and pi2 and not pi4 and lo0 and not lo1 and lo3 );
    n53 <= ( pi0 and pi2 and not pi3 and lo0 and not lo1 and lo3 );
    n54 <= ( pi0 and not pi3 and pi4 and lo0 and not lo1 and lo3 );
    n55 <= ( pi0 and pi2 and pi4 and lo0 and lo2 );
    n56 <= ( pi3 and pi4 and lo0 and lo2 );
    n57 <= ( pi1 and lo2 and not lo3 );
    n58 <= ( pi0 and lo0 and not lo2 and lo3 );
    n59 <= ( pi0 and lo0 and lo2 and not lo3 );
    n60 <= ( not lo1 and lo2 and lo3 );
    n61 <= ( pi0 and not lo0 and lo1 and lo2 );
    po12 <= ( not lo0 and not lo2 );
    n63 <= ( pi0 and not lo0 and lo1 and not lo3 );
    n64 <= ( lo2 and not lo3 );
    n65 <= ( not lo0 and not lo1 );
    po10 <= ( pi0 and lo0 and lo1 and not lo3 );
    n67 <= ( pi0 and lo0 and not lo1 and not lo2 );
    n68 <= ( pi0 and lo0 and lo1 and lo2 );
    po00 <= ( n68 );
    po03 <= ( n65 );
    po07 <= ( n65 );
    po08 <= ( n58 );
    po09 <= ( n68 );
    po11 <= ( n58 );
end top_behav;
