--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_delay is 
  Port (
    pi0, CLK: in std_logic;
    : inout std_logic
  );
end Cookbook__mlab_delay;

architecture Cookbook__mlab_delay_behav of Cookbook__mlab_delay is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,lo5,lo6,lo7,n25,n26,n27,n28,n29,li4,li5,li6,li7,li0,li1,li2,li3: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    DFF5: DFF port map (li5, CLK, lo5);
    DFF6: DFF port map (li6, CLK, lo6);
    DFF7: DFF port map (li7, CLK, lo7);
    n25 <= ( not lo4 and lo5 )
      or ( lo4 and not lo5 );
    n26 <= ( lo4 and lo5 );
    n27 <= ( not n26 and lo6 )
      or ( n26 and not lo6 );
    n28 <= ( n26 and lo6 );
    n29 <= ( not n28 and lo7 )
      or ( n28 and not lo7 );
    li4 <= ( not lo4 and pi0 )
      or ( lo4 and not pi0 );
    li5 <= ( lo5 and not pi0 )
      or ( n25 and pi0 );
    li6 <= ( lo6 and not pi0 )
      or ( n27 and pi0 );
    li7 <= ( lo7 and not pi0 )
      or ( n29 and pi0 );
    li0 <= ( lo0 and not pi0 )
      or ( lo4 and pi0 );
    li1 <= ( lo1 and not pi0 )
      or ( lo5 and pi0 );
    li2 <= ( lo2 and not pi0 )
      or ( lo6 and pi0 );
    li3 <= ( lo3 and not pi0 )
      or ( not lo7 and pi0 );
end Cookbook__mlab_delay_behav;
