--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__count is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26,pi27,pi28,pi29,pi30,pi31,pi32,pi33,pi34: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15: inout std_logic
  );
end LGSynth91__count;

architecture LGSynth91__count_behav of LGSynth91__count is
signal n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97: std_logic;
begin
    po00 <= ( pi18 )
      or ( not pi15 and not pi16 )
      or ( pi16 and not n67 );
    po01 <= ( pi18 )
      or ( not pi14 and not pi16 )
      or ( pi16 and not n68 );
    po02 <= ( pi18 )
      or ( not pi13 and not pi16 )
      or ( pi16 and not n69 );
    po03 <= ( pi18 )
      or ( not pi12 and not pi16 )
      or ( pi16 and not n70 );
    po04 <= ( pi18 )
      or ( not pi11 and not pi16 )
      or ( pi16 and not n71 );
    po05 <= ( pi18 )
      or ( not pi10 and not pi16 )
      or ( pi16 and not n72 );
    po06 <= ( pi18 )
      or ( not pi09 and not pi16 )
      or ( pi16 and not n73 );
    po07 <= ( pi18 )
      or ( not pi08 and not pi16 )
      or ( pi16 and not n74 );
    po08 <= ( pi18 )
      or ( not pi07 and not pi16 )
      or ( pi16 and not n75 );
    po09 <= ( pi18 )
      or ( not pi06 and not pi16 )
      or ( pi16 and not n76 );
    po10 <= ( pi18 )
      or ( not pi05 and not pi16 )
      or ( pi16 and not n77 );
    po11 <= ( pi18 )
      or ( not pi04 and not pi16 )
      or ( pi16 and not n78 );
    po12 <= ( pi18 )
      or ( not pi03 and not pi16 )
      or ( pi16 and not n79 );
    po13 <= ( pi18 )
      or ( not pi02 and not pi16 )
      or ( pi16 and not n80 );
    po14 <= ( pi18 )
      or ( not pi01 and not pi16 )
      or ( pi16 and not n81 );
    po15 <= ( pi18 )
      or ( not pi00 and not pi16 )
      or ( pi16 and not n82 );
    n67 <= ( not pi19 and pi17 )
      or ( pi19 and not pi17 );
    n68 <= ( pi20 and n83 )
      or ( not pi20 and not n83 );
    n69 <= ( not pi21 and n84 )
      or ( pi21 and not n84 );
    n70 <= ( pi22 and n85 )
      or ( not pi22 and not n85 );
    n71 <= ( not pi23 and n86 )
      or ( pi23 and not n86 );
    n72 <= ( pi24 and n87 )
      or ( not pi24 and not n87 );
    n73 <= ( not pi25 and n88 )
      or ( pi25 and not n88 );
    n74 <= ( pi26 and n89 )
      or ( not pi26 and not n89 );
    n75 <= ( not pi27 and n90 )
      or ( pi27 and not n90 );
    n76 <= ( pi28 and n91 )
      or ( not pi28 and not n91 );
    n77 <= ( not pi29 and n92 )
      or ( pi29 and not n92 );
    n78 <= ( pi30 and n93 )
      or ( not pi30 and not n93 );
    n79 <= ( not pi31 and n94 )
      or ( pi31 and not n94 );
    n80 <= ( pi32 and n95 )
      or ( not pi32 and not n95 );
    n81 <= ( not pi33 and n96 )
      or ( pi33 and not n96 );
    n82 <= ( pi34 and n97 )
      or ( not pi34 and not n97 );
    n83 <= ( not pi17 and not pi19 );
    n84 <= ( not n83 )
      or ( pi20 );
    n85 <= ( not pi21 and not n84 );
    n86 <= ( pi22 )
      or ( not n85 );
    n87 <= ( not pi23 and not n86 );
    n88 <= ( pi24 )
      or ( not n87 );
    n89 <= ( not pi25 and not n88 );
    n90 <= ( pi26 )
      or ( not n89 );
    n91 <= ( not pi27 and not n90 );
    n92 <= ( pi28 )
      or ( not n91 );
    n93 <= ( not pi29 and not n92 );
    n94 <= ( pi30 )
      or ( not n93 );
    n95 <= ( not pi31 and not n94 );
    n96 <= ( pi32 )
      or ( not n95 );
    n97 <= ( not pi33 and not n96 );
end LGSynth91__count_behav;
