--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b01 is 
  Port (
    pi0,pi1, CLK: in std_logic;
    po0,po1: inout std_logic
  );
end ITC99__b01;

architecture ITC99__b01_behav of ITC99__b01 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,li0,li3,li2,n22,n23,li4,li1,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    li0 <= ( lo2 and not lo1 and lo3 );
    li3 <= not (( n44 and n43 and n42 and n41 ));
    li2 <= not (( n34 and n32 and n33 ));
    n22 <= not (( not pi1 and not pi0 ));
    n23 <= not (( lo2 and not lo3 ));
    li4 <= not (( n48 and n47 ));
    li1 <= not (( n36 and n35 ));
    n26 <= not (( n46 and n45 ));
    n27 <= not (( pi0 and pi1 ));
    n28 <= not (( lo1 and n23 ));
    n29 <= not (( not n22 and not lo3 ));
    n30 <= not (( n27 and n23 ));
    n31 <= not (( lo1 and n27 ));
    n32 <= not (( lo3 and not lo2 and n27 ));
    n33 <= not (( not n23 and n31 ));
    n34 <= not (( n38 and n37 and lo1 ));
    n35 <= not (( n30 and not lo1 ));
    n36 <= not (( n29 and not lo2 and lo1 ));
    n37 <= not (( lo2 and not n22 ));
    n38 <= not (( n22 and not lo3 ));
    n39 <= not (( lo3 and n27 ));
    n40 <= not (( not n27 and not lo3 ));
    n41 <= not (( n40 and n39 and not lo2 and not lo1 ));
    n42 <= not (( n23 and n22 and lo1 ));
    n43 <= not (( li0 and n27 ));
    n44 <= not (( not n27 and not n23 ));
    n45 <= not (( pi0 and not pi1 ));
    n46 <= not (( pi1 and not pi0 ));
    n47 <= not (( not n28 and not n26 ));
    n48 <= not (( n26 and n28 ));
    po0 <= ( lo4 );
    po1 <= ( lo0 );
end ITC99__b01_behav;
