--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7,po8: inout std_logic
  );
end top;

architecture top_behav of top is
signal n27,n29,n31,n33,n35,n37,n39: std_logic;
begin
    po8 <= ( not pi16 and not pi14 and pi15 )
      or ( not pi16 and pi14 and not pi15 )
      or ( pi16 and not pi14 and not pi15 )
      or ( pi16 and pi14 and pi15 );
    n27 <= ( pi16 and pi14 )
      or ( pi16 and pi15 )
      or ( pi14 and pi15 );
    po7 <= ( not n27 and not pi06 and pi13 )
      or ( not n27 and pi06 and not pi13 )
      or ( n27 and not pi06 and not pi13 )
      or ( n27 and pi06 and pi13 );
    n29 <= ( n27 and pi06 )
      or ( n27 and pi13 )
      or ( pi06 and pi13 );
    po6 <= ( not n29 and not pi05 and pi12 )
      or ( not n29 and pi05 and not pi12 )
      or ( n29 and not pi05 and not pi12 )
      or ( n29 and pi05 and pi12 );
    n31 <= ( n29 and pi05 )
      or ( n29 and pi12 )
      or ( pi05 and pi12 );
    po5 <= ( not n31 and not pi04 and pi11 )
      or ( not n31 and pi04 and not pi11 )
      or ( n31 and not pi04 and not pi11 )
      or ( n31 and pi04 and pi11 );
    n33 <= ( n31 and pi04 )
      or ( n31 and pi11 )
      or ( pi04 and pi11 );
    po4 <= ( not n33 and not pi03 and pi10 )
      or ( not n33 and pi03 and not pi10 )
      or ( n33 and not pi03 and not pi10 )
      or ( n33 and pi03 and pi10 );
    n35 <= ( n33 and pi03 )
      or ( n33 and pi10 )
      or ( pi03 and pi10 );
    po3 <= ( not n35 and not pi02 and pi09 )
      or ( not n35 and pi02 and not pi09 )
      or ( n35 and not pi02 and not pi09 )
      or ( n35 and pi02 and pi09 );
    n37 <= ( n35 and pi02 )
      or ( n35 and pi09 )
      or ( pi02 and pi09 );
    po2 <= ( not n37 and not pi01 and pi08 )
      or ( not n37 and pi01 and not pi08 )
      or ( n37 and not pi01 and not pi08 )
      or ( n37 and pi01 and pi08 );
    n39 <= ( n37 and pi01 )
      or ( n37 and pi08 )
      or ( pi01 and pi08 );
    po1 <= ( not n39 and not pi00 and pi07 )
      or ( not n39 and pi00 and not pi07 )
      or ( n39 and not pi00 and not pi07 )
      or ( n39 and pi00 and pi07 );
    po0 <= ( n39 and pi00 )
      or ( n39 and pi07 )
      or ( pi00 and pi07 );
end top_behav;
