--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__mm4a is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6, CLK: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end LGSynth91__mm4a;

architecture LGSynth91__mm4a_behav of LGSynth91__mm4a is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,li00,li01,li02,li03,li04,li05,li06,li07,li08,li09,li10,li11,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    po0 <= ( lo00 and n81 )
      or ( n65 and not n70 and not n64 )
      or ( pi2 and li00 and n80 )
      or ( not n70 and li09 and n80 )
      or ( not n70 and n63 and li08 and n80 )
      or ( n65 and n79 and n63 and li09 and n80 );
    po1 <= ( lo01 and n81 )
      or ( not n72 and n66 and not n64 )
      or ( pi2 and li01 and n80 )
      or ( not n72 and li10 and n80 )
      or ( not li06 and not n72 and n70 and n80 )
      or ( n70 and n66 and li10 and n80 );
    po2 <= ( pi2 and li02 )
      or ( lo02 and n81 )
      or ( not li07 and not n72 and n75 )
      or ( not li07 and n72 and not n75 )
      or ( n72 and n67 and li11 )
      or ( not n72 and not n75 and n67 and not n64 );
    po3 <= ( pi2 and li03 )
      or ( n72 and li11 )
      or ( n67 and li11 )
      or ( lo03 and n81 )
      or ( n72 and n67 and not n64 );
    li00 <= ( pi3 and n80 );
    li01 <= ( pi4 and n80 );
    li02 <= ( pi5 and n80 );
    li03 <= ( pi6 and n80 );
    li04 <= ( n64 )
      or ( not pi0 and n63 );
    li05 <= ( n64 )
      or ( not pi0 and n65 );
    li06 <= ( n64 )
      or ( not pi0 and n66 );
    li07 <= ( n64 )
      or ( not pi0 and n67 );
    li08 <= ( n79 and not n64 );
    li09 <= ( n78 and not n64 );
    li10 <= ( n71 and not n64 );
    li11 <= ( n75 and not n64 );
    n63 <= ( li00 and n76 )
      or ( lo04 and n77 );
    n64 <= ( pi0 )
      or ( n81 )
      or ( not pi0 and pi2 );
    n65 <= ( li01 and n76 )
      or ( lo05 and n77 );
    n66 <= ( li02 and n76 )
      or ( lo06 and n77 );
    n67 <= ( li03 and n76 )
      or ( lo07 and n77 );
    n68 <= ( not lo11 and li03 and not n64 )
      or ( not lo10 and not lo11 and li02 and not n64 )
      or ( not lo10 and li02 and li03 and not n64 )
      or ( not lo09 and not lo10 and not lo11 and li01 and not n64 )
      or ( not lo09 and not lo11 and li01 and li02 and not n64 )
      or ( not lo09 and not lo10 and li01 and li03 and not n64 )
      or ( not lo09 and li01 and li02 and li03 and not n64 )
      or ( not lo08 and not lo09 and not lo10 and not lo11 and li00 and not n64 )
      or ( not lo08 and not lo10 and not lo11 and li00 and li01 and not n64 )
      or ( not lo08 and not lo09 and not lo11 and li00 and li02 and not n64 )
      or ( not lo08 and not lo11 and li00 and li01 and li02 and not n64 )
      or ( not lo08 and not lo09 and not lo10 and li00 and li03 and not n64 )
      or ( not lo08 and not lo10 and li00 and li01 and li03 and not n64 )
      or ( not lo08 and not lo09 and li00 and li02 and li03 and not n64 )
      or ( not lo08 and li00 and li01 and li02 and li03 and not n64 );
    n69 <= ( not lo07 and li03 and not n64 )
      or ( not lo06 and not lo07 and li02 and not n64 )
      or ( not lo06 and li02 and li03 and not n64 )
      or ( not lo05 and not lo06 and not lo07 and li01 and not n64 )
      or ( not lo05 and not lo07 and li01 and li02 and not n64 )
      or ( not lo05 and not lo06 and li01 and li03 and not n64 )
      or ( not lo05 and li01 and li02 and li03 and not n64 )
      or ( not lo04 and not lo05 and not lo06 and not lo07 and li00 and not n64 )
      or ( not lo04 and not lo06 and not lo07 and li00 and li01 and not n64 )
      or ( not lo04 and not lo05 and not lo07 and li00 and li02 and not n64 )
      or ( not lo04 and not lo07 and li00 and li01 and li02 and not n64 )
      or ( not lo04 and not lo05 and not lo06 and li00 and li03 and not n64 )
      or ( not lo04 and not lo06 and li00 and li01 and li03 and not n64 )
      or ( not lo04 and not lo05 and li00 and li02 and li03 and not n64 )
      or ( not lo04 and li00 and li01 and li02 and li03 and not n64 );
    n70 <= ( n78 and n65 )
      or ( n78 and n79 and n63 )
      or ( n65 and n79 and n63 );
    n71 <= ( li02 and n73 )
      or ( lo10 and n74 );
    n72 <= ( n70 and n71 )
      or ( n70 and n66 )
      or ( n71 and n66 );
    n73 <= ( not pi2 and n68 );
    n74 <= ( not n68 and not n64 );
    n75 <= ( li03 and n73 )
      or ( lo11 and n74 );
    n76 <= ( not pi2 and not n69 );
    n77 <= ( n69 and not n64 );
    n78 <= ( li01 and n73 )
      or ( lo09 and n74 );
    n79 <= ( li00 and n73 )
      or ( lo08 and n74 );
    n80 <= ( not pi0 and pi1 );
    n81 <= ( not pi0 and not pi1 );
end LGSynth91__mm4a_behav;
