--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__crc16_dat8 is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6: in std_logic;
    po0: inout std_logic
  );
end Cookbook__crc16_dat8;

architecture Cookbook__crc16_dat8_behav of Cookbook__crc16_dat8 is
signal n8,n9,n10,n11,n12: std_logic;
begin
    n8 <= ( not pi2 and pi5 )
      or ( pi2 and not pi5 );
    n9 <= ( not n8 and pi1 )
      or ( n8 and not pi1 );
    n10 <= ( not n9 and pi6 )
      or ( n9 and not pi6 );
    n11 <= ( not n10 and pi0 )
      or ( n10 and not pi0 );
    n12 <= ( not n11 and pi4 )
      or ( n11 and not pi4 );
    po0 <= ( not n12 and pi3 )
      or ( n12 and not pi3 );
end Cookbook__crc16_dat8_behav;
