--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__tcon is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7: inout std_logic
  );
end LGSynth91__tcon;

architecture LGSynth91__tcon_behav of LGSynth91__tcon is
begin
    po0 <= ( not pi08 and pi09 )
      or ( pi08 and pi00 )
      or ( pi09 and pi00 );
    po1 <= ( not pi08 and pi10 )
      or ( pi08 and pi01 )
      or ( pi10 and pi01 );
    po2 <= ( not pi08 and pi11 )
      or ( pi08 and pi02 )
      or ( pi11 and pi02 );
    po3 <= ( not pi08 and pi12 )
      or ( pi08 and pi03 )
      or ( pi12 and pi03 );
    po4 <= ( not pi08 and pi13 )
      or ( pi08 and pi04 )
      or ( pi13 and pi04 );
    po5 <= ( not pi08 and pi14 )
      or ( pi08 and pi05 )
      or ( pi14 and pi05 );
    po6 <= ( not pi08 and pi15 )
      or ( pi08 and pi06 )
      or ( pi15 and pi06 );
    po7 <= ( not pi08 and pi16 )
      or ( pi08 and pi07 )
      or ( pi16 and pi07 );
end LGSynth91__tcon_behav;
