--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__mult16a is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16, CLK: in std_logic;
    po0: inout std_logic
  );
end LGSynth91__mult16a;

architecture LGSynth91__mult16a_behav of LGSynth91__mult16a is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,lo12,lo13,lo14,lo15,n66,n67,n69,li01,n71,li02,n73,li03,n75,li04,n77,li05,n79,li06,n81,li07,n83,li08,n85,li09,n87,li10,n89,li11,n91,li12,n93,li13,li14,n96,li15,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,li00,n109,n110,n111,n112,n113,n114,n115,n116,n117,n118,n119,n120,n121,n122,n123,n124: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    DFF12: DFF port map (li12, CLK, lo12);
    DFF13: DFF port map (li13, CLK, lo13);
    DFF14: DFF port map (li14, CLK, lo14);
    DFF15: DFF port map (li15, CLK, lo15);
    n66 <= ( lo14 and n93 )
      or ( lo14 and n122 )
      or ( n93 and n122 );
    n67 <= ( lo15 and n66 )
      or ( lo15 and n123 )
      or ( n66 and n123 );
    po0 <= ( not lo01 and n109 )
      or ( lo01 and not n109 );
    n69 <= ( lo01 and n109 );
    li01 <= ( lo02 and n69 and n110 )
      or ( not lo02 and not n69 and n110 )
      or ( not lo02 and n69 and not n110 )
      or ( lo02 and not n69 and not n110 );
    n71 <= ( lo02 and n69 )
      or ( lo02 and n110 )
      or ( n69 and n110 );
    li02 <= ( lo03 and n71 and n111 )
      or ( not lo03 and not n71 and n111 )
      or ( not lo03 and n71 and not n111 )
      or ( lo03 and not n71 and not n111 );
    n73 <= ( lo03 and n71 )
      or ( lo03 and n111 )
      or ( n71 and n111 );
    li03 <= ( lo04 and n73 and n112 )
      or ( not lo04 and not n73 and n112 )
      or ( not lo04 and n73 and not n112 )
      or ( lo04 and not n73 and not n112 );
    n75 <= ( lo04 and n73 )
      or ( lo04 and n112 )
      or ( n73 and n112 );
    li04 <= ( lo05 and n75 and n113 )
      or ( not lo05 and not n75 and n113 )
      or ( not lo05 and n75 and not n113 )
      or ( lo05 and not n75 and not n113 );
    n77 <= ( lo05 and n75 )
      or ( lo05 and n113 )
      or ( n75 and n113 );
    li05 <= ( lo06 and n77 and n114 )
      or ( not lo06 and not n77 and n114 )
      or ( not lo06 and n77 and not n114 )
      or ( lo06 and not n77 and not n114 );
    n79 <= ( lo06 and n77 )
      or ( lo06 and n114 )
      or ( n77 and n114 );
    li06 <= ( lo07 and n79 and n115 )
      or ( not lo07 and not n79 and n115 )
      or ( not lo07 and n79 and not n115 )
      or ( lo07 and not n79 and not n115 );
    n81 <= ( lo07 and n79 )
      or ( lo07 and n115 )
      or ( n79 and n115 );
    li07 <= ( lo08 and n81 and n116 )
      or ( not lo08 and not n81 and n116 )
      or ( not lo08 and n81 and not n116 )
      or ( lo08 and not n81 and not n116 );
    n83 <= ( lo08 and n81 )
      or ( lo08 and n116 )
      or ( n81 and n116 );
    li08 <= ( lo09 and n83 and n117 )
      or ( not lo09 and not n83 and n117 )
      or ( not lo09 and n83 and not n117 )
      or ( lo09 and not n83 and not n117 );
    n85 <= ( lo09 and n83 )
      or ( lo09 and n117 )
      or ( n83 and n117 );
    li09 <= ( lo10 and n85 and n118 )
      or ( not lo10 and not n85 and n118 )
      or ( not lo10 and n85 and not n118 )
      or ( lo10 and not n85 and not n118 );
    n87 <= ( lo10 and n85 )
      or ( lo10 and n118 )
      or ( n85 and n118 );
    li10 <= ( lo11 and n87 and n119 )
      or ( not lo11 and not n87 and n119 )
      or ( not lo11 and n87 and not n119 )
      or ( lo11 and not n87 and not n119 );
    n89 <= ( lo11 and n87 )
      or ( lo11 and n119 )
      or ( n87 and n119 );
    li11 <= ( lo12 and n89 and n120 )
      or ( not lo12 and not n89 and n120 )
      or ( not lo12 and n89 and not n120 )
      or ( lo12 and not n89 and not n120 );
    n91 <= ( lo12 and n89 )
      or ( lo12 and n120 )
      or ( n89 and n120 );
    li12 <= ( lo13 and n91 and n121 )
      or ( not lo13 and not n91 and n121 )
      or ( not lo13 and n91 and not n121 )
      or ( lo13 and not n91 and not n121 );
    n93 <= ( lo13 and n91 )
      or ( lo13 and n121 )
      or ( n91 and n121 );
    li13 <= ( lo14 and n93 and n122 )
      or ( not lo14 and not n93 and n122 )
      or ( not lo14 and n93 and not n122 )
      or ( lo14 and not n93 and not n122 );
    li14 <= ( lo15 and n66 and n123 )
      or ( not lo15 and not n66 and n123 )
      or ( not lo15 and n66 and not n123 )
      or ( lo15 and not n66 and not n123 );
    n96 <= ( not n67 and n124 )
      or ( n67 and not n124 );
    li15 <= ( not lo00 and n96 )
      or ( lo00 and not n96 );
    n98 <= ( lo00 and n124 );
    n99 <= ( not n67 and n98 );
    n100 <= ( lo00 and not n124 );
    n101 <= ( n67 and n100 );
    n102 <= ( not lo00 and n124 );
    n103 <= ( n67 and n102 );
    n104 <= ( lo00 and n124 );
    n105 <= ( n67 and n104 );
    n106 <= ( n99 )
      or ( n101 );
    n107 <= ( n103 )
      or ( n105 );
    li00 <= ( n106 )
      or ( n107 );
    n109 <= ( pi00 and pi01 );
    n110 <= ( pi00 and pi02 );
    n111 <= ( pi00 and pi03 );
    n112 <= ( pi00 and pi04 );
    n113 <= ( pi00 and pi05 );
    n114 <= ( pi00 and pi06 );
    n115 <= ( pi00 and pi07 );
    n116 <= ( pi00 and pi08 );
    n117 <= ( pi00 and pi09 );
    n118 <= ( pi00 and pi10 );
    n119 <= ( pi00 and pi11 );
    n120 <= ( pi00 and pi12 );
    n121 <= ( pi00 and pi13 );
    n122 <= ( pi00 and pi14 );
    n123 <= ( pi00 and pi15 );
    n124 <= ( pi00 and pi16 );
end LGSynth91__mult16a_behav;
