--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__i1 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12: inout std_logic
  );
end IWLS93__i1;

architecture IWLS93__i1_behav of IWLS93__i1 is
signal n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64: std_logic;
begin
    po00 <= ( not n64 );
    po01 <= ( pi04 and pi06 );
    po02 <= ( pi05 and not pi06 and pi21 );
    po03 <= ( not pi06 and pi21 and pi23 );
    po04 <= ( pi05 and not pi06 and pi10 );
    po05 <= ( not pi06 and pi10 and pi23 );
    po06 <= ( not pi06 and pi20 );
    po07 <= ( not n56 );
    po08 <= ( not n62 );
    po09 <= ( not n57 );
    po10 <= ( not n55 );
    po11 <= ( pi06 and pi15 );
    po12 <= ( not n60 );
    n51 <= ( pi12 and not pi17 and n53 );
    n52 <= ( not pi19 and n51 );
    n53 <= ( not pi01 and not pi02 and not pi08 and not pi14 and not pi16 and not pi18 and not pi22 );
    n54 <= ( not pi07 and pi12 );
    n55 <= ( not pi03 and not n51 );
    n56 <= ( not pi05 and not pi09 and not pi11 and not pi13 );
    n57 <= ( not n52 and not n54 and not n61 );
    n58 <= ( pi04 and not pi06 );
    n59 <= ( pi12 and pi17 and not pi19 and n53 );
    n60 <= ( not po01 and not n58 );
    n61 <= ( pi12 and pi17 and pi19 and n53 );
    n62 <= ( not n59 and not n63 );
    n63 <= ( pi07 and pi12 and not n53 );
    n64 <= ( not pi00 and not pi24 );
end IWLS93__i1_behav;
