--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s344 is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8, CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10: inout std_logic
  );
end ISCAS__s344;

architecture ISCAS__s344_behav of ISCAS__s344 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,lo12,lo13,lo14,li00,li01,li02,li03,li04,li05,li06,li07,li08,li09,li10,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,li11,li12,li13,li14,n101,n102,n103,n104,n105,n106,n107,n108,n109,n110,n111,n112,n113,n114,n115,n116,n117,n118,n119,n120,n121,n122,n123,n124,n125,n126,n127,n128,n129,n130,n131,n132,n133,n134,n135,n136,n137,n138,n139,n140,n141,n142,n143,n144,n145,n146,n147,n148,n149,n150,n151,n152,n153,n154,n155,n156,n157,n158,n159,n160,n161,n162,n163,n164,n165,n166,n167,n168,n169,n170,n171,n172,n173,n174: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    DFF12: DFF port map (li12, CLK, lo12);
    DFF13: DFF port map (li13, CLK, lo13);
    DFF14: DFF port map (li14, CLK, lo14);
    po00 <= ( not lo06 );
    po01 <= ( not lo05 );
    po02 <= ( not lo04 );
    po03 <= ( not lo03 );
    po04 <= ( not lo10 );
    po05 <= ( not lo09 );
    po06 <= ( not lo08 );
    po07 <= ( not lo07 );
    po08 <= not (( lo00 and n170 ));
    po09 <= ( lo00 and not n93 );
    po10 <= ( not n88 );
    li00 <= ( not n173 and not pi0 );
    li01 <= ( not n174 and not pi0 );
    li02 <= ( n96 and not pi0 );
    li03 <= not (( not pi0 and not n114 ));
    li04 <= not (( not pi0 and not n115 ));
    li05 <= not (( not pi0 and not n113 ));
    li06 <= not (( not pi0 and not n110 ));
    li07 <= ( not n146 and not n145 );
    li08 <= ( not n147 and not n131 );
    li09 <= ( not n148 and not n132 );
    li10 <= ( not n149 and not n133 );
    n87 <= ( not lo02 and not lo01 and not lo00 );
    n88 <= not (( lo02 and not lo01 and lo00 ));
    n89 <= not (( not lo10 and lo14 ));
    n90 <= not (( not lo10 and lo13 ));
    n91 <= not (( not lo10 and lo12 ));
    n92 <= not (( not lo10 and lo11 ));
    n93 <= not (( lo01 and lo02 ));
    n94 <= ( n88 and not n87 );
    n95 <= not (( not n89 and not lo06 ));
    n96 <= not (( lo02 and n88 ));
    li11 <= not (( not n124 and not n116 ));
    li12 <= not (( not n125 and not n117 ));
    li13 <= not (( not n126 and not n118 ));
    li14 <= not (( not n127 and not n119 ));
    n101 <= not (( n166 and n95 ));
    n102 <= ( not n134 and not n120 );
    n103 <= ( not n135 and not n121 );
    n104 <= ( not n136 and not n122 );
    n105 <= ( not n137 and not n123 );
    n106 <= ( not n144 and not n128 );
    n107 <= ( not n142 and not n151 );
    n108 <= ( not n154 and not n129 );
    n109 <= ( not n152 and not n156 );
    n110 <= ( not n157 and not n141 );
    n111 <= ( not n160 and not n130 );
    n112 <= ( not n158 and not n162 );
    n113 <= ( not n163 and not n140 );
    n114 <= ( not n164 and not n138 );
    n115 <= ( not n165 and not n139 );
    n116 <= ( not n87 and lo11 );
    n117 <= ( not n87 and lo12 );
    n118 <= ( not n87 and lo13 );
    n119 <= ( not n87 and lo14 );
    n120 <= ( not n88 and not lo07 );
    n121 <= ( not n88 and not lo08 );
    n122 <= ( not n88 and not lo09 );
    n123 <= ( not n88 and not lo10 );
    n124 <= ( n87 and pi8 );
    n125 <= ( n87 and pi7 );
    n126 <= ( n87 and pi6 );
    n127 <= ( n87 and pi5 );
    n128 <= ( not n90 and not lo05 );
    n129 <= ( not n91 and not lo04 );
    n130 <= ( not n92 and not lo03 );
    n131 <= ( n94 and not lo07 );
    n132 <= ( n94 and not lo08 );
    n133 <= ( n94 and not lo09 );
    n134 <= ( n88 and pi4 );
    n135 <= ( n88 and pi3 );
    n136 <= ( n88 and pi2 );
    n137 <= ( n88 and pi1 );
    n138 <= ( not n94 and not lo03 );
    n139 <= ( not n94 and not lo04 );
    n140 <= ( not n94 and not lo05 );
    n141 <= ( not n94 and not lo06 );
    n142 <= ( not n95 and not n90 and not lo05 );
    n143 <= not (( n90 and lo05 ));
    n144 <= ( not n95 and n143 );
    n145 <= ( n94 and not n101 );
    n146 <= ( not n94 and not n102 );
    n147 <= ( not n94 and not n103 );
    n148 <= ( not n94 and not n104 );
    n149 <= ( not n94 and not n105 );
    n150 <= not (( n95 and n90 and lo05 ));
    n151 <= ( n150 and n106 );
    n152 <= ( not n106 and not n91 and not lo04 );
    n153 <= not (( n91 and lo04 ));
    n154 <= ( not n106 and n153 );
    n155 <= not (( n106 and n91 and lo04 ));
    n156 <= ( n155 and n108 );
    n157 <= ( n94 and not n107 );
    n158 <= ( not n108 and not n92 and not lo03 );
    n159 <= not (( n92 and lo03 ));
    n160 <= ( not n108 and n159 );
    n161 <= not (( n108 and n92 and lo03 ));
    n162 <= ( n161 and n111 );
    n163 <= ( n94 and not n109 );
    n164 <= ( n94 and not n111 );
    n165 <= ( n94 and not n112 );
    n166 <= not (( n89 and lo06 ));
    n167 <= not (( not lo00 and n93 ));
    n168 <= ( n88 and lo02 );
    n169 <= not (( not lo01 and not n168 ));
    n170 <= ( lo01 and lo02 );
    n171 <= not (( lo00 and not n93 ));
    n172 <= not (( lo01 and n168 ));
    n173 <= not (( n167 and n171 ));
    n174 <= not (( n169 and n172 ));
end ISCAS__s344_behav;
