--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__pm1__part2 is 
  Port (
    pi13,pi14,pi11,pi02,pi12,pi05,pi06,pi03,pi04,pi07,pi08,pi09,pi10: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po10,po12: inout std_logic
  );
end IWLS93__pm1__part2;

architecture IWLS93__pm1__part2_behav of IWLS93__pm1__part2 is
signal n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78: std_logic;
begin
    po00 <= ( n70 )
      or ( n71 );
    po01 <= ( pi13 and pi14 and not n61 );
    po02 <= ( not n62 );
    po03 <= ( n60 )
      or ( n57 );
    po04 <= ( not n45 );
    po05 <= ( pi13 and pi14 and not n74 );
    po06 <= ( not n46 );
    po07 <= ( not pi11 )
      or ( not pi13 )
      or ( not n47 );
    po10 <= ( n50 )
      or ( n51 )
      or ( n48 );
    po12 <= ( not pi02 )
      or ( pi12 )
      or ( not n55 );
    n42 <= ( pi05 and pi06 );
    n43 <= ( not pi03 )
      or ( not pi11 );
    n44 <= ( pi13 )
      or ( not pi14 );
    n45 <= ( not pi13 and pi14 );
    n46 <= ( pi13 and pi14 and not n64 );
    n47 <= ( n68 )
      or ( n77 )
      or ( n73 );
    n48 <= ( not pi04 and not n43 );
    n49 <= ( pi02 and not pi05 and pi11 );
    n50 <= ( not n42 and not n43 );
    n51 <= ( not n43 and not n44 );
    n52 <= ( not pi04 and pi13 );
    n53 <= ( pi13 and not n76 );
    n54 <= ( not pi05 and pi13 );
    n55 <= ( n52 )
      or ( n53 )
      or ( n54 );
    n56 <= ( pi02 and not pi04 and pi11 );
    n57 <= ( not pi03 and pi13 and not n66 );
    n58 <= ( pi02 and not pi06 and pi11 );
    n59 <= ( n49 )
      or ( n58 )
      or ( n56 );
    n60 <= ( pi13 and not n66 and not n69 );
    n61 <= ( pi12 )
      or ( not n59 );
    n62 <= ( not pi03 and not pi13 and not pi14 );
    n63 <= ( not pi02 )
      or ( pi12 )
      or ( n78 );
    n64 <= ( not pi07 )
      or ( not pi08 )
      or ( not n65 );
    n65 <= ( pi09 and pi10 and pi11 );
    n66 <= ( not pi02 )
      or ( pi12 )
      or ( n72 );
    n67 <= ( pi04 and pi05 and pi06 );
    n68 <= ( not pi07 and pi14 );
    n69 <= ( not pi11 )
      or ( not pi14 )
      or ( n67 );
    n70 <= ( not pi13 and not n63 );
    n71 <= ( pi14 and not n63 );
    n72 <= ( not pi03 and pi14 );
    n73 <= ( not pi08 and pi14 );
    n74 <= ( not pi02 )
      or ( pi11 )
      or ( pi12 );
    n75 <= ( pi09 and pi10 );
    n76 <= ( pi06 and pi11 and pi14 );
    n77 <= ( pi14 and not n75 );
    n78 <= ( not pi13 and pi14 );
end IWLS93__pm1__part2_behav;
