--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part9 is 
  Port (
    pi770,pi771: in std_logic;
    po221: inout std_logic
  );
end Other__fp_operators__part9;

architecture Other__fp_operators__part9_behav of Other__fp_operators__part9 is
begin
    po221 <= not (( not pi770 and not pi771 ));
end Other__fp_operators__part9_behav;
