--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s27 is 
  Port (
    pi0,pi1,pi2,pi3, CLK: in std_logic;
    po0: inout std_logic
  );
end ISCAS__s27;

architecture ISCAS__s27_behav of ISCAS__s27 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,li0,li1,li2,n18,n19,n20,n21,n22: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    po0 <= ( not li1 );
    li0 <= ( pi0 and not li1 );
    li1 <= ( not lo0 and not n22 );
    li2 <= ( not pi2 and not n19 );
    n18 <= ( not pi0 and lo1 );
    n19 <= ( not pi1 and not lo2 );
    n20 <= not (( not n19 and not n18 ));
    n21 <= not (( not pi3 and not n18 ));
    n22 <= not (( n21 and n20 ));
end ISCAS__s27_behav;
