--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__C7552__part3 is 
  Port (
    pi084: in std_logic;
    po00,po44,po50: inout std_logic
  );
end IWLS93__C7552__part3;

architecture IWLS93__C7552__part3_behav of IWLS93__C7552__part3 is
signal n271: std_logic;
begin
    n271 <= ( not pi084 );
    po00 <= ( n271 );
    po44 <= ( n271 );
    po50 <= ( n271 );
end IWLS93__C7552__part3_behav;
