--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misj__part2 is 
  Port (
    pi09,pi19,pi20: in std_logic;
    po06: inout std_logic
  );
end Espresso__misj__part2;

architecture Espresso__misj__part2_behav of Espresso__misj__part2 is
begin
    po06 <= ( pi09 )
      or ( pi19 )
      or ( pi20 );
end Espresso__misj__part2_behav;
