--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part8 is 
  Port (
    pi29: in std_logic;
    po11: inout std_logic
  );
end Espresso__mish__part8;

architecture Espresso__mish__part8_behav of Espresso__mish__part8 is
begin
    po11 <= ( not pi29 );
end Espresso__mish__part8_behav;
