--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__vga_driver__part0 is 
  Port (
    pi0: in std_logic;
    po24: inout std_logic
  );
end Cookbook__vga_driver__part0;

architecture Cookbook__vga_driver__part0_behav of Cookbook__vga_driver__part0 is
begin
    po24 <= ( not pi0 );
end Cookbook__vga_driver__part0_behav;
