--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi21, CLK: in std_logic;
    po81: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo375,li375,n4582,n4583,n4902: std_logic;
begin
    DFF0: DFF port map (li375, CLK, lo375);
    po81 <= ( not pi21 );
    li375 <= ( n4583 and n4902 );
    n4582 <= not (( pi21 and not lo375 ));
    n4583 <= not (( pi21 and n4582 ));
    n4902 <= not (( not lo375 and n4582 ));
end top_behav;
