--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_pci__part19 is 
  Port (
    pi255, CLK: in std_logic;
    po343: inout std_logic
  );
end QUIP__oc_pci__part19;

architecture QUIP__oc_pci__part19_behav of QUIP__oc_pci__part19 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo1159,li1159: std_logic;
begin
    DFF0: DFF port map (li1159, CLK, lo1159);
    li1159 <= ( pi255 );
    po343 <= ( lo1159 );
end QUIP__oc_pci__part19_behav;
