--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi42, CLK: in std_logic;
    po121: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo400,lo535,lo583,li535,li400,li583: std_logic;
begin
    DFF0: DFF port map (li400, CLK, lo400);
    DFF1: DFF port map (li535, CLK, lo535);
    DFF2: DFF port map (li583, CLK, lo583);
    li535 <= ( pi42 );
    li400 <= ( lo535 );
    li583 <= ( lo400 );
    po121 <= ( lo583 );
end top_behav;
