--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_pci__part29 is 
  Port (
    pi266, CLK: in std_logic;
    po363: inout std_logic
  );
end QUIP__oc_pci__part29;

architecture QUIP__oc_pci__part29_behav of QUIP__oc_pci__part29 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo1185,li1185: std_logic;
begin
    DFF0: DFF port map (li1185, CLK, lo1185);
    li1185 <= ( pi266 );
    po363 <= ( lo1185 );
end QUIP__oc_pci__part29_behav;
