--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part3 is 
  Port (
    pi03,pi19,pi35: in std_logic;
    po03,po19: inout std_logic
  );
end Cookbook__compress_32__part3;

architecture Cookbook__compress_32__part3_behav of Cookbook__compress_32__part3 is
signal n92,n124,n140,n156,n172: std_logic;
begin
    n92 <= ( not pi03 and pi19 )
      or ( pi03 and not pi19 );
    po03 <= ( not n92 and pi35 )
      or ( n92 and not pi35 );
    n124 <= ( pi03 and pi35 );
    n140 <= ( pi03 and pi19 );
    n156 <= not (( not n140 and not n124 ));
    n172 <= ( pi19 and pi35 );
    po19 <= not (( not n156 and not n172 ));
end Cookbook__compress_32__part3_behav;
