--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part87 is 
  Port (
    pi0210, CLK: in std_logic;
    po0494: inout std_logic
  );
end Other__umass_weather__part87;

architecture Other__umass_weather__part87_behav of Other__umass_weather__part87 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0580,li0580: std_logic;
begin
    DFF0: DFF port map (li0580, CLK, lo0580);
    li0580 <= ( pi0210 );
    po0494 <= ( lo0580 );
end Other__umass_weather__part87_behav;
