--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__i10__part5 is 
  Port (
    pi218: in std_logic;
    po121: inout std_logic
  );
end IWLS93__i10__part5;

architecture IWLS93__i10__part5_behav of IWLS93__i10__part5 is
begin
    po121 <= ( not pi218 );
end IWLS93__i10__part5_behav;
