--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part3 is 
  Port (
    pi2096,pi3132: in std_logic;
    po2325,po3702: inout std_logic
  );
end IWLS2005__DSP__part3;

architecture IWLS2005__DSP__part3_behav of IWLS2005__DSP__part3 is
begin
    po2325 <= not (( pi2096 and not pi3132 ));
    po3702 <= ( not pi2096 );
end IWLS2005__DSP__part3_behav;
