--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part11 is 
  Port (
    pi51: in std_logic;
    po16: inout std_logic
  );
end Espresso__misg__part11;

architecture Espresso__misg__part11_behav of Espresso__misg__part11 is
begin
    po16 <= ( not pi51 );
end Espresso__misg__part11_behav;
