--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part224 is 
  Port (
    pi2125, CLK: in std_logic;
    po2016: inout std_logic
  );
end Other__umass_weather__part224;

architecture Other__umass_weather__part224_behav of Other__umass_weather__part224 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4891,lo4920,lo4992,li4891,li4920,li4992: std_logic;
begin
    DFF0: DFF port map (li4891, CLK, lo4891);
    DFF1: DFF port map (li4920, CLK, lo4920);
    DFF2: DFF port map (li4992, CLK, lo4992);
    li4891 <= ( lo4920 );
    li4920 <= ( lo4992 );
    li4992 <= ( pi2125 );
    po2016 <= ( lo4891 );
end Other__umass_weather__part224_behav;
