--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part4 is 
  Port (
    pi15: in std_logic;
    po04: inout std_logic
  );
end Espresso__misg__part4;

architecture Espresso__misg__part4_behav of Espresso__misg__part4 is
begin
    po04 <= ( not pi15 );
end Espresso__misg__part4_behav;
