--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part221 is 
  Port (
    pi2122, CLK: in std_logic;
    po2013: inout std_logic
  );
end Other__umass_weather__part221;

architecture Other__umass_weather__part221_behav of Other__umass_weather__part221 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4888,lo4917,lo4989,li4888,li4917,li4989: std_logic;
begin
    DFF0: DFF port map (li4888, CLK, lo4888);
    DFF1: DFF port map (li4917, CLK, lo4917);
    DFF2: DFF port map (li4989, CLK, lo4989);
    li4888 <= ( lo4917 );
    li4917 <= ( lo4989 );
    li4989 <= ( pi2122 );
    po2013 <= ( lo4888 );
end Other__umass_weather__part221_behav;
