--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__b9__part1 is 
  Port (
    pi01,pi22,pi23,pi24: in std_logic;
    po16,po17: inout std_logic
  );
end LGSynth91__b9__part1;

architecture LGSynth91__b9__part1_behav of LGSynth91__b9__part1 is
signal n96,n97: std_logic;
begin
    po16 <= ( not n96 );
    po17 <= ( not n97 );
    n96 <= ( not pi01 )
      or ( not pi22 )
      or ( pi23 );
    n97 <= ( not pi01 )
      or ( not pi22 )
      or ( not pi23 )
      or ( pi24 );
end LGSynth91__b9__part1_behav;
