--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8,pi9, CLK: in std_logic;
    po0: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,lo5,lo6,lo7,li0,li1,li2,li3,li4,li5,li6,li7,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    DFF5: DFF port map (li5, CLK, lo5);
    DFF6: DFF port map (li6, CLK, lo6);
    DFF7: DFF port map (li7, CLK, lo7);
    li0 <= ( n61 )
      or ( not n68 );
    li1 <= ( not n45 and not n47 );
    li2 <= ( n92 )
      or ( n89 );
    li3 <= ( n81 )
      or ( n82 );
    li4 <= ( not n55 and not n58 );
    li5 <= ( n86 )
      or ( n83 );
    li6 <= ( not n62 )
      or ( not n63 );
    li7 <= ( not n49 )
      or ( not n52 );
    po0 <= ( n64 )
      or ( n65 );
    n44 <= ( lo4 and not n50 );
    n45 <= ( not lo1 and n66 );
    n46 <= ( not lo4 )
      or ( not lo5 );
    n47 <= ( lo1 and not n66 );
    n48 <= ( pi0 and not n46 );
    n49 <= ( not lo3 )
      or ( lo7 )
      or ( not n48 );
    n50 <= ( not pi0 )
      or ( lo5 );
    n51 <= ( not pi0 )
      or ( not lo5 );
    n52 <= ( not lo7 )
      or ( not n99 );
    n53 <= ( lo1 )
      or ( n59 );
    n54 <= ( lo1 and not n66 );
    n55 <= ( lo4 and not n51 );
    n56 <= ( n84 and n88 );
    n57 <= ( pi0 and n85 );
    n58 <= ( not lo4 and n51 );
    n59 <= ( not pi0 )
      or ( lo2 );
    n60 <= ( lo3 and not n78 );
    n61 <= ( lo0 and not n54 );
    n62 <= ( not lo0 )
      or ( lo6 )
      or ( n91 );
    n63 <= ( not lo6 )
      or ( not n73 );
    n64 <= ( pi1 and n79 );
    n65 <= ( n100 )
      or ( n95 );
    n66 <= ( not lo2 )
      or ( not n57 );
    n67 <= ( n94 and n88 );
    n68 <= ( lo0 )
      or ( n91 );
    n69 <= ( n87 and n88 );
    n70 <= ( pi4 and n69 );
    n71 <= ( not pi6 )
      or ( not n60 );
    n72 <= ( not n96 and not n98 );
    n73 <= ( not lo0 )
      or ( not lo1 )
      or ( n66 );
    n74 <= ( not lo3 and lo7 and not n78 );
    n75 <= ( not n70 and not n76 );
    n76 <= ( pi5 and n74 );
    n77 <= ( not pi2 )
      or ( not n67 );
    n78 <= ( lo4 )
      or ( n50 );
    n79 <= ( n93 and n88 );
    n80 <= ( not pi7 )
      or ( not n44 );
    n81 <= ( lo3 and not n48 );
    n82 <= ( not lo3 and n48 );
    n83 <= ( not pi0 and lo5 );
    n84 <= ( lo1 and not n59 );
    n85 <= ( lo3 and lo7 and not n46 );
    n86 <= ( pi0 and not lo5 );
    n87 <= ( pi0 and lo2 );
    n88 <= ( not lo3 and not lo4 and not lo5 and not lo7 );
    n89 <= ( lo2 and not n57 );
    n90 <= ( pi0 and lo5 );
    n91 <= ( not lo1 )
      or ( n66 );
    n92 <= ( not lo2 and n57 );
    n93 <= ( not lo0 and lo6 and not n53 );
    n94 <= ( lo0 and not n53 );
    n95 <= ( not n71 )
      or ( not n72 )
      or ( not n80 );
    n96 <= ( pi8 and n90 );
    n97 <= ( not pi3 )
      or ( not n56 );
    n98 <= ( pi0 and pi9 );
    n99 <= ( not pi0 )
      or ( not lo3 )
      or ( n46 );
    n100 <= ( not n75 )
      or ( not n77 )
      or ( not n97 );
end top_behav;
