--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part7 is 
  Port (
    pi3637: in std_logic;
    po3757: inout std_logic
  );
end IWLS2005__DSP__part7;

architecture IWLS2005__DSP__part7_behav of IWLS2005__DSP__part7 is
begin
    po3757 <= ( not pi3637 );
end IWLS2005__DSP__part7_behav;
