--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__pm1__part0 is 
  Port (
    pi00: in std_logic;
    po08: inout std_logic
  );
end IWLS93__pm1__part0;

architecture IWLS93__pm1__part0_behav of IWLS93__pm1__part0 is
begin
    po08 <= ( not pi00 );
end IWLS93__pm1__part0_behav;
