--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7: inout std_logic
  );
end top;

architecture top_behav of top is
signal n24,n26,n28,n30,n32,n34: std_logic;
begin
    po7 <= ( not pi14 and not pi12 and pi13 )
      or ( not pi14 and pi12 and not pi13 )
      or ( pi14 and not pi12 and not pi13 )
      or ( pi14 and pi12 and pi13 );
    n24 <= ( pi14 and pi12 )
      or ( pi14 and pi13 )
      or ( pi12 and pi13 );
    po6 <= ( not n24 and not pi05 and pi11 )
      or ( not n24 and pi05 and not pi11 )
      or ( n24 and not pi05 and not pi11 )
      or ( n24 and pi05 and pi11 );
    n26 <= ( n24 and pi05 )
      or ( n24 and pi11 )
      or ( pi05 and pi11 );
    po5 <= ( not n26 and not pi04 and pi10 )
      or ( not n26 and pi04 and not pi10 )
      or ( n26 and not pi04 and not pi10 )
      or ( n26 and pi04 and pi10 );
    n28 <= ( n26 and pi04 )
      or ( n26 and pi10 )
      or ( pi04 and pi10 );
    po4 <= ( not n28 and not pi03 and pi09 )
      or ( not n28 and pi03 and not pi09 )
      or ( n28 and not pi03 and not pi09 )
      or ( n28 and pi03 and pi09 );
    n30 <= ( n28 and pi03 )
      or ( n28 and pi09 )
      or ( pi03 and pi09 );
    po3 <= ( not n30 and not pi02 and pi08 )
      or ( not n30 and pi02 and not pi08 )
      or ( n30 and not pi02 and not pi08 )
      or ( n30 and pi02 and pi08 );
    n32 <= ( n30 and pi02 )
      or ( n30 and pi08 )
      or ( pi02 and pi08 );
    po2 <= ( not n32 and not pi01 and pi07 )
      or ( not n32 and pi01 and not pi07 )
      or ( n32 and not pi01 and not pi07 )
      or ( n32 and pi01 and pi07 );
    n34 <= ( n32 and pi01 )
      or ( n32 and pi07 )
      or ( pi01 and pi07 );
    po1 <= ( not n34 and not pi00 and pi06 )
      or ( not n34 and pi00 and not pi06 )
      or ( n34 and not pi00 and not pi06 )
      or ( n34 and pi00 and pi06 );
    po0 <= ( n34 and pi00 )
      or ( n34 and pi06 )
      or ( pi00 and pi06 );
end top_behav;
