--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part218 is 
  Port (
    pi2119, CLK: in std_logic;
    po2010: inout std_logic
  );
end Other__umass_weather__part218;

architecture Other__umass_weather__part218_behav of Other__umass_weather__part218 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4885,lo4914,lo4986,li4885,li4914,li4986: std_logic;
begin
    DFF0: DFF port map (li4885, CLK, lo4885);
    DFF1: DFF port map (li4914, CLK, lo4914);
    DFF2: DFF port map (li4986, CLK, lo4986);
    li4885 <= ( lo4914 );
    li4914 <= ( lo4986 );
    li4986 <= ( pi2119 );
    po2010 <= ( lo4885 );
end Other__umass_weather__part218_behav;
