--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__C2670__part1 is 
  Port (
    pi035,pi124: in std_logic;
    po32: inout std_logic
  );
end IWLS93__C2670__part1;

architecture IWLS93__C2670__part1_behav of IWLS93__C2670__part1 is
begin
    po32 <= ( pi035 and pi124 );
end IWLS93__C2670__part1_behav;
