--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part14 is 
  Port (
    pi70,pi71,pi72,pi73: in std_logic;
    po25: inout std_logic
  );
end Espresso__mish__part14;

architecture Espresso__mish__part14_behav of Espresso__mish__part14 is
begin
    po25 <= ( not pi70 )
      or ( not pi71 )
      or ( not pi72 )
      or ( not pi73 );
end Espresso__mish__part14_behav;
