--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part0 is 
  Port (
    pi09,pi00, CLK: in std_logic;
    po00: inout std_logic
  );
end Cookbook__approx_fp_div__part0;

architecture Cookbook__approx_fp_div__part0_behav of Cookbook__approx_fp_div__part0 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo08,lo17,lo26,lo27,lo28,lo84,lo85,li17,li08,li26,li27,li28,li84,li85: std_logic;
begin
    DFF0: DFF port map (li08, CLK, lo08);
    DFF1: DFF port map (li17, CLK, lo17);
    DFF2: DFF port map (li26, CLK, lo26);
    DFF3: DFF port map (li27, CLK, lo27);
    DFF4: DFF port map (li28, CLK, lo28);
    DFF5: DFF port map (li84, CLK, lo84);
    DFF6: DFF port map (li85, CLK, lo85);
    li17 <= ( not lo85 and lo08 )
      or ( lo85 and not lo08 );
    li08 <= ( pi09 );
    li26 <= ( lo17 );
    li27 <= ( lo26 );
    li28 <= ( lo27 );
    li84 <= ( lo28 );
    li85 <= ( pi00 );
    po00 <= ( lo84 );
end Cookbook__approx_fp_div__part0_behav;
