--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part1 is 
  Port (
    pi1594,pi3133,pi2561: in std_logic;
    po1821,po3759: inout std_logic
  );
end IWLS2005__DSP__part1;

architecture IWLS2005__DSP__part1_behav of IWLS2005__DSP__part1 is
signal n40014,n40015,n40016: std_logic;
begin
    n40014 <= ( pi1594 and not pi3133 );
    n40015 <= ( not pi1594 and pi3133 );
    n40016 <= ( pi2561 and not n40015 );
    po1821 <= ( not n40014 and not n40016 );
    po3759 <= ( not pi1594 );
end IWLS2005__DSP__part1_behav;
