--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__c5315__part0 is 
  Port (
    pi133,pi000: in std_logic;
    po014: inout std_logic
  );
end ISCAS__c5315__part0;

architecture ISCAS__c5315__part0_behav of ISCAS__c5315__part0 is
begin
    po014 <= ( pi133 and pi000 );
end ISCAS__c5315__part0_behav;
