--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__screen_saver_cyclone__part1 is 
  Port (
    pi01: in std_logic;
    po41: inout std_logic
  );
end Other__screen_saver_cyclone__part1;

architecture Other__screen_saver_cyclone__part1_behav of Other__screen_saver_cyclone__part1 is
begin
    po41 <= ( not pi01 );
end Other__screen_saver_cyclone__part1_behav;
