--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part236 is 
  Port (
    pi2137, CLK: in std_logic;
    po2028: inout std_logic
  );
end Other__umass_weather__part236;

architecture Other__umass_weather__part236_behav of Other__umass_weather__part236 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4903,lo4975,lo5047,li4903,li4975,li5047: std_logic;
begin
    DFF0: DFF port map (li4903, CLK, lo4903);
    DFF1: DFF port map (li4975, CLK, lo4975);
    DFF2: DFF port map (li5047, CLK, lo5047);
    li4903 <= ( lo4975 );
    li4975 <= ( lo5047 );
    li5047 <= ( pi2137 );
    po2028 <= ( lo4903 );
end Other__umass_weather__part236_behav;
