--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part8 is 
  Port (
    pi758,pi759: in std_logic;
    po160: inout std_logic
  );
end Other__fp_operators__part8;

architecture Other__fp_operators__part8_behav of Other__fp_operators__part8 is
begin
    po160 <= not (( not pi758 and not pi759 ));
end Other__fp_operators__part8_behav;
