--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi09: in std_logic;
    po248: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po248 <= ( not pi09 );
end top_behav;
