--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__x2dn__part1 is 
  Port (
    pi12,pi13,pi14: in std_logic;
    po17: inout std_logic
  );
end Espresso__x2dn__part1;

architecture Espresso__x2dn__part1_behav of Espresso__x2dn__part1 is
begin
    po17 <= ( pi12 and not pi13 )
      or ( pi12 and not pi14 );
end Espresso__x2dn__part1_behav;
