--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part15 is 
  Port (
    pi91,pi92,pi93: in std_logic;
    po33: inout std_logic
  );
end Espresso__mish__part15;

architecture Espresso__mish__part15_behav of Espresso__mish__part15 is
begin
    po33 <= ( pi91 and pi92 and pi93 );
end Espresso__mish__part15_behav;
