--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s9234__part1 is 
  Port (
    , CLK: in std_logic;
    : inout std_logic
  );
end ISCAS__s9234__part1;

architecture ISCAS__s9234__part1_behav of ISCAS__s9234__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo002,lo022,li002,li022: std_logic;
begin
    DFF0: DFF port map (li002, CLK, lo002);
    DFF1: DFF port map (li022, CLK, lo022);
    li002 <= ( lo002 );
    li022 <= ( lo022 );
end ISCAS__s9234__part1_behav;
