--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__rot__part1 is 
  Port (
    pi017,pi041,pi091,pi109,pi114,pi108: in std_logic;
    po83,po84: inout std_logic
  );
end LGSynth91__rot__part1;

architecture LGSynth91__rot__part1_behav of LGSynth91__rot__part1 is
begin
    po83 <= ( pi041 and pi091 )
      or ( pi017 and pi109 )
      or ( pi017 and not pi114 );
    po84 <= ( pi108 and pi114 );
end LGSynth91__rot__part1_behav;
