--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part28 is 
  Port (
    pi0088, CLK: in std_logic;
    po0308: inout std_logic
  );
end Other__umass_weather__part28;

architecture Other__umass_weather__part28_behav of Other__umass_weather__part28 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0409,li0409: std_logic;
begin
    DFF0: DFF port map (li0409, CLK, lo0409);
    li0409 <= ( pi0088 );
    po0308 <= ( lo0409 );
end Other__umass_weather__part28_behav;
