--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_pci__part22 is 
  Port (
    pi258, CLK: in std_logic;
    po349: inout std_logic
  );
end QUIP__oc_pci__part22;

architecture QUIP__oc_pci__part22_behav of QUIP__oc_pci__part22 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo1165,li1165: std_logic;
begin
    DFF0: DFF port map (li1165, CLK, lo1165);
    li1165 <= ( pi258 );
    po349 <= ( lo1165 );
end QUIP__oc_pci__part22_behav;
