--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_6__part1 is 
  Port (
    pi11,pi05,pi09,pi03,pi01,pi21,pi19,pi17,pi15,pi13,pi07: in std_logic;
    po19,po17,po15,po13,po11,po09,po07,po05,po03,po01: inout std_logic
  );
end Cookbook__fec_rot_6__part1;

architecture Cookbook__fec_rot_6__part1_behav of Cookbook__fec_rot_6__part1 is
signal n42,n44: std_logic;
begin
    n42 <= ( not pi11 and pi05 )
      or ( pi11 and not pi05 );
    n44 <= ( not pi09 and pi03 )
      or ( pi09 and not pi03 );
    po19 <= ( not pi05 and pi03 )
      or ( pi05 and not pi03 );
    po17 <= ( not pi03 and pi01 )
      or ( pi03 and not pi01 );
    po15 <= ( not pi21 and pi01 )
      or ( pi21 and not pi01 );
    po13 <= ( not pi19 and pi05 )
      or ( pi19 and not pi05 );
    po11 <= ( not pi17 and pi03 )
      or ( pi17 and not pi03 );
    po09 <= ( not pi15 and pi01 )
      or ( pi15 and not pi01 );
    po07 <= ( not pi13 and pi05 )
      or ( pi13 and not pi05 );
    po05 <= ( not n42 and pi03 )
      or ( n42 and not pi03 );
    po03 <= ( not n44 and pi01 )
      or ( n44 and not pi01 );
    po01 <= ( not pi07 and pi01 )
      or ( pi07 and not pi01 );
end Cookbook__fec_rot_6__part1_behav;
