--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part6 is 
  Port (
    pi3571: in std_logic;
    po1042: inout std_logic
  );
end IWLS2005__DSP__part6;

architecture IWLS2005__DSP__part6_behav of IWLS2005__DSP__part6 is
begin
    po1042 <= ( not pi3571 );
end IWLS2005__DSP__part6_behav;
