--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__ex4__part3 is 
  Port (
    pi03,pi10,pi17,pi27,pi34,pi41,pi51,pi58,pi65: in std_logic;
    po03,po10: inout std_logic
  );
end Espresso__ex4__part3;

architecture Espresso__ex4__part3_behav of Espresso__ex4__part3 is
begin
    po03 <= ( not pi27 and pi34 and not pi41 )
      or ( not pi10 and pi34 and not pi58 )
      or ( pi10 and not pi17 and pi34 and pi41 and not pi51 )
      or ( not pi17 and pi27 and pi34 and pi41 and not pi51 )
      or ( pi10 and not pi17 and pi34 and not pi51 and pi58 )
      or ( not pi17 and pi27 and pi34 and not pi51 and pi58 )
      or ( not pi03 and pi10 and pi27 and pi34 and not pi65 )
      or ( not pi03 and pi27 and pi34 and pi41 and not pi65 )
      or ( not pi03 and pi10 and pi34 and pi58 and not pi65 )
      or ( not pi03 and pi34 and pi41 and pi58 and not pi65 );
    po10 <= ( pi27 and not pi34 and pi41 )
      or ( pi10 and not pi34 and pi58 )
      or ( not pi10 and pi17 and not pi34 and not pi41 and pi51 )
      or ( pi17 and not pi27 and not pi34 and not pi41 and pi51 )
      or ( not pi10 and pi17 and not pi34 and pi51 and not pi58 )
      or ( pi17 and not pi27 and not pi34 and pi51 and not pi58 )
      or ( pi03 and not pi10 and not pi27 and not pi34 and pi65 )
      or ( pi03 and not pi27 and not pi34 and not pi41 and pi65 )
      or ( pi03 and not pi10 and not pi34 and not pi58 and pi65 )
      or ( pi03 and not pi34 and not pi41 and not pi58 and pi65 );
end Espresso__ex4__part3_behav;
