--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part1 is 
  Port (
    pi01,pi17,pi33: in std_logic;
    po01,po17: inout std_logic
  );
end Cookbook__compress_32__part1;

architecture Cookbook__compress_32__part1_behav of Cookbook__compress_32__part1 is
signal n94,n126,n142,n158,n174: std_logic;
begin
    n94 <= ( not pi01 and pi17 )
      or ( pi01 and not pi17 );
    po01 <= ( not n94 and pi33 )
      or ( n94 and not pi33 );
    n126 <= ( pi01 and pi33 );
    n142 <= ( pi01 and pi17 );
    n158 <= not (( not n142 and not n126 ));
    n174 <= ( pi17 and pi33 );
    po17 <= not (( not n158 and not n174 ));
end Cookbook__compress_32__part1_behav;
