--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__stream_mux is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21, CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11: inout std_logic
  );
end Cookbook__stream_mux;

architecture Cookbook__stream_mux_behav of Cookbook__stream_mux is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,n49,n51,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,li2,n83,n84,n85,n86,n87,li3,n89,n90,n91,n92,n93,li4,n95,n96,n97,li0,n99,li1,n101: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    n49 <= ( lo1 and not lo0 );
    po00 <= ( n49 and pi21 );
    n51 <= ( lo1 and lo0 );
    po01 <= ( n51 and pi21 );
    po03 <= ( pi08 and not lo0 )
      or ( pi18 and lo0 );
    po11 <= ( pi07 and not lo0 )
      or ( pi17 and lo0 );
    po10 <= ( pi06 and not lo0 )
      or ( pi16 and lo0 );
    po09 <= ( pi05 and not lo0 )
      or ( pi15 and lo0 );
    po08 <= ( pi04 and not lo0 )
      or ( pi14 and lo0 );
    po07 <= ( pi03 and not lo0 )
      or ( pi13 and lo0 );
    po06 <= ( pi02 and not lo0 )
      or ( pi12 and lo0 );
    po05 <= ( pi01 and not lo0 )
      or ( pi11 and lo0 );
    po04 <= ( pi00 and not lo0 )
      or ( pi10 and lo0 );
    n62 <= not (( not lo2 and not pi20 ));
    n63 <= ( lo3 and not pi20 );
    n64 <= ( lo4 and not pi20 );
    n65 <= ( lo2 and not pi09 );
    n66 <= not (( not lo3 and not pi09 ));
    n67 <= ( lo4 and not pi09 );
    n68 <= not (( not lo2 and pi09 ));
    n69 <= not (( not lo3 and pi09 ));
    n70 <= ( lo4 and pi09 );
    n71 <= ( lo2 and not pi19 );
    n72 <= ( lo3 and not pi19 );
    n73 <= not (( not lo4 and not pi19 ));
    n74 <= ( lo2 and pi19 );
    n75 <= ( lo3 and pi19 );
    n76 <= ( lo4 and pi19 );
    n77 <= ( n62 and not lo2 )
      or ( n65 and lo2 );
    n78 <= ( n68 and not lo2 )
      or ( n71 and lo2 );
    n79 <= ( n77 and not lo3 )
      or ( n78 and lo3 );
    n80 <= not (( not n74 and not lo2 ));
    n81 <= ( n80 and not lo3 )
      or ( lo2 and lo3 );
    li2 <= ( n79 and not lo4 )
      or ( n81 and lo4 );
    n83 <= ( n63 and not lo2 )
      or ( n66 and lo2 );
    n84 <= ( n69 and not lo2 )
      or ( n72 and lo2 );
    n85 <= ( n83 and not lo3 )
      or ( n84 and lo3 );
    n86 <= ( n75 and not lo2 )
      or ( lo3 and lo2 );
    n87 <= not (( not n86 and not lo3 ));
    li3 <= ( n85 and not lo4 )
      or ( n87 and lo4 );
    n89 <= ( n64 and not lo2 )
      or ( n67 and lo2 );
    n90 <= ( n70 and not lo2 )
      or ( n73 and lo2 );
    n91 <= ( n89 and not lo3 )
      or ( n90 and lo3 );
    n92 <= ( n76 and not lo2 )
      or ( lo4 and lo2 );
    n93 <= ( n92 and not lo3 )
      or ( lo4 and lo3 );
    li4 <= ( n91 and not lo4 )
      or ( n93 and lo4 );
    n95 <= ( lo0 and lo2 );
    n96 <= not (( not lo0 and not lo2 ));
    n97 <= ( n95 and not lo3 )
      or ( n96 and lo3 );
    li0 <= ( n97 and not lo4 )
      or ( lo0 and lo4 );
    n99 <= ( lo2 and not lo3 )
      or ( lo1 and lo3 );
    li1 <= ( n99 and not lo4 )
      or ( lo1 and lo4 );
    n101 <= not (( not lo2 and not lo3 ));
    po02 <= not (( not n101 and not lo4 ));
end Cookbook__stream_mux_behav;
