--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_sr_cells is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26, CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17,po18,po19,po20: inout std_logic
  );
end Cookbook__mlab_sr_cells;

architecture Cookbook__mlab_sr_cells_behav of Cookbook__mlab_sr_cells is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,lo12,lo13,lo14,lo15,lo16,lo17,lo18,lo19,lo20,lo21,lo22,lo23,lo24,lo25,lo26,lo27,lo28,lo29,lo30,lo31,lo32,lo33,lo34,lo35,lo36,lo37,lo38,lo39,lo40,lo41,lo42,lo43,lo44,lo45,li26,li27,li28,li29,li30,li31,li32,li33,li34,li35,li36,li37,li38,li39,li40,li41,li42,li43,li44,li45,li00,li01,li02,li03,li04,n211,n212,n213,n214,n215,n216,n217,n218,n219,n220,n221,n222,n223,n224,n225,n226,li05,li06,li07,li08,li09,li10,li11,li12,li13,li14,li15,li16,li17,li18,li19,li20,li21,li22,li23,li24,li25,n248,n249,n250,n251: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    DFF12: DFF port map (li12, CLK, lo12);
    DFF13: DFF port map (li13, CLK, lo13);
    DFF14: DFF port map (li14, CLK, lo14);
    DFF15: DFF port map (li15, CLK, lo15);
    DFF16: DFF port map (li16, CLK, lo16);
    DFF17: DFF port map (li17, CLK, lo17);
    DFF18: DFF port map (li18, CLK, lo18);
    DFF19: DFF port map (li19, CLK, lo19);
    DFF20: DFF port map (li20, CLK, lo20);
    DFF21: DFF port map (li21, CLK, lo21);
    DFF22: DFF port map (li22, CLK, lo22);
    DFF23: DFF port map (li23, CLK, lo23);
    DFF24: DFF port map (li24, CLK, lo24);
    DFF25: DFF port map (li25, CLK, lo25);
    DFF26: DFF port map (li26, CLK, lo26);
    DFF27: DFF port map (li27, CLK, lo27);
    DFF28: DFF port map (li28, CLK, lo28);
    DFF29: DFF port map (li29, CLK, lo29);
    DFF30: DFF port map (li30, CLK, lo30);
    DFF31: DFF port map (li31, CLK, lo31);
    DFF32: DFF port map (li32, CLK, lo32);
    DFF33: DFF port map (li33, CLK, lo33);
    DFF34: DFF port map (li34, CLK, lo34);
    DFF35: DFF port map (li35, CLK, lo35);
    DFF36: DFF port map (li36, CLK, lo36);
    DFF37: DFF port map (li37, CLK, lo37);
    DFF38: DFF port map (li38, CLK, lo38);
    DFF39: DFF port map (li39, CLK, lo39);
    DFF40: DFF port map (li40, CLK, lo40);
    DFF41: DFF port map (li41, CLK, lo41);
    DFF42: DFF port map (li42, CLK, lo42);
    DFF43: DFF port map (li43, CLK, lo43);
    DFF44: DFF port map (li44, CLK, lo44);
    DFF45: DFF port map (li45, CLK, lo45);
    li26 <= ( lo26 and not pi00 )
      or ( pi20 and pi00 );
    li27 <= ( lo27 and not pi00 )
      or ( pi19 and pi00 );
    li28 <= ( lo28 and not pi00 )
      or ( pi18 and pi00 );
    li29 <= ( lo29 and not pi00 )
      or ( pi17 and pi00 );
    li30 <= ( lo30 and not pi00 )
      or ( pi16 and pi00 );
    li31 <= ( lo31 and not pi00 )
      or ( pi15 and pi00 );
    li32 <= ( lo32 and not pi00 )
      or ( pi14 and pi00 );
    li33 <= ( lo33 and not pi00 )
      or ( pi13 and pi00 );
    li34 <= ( lo34 and not pi00 )
      or ( pi12 and pi00 );
    li35 <= ( lo35 and not pi00 )
      or ( pi11 and pi00 );
    li36 <= ( lo36 and not pi00 )
      or ( pi10 and pi00 );
    li37 <= ( lo37 and not pi00 )
      or ( pi09 and pi00 );
    li38 <= ( lo38 and not pi00 )
      or ( pi08 and pi00 );
    li39 <= ( lo39 and not pi00 )
      or ( pi07 and pi00 );
    li40 <= ( lo40 and not pi00 )
      or ( pi06 and pi00 );
    li41 <= ( lo41 and not pi00 )
      or ( pi05 and pi00 );
    li42 <= ( lo42 and not pi00 )
      or ( pi04 and pi00 );
    li43 <= ( lo43 and not pi00 )
      or ( pi03 and pi00 );
    li44 <= ( lo44 and not pi00 )
      or ( pi02 and pi00 );
    li45 <= ( lo45 and not pi00 )
      or ( pi01 and pi00 );
    li00 <= ( lo00 and not pi00 )
      or ( pi25 and pi00 );
    li01 <= ( lo01 and not pi00 )
      or ( pi24 and pi00 );
    li02 <= ( lo02 and not pi00 )
      or ( pi23 and pi00 );
    li03 <= ( lo03 and not pi00 )
      or ( pi22 and pi00 );
    li04 <= ( lo04 and not pi00 )
      or ( pi21 and pi00 );
    n211 <= ( not lo06 and lo07 )
      or ( lo06 and not lo07 );
    n212 <= ( not lo05 and n211 )
      or ( lo05 and not n211 );
    n213 <= ( not lo09 and lo10 )
      or ( lo09 and not lo10 );
    n214 <= ( not lo08 and n213 )
      or ( lo08 and not n213 );
    n215 <= ( not n212 and n214 )
      or ( n212 and not n214 );
    n216 <= ( not lo11 and lo12 )
      or ( lo11 and not lo12 );
    n217 <= ( not lo13 and lo14 )
      or ( lo13 and not lo14 );
    n218 <= ( not n216 and n217 )
      or ( n216 and not n217 );
    n219 <= ( not lo16 and lo17 )
      or ( lo16 and not lo17 );
    n220 <= ( not lo15 and n219 )
      or ( lo15 and not n219 );
    n221 <= ( not lo19 and lo20 )
      or ( lo19 and not lo20 );
    n222 <= ( not lo18 and n221 )
      or ( lo18 and not n221 );
    n223 <= ( not n220 and n222 )
      or ( n220 and not n222 );
    n224 <= ( not lo21 and lo22 )
      or ( lo21 and not lo22 );
    n225 <= ( not lo23 and lo24 )
      or ( lo23 and not lo24 );
    n226 <= ( not n224 and n225 )
      or ( n224 and not n225 );
    li05 <= ( lo05 and not pi00 );
    li06 <= ( lo06 and not pi00 );
    li07 <= ( lo07 and not pi00 );
    li08 <= ( lo08 and not pi00 );
    li09 <= ( lo09 and not pi00 );
    li10 <= ( lo10 and not pi00 );
    li11 <= ( lo11 and not pi00 );
    li12 <= ( lo12 and not pi00 );
    li13 <= ( lo13 and not pi00 );
    li14 <= ( lo14 and not pi00 );
    li15 <= ( lo15 and not pi00 );
    li16 <= ( lo16 and not pi00 );
    li17 <= ( lo17 and not pi00 );
    li18 <= ( lo18 and not pi00 );
    li19 <= ( lo19 and not pi00 );
    li20 <= ( lo20 and not pi00 );
    li21 <= ( lo21 and not pi00 );
    li22 <= ( lo22 and not pi00 );
    li23 <= ( lo23 and not pi00 );
    li24 <= ( lo24 and not pi00 );
    li25 <= ( lo25 and not pi00 )
      or ( not n251 and pi00 );
    n248 <= ( not n218 and n215 )
      or ( n218 and not n215 );
    n249 <= ( not n226 and n223 )
      or ( n226 and not n223 );
    n250 <= ( n248 and not pi26 );
    n251 <= ( n249 and n250 );
    po00 <= ( lo24 );
    po01 <= ( lo23 );
    po02 <= ( lo22 );
    po03 <= ( lo21 );
    po04 <= ( lo20 );
    po05 <= ( lo19 );
    po06 <= ( lo18 );
    po07 <= ( lo17 );
    po08 <= ( lo16 );
    po09 <= ( lo15 );
    po10 <= ( lo14 );
    po11 <= ( lo13 );
    po12 <= ( lo12 );
    po13 <= ( lo11 );
    po14 <= ( lo10 );
    po15 <= ( lo09 );
    po16 <= ( lo08 );
    po17 <= ( lo07 );
    po18 <= ( lo06 );
    po19 <= ( lo05 );
    po20 <= ( lo25 );
end Cookbook__mlab_sr_cells_behav;
