--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__C17 is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1: inout std_logic
  );
end IWLS93__C17;

architecture IWLS93__C17_behav of IWLS93__C17 is
signal n9,n10,n11,n12,n13,n14: std_logic;
begin
    po0 <= ( not n10 );
    po1 <= ( not n11 );
    n9 <= ( pi2 and not n14 );
    n10 <= ( not n12 and not n13 );
    n11 <= ( not n9 and not n12 );
    n12 <= ( pi3 and not n14 );
    n13 <= ( pi0 and pi4 );
    n14 <= ( pi1 and pi4 );
end IWLS93__C17_behav;
