--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part8 is 
  Port (
    pi08,pi24,pi40: in std_logic;
    po08,po24: inout std_logic
  );
end Cookbook__compress_32__part8;

architecture Cookbook__compress_32__part8_behav of Cookbook__compress_32__part8 is
signal n87,n119,n135,n151,n167: std_logic;
begin
    n87 <= ( not pi08 and pi24 )
      or ( pi08 and not pi24 );
    po08 <= ( not n87 and pi40 )
      or ( n87 and not pi40 );
    n119 <= ( pi08 and pi40 );
    n135 <= ( pi08 and pi24 );
    n151 <= not (( not n135 and not n119 ));
    n167 <= ( pi24 and pi40 );
    po24 <= not (( not n151 and not n167 ));
end Cookbook__compress_32__part8_behav;
