--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__insert_parity__part3 is 
  Port (
    pi35,pi34,pi33,pi32,pi31,pi30,pi28,pi27,pi29: in std_logic;
    po3: inout std_logic
  );
end Cookbook__insert_parity__part3;

architecture Cookbook__insert_parity__part3_behav of Cookbook__insert_parity__part3 is
signal n58,n59,n60,n61,n62,n63,n64: std_logic;
begin
    n58 <= ( not pi35 and pi34 )
      or ( pi35 and not pi34 );
    n59 <= ( not pi33 and pi32 )
      or ( pi33 and not pi32 );
    n60 <= ( not n58 and n59 )
      or ( n58 and not n59 );
    n61 <= ( not pi31 and pi30 )
      or ( pi31 and not pi30 );
    n62 <= ( not pi28 and pi27 )
      or ( pi28 and not pi27 );
    n63 <= ( not pi29 and n62 )
      or ( pi29 and not n62 );
    n64 <= ( not n61 and n63 )
      or ( n61 and not n63 );
    po3 <= ( not n60 and not n64 )
      or ( n60 and n64 );
end Cookbook__insert_parity__part3_behav;
