--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0, CLK: in std_logic;
    po0,po1: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,li0,li1,li2,n16,n17,n18,n19,n20,n21,n23,n24,n25,n26,n27,n28: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    po0 <= ( not n16 );
    li0 <= ( not n17 );
    li1 <= ( not n18 );
    li2 <= ( not n19 );
    n16 <= ( not n26 and not n28 );
    n17 <= ( not n21 and not n24 and not n26 and not n27 );
    n18 <= ( not n20 and not po1 and not n25 and not n28 );
    n19 <= ( not n23 and not n25 );
    n20 <= ( pi0 and not lo0 and not lo2 );
    n21 <= ( not pi0 and not lo0 and lo1 );
    po1 <= ( lo0 and not lo1 and not lo2 );
    n23 <= ( pi0 and lo1 and not lo2 );
    n24 <= ( pi0 and not lo1 );
    n25 <= ( pi0 and not lo1 and lo2 );
    n26 <= ( pi0 and lo1 and lo2 );
    n27 <= ( pi0 and lo0 );
    n28 <= ( not lo0 and not lo1 );
end top_behav;
