--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__rot__part2 is 
  Port (
    pi104,pi123,pi080,pi099,pi111: in std_logic;
    po46,po56: inout std_logic
  );
end IWLS93__rot__part2;

architecture IWLS93__rot__part2_behav of IWLS93__rot__part2 is
signal n486,n487,n488,n553,n554,n555: std_logic;
begin
    po46 <= ( n553 )
      or ( n554 )
      or ( n555 );
    po56 <= ( n486 )
      or ( n487 )
      or ( n488 );
    n486 <= ( not pi104 and pi123 );
    n487 <= ( pi080 and not pi099 and pi104 );
    n488 <= ( pi099 and pi123 );
    n553 <= ( pi080 and pi104 );
    n554 <= ( pi099 and not pi104 and pi111 );
    n555 <= ( pi080 and not pi099 );
end IWLS93__rot__part2_behav;
