--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part0 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05: in std_logic;
    po00,po01,po02: inout std_logic
  );
end Espresso__mish__part0;

architecture Espresso__mish__part0_behav of Espresso__mish__part0 is
begin
    po00 <= ( not pi00 );
    po01 <= ( not pi01 )
      or ( pi00 and pi02 and not pi03 and pi04 and pi05 )
      or ( pi00 and pi02 and pi03 and not pi04 and pi05 )
      or ( pi00 and pi02 and pi03 and pi04 and not pi05 )
      or ( pi00 and pi02 and not pi03 and not pi04 and not pi05 );
    po02 <= ( not pi03 and pi04 and pi05 )
      or ( pi03 and not pi04 and pi05 )
      or ( pi03 and pi04 and not pi05 )
      or ( not pi03 and not pi04 and not pi05 );
end Espresso__mish__part0_behav;
