--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_2__part1 is 
  Port (
    pi9,pi1,pi7,pi5,pi3: in std_logic;
    po7,po5,po3,po1: inout std_logic
  );
end Cookbook__fec_rot_2__part1;

architecture Cookbook__fec_rot_2__part1_behav of Cookbook__fec_rot_2__part1 is
begin
    po7 <= ( not pi9 and pi1 )
      or ( pi9 and not pi1 );
    po5 <= ( not pi7 and pi1 )
      or ( pi7 and not pi1 );
    po3 <= ( not pi5 and pi1 )
      or ( pi5 and not pi1 );
    po1 <= ( not pi3 and pi1 )
      or ( pi3 and not pi1 );
end Cookbook__fec_rot_2__part1_behav;
