--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_7__part0 is 
  Port (
    pi13,pi06,pi11,pi04,pi09,pi02,pi00,pi23,pi22,pi20,pi18,pi16,pi15,pi07: in std_logic;
    po22,po20,po18,po16,po15,po13,po11,po09,po08,po06,po04,po02,po00: inout std_logic
  );
end Cookbook__fec_rot_7__part0;

architecture Cookbook__fec_rot_7__part0_behav of Cookbook__fec_rot_7__part0 is
signal n48,n50,n52: std_logic;
begin
    n48 <= ( not pi13 and pi06 )
      or ( pi13 and not pi06 );
    n50 <= ( not pi11 and pi04 )
      or ( pi11 and not pi04 );
    n52 <= ( not pi09 and pi02 )
      or ( pi09 and not pi02 );
    po22 <= ( not pi06 and pi04 )
      or ( pi06 and not pi04 );
    po20 <= ( not pi04 and pi02 )
      or ( pi04 and not pi02 );
    po18 <= ( not pi02 and pi00 )
      or ( pi02 and not pi00 );
    po16 <= ( not pi23 and pi00 )
      or ( pi23 and not pi00 );
    po15 <= ( not pi22 and pi06 )
      or ( pi22 and not pi06 );
    po13 <= ( not pi20 and pi04 )
      or ( pi20 and not pi04 );
    po11 <= ( not pi18 and pi02 )
      or ( pi18 and not pi02 );
    po09 <= ( not pi16 and pi00 )
      or ( pi16 and not pi00 );
    po08 <= ( not pi15 and pi06 )
      or ( pi15 and not pi06 );
    po06 <= ( not n48 and pi04 )
      or ( n48 and not pi04 );
    po04 <= ( not n50 and pi02 )
      or ( n50 and not pi02 );
    po02 <= ( not n52 and pi00 )
      or ( n52 and not pi00 );
    po00 <= ( not pi07 and pi00 )
      or ( pi07 and not pi00 );
end Cookbook__fec_rot_7__part0_behav;
