--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__lal__part0 is 
  Port (
    pi03,pi20,pi25,pi00,pi18,pi15,pi24,pi12,pi21,pi22,pi13,pi14,pi23: in std_logic;
    po00,po03,po04,po05,po06: inout std_logic
  );
end IWLS93__lal__part0;

architecture IWLS93__lal__part0_behav of IWLS93__lal__part0 is
signal n118,n140,n142,n145,n146,n147,n149,n150,n151,n152,n153,n154,n155,n156,n158,n159: std_logic;
begin
    po00 <= ( not pi03 and pi20 );
    po03 <= ( not pi20 and not n140 );
    po04 <= ( not pi20 and not pi25 );
    po05 <= ( pi00 and not pi20 );
    po06 <= ( not n118 );
    n118 <= ( pi18 and not pi20 );
    n140 <= ( n155 )
      or ( n152 )
      or ( n156 )
      or ( n150 );
    n142 <= ( pi15 and not pi24 );
    n145 <= ( pi12 and not n149 );
    n146 <= ( not pi21 and not n149 );
    n147 <= ( n145 )
      or ( n146 );
    n149 <= ( n153 )
      or ( n154 )
      or ( n151 );
    n150 <= ( pi21 and pi22 and not n158 );
    n151 <= ( not pi13 and pi22 );
    n152 <= ( not pi12 and pi22 and not n158 );
    n153 <= ( not pi14 and pi23 );
    n154 <= ( not pi15 and pi24 );
    n155 <= ( not pi12 and not pi13 and not n158 );
    n156 <= ( not pi13 and pi21 and not n158 );
    n158 <= ( n142 )
      or ( not n147 )
      or ( n159 );
    n159 <= ( pi14 and not pi23 );
end IWLS93__lal__part0_behav;
