--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_3__part1 is 
  Port (
    pi12,pi01,pi09,pi06,pi04: in std_logic;
    po09,po06,po03,po01: inout std_logic
  );
end Cookbook__fec_rot_3__part1;

architecture Cookbook__fec_rot_3__part1_behav of Cookbook__fec_rot_3__part1 is
begin
    po09 <= ( not pi12 and pi01 )
      or ( pi12 and not pi01 );
    po06 <= ( not pi09 and pi01 )
      or ( pi09 and not pi01 );
    po03 <= ( not pi06 and pi01 )
      or ( pi06 and not pi01 );
    po01 <= ( not pi04 and pi01 )
      or ( pi04 and not pi01 );
end Cookbook__fec_rot_3__part1_behav;
