--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__insert_parity__part4 is 
  Port (
    pi44,pi43,pi42,pi41,pi40,pi39,pi37,pi36,pi38: in std_logic;
    po4: inout std_logic
  );
end Cookbook__insert_parity__part4;

architecture Cookbook__insert_parity__part4_behav of Cookbook__insert_parity__part4 is
signal n50,n51,n52,n53,n54,n55,n56: std_logic;
begin
    n50 <= ( not pi44 and pi43 )
      or ( pi44 and not pi43 );
    n51 <= ( not pi42 and pi41 )
      or ( pi42 and not pi41 );
    n52 <= ( not n50 and n51 )
      or ( n50 and not n51 );
    n53 <= ( not pi40 and pi39 )
      or ( pi40 and not pi39 );
    n54 <= ( not pi37 and pi36 )
      or ( pi37 and not pi36 );
    n55 <= ( not pi38 and n54 )
      or ( pi38 and not n54 );
    n56 <= ( not n53 and n55 )
      or ( n53 and not n55 );
    po4 <= ( not n52 and not n56 )
      or ( n52 and n56 );
end Cookbook__insert_parity__part4_behav;
