--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b01_opt is 
  Port (
    pi0,pi1,lo0,lo1,lo2,lo3,lo4: in std_logic;
    po0,po1,n9,n14,n19_1,n24_1,n29_1: inout std_logic
  );
end ITC99__b01_opt;

architecture ITC99__b01_opt_behav of ITC99__b01_opt is
signal n19,n20,n24,n25,n26,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50: std_logic;
begin
    n19 <= not (( n49 and n26 ));
    n20 <= not (( pi1 and not pi0 ));
    n29_1 <= ( lo1 and not lo0 and lo2 );
    n19_1 <= not (( n40 and n39 and n45 and n44 ));
    n14 <= not (( n37 and n36 and n38 ));
    n24 <= not (( not pi1 and not pi0 ));
    n25 <= not (( lo1 and not lo2 ));
    n26 <= not (( lo0 and n25 ));
    n9 <= not (( n43 and n42 ));
    n24_1 <= not (( n19 and n50 ));
    n29 <= not (( pi0 and pi1 ));
    n30 <= not (( not n24 and not lo2 ));
    n31 <= not (( n25 and n29 ));
    n32 <= not (( lo0 and not n24 ));
    n33 <= not (( lo2 and n29 ));
    n34 <= not (( n33 and n32 ));
    n35 <= not (( lo0 and n29 ));
    n36 <= not (( lo0 and lo2 and n24 ));
    n37 <= not (( not n25 and n35 ));
    n38 <= not (( n34 and not lo1 ));
    n39 <= not (( not lo0 and not lo1 and n47 and n46 ));
    n40 <= not (( not n26 and n24 ));
    n41 <= not (( n29 and n24 ));
    n42 <= not (( n31 and not lo0 ));
    n43 <= not (( n30 and not lo1 and lo0 ));
    n44 <= not (( n29_1 and n29 ));
    n45 <= not (( not n29 and not n25 ));
    n46 <= not (( lo2 and n29 ));
    n47 <= not (( not n29 and not lo2 ));
    n48 <= not (( pi0 and not pi1 ));
    n49 <= not (( n20 and n48 ));
    n50 <= not (( not n26 and n41 ));
    po0 <= ( lo3 );
    po1 <= ( lo4 );
end ITC99__b01_opt_behav;
