--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__eight_to_one is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10: in std_logic;
    po0: inout std_logic
  );
end Cookbook__eight_to_one;

architecture Cookbook__eight_to_one_behav of Cookbook__eight_to_one is
signal n12,n13,n14,n15,n16,n17: std_logic;
begin
    n12 <= ( pi07 and not pi10 )
      or ( pi06 and pi10 );
    n13 <= ( pi05 and not pi10 )
      or ( pi04 and pi10 );
    n14 <= ( n12 and not pi09 )
      or ( n13 and pi09 );
    n15 <= ( pi03 and not pi10 )
      or ( pi02 and pi10 );
    n16 <= ( pi01 and not pi10 )
      or ( pi00 and pi10 );
    n17 <= ( n15 and not pi09 )
      or ( n16 and pi09 );
    po0 <= ( n14 and not pi08 )
      or ( n17 and pi08 );
end Cookbook__eight_to_one_behav;
