--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__onehot_to_bin is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end Cookbook__onehot_to_bin;

architecture Cookbook__onehot_to_bin_behav of Cookbook__onehot_to_bin is
signal n19,n20,n21,n22,n23,n24,n26,n27,n28,n29,n30,n31,n33,n34,n35,n36,n37,n38,n40,n41,n42,n43,n44,n45: std_logic;
begin
    n19 <= not (( not pi14 and not pi12 ));
    n20 <= not (( not pi10 and not pi08 ));
    n21 <= not (( not n19 and not n20 ));
    n22 <= not (( not pi06 and not pi04 ));
    n23 <= not (( not pi02 and not pi00 ));
    n24 <= not (( not n22 and not n23 ));
    po3 <= not (( not n21 and not n24 ));
    n26 <= not (( not pi13 and not pi12 ));
    n27 <= not (( not pi09 and not pi08 ));
    n28 <= not (( not n26 and not n27 ));
    n29 <= not (( not pi05 and not pi04 ));
    n30 <= not (( not pi01 and not pi00 ));
    n31 <= not (( not n29 and not n30 ));
    po2 <= not (( not n28 and not n31 ));
    n33 <= not (( not pi11 and not pi10 ));
    n34 <= not (( not pi09 and not pi08 ));
    n35 <= not (( not n33 and not n34 ));
    n36 <= not (( not pi03 and not pi02 ));
    n37 <= not (( not pi01 and not pi00 ));
    n38 <= not (( not n36 and not n37 ));
    po1 <= not (( not n35 and not n38 ));
    n40 <= not (( not pi07 and not pi06 ));
    n41 <= not (( not pi05 and not pi04 ));
    n42 <= not (( not n40 and not n41 ));
    n43 <= not (( not pi03 and not pi02 ));
    n44 <= not (( not pi01 and not pi00 ));
    n45 <= not (( not n43 and not n44 ));
    po0 <= not (( not n42 and not n45 ));
end Cookbook__onehot_to_bin_behav;
