--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__mm4a is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11: in std_logic;
    po0,po1,po2,po3,n23,n28,n33,n38,n43,n48,n53,n58,n63_1,n68_1,n73_1,n78_1: inout std_logic
  );
end LGSynth91__mm4a;

architecture LGSynth91__mm4a_behav of LGSynth91__mm4a is
signal n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81: std_logic;
begin
    po0 <= ( lo00 and n81 )
      or ( n65 and not n70 and not n64 )
      or ( pi2 and n23 and n80 )
      or ( not n70 and n68_1 and n80 )
      or ( not n70 and n63 and n63_1 and n80 )
      or ( n65 and n79 and n63 and n68_1 and n80 );
    po1 <= ( lo01 and n81 )
      or ( not n72 and n66 and not n64 )
      or ( pi2 and n28 and n80 )
      or ( not n72 and n73_1 and n80 )
      or ( not n53 and not n72 and n70 and n80 )
      or ( n70 and n66 and n73_1 and n80 );
    po2 <= ( pi2 and n33 )
      or ( lo02 and n81 )
      or ( not n58 and not n72 and n75 )
      or ( not n58 and n72 and not n75 )
      or ( n72 and n67 and n78_1 )
      or ( not n72 and not n75 and n67 and not n64 );
    po3 <= ( pi2 and n38 )
      or ( n72 and n78_1 )
      or ( n67 and n78_1 )
      or ( lo03 and n81 )
      or ( n72 and n67 and not n64 );
    n23 <= ( pi3 and n80 );
    n28 <= ( pi4 and n80 );
    n33 <= ( pi5 and n80 );
    n38 <= ( pi6 and n80 );
    n43 <= ( n64 )
      or ( not pi0 and n63 );
    n48 <= ( n64 )
      or ( not pi0 and n65 );
    n53 <= ( n64 )
      or ( not pi0 and n66 );
    n58 <= ( n64 )
      or ( not pi0 and n67 );
    n63_1 <= ( n79 and not n64 );
    n68_1 <= ( n78 and not n64 );
    n73_1 <= ( n71 and not n64 );
    n78_1 <= ( n75 and not n64 );
    n63 <= ( n23 and n76 )
      or ( lo04 and n77 );
    n64 <= ( pi0 )
      or ( n81 )
      or ( not pi0 and pi2 );
    n65 <= ( n28 and n76 )
      or ( lo05 and n77 );
    n66 <= ( n33 and n76 )
      or ( lo06 and n77 );
    n67 <= ( n38 and n76 )
      or ( lo07 and n77 );
    n68 <= ( not lo11 and n38 and not n64 )
      or ( not lo10 and not lo11 and n33 and not n64 )
      or ( not lo10 and n33 and n38 and not n64 )
      or ( not lo09 and not lo10 and not lo11 and n28 and not n64 )
      or ( not lo09 and not lo11 and n28 and n33 and not n64 )
      or ( not lo09 and not lo10 and n28 and n38 and not n64 )
      or ( not lo09 and n28 and n33 and n38 and not n64 )
      or ( not lo08 and not lo09 and not lo10 and not lo11 and n23 and not n64 )
      or ( not lo08 and not lo10 and not lo11 and n23 and n28 and not n64 )
      or ( not lo08 and not lo09 and not lo11 and n23 and n33 and not n64 )
      or ( not lo08 and not lo11 and n23 and n28 and n33 and not n64 )
      or ( not lo08 and not lo09 and not lo10 and n23 and n38 and not n64 )
      or ( not lo08 and not lo10 and n23 and n28 and n38 and not n64 )
      or ( not lo08 and not lo09 and n23 and n33 and n38 and not n64 )
      or ( not lo08 and n23 and n28 and n33 and n38 and not n64 );
    n69 <= ( not lo07 and n38 and not n64 )
      or ( not lo06 and not lo07 and n33 and not n64 )
      or ( not lo06 and n33 and n38 and not n64 )
      or ( not lo05 and not lo06 and not lo07 and n28 and not n64 )
      or ( not lo05 and not lo07 and n28 and n33 and not n64 )
      or ( not lo05 and not lo06 and n28 and n38 and not n64 )
      or ( not lo05 and n28 and n33 and n38 and not n64 )
      or ( not lo04 and not lo05 and not lo06 and not lo07 and n23 and not n64 )
      or ( not lo04 and not lo06 and not lo07 and n23 and n28 and not n64 )
      or ( not lo04 and not lo05 and not lo07 and n23 and n33 and not n64 )
      or ( not lo04 and not lo07 and n23 and n28 and n33 and not n64 )
      or ( not lo04 and not lo05 and not lo06 and n23 and n38 and not n64 )
      or ( not lo04 and not lo06 and n23 and n28 and n38 and not n64 )
      or ( not lo04 and not lo05 and n23 and n33 and n38 and not n64 )
      or ( not lo04 and n23 and n28 and n33 and n38 and not n64 );
    n70 <= ( n78 and n65 )
      or ( n78 and n79 and n63 )
      or ( n65 and n79 and n63 );
    n71 <= ( n33 and n73 )
      or ( lo10 and n74 );
    n72 <= ( n70 and n71 )
      or ( n70 and n66 )
      or ( n71 and n66 );
    n73 <= ( not pi2 and n68 );
    n74 <= ( not n68 and not n64 );
    n75 <= ( n38 and n73 )
      or ( lo11 and n74 );
    n76 <= ( not pi2 and not n69 );
    n77 <= ( n69 and not n64 );
    n78 <= ( n28 and n73 )
      or ( lo09 and n74 );
    n79 <= ( n23 and n73 )
      or ( lo08 and n74 );
    n80 <= ( not pi0 and pi1 );
    n81 <= ( not pi0 and not pi1 );
end LGSynth91__mm4a_behav;
