--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mask_16 is 
  Port (
    pi0,pi1,pi2,pi3: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13: inout std_logic
  );
end Cookbook__mask_16;

architecture Cookbook__mask_16_behav of Cookbook__mask_16 is
signal n18,n19,n21,n23,n24,n27,n28,n30,n32,n33,n35,n36,n38,n40,n41,n44,n45,n47,n49,n50: std_logic;
begin
    n18 <= ( pi3 and pi2 );
    n19 <= ( n18 and pi1 );
    po13 <= ( n19 and pi0 );
    n21 <= ( pi2 and pi1 );
    po12 <= ( n21 and pi0 );
    n23 <= not (( not pi3 and not pi2 ));
    n24 <= ( n23 and pi1 );
    po11 <= ( n24 and pi0 );
    po10 <= ( pi1 and pi0 );
    n27 <= ( pi3 and pi2 );
    n28 <= not (( not n27 and not pi1 ));
    po09 <= ( n28 and pi0 );
    n30 <= not (( not pi2 and not pi1 ));
    po08 <= ( n30 and pi0 );
    n32 <= not (( not pi3 and not pi2 ));
    n33 <= not (( not n32 and not pi1 ));
    po07 <= ( n33 and pi0 );
    n35 <= ( pi3 and pi2 );
    n36 <= ( n35 and pi1 );
    po06 <= not (( not n36 and not pi0 ));
    n38 <= ( pi2 and pi1 );
    po05 <= not (( not n38 and not pi0 ));
    n40 <= not (( not pi3 and not pi2 ));
    n41 <= ( n40 and pi1 );
    po04 <= not (( not n41 and not pi0 ));
    po03 <= not (( not pi1 and not pi0 ));
    n44 <= ( pi3 and pi2 );
    n45 <= not (( not n44 and not pi1 ));
    po02 <= not (( not n45 and not pi0 ));
    n47 <= not (( not pi2 and not pi1 ));
    po01 <= not (( not n47 and not pi0 ));
    n49 <= not (( not pi3 and not pi2 ));
    n50 <= not (( not n49 and not pi1 ));
    po00 <= not (( not n50 and not pi0 ));
end Cookbook__mask_16_behav;
