--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__equal_const is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7: in std_logic;
    po0: inout std_logic
  );
end Cookbook__equal_const;

architecture Cookbook__equal_const_behav of Cookbook__equal_const is
signal n9,n10,n11,n12,n13,n14: std_logic;
begin
    n9 <= not (( pi7 and not pi6 ));
    n10 <= not (( pi5 and not pi4 ));
    n11 <= not (( not n9 and not n10 ));
    n12 <= not (( not pi3 and not pi2 ));
    n13 <= not (( pi1 and not pi0 ));
    n14 <= not (( not n12 and not n13 ));
    po0 <= ( not n11 and not n14 );
end Cookbook__equal_const_behav;
