--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__cm82a is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1,po2: inout std_logic
  );
end IWLS93__cm82a;

architecture IWLS93__cm82a_behav of IWLS93__cm82a is
signal n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27: std_logic;
begin
    po0 <= ( n23 )
      or ( n26 );
    po1 <= ( n22 )
      or ( n20 );
    po2 <= ( n16 )
      or ( n17 )
      or ( n18 );
    n11 <= ( not pi1 and pi2 );
    n12 <= ( pi1 and not pi2 );
    n13 <= ( n19 )
      or ( n21 );
    n14 <= ( n25 )
      or ( n24 )
      or ( n27 );
    n15 <= ( n12 )
      or ( n11 );
    n16 <= ( pi4 and not n14 );
    n17 <= ( pi3 and pi4 );
    n18 <= ( pi3 and not n14 );
    n19 <= ( pi3 and not pi4 );
    n20 <= ( n13 and n14 );
    n21 <= ( not pi3 and pi4 );
    n22 <= ( not n13 and not n14 );
    n23 <= ( pi0 and not n15 );
    n24 <= ( not pi1 and not pi2 );
    n25 <= ( not pi0 and not pi2 );
    n26 <= ( not pi0 and n15 );
    n27 <= ( not pi0 and not pi1 );
end IWLS93__cm82a_behav;
