--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3091 is 
  Port (
    lo8404: in std_logic;
    n42265_1: inout std_logic
  );
end IWLS2005__des_perf__part3091;

architecture IWLS2005__des_perf__part3091_behav of IWLS2005__des_perf__part3091 is
begin
    n42265_1 <= ( lo8404 );
end IWLS2005__des_perf__part3091_behav;
