--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1300 is 
  Port (
    lo1369: in std_logic;
    n7144: inout std_logic
  );
end Cookbook__fec_check__part1300;

architecture Cookbook__fec_check__part1300_behav of Cookbook__fec_check__part1300 is
begin
    n7144 <= ( lo1369 );
end Cookbook__fec_check__part1300_behav;
