--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s5378__part5 is 
  Port (
    lo112: in std_logic;
    n734_1: inout std_logic
  );
end LGSynth91__s5378__part5;

architecture LGSynth91__s5378__part5_behav of LGSynth91__s5378__part5 is
begin
    n734_1 <= ( not lo112 );
end LGSynth91__s5378__part5_behav;
