--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1665 is 
  Port (
    lo1734: in std_logic;
    n8969: inout std_logic
  );
end Cookbook__fec_check__part1665;

architecture Cookbook__fec_check__part1665_behav of Cookbook__fec_check__part1665 is
begin
    n8969 <= ( lo1734 );
end Cookbook__fec_check__part1665_behav;
