--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1042 is 
  Port (
    lo1111: in std_logic;
    n5854: inout std_logic
  );
end Cookbook__fec_check__part1042;

architecture Cookbook__fec_check__part1042_behav of Cookbook__fec_check__part1042 is
begin
    n5854 <= ( lo1111 );
end Cookbook__fec_check__part1042_behav;
