--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_fifo_cells__part1 is 
  Port (
    lo20: in std_logic;
    po20: inout std_logic
  );
end Cookbook__mlab_fifo_cells__part1;

architecture Cookbook__mlab_fifo_cells__part1_behav of Cookbook__mlab_fifo_cells__part1 is
begin
    po20 <= ( lo20 );
end Cookbook__mlab_fifo_cells__part1_behav;
