--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1159 is 
  Port (
    lo4528: in std_logic;
    n18129: inout std_logic
  );
end Other__sudoku_check__part1159;

architecture Other__sudoku_check__part1159_behav of Other__sudoku_check__part1159 is
begin
    n18129 <= ( lo4528 );
end Other__sudoku_check__part1159_behav;
