--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1500 is 
  Port (
    lo8131: in std_logic;
    n44704_1: inout std_logic
  );
end Other__carpat__part1500;

architecture Other__carpat__part1500_behav of Other__carpat__part1500 is
begin
    n44704_1 <= ( lo8131 );
end Other__carpat__part1500_behav;
