--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1391 is 
  Port (
    lo1460: in std_logic;
    n7599: inout std_logic
  );
end Cookbook__fec_check__part1391;

architecture Cookbook__fec_check__part1391_behav of Cookbook__fec_check__part1391 is
begin
    n7599 <= ( lo1460 );
end Cookbook__fec_check__part1391_behav;
