--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ac97_ctrl__part73 is 
  Port (
    lo2002: in std_logic;
    n9968_1: inout std_logic
  );
end IWLS2005__ac97_ctrl__part73;

architecture IWLS2005__ac97_ctrl__part73_behav of IWLS2005__ac97_ctrl__part73 is
begin
    n9968_1 <= ( lo2002 );
end IWLS2005__ac97_ctrl__part73_behav;
