--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1917 is 
  Port (
    lo4300: in std_logic;
    n26086: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1917;

architecture Other__ucsb_152_tap_fir__part1917_behav of Other__ucsb_152_tap_fir__part1917 is
begin
    n26086 <= ( lo4300 );
end Other__ucsb_152_tap_fir__part1917_behav;
