--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part125 is 
  Port (
    pi0535: in std_logic;
    n43221_1: inout std_logic
  );
end Other__radar__part125;

architecture Other__radar__part125_behav of Other__radar__part125 is
begin
    n43221_1 <= ( pi0535 );
end Other__radar__part125_behav;
