--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part664 is 
  Port (
    lo06161: in std_logic;
    po1822,po1917: inout std_logic
  );
end Other__ray__part664;

architecture Other__ray__part664_behav of Other__ray__part664 is
begin
    po1822 <= ( lo06161 );
    po1917 <= ( lo06161 );
end Other__ray__part664_behav;
