--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part653 is 
  Port (
    lo3302: in std_logic;
    n11449: inout std_logic
  );
end Other__sudoku_check__part653;

architecture Other__sudoku_check__part653_behav of Other__sudoku_check__part653 is
begin
    n11449 <= ( lo3302 );
end Other__sudoku_check__part653_behav;
