--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part114 is 
  Port (
    lo0415: in std_logic;
    n4555: inout std_logic
  );
end Other__fp_operators__part114;

architecture Other__fp_operators__part114_behav of Other__fp_operators__part114 is
begin
    n4555 <= ( lo0415 );
end Other__fp_operators__part114_behav;
