--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1748 is 
  Port (
    lo3944: in std_logic;
    n24221: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1748;

architecture Other__ucsb_152_tap_fir__part1748_behav of Other__ucsb_152_tap_fir__part1748 is
begin
    n24221 <= ( lo3944 );
end Other__ucsb_152_tap_fir__part1748_behav;
