--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part31 is 
  Port (
    pi0359: in std_logic;
    n19544: inout std_logic
  );
end Other__carpat__part31;

architecture Other__carpat__part31_behav of Other__carpat__part31 is
begin
    n19544 <= ( pi0359 );
end Other__carpat__part31_behav;
