--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1244 is 
  Port (
    lo4613: in std_logic;
    n18554: inout std_logic
  );
end Other__sudoku_check__part1244;

architecture Other__sudoku_check__part1244_behav of Other__sudoku_check__part1244 is
begin
    n18554 <= ( lo4613 );
end Other__sudoku_check__part1244_behav;
