--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part742 is 
  Port (
    lo3391: in std_logic;
    n12339: inout std_logic
  );
end Other__sudoku_check__part742;

architecture Other__sudoku_check__part742_behav of Other__sudoku_check__part742 is
begin
    n12339 <= ( lo3391 );
end Other__sudoku_check__part742_behav;
