--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1307 is 
  Port (
    lo4676: in std_logic;
    n18869: inout std_logic
  );
end Other__sudoku_check__part1307;

architecture Other__sudoku_check__part1307_behav of Other__sudoku_check__part1307 is
begin
    n18869 <= ( lo4676 );
end Other__sudoku_check__part1307_behav;
