--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part122 is 
  Port (
    lo3284: in std_logic;
    n16839: inout std_logic
  );
end IWLS2005__pci_bridge32__part122;

architecture IWLS2005__pci_bridge32__part122_behav of IWLS2005__pci_bridge32__part122 is
begin
    n16839 <= ( lo3284 );
end IWLS2005__pci_bridge32__part122_behav;
