--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part505 is 
  Port (
    lo4087: in std_logic;
    n20810: inout std_logic
  );
end IWLS2005__des_perf__part505;

architecture IWLS2005__des_perf__part505_behav of IWLS2005__des_perf__part505 is
begin
    n20810 <= ( lo4087 );
end IWLS2005__des_perf__part505_behav;
