--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part944 is 
  Port (
    lo1013: in std_logic;
    n5364: inout std_logic
  );
end Cookbook__fec_check__part944;

architecture Cookbook__fec_check__part944_behav of Cookbook__fec_check__part944 is
begin
    n5364 <= ( lo1013 );
end Cookbook__fec_check__part944_behav;
