--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1933 is 
  Port (
    lo4316: in std_logic;
    n26171: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1933;

architecture Other__ucsb_152_tap_fir__part1933_behav of Other__ucsb_152_tap_fir__part1933 is
begin
    n26171 <= ( lo4316 );
end Other__ucsb_152_tap_fir__part1933_behav;
