--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part12 is 
  Port (
    pi104: in std_logic;
    n9054: inout std_logic
  );
end IWLS2005__usb_funct__part12;

architecture IWLS2005__usb_funct__part12_behav of IWLS2005__usb_funct__part12 is
begin
    n9054 <= ( pi104 );
end IWLS2005__usb_funct__part12_behav;
