--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part475 is 
  Port (
    lo3124: in std_logic;
    n9669: inout std_logic
  );
end Other__sudoku_check__part475;

architecture Other__sudoku_check__part475_behav of Other__sudoku_check__part475 is
begin
    n9669 <= ( lo3124 );
end Other__sudoku_check__part475_behav;
