--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part959 is 
  Port (
    lo10645: in std_logic;
    n71161_1: inout std_logic
  );
end Other__ray__part959;

architecture Other__ray__part959_behav of Other__ray__part959 is
begin
    n71161_1 <= ( lo10645 );
end Other__ray__part959_behav;
