--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1726 is 
  Port (
    lo1795: in std_logic;
    n9274: inout std_logic
  );
end Cookbook__fec_check__part1726;

architecture Cookbook__fec_check__part1726_behav of Cookbook__fec_check__part1726 is
begin
    n9274 <= ( lo1795 );
end Cookbook__fec_check__part1726_behav;
