--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1144 is 
  Port (
    lo12991: in std_logic;
    po1969,po2003,po2149,po2183,n51686_1: inout std_logic
  );
end Other__ray__part1144;

architecture Other__ray__part1144_behav of Other__ray__part1144 is
begin
    po1969 <= ( lo12991 );
    po2003 <= ( lo12991 );
    po2149 <= ( lo12991 );
    po2183 <= ( lo12991 );
    n51686_1 <= ( lo12991 );
end Other__ray__part1144_behav;
