--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1006 is 
  Port (
    lo1075: in std_logic;
    n5674: inout std_logic
  );
end Cookbook__fec_check__part1006;

architecture Cookbook__fec_check__part1006_behav of Cookbook__fec_check__part1006 is
begin
    n5674 <= ( lo1075 );
end Cookbook__fec_check__part1006_behav;
