--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part532 is 
  Port (
    lo06004: in std_logic;
    po1519,po1568,po1878,po1940: inout std_logic
  );
end Other__ray__part532;

architecture Other__ray__part532_behav of Other__ray__part532 is
begin
    po1519 <= ( lo06004 );
    po1568 <= ( lo06004 );
    po1878 <= ( lo06004 );
    po1940 <= ( lo06004 );
end Other__ray__part532_behav;
