--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1315 is 
  Port (
    lo4684: in std_logic;
    n18909: inout std_logic
  );
end Other__sudoku_check__part1315;

architecture Other__sudoku_check__part1315_behav of Other__sudoku_check__part1315 is
begin
    n18909 <= ( lo4684 );
end Other__sudoku_check__part1315_behav;
