--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1150 is 
  Port (
    lo4519: in std_logic;
    n18084: inout std_logic
  );
end Other__sudoku_check__part1150;

architecture Other__sudoku_check__part1150_behav of Other__sudoku_check__part1150 is
begin
    n18084 <= ( lo4519 );
end Other__sudoku_check__part1150_behav;
