--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1225 is 
  Port (
    lo4594: in std_logic;
    n18459: inout std_logic
  );
end Other__sudoku_check__part1225;

architecture Other__sudoku_check__part1225_behav of Other__sudoku_check__part1225 is
begin
    n18459 <= ( lo4594 );
end Other__sudoku_check__part1225_behav;
