--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part38 is 
  Port (
    lo101: in std_logic;
    po035: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part38;

architecture Cookbook__soft_ecc_ram_64bit__part38_behav of Cookbook__soft_ecc_ram_64bit__part38 is
begin
    po035 <= ( lo101 );
end Cookbook__soft_ecc_ram_64bit__part38_behav;
