--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part256 is 
  Port (
    lo0605: in std_logic;
    n7506: inout std_logic
  );
end Other__ucsb_152_tap_fir__part256;

architecture Other__ucsb_152_tap_fir__part256_behav of Other__ucsb_152_tap_fir__part256 is
begin
    n7506 <= ( lo0605 );
end Other__ucsb_152_tap_fir__part256_behav;
