--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2844 is 
  Port (
    lo8157: in std_logic;
    n41145_1: inout std_logic
  );
end IWLS2005__des_perf__part2844;

architecture IWLS2005__des_perf__part2844_behav of IWLS2005__des_perf__part2844 is
begin
    n41145_1 <= ( lo8157 );
end IWLS2005__des_perf__part2844_behav;
