--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1508 is 
  Port (
    lo3447: in std_logic;
    n21821: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1508;

architecture Other__ucsb_152_tap_fir__part1508_behav of Other__ucsb_152_tap_fir__part1508 is
begin
    n21821 <= ( lo3447 );
end Other__ucsb_152_tap_fir__part1508_behav;
