--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1754 is 
  Port (
    lo1823: in std_logic;
    n9414: inout std_logic
  );
end Cookbook__fec_check__part1754;

architecture Cookbook__fec_check__part1754_behav of Cookbook__fec_check__part1754 is
begin
    n9414 <= ( lo1823 );
end Cookbook__fec_check__part1754_behav;
