--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1503 is 
  Port (
    lo1572: in std_logic;
    n8159: inout std_logic
  );
end Cookbook__fec_check__part1503;

architecture Cookbook__fec_check__part1503_behav of Cookbook__fec_check__part1503 is
begin
    n8159 <= ( lo1572 );
end Cookbook__fec_check__part1503_behav;
