--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part103 is 
  Port (
    pi0938: in std_logic;
    n31349_1: inout std_logic
  );
end Other__carpat__part103;

architecture Other__carpat__part103_behav of Other__carpat__part103 is
begin
    n31349_1 <= ( pi0938 );
end Other__carpat__part103_behav;
