--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1856 is 
  Port (
    lo1925: in std_logic;
    n9924: inout std_logic
  );
end Cookbook__fec_check__part1856;

architecture Cookbook__fec_check__part1856_behav of Cookbook__fec_check__part1856 is
begin
    n9924 <= ( lo1925 );
end Cookbook__fec_check__part1856_behav;
