--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2114 is 
  Port (
    lo2183: in std_logic;
    n11214: inout std_logic
  );
end Cookbook__fec_check__part2114;

architecture Cookbook__fec_check__part2114_behav of Cookbook__fec_check__part2114 is
begin
    n11214 <= ( lo2183 );
end Cookbook__fec_check__part2114_behav;
