--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part28 is 
  Port (
    pi0434: in std_logic;
    n42541_1: inout std_logic
  );
end Other__radar__part28;

architecture Other__radar__part28_behav of Other__radar__part28 is
begin
    n42541_1 <= ( pi0434 );
end Other__radar__part28_behav;
