--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part100 is 
  Port (
    pi100: in std_logic;
    n2062: inout std_logic
  );
end Other__fpu__part100;

architecture Other__fpu__part100_behav of Other__fpu__part100 is
begin
    n2062 <= ( pi100 );
end Other__fpu__part100_behav;
