--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part10 is 
  Port (
    pi10: in std_logic;
    n746802: inout std_logic
  );
end IWLS2005__leon2__part10;

architecture IWLS2005__leon2__part10_behav of IWLS2005__leon2__part10 is
begin
    n746802 <= ( pi10 );
end IWLS2005__leon2__part10_behav;
