--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1282 is 
  Port (
    lo4651: in std_logic;
    n18744: inout std_logic
  );
end Other__sudoku_check__part1282;

architecture Other__sudoku_check__part1282_behav of Other__sudoku_check__part1282 is
begin
    n18744 <= ( lo4651 );
end Other__sudoku_check__part1282_behav;
