--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1337 is 
  Port (
    lo1406: in std_logic;
    n7329: inout std_logic
  );
end Cookbook__fec_check__part1337;

architecture Cookbook__fec_check__part1337_behav of Cookbook__fec_check__part1337 is
begin
    n7329 <= ( lo1406 );
end Cookbook__fec_check__part1337_behav;
