--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part524 is 
  Port (
    lo3173: in std_logic;
    n10159: inout std_logic
  );
end Other__sudoku_check__part524;

architecture Other__sudoku_check__part524_behav of Other__sudoku_check__part524 is
begin
    n10159 <= ( lo3173 );
end Other__sudoku_check__part524_behav;
