--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s1238__part1 is 
  Port (
    lo08: in std_logic;
    po01: inout std_logic
  );
end IWLS93__s1238__part1;

architecture IWLS93__s1238__part1_behav of IWLS93__s1238__part1 is
begin
    po01 <= ( not lo08 );
end IWLS93__s1238__part1_behav;
