--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part7 is 
  Port (
    lo195: in std_logic;
    po109: inout std_logic
  );
end IWLS2005__aes_core__part7;

architecture IWLS2005__aes_core__part7_behav of IWLS2005__aes_core__part7 is
begin
    po109 <= ( lo195 );
end IWLS2005__aes_core__part7_behav;
