--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part401 is 
  Port (
    lo3050: in std_logic;
    n8929: inout std_logic
  );
end Other__sudoku_check__part401;

architecture Other__sudoku_check__part401_behav of Other__sudoku_check__part401 is
begin
    n8929 <= ( lo3050 );
end Other__sudoku_check__part401_behav;
