--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part689 is 
  Port (
    lo3338: in std_logic;
    n11809: inout std_logic
  );
end Other__sudoku_check__part689;

architecture Other__sudoku_check__part689_behav of Other__sudoku_check__part689 is
begin
    n11809 <= ( lo3338 );
end Other__sudoku_check__part689_behav;
