--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2602 is 
  Port (
    lo5720: in std_logic;
    n33186_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2602;

architecture Other__ucsb_152_tap_fir__part2602_behav of Other__ucsb_152_tap_fir__part2602 is
begin
    n33186_1 <= ( lo5720 );
end Other__ucsb_152_tap_fir__part2602_behav;
