--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part332 is 
  Port (
    lo03737: in std_logic;
    po6288,po6339,po6594,po6645: inout std_logic
  );
end Other__ray__part332;

architecture Other__ray__part332_behav of Other__ray__part332 is
begin
    po6288 <= ( lo03737 );
    po6339 <= ( lo03737 );
    po6594 <= ( lo03737 );
    po6645 <= ( lo03737 );
end Other__ray__part332_behav;
