--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part960 is 
  Port (
    lo4329: in std_logic;
    n17134: inout std_logic
  );
end Other__sudoku_check__part960;

architecture Other__sudoku_check__part960_behav of Other__sudoku_check__part960 is
begin
    n17134 <= ( lo4329 );
end Other__sudoku_check__part960_behav;
