--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part57 is 
  Port (
    lo149305: in std_logic;
    n746622: inout std_logic
  );
end IWLS2005__leon2__part57;

architecture IWLS2005__leon2__part57_behav of IWLS2005__leon2__part57 is
begin
    n746622 <= ( lo149305 );
end IWLS2005__leon2__part57_behav;
