--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part128 is 
  Port (
    lo0463: in std_logic;
    n4715: inout std_logic
  );
end Other__fp_operators__part128;

architecture Other__fp_operators__part128_behav of Other__fp_operators__part128 is
begin
    n4715 <= ( lo0463 );
end Other__fp_operators__part128_behav;
