--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1686 is 
  Port (
    lo3806: in std_logic;
    n23606: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1686;

architecture Other__ucsb_152_tap_fir__part1686_behav of Other__ucsb_152_tap_fir__part1686 is
begin
    n23606 <= ( lo3806 );
end Other__ucsb_152_tap_fir__part1686_behav;
