--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part77 is 
  Port (
    lo2480: in std_logic;
    n5689: inout std_logic
  );
end Other__sudoku_check__part77;

architecture Other__sudoku_check__part77_behav of Other__sudoku_check__part77 is
begin
    n5689 <= ( lo2480 );
end Other__sudoku_check__part77_behav;
