--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part31 is 
  Port (
    lo15509: in std_logic;
    po82: inout std_logic
  );
end IWLS2005__vga_lcd__part31;

architecture IWLS2005__vga_lcd__part31_behav of IWLS2005__vga_lcd__part31 is
begin
    po82 <= ( lo15509 );
end IWLS2005__vga_lcd__part31_behav;
