--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part6 is 
  Port (
    lo004: in std_logic;
    n313,n1083: inout std_logic
  );
end ISCAS__s13207__part6;

architecture ISCAS__s13207__part6_behav of ISCAS__s13207__part6 is
begin
    n313 <= ( lo004 );
    n1083 <= ( lo004 );
end ISCAS__s13207__part6_behav;
