--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3334 is 
  Port (
    lo8742: in std_logic;
    n43645_1: inout std_logic
  );
end IWLS2005__des_perf__part3334;

architecture IWLS2005__des_perf__part3334_behav of IWLS2005__des_perf__part3334 is
begin
    n43645_1 <= ( lo8742 );
end IWLS2005__des_perf__part3334_behav;
