--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part295 is 
  Port (
    lo490: in std_logic;
    po036: inout std_logic
  );
end Other__fpu__part295;

architecture Other__fpu__part295_behav of Other__fpu__part295 is
begin
    po036 <= ( lo490 );
end Other__fpu__part295_behav;
