--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part80 is 
  Port (
    lo306: in std_logic;
    n1828: inout std_logic
  );
end ISCAS__s13207__part80;

architecture ISCAS__s13207__part80_behav of ISCAS__s13207__part80 is
begin
    n1828 <= ( lo306 );
end ISCAS__s13207__part80_behav;
