--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part123 is 
  Port (
    lo0458: in std_logic;
    n4690: inout std_logic
  );
end Other__fp_operators__part123;

architecture Other__fp_operators__part123_behav of Other__fp_operators__part123 is
begin
    n4690 <= ( lo0458 );
end Other__fp_operators__part123_behav;
