--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3317 is 
  Port (
    lo8700: in std_logic;
    n43625_1: inout std_logic
  );
end IWLS2005__des_perf__part3317;

architecture IWLS2005__des_perf__part3317_behav of IWLS2005__des_perf__part3317 is
begin
    n43625_1 <= ( lo8700 );
end IWLS2005__des_perf__part3317_behav;
