--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part945 is 
  Port (
    lo4314: in std_logic;
    n17059: inout std_logic
  );
end Other__sudoku_check__part945;

architecture Other__sudoku_check__part945_behav of Other__sudoku_check__part945 is
begin
    n17059 <= ( lo4314 );
end Other__sudoku_check__part945_behav;
