--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part9 is 
  Port (
    pi13: in std_logic;
    n414: inout std_logic
  );
end LGSynth91__s38417__part9;

architecture LGSynth91__s38417__part9_behav of LGSynth91__s38417__part9 is
begin
    n414 <= ( pi13 );
end LGSynth91__s38417__part9_behav;
