--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1545 is 
  Port (
    lo8176: in std_logic;
    n45949_1: inout std_logic
  );
end Other__carpat__part1545;

architecture Other__carpat__part1545_behav of Other__carpat__part1545 is
begin
    n45949_1 <= ( lo8176 );
end Other__carpat__part1545_behav;
