--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part41 is 
  Port (
    lo0331: in std_logic;
    n1929: inout std_logic
  );
end ISCAS__s38417__part41;

architecture ISCAS__s38417__part41_behav of ISCAS__s38417__part41 is
begin
    n1929 <= ( lo0331 );
end ISCAS__s38417__part41_behav;
