--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1069 is 
  Port (
    lo2490: in std_logic;
    n17041: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1069;

architecture Other__ucsb_152_tap_fir__part1069_behav of Other__ucsb_152_tap_fir__part1069 is
begin
    n17041 <= ( lo2490 );
end Other__ucsb_152_tap_fir__part1069_behav;
