--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part13 is 
  Port (
    lo12: in std_logic;
    po33: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part13;

architecture Cookbook__x4_decoder_8b10b__part13_behav of Cookbook__x4_decoder_8b10b__part13 is
begin
    po33 <= ( lo12 );
end Cookbook__x4_decoder_8b10b__part13_behav;
