--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part690 is 
  Port (
    lo4369: in std_logic;
    n22010: inout std_logic
  );
end IWLS2005__des_perf__part690;

architecture IWLS2005__des_perf__part690_behav of IWLS2005__des_perf__part690 is
begin
    n22010 <= ( lo4369 );
end IWLS2005__des_perf__part690_behav;
