--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part62 is 
  Port (
    lo0020: in std_logic;
    po147: inout std_logic
  );
end IWLS2005__mem_ctrl__part62;

architecture IWLS2005__mem_ctrl__part62_behav of IWLS2005__mem_ctrl__part62 is
begin
    po147 <= ( lo0020 );
end IWLS2005__mem_ctrl__part62_behav;
