--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2176 is 
  Port (
    lo4813: in std_logic;
    n28651: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2176;

architecture Other__ucsb_152_tap_fir__part2176_behav of Other__ucsb_152_tap_fir__part2176 is
begin
    n28651 <= ( lo4813 );
end Other__ucsb_152_tap_fir__part2176_behav;
