--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1430 is 
  Port (
    lo5908: in std_logic;
    n29610_1: inout std_logic
  );
end IWLS2005__des_perf__part1430;

architecture IWLS2005__des_perf__part1430_behav of IWLS2005__des_perf__part1430 is
begin
    n29610_1 <= ( lo5908 );
end IWLS2005__des_perf__part1430_behav;
