--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part54 is 
  Port (
    lo161,lo160: in std_logic;
    po045: inout std_logic
  );
end ISCAS__s13207__part54;

architecture ISCAS__s13207__part54_behav of ISCAS__s13207__part54 is
begin
    po045 <= ( lo161 and not lo160 );
end ISCAS__s13207__part54_behav;
