--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2323 is 
  Port (
    lo5117: in std_logic;
    n30116: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2323;

architecture Other__ucsb_152_tap_fir__part2323_behav of Other__ucsb_152_tap_fir__part2323 is
begin
    n30116 <= ( lo5117 );
end Other__ucsb_152_tap_fir__part2323_behav;
