--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part214 is 
  Port (
    lo0283: in std_logic;
    n1714: inout std_logic
  );
end Cookbook__fec_check__part214;

architecture Cookbook__fec_check__part214_behav of Cookbook__fec_check__part214 is
begin
    n1714 <= ( lo0283 );
end Cookbook__fec_check__part214_behav;
