--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2542 is 
  Port (
    lo5603: in std_logic;
    n32601: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2542;

architecture Other__ucsb_152_tap_fir__part2542_behav of Other__ucsb_152_tap_fir__part2542 is
begin
    n32601 <= ( lo5603 );
end Other__ucsb_152_tap_fir__part2542_behav;
