--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part554 is 
  Port (
    lo3203: in std_logic;
    n10459: inout std_logic
  );
end Other__sudoku_check__part554;

architecture Other__sudoku_check__part554_behav of Other__sudoku_check__part554 is
begin
    n10459 <= ( lo3203 );
end Other__sudoku_check__part554_behav;
