--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1551 is 
  Port (
    lo8182: in std_logic;
    n45979_1: inout std_logic
  );
end Other__carpat__part1551;

architecture Other__carpat__part1551_behav of Other__carpat__part1551 is
begin
    n45979_1 <= ( lo8182 );
end Other__carpat__part1551_behav;
