--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part14 is 
  Port (
    pi14: in std_logic;
    n544118: inout std_logic
  );
end IWLS2005__leon3mp__part14;

architecture IWLS2005__leon3mp__part14_behav of IWLS2005__leon3mp__part14 is
begin
    n544118 <= ( pi14 );
end IWLS2005__leon3mp__part14_behav;
