--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part358 is 
  Port (
    lo0427: in std_logic;
    n2434: inout std_logic
  );
end Cookbook__fec_check__part358;

architecture Cookbook__fec_check__part358_behav of Cookbook__fec_check__part358 is
begin
    n2434 <= ( lo0427 );
end Cookbook__fec_check__part358_behav;
