--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part547 is 
  Port (
    lo1994: in std_logic;
    n11229: inout std_logic
  );
end Cookbook__ucrypt__part547;

architecture Cookbook__ucrypt__part547_behav of Cookbook__ucrypt__part547 is
begin
    n11229 <= ( lo1994 );
end Cookbook__ucrypt__part547_behav;
