--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1738 is 
  Port (
    lo6522: in std_logic;
    n32420_1: inout std_logic
  );
end IWLS2005__des_perf__part1738;

architecture IWLS2005__des_perf__part1738_behav of IWLS2005__des_perf__part1738 is
begin
    n32420_1 <= ( lo6522 );
end IWLS2005__des_perf__part1738_behav;
