--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part977 is 
  Port (
    lo7032: in std_logic;
    n36734_1: inout std_logic
  );
end Other__carpat__part977;

architecture Other__carpat__part977_behav of Other__carpat__part977 is
begin
    n36734_1 <= ( lo7032 );
end Other__carpat__part977_behav;
