--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1621 is 
  Port (
    lo8413: in std_logic;
    n46964_1: inout std_logic
  );
end Other__carpat__part1621;

architecture Other__carpat__part1621_behav of Other__carpat__part1621 is
begin
    n46964_1 <= ( lo8413 );
end Other__carpat__part1621_behav;
