--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part441 is 
  Port (
    lo0510: in std_logic;
    n2849: inout std_logic
  );
end Cookbook__fec_check__part441;

architecture Cookbook__fec_check__part441_behav of Cookbook__fec_check__part441 is
begin
    n2849 <= ( lo0510 );
end Cookbook__fec_check__part441_behav;
