--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1461 is 
  Port (
    lo1530: in std_logic;
    n7949: inout std_logic
  );
end Cookbook__fec_check__part1461;

architecture Cookbook__fec_check__part1461_behav of Cookbook__fec_check__part1461 is
begin
    n7949 <= ( lo1530 );
end Cookbook__fec_check__part1461_behav;
