--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1699 is 
  Port (
    lo3849: in std_logic;
    n23826: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1699;

architecture Other__ucsb_152_tap_fir__part1699_behav of Other__ucsb_152_tap_fir__part1699 is
begin
    n23826 <= ( lo3849 );
end Other__ucsb_152_tap_fir__part1699_behav;
