--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part957 is 
  Port (
    lo10641: in std_logic;
    n71141_1: inout std_logic
  );
end Other__ray__part957;

architecture Other__ray__part957_behav of Other__ray__part957 is
begin
    n71141_1 <= ( lo10641 );
end Other__ray__part957_behav;
