--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ava__part4 is 
  Port (
    lo0720: in std_logic;
    n2702: inout std_logic
  );
end Other__ava__part4;

architecture Other__ava__part4_behav of Other__ava__part4 is
begin
    n2702 <= ( lo0720 );
end Other__ava__part4_behav;
