--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part97 is 
  Port (
    lo0166: in std_logic;
    n1129: inout std_logic
  );
end Cookbook__fec_check__part97;

architecture Cookbook__fec_check__part97_behav of Cookbook__fec_check__part97 is
begin
    n1129 <= ( lo0166 );
end Cookbook__fec_check__part97_behav;
