--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part99 is 
  Port (
    lo336: in std_logic;
    po012: inout std_logic
  );
end IWLS2005__aes_core__part99;

architecture IWLS2005__aes_core__part99_behav of IWLS2005__aes_core__part99 is
begin
    po012 <= ( lo336 );
end IWLS2005__aes_core__part99_behav;
