--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part172 is 
  Port (
    lo0241: in std_logic;
    n1504: inout std_logic
  );
end Cookbook__fec_check__part172;

architecture Cookbook__fec_check__part172_behav of Cookbook__fec_check__part172 is
begin
    n1504 <= ( lo0241 );
end Cookbook__fec_check__part172_behav;
