--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part408 is 
  Port (
    lo0094: in std_logic;
    po067: inout std_logic
  );
end Other__carpat__part408;

architecture Other__carpat__part408_behav of Other__carpat__part408 is
begin
    po067 <= ( lo0094 );
end Other__carpat__part408_behav;
