--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2613 is 
  Port (
    lo7872: in std_logic;
    n39555_1: inout std_logic
  );
end IWLS2005__des_perf__part2613;

architecture IWLS2005__des_perf__part2613_behav of IWLS2005__des_perf__part2613 is
begin
    n39555_1 <= ( lo7872 );
end IWLS2005__des_perf__part2613_behav;
