--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part196 is 
  Port (
    lo182: in std_logic;
    po084: inout std_logic
  );
end Cookbook__lc_mult_signed__part196;

architecture Cookbook__lc_mult_signed__part196_behav of Cookbook__lc_mult_signed__part196 is
begin
    po084 <= ( lo182 );
end Cookbook__lc_mult_signed__part196_behav;
