--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1645 is 
  Port (
    lo8437: in std_logic;
    n47084_1: inout std_logic
  );
end Other__carpat__part1645;

architecture Other__carpat__part1645_behav of Other__carpat__part1645 is
begin
    n47084_1 <= ( lo8437 );
end Other__carpat__part1645_behav;
