--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part232 is 
  Port (
    lo0134: in std_logic;
    n740: inout std_logic
  );
end IWLS2005__des_perf__part232;

architecture IWLS2005__des_perf__part232_behav of IWLS2005__des_perf__part232 is
begin
    n740 <= ( lo0134 );
end IWLS2005__des_perf__part232_behav;
