--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part942 is 
  Port (
    lo10523: in std_logic;
    n69156_1: inout std_logic
  );
end Other__ray__part942;

architecture Other__ray__part942_behav of Other__ray__part942 is
begin
    n69156_1 <= ( lo10523 );
end Other__ray__part942_behav;
