--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part91 is 
  Port (
    lo1765: in std_logic;
    po084: inout std_logic
  );
end Other__mem__part91;

architecture Other__mem__part91_behav of Other__mem__part91 is
begin
    po084 <= ( lo1765 );
end Other__mem__part91_behav;
