--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part527 is 
  Port (
    lo3266: in std_logic;
    n15449: inout std_logic
  );
end Other__carpat__part527;

architecture Other__carpat__part527_behav of Other__carpat__part527 is
begin
    n15449 <= ( lo3266 );
end Other__carpat__part527_behav;
