--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part74 is 
  Port (
    lo241: in std_logic;
    po09: inout std_logic
  );
end Cookbook__gearbox_67_40__part74;

architecture Cookbook__gearbox_67_40__part74_behav of Cookbook__gearbox_67_40__part74 is
begin
    po09 <= ( lo241 );
end Cookbook__gearbox_67_40__part74_behav;
