--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part579 is 
  Port (
    lo4184: in std_logic;
    n21195: inout std_logic
  );
end IWLS2005__des_perf__part579;

architecture IWLS2005__des_perf__part579_behav of IWLS2005__des_perf__part579 is
begin
    n21195 <= ( lo4184 );
end IWLS2005__des_perf__part579_behav;
