--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part256 is 
  Port (
    lo2905: in std_logic;
    n7479: inout std_logic
  );
end Other__sudoku_check__part256;

architecture Other__sudoku_check__part256_behav of Other__sudoku_check__part256 is
begin
    n7479 <= ( lo2905 );
end Other__sudoku_check__part256_behav;
