--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part22 is 
  Port (
    lo20: in std_logic;
    po19: inout std_logic
  );
end Cookbook__pipeline_add__part22;

architecture Cookbook__pipeline_add__part22_behav of Cookbook__pipeline_add__part22 is
begin
    po19 <= ( lo20 );
end Cookbook__pipeline_add__part22_behav;
