--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i1__part1 is 
  Port (
    pi24,pi18,pi11,pi14,pi22,pi17,pi23,pi16,pi15,pi13,pi12: in std_logic;
    po04,po05,po07,po08,po09,po10,po11,po12: inout std_logic
  );
end LGSynth91__i1__part1;

architecture LGSynth91__i1__part1_behav of LGSynth91__i1__part1 is
signal po06,n58: std_logic;
begin
    po04 <= ( pi24 and pi18 );
    po05 <= ( po06 )
      or ( n58 );
    po06 <= ( pi24 and pi11 );
    po07 <= ( pi14 and pi22 and not pi24 );
    po08 <= ( pi17 and pi22 and not pi24 );
    po09 <= ( pi14 and pi23 and not pi24 );
    po10 <= ( pi17 and pi23 and not pi24 );
    po11 <= ( pi16 and not pi24 );
    po12 <= ( pi15 )
      or ( pi13 )
      or ( pi12 )
      or ( pi14 );
    n58 <= ( pi11 and not pi24 );
end LGSynth91__i1__part1_behav;
