--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part22 is 
  Port (
    lo214: in std_logic;
    po033: inout std_logic
  );
end IWLS2005__aes_core__part22;

architecture IWLS2005__aes_core__part22_behav of IWLS2005__aes_core__part22 is
begin
    po033 <= ( lo214 );
end IWLS2005__aes_core__part22_behav;
