--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1197 is 
  Port (
    lo1266: in std_logic;
    n6629: inout std_logic
  );
end Cookbook__fec_check__part1197;

architecture Cookbook__fec_check__part1197_behav of Cookbook__fec_check__part1197 is
begin
    n6629 <= ( lo1266 );
end Cookbook__fec_check__part1197_behav;
