--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2013 is 
  Port (
    lo2082: in std_logic;
    n10709: inout std_logic
  );
end Cookbook__fec_check__part2013;

architecture Cookbook__fec_check__part2013_behav of Cookbook__fec_check__part2013 is
begin
    n10709 <= ( lo2082 );
end Cookbook__fec_check__part2013_behav;
