--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1446 is 
  Port (
    lo4815: in std_logic;
    n19564_1: inout std_logic
  );
end Other__sudoku_check__part1446;

architecture Other__sudoku_check__part1446_behav of Other__sudoku_check__part1446 is
begin
    n19564_1 <= ( lo4815 );
end Other__sudoku_check__part1446_behav;
