--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__tv80__part3 is 
  Port (
    lo293: in std_logic;
    po03: inout std_logic
  );
end IWLS2005__tv80__part3;

architecture IWLS2005__tv80__part3_behav of IWLS2005__tv80__part3 is
begin
    po03 <= ( lo293 );
end IWLS2005__tv80__part3_behav;
