--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part261 is 
  Port (
    lo0610: in std_logic;
    n7531: inout std_logic
  );
end Other__ucsb_152_tap_fir__part261;

architecture Other__ucsb_152_tap_fir__part261_behav of Other__ucsb_152_tap_fir__part261 is
begin
    n7531 <= ( lo0610 );
end Other__ucsb_152_tap_fir__part261_behav;
