--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part44 is 
  Port (
    lo62: in std_logic;
    n373: inout std_logic
  );
end Cookbook__mlab_dcfifo__part44;

architecture Cookbook__mlab_dcfifo__part44_behav of Cookbook__mlab_dcfifo__part44 is
begin
    n373 <= ( lo62 );
end Cookbook__mlab_dcfifo__part44_behav;
