--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2428 is 
  Port (
    lo5368: in std_logic;
    n31436_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2428;

architecture Other__ucsb_152_tap_fir__part2428_behav of Other__ucsb_152_tap_fir__part2428 is
begin
    n31436_1 <= ( lo5368 );
end Other__ucsb_152_tap_fir__part2428_behav;
