--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part252 is 
  Port (
    lo1266: in std_logic;
    n8770_1: inout std_logic
  );
end Other__fp_operators__part252;

architecture Other__fp_operators__part252_behav of Other__fp_operators__part252 is
begin
    n8770_1 <= ( lo1266 );
end Other__fp_operators__part252_behav;
