--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1079 is 
  Port (
    lo11024: in std_logic;
    n73601_1: inout std_logic
  );
end Other__ray__part1079;

architecture Other__ray__part1079_behav of Other__ray__part1079 is
begin
    n73601_1 <= ( lo11024 );
end Other__ray__part1079_behav;
