--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part228 is 
  Port (
    lo0772: in std_logic;
    n3474: inout std_logic
  );
end Other__desperf__part228;

architecture Other__desperf__part228_behav of Other__desperf__part228 is
begin
    n3474 <= ( lo0772 );
end Other__desperf__part228_behav;
