--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1037 is 
  Port (
    lo1106: in std_logic;
    n5829: inout std_logic
  );
end Cookbook__fec_check__part1037;

architecture Cookbook__fec_check__part1037_behav of Cookbook__fec_check__part1037 is
begin
    n5829 <= ( lo1106 );
end Cookbook__fec_check__part1037_behav;
