--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part958 is 
  Port (
    lo10644: in std_logic;
    n71156_1: inout std_logic
  );
end Other__ray__part958;

architecture Other__ray__part958_behav of Other__ray__part958 is
begin
    n71156_1 <= ( lo10644 );
end Other__ray__part958_behav;
