--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part91 is 
  Port (
    pi0501: in std_logic;
    n43051_1: inout std_logic
  );
end Other__radar__part91;

architecture Other__radar__part91_behav of Other__radar__part91 is
begin
    n43051_1 <= ( pi0501 );
end Other__radar__part91_behav;
