--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part705 is 
  Port (
    lo5229: in std_logic;
    n25149: inout std_logic
  );
end Other__carpat__part705;

architecture Other__carpat__part705_behav of Other__carpat__part705 is
begin
    n25149 <= ( lo5229 );
end Other__carpat__part705_behav;
