--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part438 is 
  Port (
    lo05910: in std_logic;
    po1327,po1376,po1634,po1696: inout std_logic
  );
end Other__ray__part438;

architecture Other__ray__part438_behav of Other__ray__part438 is
begin
    po1327 <= ( lo05910 );
    po1376 <= ( lo05910 );
    po1634 <= ( lo05910 );
    po1696 <= ( lo05910 );
end Other__ray__part438_behav;
