--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1636 is 
  Port (
    lo8428: in std_logic;
    n47039_1: inout std_logic
  );
end Other__carpat__part1636;

architecture Other__carpat__part1636_behav of Other__carpat__part1636 is
begin
    n47039_1 <= ( lo8428 );
end Other__carpat__part1636_behav;
