--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part91 is 
  Port (
    lo217: in std_logic;
    po121: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part91;

architecture Cookbook__soft_ecc_ram_64bit__part91_behav of Cookbook__soft_ecc_ram_64bit__part91 is
begin
    po121 <= ( lo217 );
end Cookbook__soft_ecc_ram_64bit__part91_behav;
