--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part754 is 
  Port (
    lo5488: in std_logic;
    n25889: inout std_logic
  );
end Other__carpat__part754;

architecture Other__carpat__part754_behav of Other__carpat__part754 is
begin
    n25889 <= ( lo5488 );
end Other__carpat__part754_behav;
