--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s953__part21 is 
  Port (
    lo26: in std_logic;
    po00: inout std_logic
  );
end ISCAS__s953__part21;

architecture ISCAS__s953__part21_behav of ISCAS__s953__part21 is
begin
    po00 <= ( lo26 );
end ISCAS__s953__part21_behav;
