--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1634 is 
  Port (
    lo8426: in std_logic;
    n47029_1: inout std_logic
  );
end Other__carpat__part1634;

architecture Other__carpat__part1634_behav of Other__carpat__part1634 is
begin
    n47029_1 <= ( lo8426 );
end Other__carpat__part1634_behav;
