--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part961 is 
  Port (
    lo6806: in std_logic;
    n34369_1: inout std_logic
  );
end Other__carpat__part961;

architecture Other__carpat__part961_behav of Other__carpat__part961 is
begin
    n34369_1 <= ( lo6806 );
end Other__carpat__part961_behav;
