--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part35 is 
  Port (
    lo47: in std_logic;
    n298: inout std_logic
  );
end Cookbook__mlab_dcfifo__part35;

architecture Cookbook__mlab_dcfifo__part35_behav of Cookbook__mlab_dcfifo__part35 is
begin
    n298 <= ( lo47 );
end Cookbook__mlab_dcfifo__part35_behav;
