--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part89 is 
  Port (
    lo0473: in std_logic;
    po127: inout std_logic
  );
end IWLS2005__mem_ctrl__part89;

architecture IWLS2005__mem_ctrl__part89_behav of IWLS2005__mem_ctrl__part89 is
begin
    po127 <= ( lo0473 );
end IWLS2005__mem_ctrl__part89_behav;
