--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part56 is 
  Port (
    lo287: in std_logic;
    po084: inout std_logic
  );
end IWLS2005__aes_core__part56;

architecture IWLS2005__aes_core__part56_behav of IWLS2005__aes_core__part56 is
begin
    po084 <= ( lo287 );
end IWLS2005__aes_core__part56_behav;
