--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part40 is 
  Port (
    lo104: in std_logic;
    n913: inout std_logic
  );
end ISCAS__s13207__part40;

architecture ISCAS__s13207__part40_behav of ISCAS__s13207__part40 is
begin
    n913 <= ( lo104 );
end ISCAS__s13207__part40_behav;
