--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3152 is 
  Port (
    lo8468: in std_logic;
    n42630: inout std_logic
  );
end IWLS2005__des_perf__part3152;

architecture IWLS2005__des_perf__part3152_behav of IWLS2005__des_perf__part3152 is
begin
    n42630 <= ( lo8468 );
end IWLS2005__des_perf__part3152_behav;
