--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part897 is 
  Port (
    lo6742: in std_logic;
    n33759_1: inout std_logic
  );
end Other__carpat__part897;

architecture Other__carpat__part897_behav of Other__carpat__part897 is
begin
    n33759_1 <= ( lo6742 );
end Other__carpat__part897_behav;
