--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part655 is 
  Port (
    lo3304: in std_logic;
    n11469: inout std_logic
  );
end Other__sudoku_check__part655;

architecture Other__sudoku_check__part655_behav of Other__sudoku_check__part655 is
begin
    n11469 <= ( lo3304 );
end Other__sudoku_check__part655_behav;
