--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part144 is 
  Port (
    lo0974: in std_logic;
    n5144_1: inout std_logic
  );
end LGSynth91__s38417__part144;

architecture LGSynth91__s38417__part144_behav of LGSynth91__s38417__part144 is
begin
    n5144_1 <= ( lo0974 );
end LGSynth91__s38417__part144_behav;
