--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part71 is 
  Port (
    lo70: in std_logic;
    po70: inout std_logic
  );
end Other__idxlat02n_m12__part71;

architecture Other__idxlat02n_m12__part71_behav of Other__idxlat02n_m12__part71 is
begin
    po70 <= ( lo70 );
end Other__idxlat02n_m12__part71_behav;
