--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1722 is 
  Port (
    lo3902: in std_logic;
    n24091: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1722;

architecture Other__ucsb_152_tap_fir__part1722_behav of Other__ucsb_152_tap_fir__part1722 is
begin
    n24091 <= ( lo3902 );
end Other__ucsb_152_tap_fir__part1722_behav;
