--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part7 is 
  Port (
    pi07: in std_logic;
    n869_1: inout std_logic
  );
end ISCAS__s3384__part7;

architecture ISCAS__s3384__part7_behav of ISCAS__s3384__part7 is
begin
    n869_1 <= ( pi07 );
end ISCAS__s3384__part7_behav;
