--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part184 is 
  Port (
    pi0614: in std_logic;
    n44216_1: inout std_logic
  );
end Other__radar__part184;

architecture Other__radar__part184_behav of Other__radar__part184 is
begin
    n44216_1 <= ( pi0614 );
end Other__radar__part184_behav;
