--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part386 is 
  Port (
    lo0455: in std_logic;
    n2574: inout std_logic
  );
end Cookbook__fec_check__part386;

architecture Cookbook__fec_check__part386_behav of Cookbook__fec_check__part386 is
begin
    n2574 <= ( lo0455 );
end Cookbook__fec_check__part386_behav;
