--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part61 is 
  Port (
    lo2350: in std_logic;
    n5529: inout std_logic
  );
end Other__sudoku_check__part61;

architecture Other__sudoku_check__part61_behav of Other__sudoku_check__part61 is
begin
    n5529 <= ( lo2350 );
end Other__sudoku_check__part61_behav;
