--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1543 is 
  Port (
    lo1612: in std_logic;
    n8359: inout std_logic
  );
end Cookbook__fec_check__part1543;

architecture Cookbook__fec_check__part1543_behav of Cookbook__fec_check__part1543 is
begin
    n8359 <= ( lo1612 );
end Cookbook__fec_check__part1543_behav;
