--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part163 is 
  Port (
    lo0043: in std_logic;
    po43: inout std_logic
  );
end Other__desperf__part163;

architecture Other__desperf__part163_behav of Other__desperf__part163 is
begin
    po43 <= ( lo0043 );
end Other__desperf__part163_behav;
