--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part155 is 
  Port (
    lo0224: in std_logic;
    n1419: inout std_logic
  );
end Cookbook__fec_check__part155;

architecture Cookbook__fec_check__part155_behav of Cookbook__fec_check__part155 is
begin
    n1419 <= ( lo0224 );
end Cookbook__fec_check__part155_behav;
