--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1588 is 
  Port (
    lo8301: in std_logic;
    n46394_1: inout std_logic
  );
end Other__carpat__part1588;

architecture Other__carpat__part1588_behav of Other__carpat__part1588 is
begin
    n46394_1 <= ( lo8301 );
end Other__carpat__part1588_behav;
