--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part317 is 
  Port (
    lo1497: in std_logic;
    n10510_1: inout std_logic
  );
end Other__fp_operators__part317;

architecture Other__fp_operators__part317_behav of Other__fp_operators__part317 is
begin
    n10510_1 <= ( lo1497 );
end Other__fp_operators__part317_behav;
