--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part27 is 
  Port (
    lo39: in std_logic;
    n258: inout std_logic
  );
end Cookbook__mlab_dcfifo__part27;

architecture Cookbook__mlab_dcfifo__part27_behav of Cookbook__mlab_dcfifo__part27 is
begin
    n258 <= ( lo39 );
end Cookbook__mlab_dcfifo__part27_behav;
