--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1760 is 
  Port (
    lo6569: in std_logic;
    n33090_1: inout std_logic
  );
end IWLS2005__des_perf__part1760;

architecture IWLS2005__des_perf__part1760_behav of IWLS2005__des_perf__part1760 is
begin
    n33090_1 <= ( lo6569 );
end IWLS2005__des_perf__part1760_behav;
