--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part332 is 
  Port (
    lo1200: in std_logic;
    n5580: inout std_logic
  );
end IWLS2005__des_perf__part332;

architecture IWLS2005__des_perf__part332_behav of IWLS2005__des_perf__part332 is
begin
    n5580 <= ( not lo1200 );
end IWLS2005__des_perf__part332_behav;
