--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1110 is 
  Port (
    lo4479: in std_logic;
    n17884: inout std_logic
  );
end Other__sudoku_check__part1110;

architecture Other__sudoku_check__part1110_behav of Other__sudoku_check__part1110 is
begin
    n17884 <= ( lo4479 );
end Other__sudoku_check__part1110_behav;
