--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part642 is 
  Port (
    lo4288: in std_logic;
    n21665: inout std_logic
  );
end IWLS2005__des_perf__part642;

architecture IWLS2005__des_perf__part642_behav of IWLS2005__des_perf__part642 is
begin
    n21665 <= ( lo4288 );
end IWLS2005__des_perf__part642_behav;
