--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part247 is 
  Port (
    lo0596: in std_logic;
    n7461: inout std_logic
  );
end Other__ucsb_152_tap_fir__part247;

architecture Other__ucsb_152_tap_fir__part247_behav of Other__ucsb_152_tap_fir__part247 is
begin
    n7461 <= ( lo0596 );
end Other__ucsb_152_tap_fir__part247_behav;
