--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part3 is 
  Port (
    lo041: in std_logic;
    po29: inout std_logic
  );
end Cookbook__fec_gen__part3;

architecture Cookbook__fec_gen__part3_behav of Cookbook__fec_gen__part3 is
begin
    po29 <= ( lo041 );
end Cookbook__fec_gen__part3_behav;
