--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1076 is 
  Port (
    lo5136: in std_logic;
    n25965: inout std_logic
  );
end IWLS2005__des_perf__part1076;

architecture IWLS2005__des_perf__part1076_behav of IWLS2005__des_perf__part1076 is
begin
    n25965 <= ( lo5136 );
end IWLS2005__des_perf__part1076_behav;
