--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part64 is 
  Port (
    lo140: in std_logic;
    po38: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part64;

architecture Cookbook__soft_ecc_ram_32bit__part64_behav of Cookbook__soft_ecc_ram_32bit__part64 is
begin
    po38 <= ( lo140 );
end Cookbook__soft_ecc_ram_32bit__part64_behav;
