--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part420 is 
  Port (
    lo1531: in std_logic;
    n8914_1: inout std_logic
  );
end Cookbook__ucrypt__part420;

architecture Cookbook__ucrypt__part420_behav of Cookbook__ucrypt__part420 is
begin
    n8914_1 <= ( lo1531 );
end Cookbook__ucrypt__part420_behav;
