--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1303 is 
  Port (
    lo4672: in std_logic;
    n18849: inout std_logic
  );
end Other__sudoku_check__part1303;

architecture Other__sudoku_check__part1303_behav of Other__sudoku_check__part1303 is
begin
    n18849 <= ( lo4672 );
end Other__sudoku_check__part1303_behav;
