--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1313 is 
  Port (
    lo1382: in std_logic;
    n7209: inout std_logic
  );
end Cookbook__fec_check__part1313;

architecture Cookbook__fec_check__part1313_behav of Cookbook__fec_check__part1313 is
begin
    n7209 <= ( lo1382 );
end Cookbook__fec_check__part1313_behav;
