--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part432 is 
  Port (
    lo0501: in std_logic;
    n2804: inout std_logic
  );
end Cookbook__fec_check__part432;

architecture Cookbook__fec_check__part432_behav of Cookbook__fec_check__part432 is
begin
    n2804 <= ( lo0501 );
end Cookbook__fec_check__part432_behav;
