--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part115 is 
  Port (
    lo0416: in std_logic;
    n4560: inout std_logic
  );
end Other__fp_operators__part115;

architecture Other__fp_operators__part115_behav of Other__fp_operators__part115 is
begin
    n4560 <= ( lo0416 );
end Other__fp_operators__part115_behav;
