--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part904 is 
  Port (
    lo0973: in std_logic;
    n5164: inout std_logic
  );
end Cookbook__fec_check__part904;

architecture Cookbook__fec_check__part904_behav of Cookbook__fec_check__part904 is
begin
    n5164 <= ( lo0973 );
end Cookbook__fec_check__part904_behav;
