--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1774 is 
  Port (
    lo4012: in std_logic;
    n24571: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1774;

architecture Other__ucsb_152_tap_fir__part1774_behav of Other__ucsb_152_tap_fir__part1774 is
begin
    n24571 <= ( lo4012 );
end Other__ucsb_152_tap_fir__part1774_behav;
