--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part593 is 
  Port (
    lo4248: in std_logic;
    n21649: inout std_logic
  );
end Other__carpat__part593;

architecture Other__carpat__part593_behav of Other__carpat__part593 is
begin
    n21649 <= ( lo4248 );
end Other__carpat__part593_behav;
