--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part222 is 
  Port (
    lo0708: in std_logic;
    n3089: inout std_logic
  );
end Other__desperf__part222;

architecture Other__desperf__part222_behav of Other__desperf__part222 is
begin
    n3089 <= ( lo0708 );
end Other__desperf__part222_behav;
