--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1394 is 
  Port (
    lo3192: in std_logic;
    n20546: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1394;

architecture Other__ucsb_152_tap_fir__part1394_behav of Other__ucsb_152_tap_fir__part1394 is
begin
    n20546 <= ( lo3192 );
end Other__ucsb_152_tap_fir__part1394_behav;
