--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part100 is 
  Port (
    pi100: in std_logic;
    n10149_1: inout std_logic
  );
end Other__desperf__part100;

architecture Other__desperf__part100_behav of Other__desperf__part100 is
begin
    n10149_1 <= ( pi100 );
end Other__desperf__part100_behav;
