--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part813 is 
  Port (
    lo0882: in std_logic;
    n4709: inout std_logic
  );
end Cookbook__fec_check__part813;

architecture Cookbook__fec_check__part813_behav of Cookbook__fec_check__part813 is
begin
    n4709 <= ( lo0882 );
end Cookbook__fec_check__part813_behav;
