--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part167 is 
  Port (
    pi0597: in std_logic;
    n44031: inout std_logic
  );
end Other__radar__part167;

architecture Other__radar__part167_behav of Other__radar__part167 is
begin
    n44031 <= ( pi0597 );
end Other__radar__part167_behav;
