--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2608 is 
  Port (
    lo5735: in std_logic;
    n33261_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2608;

architecture Other__ucsb_152_tap_fir__part2608_behav of Other__ucsb_152_tap_fir__part2608 is
begin
    n33261_1 <= ( lo5735 );
end Other__ucsb_152_tap_fir__part2608_behav;
