--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part541 is 
  Port (
    lo4125: in std_logic;
    n20615: inout std_logic
  );
end IWLS2005__des_perf__part541;

architecture IWLS2005__des_perf__part541_behav of IWLS2005__des_perf__part541 is
begin
    n20615 <= ( lo4125 );
end IWLS2005__des_perf__part541_behav;
