--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1538 is 
  Port (
    lo3505: in std_logic;
    n22111: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1538;

architecture Other__ucsb_152_tap_fir__part1538_behav of Other__ucsb_152_tap_fir__part1538 is
begin
    n22111 <= ( lo3505 );
end Other__ucsb_152_tap_fir__part1538_behav;
