--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part3 is 
  Port (
    lo02: in std_logic;
    po02: inout std_logic
  );
end Other__idxlat03n_m12__part3;

architecture Other__idxlat03n_m12__part3_behav of Other__idxlat03n_m12__part3 is
begin
    po02 <= ( lo02 );
end Other__idxlat03n_m12__part3_behav;
