--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part65 is 
  Port (
    lo215: in std_logic;
    po000,po001,po002,po003,po004,po005: inout std_logic
  );
end ISCAS__s13207__part65;

architecture ISCAS__s13207__part65_behav of ISCAS__s13207__part65 is
begin
    po000 <= ( lo215 );
    po001 <= ( lo215 );
    po002 <= ( lo215 );
    po003 <= ( lo215 );
    po004 <= ( lo215 );
    po005 <= ( lo215 );
end ISCAS__s13207__part65_behav;
