--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part247 is 
  Port (
    lo0892: in std_logic;
    n5569: inout std_logic
  );
end Cookbook__ucrypt__part247;

architecture Cookbook__ucrypt__part247_behav of Cookbook__ucrypt__part247 is
begin
    n5569 <= ( lo0892 );
end Cookbook__ucrypt__part247_behav;
