--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part86 is 
  Port (
    lo0272: in std_logic;
    n3960: inout std_logic
  );
end Other__fp_operators__part86;

architecture Other__fp_operators__part86_behav of Other__fp_operators__part86 is
begin
    n3960 <= ( lo0272 );
end Other__fp_operators__part86_behav;
