--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1027 is 
  Port (
    lo1096: in std_logic;
    n5779: inout std_logic
  );
end Cookbook__fec_check__part1027;

architecture Cookbook__fec_check__part1027_behav of Cookbook__fec_check__part1027 is
begin
    n5779 <= ( lo1096 );
end Cookbook__fec_check__part1027_behav;
