--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2113 is 
  Port (
    lo2182: in std_logic;
    n11209: inout std_logic
  );
end Cookbook__fec_check__part2113;

architecture Cookbook__fec_check__part2113_behav of Cookbook__fec_check__part2113 is
begin
    n11209 <= ( lo2182 );
end Cookbook__fec_check__part2113_behav;
