--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part19 is 
  Port (
    pi057,pi121,pi056,pi120,pi055,pi119: in std_logic;
    n299_1: inout std_logic
  );
end Cookbook__pipe_equal__part19;

architecture Cookbook__pipe_equal__part19_behav of Cookbook__pipe_equal__part19 is
signal n223,n224,n225,n226: std_logic;
begin
    n223 <= ( not pi057 and pi121 )
      or ( pi057 and not pi121 );
    n224 <= ( not pi056 and pi120 )
      or ( pi056 and not pi120 );
    n225 <= ( not pi055 and pi119 )
      or ( pi055 and not pi119 );
    n226 <= not (( not n224 and not n225 ));
    n299_1 <= ( not n223 and not n226 );
end Cookbook__pipe_equal__part19_behav;
