--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1516 is 
  Port (
    lo5673,lo5674,lo5675,lo5676: in std_logic;
    n27199_1,n27204_1,n27209_1,n27214_1,n27219_1,n27224_1,n27229_1,n27234_1,n28499_1: inout std_logic
  );
end Other__sudoku_check__part1516;

architecture Other__sudoku_check__part1516_behav of Other__sudoku_check__part1516 is
begin
    n27199_1 <= ( lo5673 and not lo5674 and not lo5675 and lo5676 );
    n27204_1 <= ( not lo5673 and not lo5674 and not lo5675 and lo5676 );
    n27209_1 <= ( lo5673 and lo5674 and lo5675 and not lo5676 );
    n27214_1 <= ( not lo5673 and lo5674 and lo5675 and not lo5676 );
    n27219_1 <= ( lo5673 and not lo5674 and lo5675 and not lo5676 );
    n27224_1 <= ( not lo5673 and not lo5674 and lo5675 and not lo5676 );
    n27229_1 <= ( lo5673 and lo5674 and not lo5675 and not lo5676 );
    n27234_1 <= ( not lo5673 and lo5674 and not lo5675 and not lo5676 );
    n28499_1 <= ( lo5673 and not lo5674 and not lo5675 and not lo5676 );
end Other__sudoku_check__part1516_behav;
