--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1546 is 
  Port (
    lo3517: in std_logic;
    n22166: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1546;

architecture Other__ucsb_152_tap_fir__part1546_behav of Other__ucsb_152_tap_fir__part1546 is
begin
    n22166 <= ( lo3517 );
end Other__ucsb_152_tap_fir__part1546_behav;
