--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1104 is 
  Port (
    lo5181: in std_logic;
    n25885: inout std_logic
  );
end IWLS2005__des_perf__part1104;

architecture IWLS2005__des_perf__part1104_behav of IWLS2005__des_perf__part1104 is
begin
    n25885 <= ( lo5181 );
end IWLS2005__des_perf__part1104_behav;
