--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part29 is 
  Port (
    lo97615: in std_logic;
    n488110_1: inout std_logic
  );
end IWLS2005__netcard__part29;

architecture IWLS2005__netcard__part29_behav of IWLS2005__netcard__part29 is
begin
    n488110_1 <= ( lo97615 );
end IWLS2005__netcard__part29_behav;
