--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2244 is 
  Port (
    lo2344: in std_logic;
    n11864: inout std_logic
  );
end Cookbook__fec_check__part2244;

architecture Cookbook__fec_check__part2244_behav of Cookbook__fec_check__part2244 is
begin
    n11864 <= ( lo2344 );
end Cookbook__fec_check__part2244_behav;
