--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part677 is 
  Port (
    lo0746: in std_logic;
    n4029: inout std_logic
  );
end Cookbook__fec_check__part677;

architecture Cookbook__fec_check__part677_behav of Cookbook__fec_check__part677 is
begin
    n4029 <= ( lo0746 );
end Cookbook__fec_check__part677_behav;
