--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2427 is 
  Port (
    lo5367: in std_logic;
    n31426_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2427;

architecture Other__ucsb_152_tap_fir__part2427_behav of Other__ucsb_152_tap_fir__part2427 is
begin
    n31426_1 <= ( lo5367 );
end Other__ucsb_152_tap_fir__part2427_behav;
