--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part89 is 
  Port (
    lo183: in std_logic;
    po52: inout std_logic
  );
end Cookbook__gearbox_40_67__part89;

architecture Cookbook__gearbox_40_67__part89_behav of Cookbook__gearbox_40_67__part89 is
begin
    po52 <= ( lo183 );
end Cookbook__gearbox_40_67__part89_behav;
