--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1797 is 
  Port (
    lo8892: in std_logic;
    po328: inout std_logic
  );
end Other__carpat__part1797;

architecture Other__carpat__part1797_behav of Other__carpat__part1797 is
begin
    po328 <= ( lo8892 );
end Other__carpat__part1797_behav;
