--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part17 is 
  Port (
    pi20: in std_logic;
    n112: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part17;

architecture Cookbook__ycbcr_to_rgb__part17_behav of Cookbook__ycbcr_to_rgb__part17 is
begin
    n112 <= ( pi20 );
end Cookbook__ycbcr_to_rgb__part17_behav;
