--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part739 is 
  Port (
    lo5467: in std_logic;
    n25814: inout std_logic
  );
end Other__carpat__part739;

architecture Other__carpat__part739_behav of Other__carpat__part739 is
begin
    n25814 <= ( lo5467 );
end Other__carpat__part739_behav;
