--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part221 is 
  Port (
    pi1317: in std_logic;
    n33109_1: inout std_logic
  );
end Other__carpat__part221;

architecture Other__carpat__part221_behav of Other__carpat__part221 is
begin
    n33109_1 <= ( pi1317 );
end Other__carpat__part221_behav;
