--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part199 is 
  Port (
    lo1635: in std_logic;
    po074: inout std_logic
  );
end ISCAS__s38417__part199;

architecture ISCAS__s38417__part199_behav of ISCAS__s38417__part199 is
begin
    po074 <= ( lo1635 );
end ISCAS__s38417__part199_behav;
