--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part819 is 
  Port (
    lo6448: in std_logic;
    n30469: inout std_logic
  );
end Other__carpat__part819;

architecture Other__carpat__part819_behav of Other__carpat__part819 is
begin
    n30469 <= ( lo6448 );
end Other__carpat__part819_behav;
