--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__simple_spi__part4 is 
  Port (
    lo069: in std_logic;
    po01: inout std_logic
  );
end IWLS2005__simple_spi__part4;

architecture IWLS2005__simple_spi__part4_behav of IWLS2005__simple_spi__part4 is
begin
    po01 <= ( lo069 );
end IWLS2005__simple_spi__part4_behav;
