--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part24 is 
  Port (
    lo0124: in std_logic;
    po195: inout std_logic
  );
end Other__cfft__part24;

architecture Other__cfft__part24_behav of Other__cfft__part24 is
begin
    po195 <= ( lo0124 );
end Other__cfft__part24_behav;
