--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1663 is 
  Port (
    lo8608: in std_logic;
    n48539_1: inout std_logic
  );
end Other__carpat__part1663;

architecture Other__carpat__part1663_behav of Other__carpat__part1663 is
begin
    n48539_1 <= ( lo8608 );
end Other__carpat__part1663_behav;
