--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part40 is 
  Port (
    pi040: in std_logic;
    n44205_1: inout std_logic
  );
end IWLS2005__des_perf__part40;

architecture IWLS2005__des_perf__part40_behav of IWLS2005__des_perf__part40 is
begin
    n44205_1 <= ( pi040 );
end IWLS2005__des_perf__part40_behav;
