--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1534 is 
  Port (
    lo8165: in std_logic;
    n45894_1: inout std_logic
  );
end Other__carpat__part1534;

architecture Other__carpat__part1534_behav of Other__carpat__part1534 is
begin
    n45894_1 <= ( lo8165 );
end Other__carpat__part1534_behav;
