--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2266 is 
  Port (
    lo2366: in std_logic;
    n12129: inout std_logic
  );
end Cookbook__fec_check__part2266;

architecture Cookbook__fec_check__part2266_behav of Cookbook__fec_check__part2266 is
begin
    n12129 <= ( lo2366 );
end Cookbook__fec_check__part2266_behav;
