--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2168 is 
  Port (
    lo7318: in std_logic;
    n36590_1: inout std_logic
  );
end IWLS2005__des_perf__part2168;

architecture IWLS2005__des_perf__part2168_behav of IWLS2005__des_perf__part2168 is
begin
    n36590_1 <= ( lo7318 );
end IWLS2005__des_perf__part2168_behav;
