--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1831 is 
  Port (
    lo9104: in std_logic;
    po468: inout std_logic
  );
end Other__carpat__part1831;

architecture Other__carpat__part1831_behav of Other__carpat__part1831 is
begin
    po468 <= ( lo9104 );
end Other__carpat__part1831_behav;
