--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part70 is 
  Port (
    lo149344: in std_logic;
    n746717: inout std_logic
  );
end IWLS2005__leon2__part70;

architecture IWLS2005__leon2__part70_behav of IWLS2005__leon2__part70 is
begin
    n746717 <= ( lo149344 );
end IWLS2005__leon2__part70_behav;
