--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part30 is 
  Port (
    lo72: in std_logic;
    po24: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part30;

architecture Cookbook__soft_ecc_ram_16bit__part30_behav of Cookbook__soft_ecc_ram_16bit__part30 is
begin
    po24 <= ( lo72 );
end Cookbook__soft_ecc_ram_16bit__part30_behav;
