--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part326 is 
  Port (
    lo0395: in std_logic;
    n2274: inout std_logic
  );
end Cookbook__fec_check__part326;

architecture Cookbook__fec_check__part326_behav of Cookbook__fec_check__part326 is
begin
    n2274 <= ( lo0395 );
end Cookbook__fec_check__part326_behav;
