--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part953 is 
  Port (
    lo6798: in std_logic;
    n34329_1: inout std_logic
  );
end Other__carpat__part953;

architecture Other__carpat__part953_behav of Other__carpat__part953 is
begin
    n34329_1 <= ( lo6798 );
end Other__carpat__part953_behav;
