--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1844 is 
  Port (
    lo1913: in std_logic;
    n9864: inout std_logic
  );
end Cookbook__fec_check__part1844;

architecture Cookbook__fec_check__part1844_behav of Cookbook__fec_check__part1844 is
begin
    n9864 <= ( lo1913 );
end Cookbook__fec_check__part1844_behav;
