--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1384 is 
  Port (
    lo7834: in std_logic;
    n44049_1: inout std_logic
  );
end Other__carpat__part1384;

architecture Other__carpat__part1384_behav of Other__carpat__part1384 is
begin
    n44049_1 <= ( lo7834 );
end Other__carpat__part1384_behav;
