--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part132 is 
  Port (
    lo015: in std_logic;
    po015: inout std_logic
  );
end Other__fpu__part132;

architecture Other__fpu__part132_behav of Other__fpu__part132 is
begin
    po015 <= ( lo015 );
end Other__fpu__part132_behav;
