--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part631 is 
  Port (
    lo5019: in std_logic;
    n22239: inout std_logic
  );
end Other__carpat__part631;

architecture Other__carpat__part631_behav of Other__carpat__part631 is
begin
    n22239 <= ( lo5019 );
end Other__carpat__part631_behav;
