--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part490 is 
  Port (
    lo3139: in std_logic;
    n9819: inout std_logic
  );
end Other__sudoku_check__part490;

architecture Other__sudoku_check__part490_behav of Other__sudoku_check__part490 is
begin
    n9819 <= ( lo3139 );
end Other__sudoku_check__part490_behav;
