--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part36 is 
  Port (
    pi0442: in std_logic;
    n42581_1: inout std_logic
  );
end Other__radar__part36;

architecture Other__radar__part36_behav of Other__radar__part36 is
begin
    n42581_1 <= ( pi0442 );
end Other__radar__part36_behav;
