--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part674 is 
  Port (
    lo0743: in std_logic;
    n4014: inout std_logic
  );
end Cookbook__fec_check__part674;

architecture Cookbook__fec_check__part674_behav of Cookbook__fec_check__part674 is
begin
    n4014 <= ( lo0743 );
end Cookbook__fec_check__part674_behav;
