--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part155 is 
  Port (
    lo149: in std_logic;
    n707: inout std_logic
  );
end Other__fpu__part155;

architecture Other__fpu__part155_behav of Other__fpu__part155 is
begin
    n707 <= ( lo149 );
end Other__fpu__part155_behav;
