--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1215 is 
  Port (
    lo4584: in std_logic;
    n18409: inout std_logic
  );
end Other__sudoku_check__part1215;

architecture Other__sudoku_check__part1215_behav of Other__sudoku_check__part1215 is
begin
    n18409 <= ( lo4584 );
end Other__sudoku_check__part1215_behav;
