--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part137 is 
  Port (
    lo2786: in std_logic;
    n6289: inout std_logic
  );
end Other__sudoku_check__part137;

architecture Other__sudoku_check__part137_behav of Other__sudoku_check__part137 is
begin
    n6289 <= ( lo2786 );
end Other__sudoku_check__part137_behav;
