--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part581 is 
  Port (
    lo3585: in std_logic;
    n16944: inout std_logic
  );
end Other__carpat__part581;

architecture Other__carpat__part581_behav of Other__carpat__part581 is
begin
    n16944 <= ( lo3585 );
end Other__carpat__part581_behav;
