--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part419 is 
  Port (
    lo1530: in std_logic;
    n8909_1: inout std_logic
  );
end Cookbook__ucrypt__part419;

architecture Cookbook__ucrypt__part419_behav of Cookbook__ucrypt__part419 is
begin
    n8909_1 <= ( lo1530 );
end Cookbook__ucrypt__part419_behav;
