--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part25 is 
  Port (
    lo0094: in std_logic;
    n769: inout std_logic
  );
end Cookbook__fec_check__part25;

architecture Cookbook__fec_check__part25_behav of Cookbook__fec_check__part25 is
begin
    n769 <= ( lo0094 );
end Cookbook__fec_check__part25_behav;
