--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2022 is 
  Port (
    lo2091: in std_logic;
    n10754: inout std_logic
  );
end Cookbook__fec_check__part2022;

architecture Cookbook__fec_check__part2022_behav of Cookbook__fec_check__part2022 is
begin
    n10754 <= ( lo2091 );
end Cookbook__fec_check__part2022_behav;
