--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part641 is 
  Port (
    lo4287: in std_logic;
    n21510: inout std_logic
  );
end IWLS2005__des_perf__part641;

architecture IWLS2005__des_perf__part641_behav of IWLS2005__des_perf__part641 is
begin
    n21510 <= ( lo4287 );
end IWLS2005__des_perf__part641_behav;
