--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1209 is 
  Port (
    lo4578: in std_logic;
    n18379: inout std_logic
  );
end Other__sudoku_check__part1209;

architecture Other__sudoku_check__part1209_behav of Other__sudoku_check__part1209 is
begin
    n18379 <= ( lo4578 );
end Other__sudoku_check__part1209_behav;
