--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part47 is 
  Port (
    lo161: in std_logic;
    po19: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part47;

architecture Cookbook__ycbcr_to_rgb__part47_behav of Cookbook__ycbcr_to_rgb__part47 is
begin
    po19 <= ( lo161 );
end Cookbook__ycbcr_to_rgb__part47_behav;
