--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part335 is 
  Port (
    lo1578,lo1579,lo1580: in std_logic;
    n11265_1,n11270_1,n11275_1,po253,po254,po255: inout std_logic
  );
end Other__fp_operators__part335;

architecture Other__fp_operators__part335_behav of Other__fp_operators__part335 is
signal n37097: std_logic;
begin
    n11265_1 <= ( not lo1578 );
    n11270_1 <= ( not lo1579 and lo1578 )
      or ( lo1579 and not lo1578 );
    n37097 <= ( lo1579 and lo1578 );
    n11275_1 <= ( not lo1580 and n37097 )
      or ( lo1580 and not n37097 );
    po253 <= ( lo1578 );
    po254 <= ( lo1579 );
    po255 <= ( lo1580 );
end Other__fp_operators__part335_behav;
