--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1250 is 
  Port (
    lo5532: in std_logic;
    n27865: inout std_logic
  );
end IWLS2005__des_perf__part1250;

architecture IWLS2005__des_perf__part1250_behav of IWLS2005__des_perf__part1250 is
begin
    n27865 <= ( lo5532 );
end IWLS2005__des_perf__part1250_behav;
