--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part138 is 
  Port (
    lo0311: in std_logic;
    n6056: inout std_logic
  );
end Other__ucsb_152_tap_fir__part138;

architecture Other__ucsb_152_tap_fir__part138_behav of Other__ucsb_152_tap_fir__part138 is
begin
    n6056 <= ( lo0311 );
end Other__ucsb_152_tap_fir__part138_behav;
