--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1348 is 
  Port (
    lo7798: in std_logic;
    n43869_1: inout std_logic
  );
end Other__carpat__part1348;

architecture Other__carpat__part1348_behav of Other__carpat__part1348 is
begin
    n43869_1 <= ( lo7798 );
end Other__carpat__part1348_behav;
