--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part41 is 
  Port (
    lo15707: in std_logic;
    po94: inout std_logic
  );
end IWLS2005__vga_lcd__part41;

architecture IWLS2005__vga_lcd__part41_behav of IWLS2005__vga_lcd__part41 is
begin
    po94 <= ( lo15707 );
end IWLS2005__vga_lcd__part41_behav;
