--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part538 is 
  Port (
    lo0607: in std_logic;
    n3334: inout std_logic
  );
end Cookbook__fec_check__part538;

architecture Cookbook__fec_check__part538_behav of Cookbook__fec_check__part538 is
begin
    n3334 <= ( lo0607 );
end Cookbook__fec_check__part538_behav;
