--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2040 is 
  Port (
    lo4541: in std_logic;
    n27291: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2040;

architecture Other__ucsb_152_tap_fir__part2040_behav of Other__ucsb_152_tap_fir__part2040 is
begin
    n27291 <= ( lo4541 );
end Other__ucsb_152_tap_fir__part2040_behav;
