--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part135 is 
  Port (
    pi1007: in std_logic;
    n31929: inout std_logic
  );
end Other__carpat__part135;

architecture Other__carpat__part135_behav of Other__carpat__part135 is
begin
    n31929 <= ( pi1007 );
end Other__carpat__part135_behav;
