--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part14 is 
  Port (
    lo052: in std_logic;
    po18: inout std_logic
  );
end Cookbook__fec_gen__part14;

architecture Cookbook__fec_gen__part14_behav of Cookbook__fec_gen__part14 is
begin
    po18 <= ( lo052 );
end Cookbook__fec_gen__part14_behav;
