--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1825 is 
  Port (
    lo1894: in std_logic;
    n9769: inout std_logic
  );
end Cookbook__fec_check__part1825;

architecture Cookbook__fec_check__part1825_behav of Cookbook__fec_check__part1825 is
begin
    n9769 <= ( lo1894 );
end Cookbook__fec_check__part1825_behav;
