--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part422 is 
  Port (
    lo2281: in std_logic;
    n11185: inout std_logic
  );
end IWLS2005__des_perf__part422;

architecture IWLS2005__des_perf__part422_behav of IWLS2005__des_perf__part422 is
begin
    n11185 <= ( not lo2281 );
end IWLS2005__des_perf__part422_behav;
