--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1018 is 
  Port (
    lo1087: in std_logic;
    n5734: inout std_logic
  );
end Cookbook__fec_check__part1018;

architecture Cookbook__fec_check__part1018_behav of Cookbook__fec_check__part1018 is
begin
    n5734 <= ( lo1087 );
end Cookbook__fec_check__part1018_behav;
