--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part645 is 
  Port (
    lo5058: in std_logic;
    n22499: inout std_logic
  );
end Other__carpat__part645;

architecture Other__carpat__part645_behav of Other__carpat__part645 is
begin
    n22499 <= ( lo5058 );
end Other__carpat__part645_behav;
