--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part249 is 
  Port (
    pi1506: in std_logic;
    n44329_1: inout std_logic
  );
end Other__carpat__part249;

architecture Other__carpat__part249_behav of Other__carpat__part249 is
begin
    n44329_1 <= ( pi1506 );
end Other__carpat__part249_behav;
