--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part114 is 
  Port (
    lo01341: in std_logic;
    po2755,po2851,po2947,po3734,po3782,po3830,n20966: inout std_logic
  );
end Other__ray__part114;

architecture Other__ray__part114_behav of Other__ray__part114 is
begin
    po2755 <= ( lo01341 );
    po2851 <= ( lo01341 );
    po2947 <= ( lo01341 );
    po3734 <= ( lo01341 );
    po3782 <= ( lo01341 );
    po3830 <= ( lo01341 );
    n20966 <= ( lo01341 );
end Other__ray__part114_behav;
