--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part666 is 
  Port (
    lo4312: in std_logic;
    n21690: inout std_logic
  );
end IWLS2005__des_perf__part666;

architecture IWLS2005__des_perf__part666_behav of IWLS2005__des_perf__part666 is
begin
    n21690 <= ( lo4312 );
end IWLS2005__des_perf__part666_behav;
