--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1443 is 
  Port (
    lo8074: in std_logic;
    n44419_1: inout std_logic
  );
end Other__carpat__part1443;

architecture Other__carpat__part1443_behav of Other__carpat__part1443 is
begin
    n44419_1 <= ( lo8074 );
end Other__carpat__part1443_behav;
