--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1309 is 
  Port (
    lo4678: in std_logic;
    n18879: inout std_logic
  );
end Other__sudoku_check__part1309;

architecture Other__sudoku_check__part1309_behav of Other__sudoku_check__part1309 is
begin
    n18879 <= ( lo4678 );
end Other__sudoku_check__part1309_behav;
