--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part739 is 
  Port (
    lo3388: in std_logic;
    n12309: inout std_logic
  );
end Other__sudoku_check__part739;

architecture Other__sudoku_check__part739_behav of Other__sudoku_check__part739 is
begin
    n12309 <= ( lo3388 );
end Other__sudoku_check__part739_behav;
