--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2395 is 
  Port (
    lo7618: in std_logic;
    n37980: inout std_logic
  );
end IWLS2005__des_perf__part2395;

architecture IWLS2005__des_perf__part2395_behav of IWLS2005__des_perf__part2395 is
begin
    n37980 <= ( lo7618 );
end IWLS2005__des_perf__part2395_behav;
