--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part12 is 
  Port (
    lo0080: in std_logic;
    po079: inout std_logic
  );
end Other__mem__part12;

architecture Other__mem__part12_behav of Other__mem__part12 is
begin
    po079 <= ( lo0080 );
end Other__mem__part12_behav;
