--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part614 is 
  Port (
    lo06095: in std_logic;
    n38421: inout std_logic
  );
end Other__ray__part614;

architecture Other__ray__part614_behav of Other__ray__part614 is
begin
    n38421 <= ( lo06095 );
end Other__ray__part614_behav;
