--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part690 is 
  Port (
    lo0759: in std_logic;
    n4094: inout std_logic
  );
end Cookbook__fec_check__part690;

architecture Cookbook__fec_check__part690_behav of Cookbook__fec_check__part690 is
begin
    n4094 <= ( lo0759 );
end Cookbook__fec_check__part690_behav;
