--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part139 is 
  Port (
    lo022: in std_logic;
    po022: inout std_logic
  );
end Other__fpu__part139;

architecture Other__fpu__part139_behav of Other__fpu__part139 is
begin
    po022 <= ( lo022 );
end Other__fpu__part139_behav;
