--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1175 is 
  Port (
    lo5342: in std_logic;
    n26525: inout std_logic
  );
end IWLS2005__des_perf__part1175;

architecture IWLS2005__des_perf__part1175_behav of IWLS2005__des_perf__part1175 is
begin
    n26525 <= ( lo5342 );
end IWLS2005__des_perf__part1175_behav;
