--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1299 is 
  Port (
    lo3019: in std_logic;
    n19591: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1299;

architecture Other__ucsb_152_tap_fir__part1299_behav of Other__ucsb_152_tap_fir__part1299 is
begin
    n19591 <= ( lo3019 );
end Other__ucsb_152_tap_fir__part1299_behav;
