--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1002 is 
  Port (
    lo4371: in std_logic;
    n17344: inout std_logic
  );
end Other__sudoku_check__part1002;

architecture Other__sudoku_check__part1002_behav of Other__sudoku_check__part1002 is
begin
    n17344 <= ( lo4371 );
end Other__sudoku_check__part1002_behav;
