--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part234 is 
  Port (
    lo03504: in std_logic;
    n34726: inout std_logic
  );
end Other__ray__part234;

architecture Other__ray__part234_behav of Other__ray__part234 is
begin
    n34726 <= ( lo03504 );
end Other__ray__part234_behav;
