--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part478 is 
  Port (
    lo1722: in std_logic;
    n11589: inout std_logic
  );
end Other__carpat__part478;

architecture Other__carpat__part478_behav of Other__carpat__part478 is
begin
    n11589 <= ( lo1722 );
end Other__carpat__part478_behav;
