--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1527 is 
  Port (
    lo6098: in std_logic;
    n30185_1: inout std_logic
  );
end IWLS2005__des_perf__part1527;

architecture IWLS2005__des_perf__part1527_behav of IWLS2005__des_perf__part1527 is
begin
    n30185_1 <= ( lo6098 );
end IWLS2005__des_perf__part1527_behav;
