--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1191 is 
  Port (
    lo1260: in std_logic;
    n6599: inout std_logic
  );
end Cookbook__fec_check__part1191;

architecture Cookbook__fec_check__part1191_behav of Cookbook__fec_check__part1191 is
begin
    n6599 <= ( lo1260 );
end Cookbook__fec_check__part1191_behav;
