--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1266 is 
  Port (
    lo2923: in std_logic;
    n19196: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1266;

architecture Other__ucsb_152_tap_fir__part1266_behav of Other__ucsb_152_tap_fir__part1266 is
begin
    n19196 <= ( lo2923 );
end Other__ucsb_152_tap_fir__part1266_behav;
