--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1374 is 
  Port (
    lo3172: in std_logic;
    n20446: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1374;

architecture Other__ucsb_152_tap_fir__part1374_behav of Other__ucsb_152_tap_fir__part1374 is
begin
    n20446 <= ( lo3172 );
end Other__ucsb_152_tap_fir__part1374_behav;
