--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part91 is 
  Port (
    pi091: in std_logic;
    n10104_1: inout std_logic
  );
end Other__desperf__part91;

architecture Other__desperf__part91_behav of Other__desperf__part91 is
begin
    n10104_1 <= ( pi091 );
end Other__desperf__part91_behav;
