--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part89 is 
  Port (
    pi0499: in std_logic;
    n43041_1: inout std_logic
  );
end Other__radar__part89;

architecture Other__radar__part89_behav of Other__radar__part89 is
begin
    n43041_1 <= ( pi0499 );
end Other__radar__part89_behav;
