--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part190 is 
  Port (
    lo1362: in std_logic;
    n7149_1: inout std_logic
  );
end IWLS93__s38417__part190;

architecture IWLS93__s38417__part190_behav of IWLS93__s38417__part190 is
begin
    n7149_1 <= ( lo1362 );
end IWLS93__s38417__part190_behav;
