--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38584__part6 is 
  Port (
    lo1439: in std_logic;
    n7706_1: inout std_logic
  );
end ISCAS__s38584__part6;

architecture ISCAS__s38584__part6_behav of ISCAS__s38584__part6 is
begin
    n7706_1 <= ( not lo1439 );
end ISCAS__s38584__part6_behav;
