--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1316 is 
  Port (
    lo5658: in std_logic;
    n28545_1: inout std_logic
  );
end IWLS2005__des_perf__part1316;

architecture IWLS2005__des_perf__part1316_behav of IWLS2005__des_perf__part1316 is
begin
    n28545_1 <= ( lo5658 );
end IWLS2005__des_perf__part1316_behav;
