--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part541 is 
  Port (
    lo3190: in std_logic;
    n10329: inout std_logic
  );
end Other__sudoku_check__part541;

architecture Other__sudoku_check__part541_behav of Other__sudoku_check__part541 is
begin
    n10329 <= ( lo3190 );
end Other__sudoku_check__part541_behav;
