--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part360 is 
  Port (
    pi1709: in std_logic;
    n48254_1: inout std_logic
  );
end Other__carpat__part360;

architecture Other__carpat__part360_behav of Other__carpat__part360 is
begin
    n48254_1 <= ( pi1709 );
end Other__carpat__part360_behav;
