--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2624 is 
  Port (
    lo5754: in std_logic;
    n33361_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2624;

architecture Other__ucsb_152_tap_fir__part2624_behav of Other__ucsb_152_tap_fir__part2624 is
begin
    n33361_1 <= ( lo5754 );
end Other__ucsb_152_tap_fir__part2624_behav;
