--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_20__part25 is 
  Port (
    lo099: in std_logic;
    po16: inout std_logic
  );
end Cookbook__gearbox_66_20__part25;

architecture Cookbook__gearbox_66_20__part25_behav of Cookbook__gearbox_66_20__part25 is
begin
    po16 <= ( lo099 );
end Cookbook__gearbox_66_20__part25_behav;
