--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2600 is 
  Port (
    lo7857: in std_logic;
    n39275_1: inout std_logic
  );
end IWLS2005__des_perf__part2600;

architecture IWLS2005__des_perf__part2600_behav of IWLS2005__des_perf__part2600 is
begin
    n39275_1 <= ( lo7857 );
end IWLS2005__des_perf__part2600_behav;
