--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part7 is 
  Port (
    lo063: in std_logic;
    n949: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part7;

architecture Cookbook__soft_ecc_ram_64bit__part7_behav of Cookbook__soft_ecc_ram_64bit__part7 is
begin
    n949 <= ( lo063 );
end Cookbook__soft_ecc_ram_64bit__part7_behav;
