--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part53 is 
  Port (
    lo0363: in std_logic;
    n2089: inout std_logic
  );
end ISCAS__s38417__part53;

architecture ISCAS__s38417__part53_behav of ISCAS__s38417__part53 is
begin
    n2089 <= ( lo0363 );
end ISCAS__s38417__part53_behav;
