--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2340 is 
  Port (
    lo5179: in std_logic;
    n30401: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2340;

architecture Other__ucsb_152_tap_fir__part2340_behav of Other__ucsb_152_tap_fir__part2340 is
begin
    n30401 <= ( lo5179 );
end Other__ucsb_152_tap_fir__part2340_behav;
