--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part918 is 
  Port (
    lo0987: in std_logic;
    n5234: inout std_logic
  );
end Cookbook__fec_check__part918;

architecture Cookbook__fec_check__part918_behav of Cookbook__fec_check__part918 is
begin
    n5234 <= ( lo0987 );
end Cookbook__fec_check__part918_behav;
