--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1282 is 
  Port (
    lo1351: in std_logic;
    n7054: inout std_logic
  );
end Cookbook__fec_check__part1282;

architecture Cookbook__fec_check__part1282_behav of Cookbook__fec_check__part1282 is
begin
    n7054 <= ( lo1351 );
end Cookbook__fec_check__part1282_behav;
