--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part480 is 
  Port (
    lo1703: in std_logic;
    n9774_1: inout std_logic
  );
end Cookbook__ucrypt__part480;

architecture Cookbook__ucrypt__part480_behav of Cookbook__ucrypt__part480 is
begin
    n9774_1 <= ( lo1703 );
end Cookbook__ucrypt__part480_behav;
