--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2317 is 
  Port (
    lo3445,lo3433,lo3421,lo3409,lo3789: in std_logic;
    n18924: inout std_logic
  );
end Cookbook__fec_check__part2317;

architecture Cookbook__fec_check__part2317_behav of Cookbook__fec_check__part2317 is
signal n13711,n13712,n13713: std_logic;
begin
    n13711 <= not (( not lo3445 and not lo3433 ));
    n13712 <= not (( not lo3421 and not lo3409 ));
    n13713 <= not (( not n13711 and not n13712 ));
    n18924 <= not (( not n13713 and not lo3789 ));
end Cookbook__fec_check__part2317_behav;
