--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part92 is 
  Port (
    lo184655: in std_logic;
    n923276: inout std_logic
  );
end IWLS2005__leon3__part92;

architecture IWLS2005__leon3__part92_behav of IWLS2005__leon3__part92 is
begin
    n923276 <= ( lo184655 );
end IWLS2005__leon3__part92_behav;
