--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2072 is 
  Port (
    lo4604: in std_logic;
    n27601: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2072;

architecture Other__ucsb_152_tap_fir__part2072_behav of Other__ucsb_152_tap_fir__part2072 is
begin
    n27601 <= ( lo4604 );
end Other__ucsb_152_tap_fir__part2072_behav;
