--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2054 is 
  Port (
    lo2123: in std_logic;
    n10914: inout std_logic
  );
end Cookbook__fec_check__part2054;

architecture Cookbook__fec_check__part2054_behav of Cookbook__fec_check__part2054 is
begin
    n10914 <= ( lo2123 );
end Cookbook__fec_check__part2054_behav;
