--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part236 is 
  Port (
    lo0305: in std_logic;
    n1824: inout std_logic
  );
end Cookbook__fec_check__part236;

architecture Cookbook__fec_check__part236_behav of Cookbook__fec_check__part236 is
begin
    n1824 <= ( lo0305 );
end Cookbook__fec_check__part236_behav;
