--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part671 is 
  Port (
    lo06168: in std_logic;
    po1829,po1924: inout std_logic
  );
end Other__ray__part671;

architecture Other__ray__part671_behav of Other__ray__part671 is
begin
    po1829 <= ( lo06168 );
    po1924 <= ( lo06168 );
end Other__ray__part671_behav;
