--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part95 is 
  Port (
    pi0910: in std_logic;
    n31084: inout std_logic
  );
end Other__carpat__part95;

architecture Other__carpat__part95_behav of Other__carpat__part95 is
begin
    n31084 <= ( pi0910 );
end Other__carpat__part95_behav;
