--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part15 is 
  Port (
    pi015: in std_logic;
    n2302_1: inout std_logic
  );
end Other__fpu__part15;

architecture Other__fpu__part15_behav of Other__fpu__part15 is
begin
    n2302_1 <= ( pi015 );
end Other__fpu__part15_behav;
