--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2388 is 
  Port (
    lo5273: in std_logic;
    n30951_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2388;

architecture Other__ucsb_152_tap_fir__part2388_behav of Other__ucsb_152_tap_fir__part2388 is
begin
    n30951_1 <= ( lo5273 );
end Other__ucsb_152_tap_fir__part2388_behav;
