--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part121 is 
  Port (
    lo01348: in std_logic;
    po2784,po2880,po2976,po4038,po4086,po4134,n21011: inout std_logic
  );
end Other__ray__part121;

architecture Other__ray__part121_behav of Other__ray__part121 is
begin
    po2784 <= ( lo01348 );
    po2880 <= ( lo01348 );
    po2976 <= ( lo01348 );
    po4038 <= ( lo01348 );
    po4086 <= ( lo01348 );
    po4134 <= ( lo01348 );
    n21011 <= ( lo01348 );
end Other__ray__part121_behav;
