--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__jbp__part1 is 
  Port (
    pi16,pi25: in std_logic;
    po04,po20: inout std_logic
  );
end Espresso__jbp__part1;

architecture Espresso__jbp__part1_behav of Espresso__jbp__part1 is
begin
    po04 <= ( pi16 and pi25 );
    po20 <= ( not pi16 and pi25 );
end Espresso__jbp__part1_behav;
