--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part695 is 
  Port (
    lo3344: in std_logic;
    n11869: inout std_logic
  );
end Other__sudoku_check__part695;

architecture Other__sudoku_check__part695_behav of Other__sudoku_check__part695 is
begin
    n11869 <= ( lo3344 );
end Other__sudoku_check__part695_behav;
