--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part87 is 
  Port (
    lo0471: in std_logic;
    po130: inout std_logic
  );
end IWLS2005__mem_ctrl__part87;

architecture IWLS2005__mem_ctrl__part87_behav of IWLS2005__mem_ctrl__part87 is
begin
    po130 <= ( lo0471 );
end IWLS2005__mem_ctrl__part87_behav;
