--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1030 is 
  Port (
    lo10751: in std_logic;
    n72061_1: inout std_logic
  );
end Other__ray__part1030;

architecture Other__ray__part1030_behav of Other__ray__part1030 is
begin
    n72061_1 <= ( lo10751 );
end Other__ray__part1030_behav;
