--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1896 is 
  Port (
    lo4252: in std_logic;
    n25841: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1896;

architecture Other__ucsb_152_tap_fir__part1896_behav of Other__ucsb_152_tap_fir__part1896 is
begin
    n25841 <= ( lo4252 );
end Other__ucsb_152_tap_fir__part1896_behav;
