--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part241 is 
  Port (
    lo1177: in std_logic;
    n7355_1: inout std_logic
  );
end Other__fp_operators__part241;

architecture Other__fp_operators__part241_behav of Other__fp_operators__part241 is
begin
    n7355_1 <= ( lo1177 );
end Other__fp_operators__part241_behav;
