--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part415 is 
  Port (
    lo2273: in std_logic;
    n11165: inout std_logic
  );
end IWLS2005__des_perf__part415;

architecture IWLS2005__des_perf__part415_behav of IWLS2005__des_perf__part415 is
begin
    n11165 <= ( not lo2273 );
end IWLS2005__des_perf__part415_behav;
