--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part9 is 
  Port (
    pi1101: in std_logic;
    n51216_1: inout std_logic
  );
end Other__ray__part9;

architecture Other__ray__part9_behav of Other__ray__part9 is
begin
    n51216_1 <= ( pi1101 );
end Other__ray__part9_behav;
