--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part549 is 
  Port (
    lo4134: in std_logic;
    n20930: inout std_logic
  );
end IWLS2005__des_perf__part549;

architecture IWLS2005__des_perf__part549_behav of IWLS2005__des_perf__part549 is
begin
    n20930 <= ( lo4134 );
end IWLS2005__des_perf__part549_behav;
