--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part975 is 
  Port (
    lo4344: in std_logic;
    n17209: inout std_logic
  );
end Other__sudoku_check__part975;

architecture Other__sudoku_check__part975_behav of Other__sudoku_check__part975 is
begin
    n17209 <= ( lo4344 );
end Other__sudoku_check__part975_behav;
