--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part209 is 
  Port (
    lo2858: in std_logic;
    n7009: inout std_logic
  );
end Other__sudoku_check__part209;

architecture Other__sudoku_check__part209_behav of Other__sudoku_check__part209 is
begin
    n7009 <= ( lo2858 );
end Other__sudoku_check__part209_behav;
