--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part469 is 
  Port (
    lo4018: in std_logic;
    n20250: inout std_logic
  );
end IWLS2005__des_perf__part469;

architecture IWLS2005__des_perf__part469_behav of IWLS2005__des_perf__part469 is
begin
    n20250 <= ( lo4018 );
end IWLS2005__des_perf__part469_behav;
