--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part458 is 
  Port (
    lo0929: in std_logic;
    n10059: inout std_logic
  );
end Other__carpat__part458;

architecture Other__carpat__part458_behav of Other__carpat__part458 is
begin
    n10059 <= ( lo0929 );
end Other__carpat__part458_behav;
