--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part721 is 
  Port (
    lo5446: in std_logic;
    n25724: inout std_logic
  );
end Other__carpat__part721;

architecture Other__carpat__part721_behav of Other__carpat__part721 is
begin
    n25724 <= ( lo5446 );
end Other__carpat__part721_behav;
