--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part64 is 
  Port (
    lo17009: in std_logic;
    po07: inout std_logic
  );
end IWLS2005__vga_lcd__part64;

architecture IWLS2005__vga_lcd__part64_behav of IWLS2005__vga_lcd__part64 is
begin
    po07 <= ( lo17009 );
end IWLS2005__vga_lcd__part64_behav;
