--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part17 is 
  Port (
    lo2878: in std_logic;
    n13657: inout std_logic
  );
end Other__top_rs_decode__part17;

architecture Other__top_rs_decode__part17_behav of Other__top_rs_decode__part17 is
begin
    n13657 <= ( lo2878 );
end Other__top_rs_decode__part17_behav;
