--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part120 is 
  Port (
    lo2769: in std_logic;
    n6119: inout std_logic
  );
end Other__sudoku_check__part120;

architecture Other__sudoku_check__part120_behav of Other__sudoku_check__part120 is
begin
    n6119 <= ( lo2769 );
end Other__sudoku_check__part120_behav;
