--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2001 is 
  Port (
    lo7037: in std_logic;
    n35610_1: inout std_logic
  );
end IWLS2005__des_perf__part2001;

architecture IWLS2005__des_perf__part2001_behav of IWLS2005__des_perf__part2001 is
begin
    n35610_1 <= ( lo7037 );
end IWLS2005__des_perf__part2001_behav;
