--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part362 is 
  Port (
    lo2129: in std_logic;
    n11100: inout std_logic
  );
end IWLS2005__des_perf__part362;

architecture IWLS2005__des_perf__part362_behav of IWLS2005__des_perf__part362 is
begin
    n11100 <= ( lo2129 );
end IWLS2005__des_perf__part362_behav;
