--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part475 is 
  Port (
    lo05947: in std_logic;
    po1413,po1462,po1746,po1808: inout std_logic
  );
end Other__ray__part475;

architecture Other__ray__part475_behav of Other__ray__part475 is
begin
    po1413 <= ( lo05947 );
    po1462 <= ( lo05947 );
    po1746 <= ( lo05947 );
    po1808 <= ( lo05947 );
end Other__ray__part475_behav;
