--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part291 is 
  Port (
    lo481: in std_logic;
    n1682: inout std_logic
  );
end Other__fpu__part291;

architecture Other__fpu__part291_behav of Other__fpu__part291 is
begin
    n1682 <= ( lo481 );
end Other__fpu__part291_behav;
