--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part415 is 
  Port (
    lo1526: in std_logic;
    n8889_1: inout std_logic
  );
end Cookbook__ucrypt__part415;

architecture Cookbook__ucrypt__part415_behav of Cookbook__ucrypt__part415 is
begin
    n8889_1 <= ( lo1526 );
end Cookbook__ucrypt__part415_behav;
