--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part746 is 
  Port (
    lo4470: in std_logic;
    n22600: inout std_logic
  );
end IWLS2005__des_perf__part746;

architecture IWLS2005__des_perf__part746_behav of IWLS2005__des_perf__part746 is
begin
    n22600 <= ( lo4470 );
end IWLS2005__des_perf__part746_behav;
