--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part661 is 
  Port (
    lo3310: in std_logic;
    n11529: inout std_logic
  );
end Other__sudoku_check__part661;

architecture Other__sudoku_check__part661_behav of Other__sudoku_check__part661 is
begin
    n11529 <= ( lo3310 );
end Other__sudoku_check__part661_behav;
