--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part144 is 
  Port (
    lo0213: in std_logic;
    n1364: inout std_logic
  );
end Cookbook__fec_check__part144;

architecture Cookbook__fec_check__part144_behav of Cookbook__fec_check__part144 is
begin
    n1364 <= ( lo0213 );
end Cookbook__fec_check__part144_behav;
