--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part77 is 
  Port (
    pi86: in std_logic;
    n924661: inout std_logic
  );
end IWLS2005__leon3__part77;

architecture IWLS2005__leon3__part77_behav of IWLS2005__leon3__part77 is
begin
    n924661 <= ( pi86 );
end IWLS2005__leon3__part77_behav;
