--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1629 is 
  Port (
    lo1698: in std_logic;
    n8789: inout std_logic
  );
end Cookbook__fec_check__part1629;

architecture Cookbook__fec_check__part1629_behav of Cookbook__fec_check__part1629 is
begin
    n8789 <= ( lo1698 );
end Cookbook__fec_check__part1629_behav;
