--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part592 is 
  Port (
    lo06073: in std_logic;
    po1609,po1645: inout std_logic
  );
end Other__ray__part592;

architecture Other__ray__part592_behav of Other__ray__part592 is
begin
    po1609 <= ( lo06073 );
    po1645 <= ( lo06073 );
end Other__ray__part592_behav;
