--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1579 is 
  Port (
    lo1648: in std_logic;
    n8539: inout std_logic
  );
end Cookbook__fec_check__part1579;

architecture Cookbook__fec_check__part1579_behav of Cookbook__fec_check__part1579 is
begin
    n8539 <= ( lo1648 );
end Cookbook__fec_check__part1579_behav;
