--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part389 is 
  Port (
    lo2215: in std_logic;
    n11570: inout std_logic
  );
end IWLS2005__des_perf__part389;

architecture IWLS2005__des_perf__part389_behav of IWLS2005__des_perf__part389 is
begin
    n11570 <= ( lo2215 );
end IWLS2005__des_perf__part389_behav;
