--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1071 is 
  Port (
    lo1140: in std_logic;
    n5999: inout std_logic
  );
end Cookbook__fec_check__part1071;

architecture Cookbook__fec_check__part1071_behav of Cookbook__fec_check__part1071 is
begin
    n5999 <= ( lo1140 );
end Cookbook__fec_check__part1071_behav;
