--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part8 is 
  Port (
    lo0006: in std_logic;
    po0006: inout std_logic
  );
end Other__ether__part8;

architecture Other__ether__part8_behav of Other__ether__part8 is
begin
    po0006 <= ( lo0006 );
end Other__ether__part8_behav;
