--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part798 is 
  Port (
    lo6351: in std_logic;
    n30244: inout std_logic
  );
end Other__carpat__part798;

architecture Other__carpat__part798_behav of Other__carpat__part798 is
begin
    n30244 <= ( lo6351 );
end Other__carpat__part798_behav;
