--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1774 is 
  Port (
    lo1843: in std_logic;
    n9514: inout std_logic
  );
end Cookbook__fec_check__part1774;

architecture Cookbook__fec_check__part1774_behav of Cookbook__fec_check__part1774 is
begin
    n9514 <= ( lo1843 );
end Cookbook__fec_check__part1774_behav;
