--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1357 is 
  Port (
    lo7807: in std_logic;
    n43914_1: inout std_logic
  );
end Other__carpat__part1357;

architecture Other__carpat__part1357_behav of Other__carpat__part1357 is
begin
    n43914_1 <= ( lo7807 );
end Other__carpat__part1357_behav;
