--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part25 is 
  Port (
    pi025: in std_logic;
    n43845_1: inout std_logic
  );
end IWLS2005__des_perf__part25;

architecture IWLS2005__des_perf__part25_behav of IWLS2005__des_perf__part25 is
begin
    n43845_1 <= ( pi025 );
end IWLS2005__des_perf__part25_behav;
