--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part61 is 
  Port (
    pi0471: in std_logic;
    n42731_1: inout std_logic
  );
end Other__radar__part61;

architecture Other__radar__part61_behav of Other__radar__part61 is
begin
    n42731_1 <= ( pi0471 );
end Other__radar__part61_behav;
