--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1195 is 
  Port (
    lo1264: in std_logic;
    n6619: inout std_logic
  );
end Cookbook__fec_check__part1195;

architecture Cookbook__fec_check__part1195_behav of Cookbook__fec_check__part1195 is
begin
    n6619 <= ( lo1264 );
end Cookbook__fec_check__part1195_behav;
