--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1873 is 
  Port (
    lo1942: in std_logic;
    n10009: inout std_logic
  );
end Cookbook__fec_check__part1873;

architecture Cookbook__fec_check__part1873_behav of Cookbook__fec_check__part1873 is
begin
    n10009 <= ( lo1942 );
end Cookbook__fec_check__part1873_behav;
