--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part951 is 
  Port (
    lo6796: in std_logic;
    n34319_1: inout std_logic
  );
end Other__carpat__part951;

architecture Other__carpat__part951_behav of Other__carpat__part951 is
begin
    n34319_1 <= ( lo6796 );
end Other__carpat__part951_behav;
