--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1031 is 
  Port (
    lo4400: in std_logic;
    n17489: inout std_logic
  );
end Other__sudoku_check__part1031;

architecture Other__sudoku_check__part1031_behav of Other__sudoku_check__part1031 is
begin
    n17489 <= ( lo4400 );
end Other__sudoku_check__part1031_behav;
