--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part877 is 
  Port (
    lo4246: in std_logic;
    n16719: inout std_logic
  );
end Other__sudoku_check__part877;

architecture Other__sudoku_check__part877_behav of Other__sudoku_check__part877 is
begin
    n16719 <= ( lo4246 );
end Other__sudoku_check__part877_behav;
