--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part500 is 
  Port (
    lo2330: in std_logic;
    n14719: inout std_logic
  );
end Other__carpat__part500;

architecture Other__carpat__part500_behav of Other__carpat__part500 is
begin
    n14719 <= ( lo2330 );
end Other__carpat__part500_behav;
