--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part23 is 
  Port (
    lo033: in std_logic;
    n909_1: inout std_logic
  );
end ISCAS__s3384__part23;

architecture ISCAS__s3384__part23_behav of ISCAS__s3384__part23 is
begin
    n909_1 <= ( not lo033 );
end ISCAS__s3384__part23_behav;
