--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part226 is 
  Port (
    lo0295: in std_logic;
    n1774: inout std_logic
  );
end Cookbook__fec_check__part226;

architecture Cookbook__fec_check__part226_behav of Cookbook__fec_check__part226 is
begin
    n1774 <= ( lo0295 );
end Cookbook__fec_check__part226_behav;
