--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part217 is 
  Port (
    lo0516: in std_logic;
    n7156: inout std_logic
  );
end Other__ucsb_152_tap_fir__part217;

architecture Other__ucsb_152_tap_fir__part217_behav of Other__ucsb_152_tap_fir__part217 is
begin
    n7156 <= ( lo0516 );
end Other__ucsb_152_tap_fir__part217_behav;
