--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2192 is 
  Port (
    lo4855: in std_logic;
    n28866: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2192;

architecture Other__ucsb_152_tap_fir__part2192_behav of Other__ucsb_152_tap_fir__part2192 is
begin
    n28866 <= ( lo4855 );
end Other__ucsb_152_tap_fir__part2192_behav;
