--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part950 is 
  Port (
    lo1019: in std_logic;
    n5394: inout std_logic
  );
end Cookbook__fec_check__part950;

architecture Cookbook__fec_check__part950_behav of Cookbook__fec_check__part950 is
begin
    n5394 <= ( lo1019 );
end Cookbook__fec_check__part950_behav;
