--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1309 is 
  Port (
    lo1378: in std_logic;
    n7189: inout std_logic
  );
end Cookbook__fec_check__part1309;

architecture Cookbook__fec_check__part1309_behav of Cookbook__fec_check__part1309 is
begin
    n7189 <= ( lo1378 );
end Cookbook__fec_check__part1309_behav;
