--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part132 is 
  Port (
    lo3322: in std_logic;
    n16934: inout std_logic
  );
end IWLS2005__pci_bridge32__part132;

architecture IWLS2005__pci_bridge32__part132_behav of IWLS2005__pci_bridge32__part132 is
begin
    n16934 <= ( lo3322 );
end IWLS2005__pci_bridge32__part132_behav;
