--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2080 is 
  Port (
    lo2149: in std_logic;
    n11044: inout std_logic
  );
end Cookbook__fec_check__part2080;

architecture Cookbook__fec_check__part2080_behav of Cookbook__fec_check__part2080 is
begin
    n11044 <= ( lo2149 );
end Cookbook__fec_check__part2080_behav;
