--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part146 is 
  Port (
    lo029: in std_logic;
    po029: inout std_logic
  );
end Other__fpu__part146;

architecture Other__fpu__part146_behav of Other__fpu__part146 is
begin
    po029 <= ( lo029 );
end Other__fpu__part146_behav;
