--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s953__part17 is 
  Port (
    lo22: in std_logic;
    po02: inout std_logic
  );
end ISCAS__s953__part17;

architecture ISCAS__s953__part17_behav of ISCAS__s953__part17 is
begin
    po02 <= ( lo22 );
end ISCAS__s953__part17_behav;
