--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part750 is 
  Port (
    lo0819: in std_logic;
    n4394: inout std_logic
  );
end Cookbook__fec_check__part750;

architecture Cookbook__fec_check__part750_behav of Cookbook__fec_check__part750 is
begin
    n4394 <= ( lo0819 );
end Cookbook__fec_check__part750_behav;
