--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1373 is 
  Port (
    lo5799: in std_logic;
    n28825_1: inout std_logic
  );
end IWLS2005__des_perf__part1373;

architecture IWLS2005__des_perf__part1373_behav of IWLS2005__des_perf__part1373 is
begin
    n28825_1 <= ( lo5799 );
end IWLS2005__des_perf__part1373_behav;
