--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part789 is 
  Port (
    lo0858: in std_logic;
    n4589: inout std_logic
  );
end Cookbook__fec_check__part789;

architecture Cookbook__fec_check__part789_behav of Cookbook__fec_check__part789 is
begin
    n4589 <= ( lo0858 );
end Cookbook__fec_check__part789_behav;
