--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2210 is 
  Port (
    lo4900: in std_logic;
    n29086: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2210;

architecture Other__ucsb_152_tap_fir__part2210_behav of Other__ucsb_152_tap_fir__part2210 is
begin
    n29086 <= ( lo4900 );
end Other__ucsb_152_tap_fir__part2210_behav;
