--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part244 is 
  Port (
    lo03524: in std_logic;
    n34921: inout std_logic
  );
end Other__ray__part244;

architecture Other__ray__part244_behav of Other__ray__part244 is
begin
    n34921 <= ( lo03524 );
end Other__ray__part244_behav;
