--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part207 is 
  Port (
    lo03253: in std_logic;
    po1177: inout std_logic
  );
end Other__ray__part207;

architecture Other__ray__part207_behav of Other__ray__part207 is
begin
    po1177 <= ( lo03253 );
end Other__ray__part207_behav;
