--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1037 is 
  Port (
    lo5069: in std_logic;
    n25325: inout std_logic
  );
end IWLS2005__des_perf__part1037;

architecture IWLS2005__des_perf__part1037_behav of IWLS2005__des_perf__part1037 is
begin
    n25325 <= ( lo5069 );
end IWLS2005__des_perf__part1037_behav;
