--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1343 is 
  Port (
    lo7793: in std_logic;
    n43844_1: inout std_logic
  );
end Other__carpat__part1343;

architecture Other__carpat__part1343_behav of Other__carpat__part1343 is
begin
    n43844_1 <= ( lo7793 );
end Other__carpat__part1343_behav;
