--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part27 is 
  Port (
    lo238: in std_logic;
    po106: inout std_logic
  );
end IWLS2005__aes_core__part27;

architecture IWLS2005__aes_core__part27_behav of IWLS2005__aes_core__part27 is
begin
    po106 <= ( lo238 );
end IWLS2005__aes_core__part27_behav;
