--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part815 is 
  Port (
    lo6428: in std_logic;
    n30404: inout std_logic
  );
end Other__carpat__part815;

architecture Other__carpat__part815_behav of Other__carpat__part815 is
begin
    n30404 <= ( lo6428 );
end Other__carpat__part815_behav;
