--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part71 is 
  Port (
    lo0998: in std_logic;
    po0012: inout std_logic
  );
end Other__ether__part71;

architecture Other__ether__part71_behav of Other__ether__part71 is
begin
    po0012 <= ( lo0998 );
end Other__ether__part71_behav;
