--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part20 is 
  Port (
    lo85: in std_logic;
    po00: inout std_logic
  );
end Cookbook__gearbox_67_20__part20;

architecture Cookbook__gearbox_67_20__part20_behav of Cookbook__gearbox_67_20__part20 is
begin
    po00 <= ( lo85 );
end Cookbook__gearbox_67_20__part20_behav;
