--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part53 is 
  Port (
    lo0011: in std_logic;
    po113: inout std_logic
  );
end IWLS2005__mem_ctrl__part53;

architecture IWLS2005__mem_ctrl__part53_behav of IWLS2005__mem_ctrl__part53 is
begin
    po113 <= ( lo0011 );
end IWLS2005__mem_ctrl__part53_behav;
