--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b06__part3 is 
  Port (
    lo5: in std_logic;
    po1: inout std_logic
  );
end ITC99__b06__part3;

architecture ITC99__b06__part3_behav of ITC99__b06__part3 is
begin
    po1 <= ( lo5 );
end ITC99__b06__part3_behav;
