--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part144 is 
  Port (
    lo0326: in std_logic;
    n6106: inout std_logic
  );
end Other__ucsb_152_tap_fir__part144;

architecture Other__ucsb_152_tap_fir__part144_behav of Other__ucsb_152_tap_fir__part144 is
begin
    n6106 <= ( lo0326 );
end Other__ucsb_152_tap_fir__part144_behav;
