--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part203 is 
  Port (
    lo03247: in std_logic;
    po1151: inout std_logic
  );
end Other__ray__part203;

architecture Other__ray__part203_behav of Other__ray__part203 is
begin
    po1151 <= ( lo03247 );
end Other__ray__part203_behav;
