--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1057 is 
  Port (
    lo4426: in std_logic;
    n17619: inout std_logic
  );
end Other__sudoku_check__part1057;

architecture Other__sudoku_check__part1057_behav of Other__sudoku_check__part1057 is
begin
    n17619 <= ( lo4426 );
end Other__sudoku_check__part1057_behav;
