--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part55 is 
  Port (
    lo2272: in std_logic;
    n5469: inout std_logic
  );
end Other__sudoku_check__part55;

architecture Other__sudoku_check__part55_behav of Other__sudoku_check__part55 is
begin
    n5469 <= ( lo2272 );
end Other__sudoku_check__part55_behav;
