--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2631 is 
  Port (
    lo5775: in std_logic;
    n33466_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2631;

architecture Other__ucsb_152_tap_fir__part2631_behav of Other__ucsb_152_tap_fir__part2631 is
begin
    n33466_1 <= ( lo5775 );
end Other__ucsb_152_tap_fir__part2631_behav;
