--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1433 is 
  Port (
    lo4802: in std_logic;
    n19499_1: inout std_logic
  );
end Other__sudoku_check__part1433;

architecture Other__sudoku_check__part1433_behav of Other__sudoku_check__part1433 is
begin
    n19499_1 <= ( lo4802 );
end Other__sudoku_check__part1433_behav;
