--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part197 is 
  Port (
    lo2846: in std_logic;
    n6889: inout std_logic
  );
end Other__sudoku_check__part197;

architecture Other__sudoku_check__part197_behav of Other__sudoku_check__part197 is
begin
    n6889 <= ( lo2846 );
end Other__sudoku_check__part197_behav;
