--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part57 is 
  Port (
    pi1152: in std_logic;
    n72266_1: inout std_logic
  );
end Other__ray__part57;

architecture Other__ray__part57_behav of Other__ray__part57 is
begin
    n72266_1 <= ( pi1152 );
end Other__ray__part57_behav;
