--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part153 is 
  Port (
    lo0033: in std_logic;
    po33: inout std_logic
  );
end Other__desperf__part153;

architecture Other__desperf__part153_behav of Other__desperf__part153 is
begin
    po33 <= ( lo0033 );
end Other__desperf__part153_behav;
