--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1751 is 
  Port (
    lo3986: in std_logic;
    n24426: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1751;

architecture Other__ucsb_152_tap_fir__part1751_behav of Other__ucsb_152_tap_fir__part1751 is
begin
    n24426 <= ( lo3986 );
end Other__ucsb_152_tap_fir__part1751_behav;
