--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part808 is 
  Port (
    lo0877: in std_logic;
    n4684: inout std_logic
  );
end Cookbook__fec_check__part808;

architecture Cookbook__fec_check__part808_behav of Cookbook__fec_check__part808 is
begin
    n4684 <= ( lo0877 );
end Cookbook__fec_check__part808_behav;
