--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part67 is 
  Port (
    lo130: in std_logic;
    po006: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part67;

architecture Cookbook__soft_ecc_ram_64bit__part67_behav of Cookbook__soft_ecc_ram_64bit__part67 is
begin
    po006 <= ( lo130 );
end Cookbook__soft_ecc_ram_64bit__part67_behav;
