--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1737 is 
  Port (
    lo3932: in std_logic;
    n24166: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1737;

architecture Other__ucsb_152_tap_fir__part1737_behav of Other__ucsb_152_tap_fir__part1737 is
begin
    n24166 <= ( lo3932 );
end Other__ucsb_152_tap_fir__part1737_behav;
