--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1242 is 
  Port (
    lo2869: in std_logic;
    n18911: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1242;

architecture Other__ucsb_152_tap_fir__part1242_behav of Other__ucsb_152_tap_fir__part1242 is
begin
    n18911 <= ( lo2869 );
end Other__ucsb_152_tap_fir__part1242_behav;
