--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part465 is 
  Port (
    lo0534: in std_logic;
    n2969: inout std_logic
  );
end Cookbook__fec_check__part465;

architecture Cookbook__fec_check__part465_behav of Cookbook__fec_check__part465 is
begin
    n2969 <= ( lo0534 );
end Cookbook__fec_check__part465_behav;
