--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part873 is 
  Port (
    lo0942: in std_logic;
    n5009: inout std_logic
  );
end Cookbook__fec_check__part873;

architecture Cookbook__fec_check__part873_behav of Cookbook__fec_check__part873 is
begin
    n5009 <= ( lo0942 );
end Cookbook__fec_check__part873_behav;
