--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1061 is 
  Port (
    lo10962: in std_logic;
    n73266_1: inout std_logic
  );
end Other__ray__part1061;

architecture Other__ray__part1061_behav of Other__ray__part1061 is
begin
    n73266_1 <= ( lo10962 );
end Other__ray__part1061_behav;
