--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part96 is 
  Port (
    pi0911: in std_logic;
    n31079: inout std_logic
  );
end Other__carpat__part96;

architecture Other__carpat__part96_behav of Other__carpat__part96 is
begin
    n31079 <= ( pi0911 );
end Other__carpat__part96_behav;
