--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part215 is 
  Port (
    lo0284: in std_logic;
    n1719: inout std_logic
  );
end Cookbook__fec_check__part215;

architecture Cookbook__fec_check__part215_behav of Cookbook__fec_check__part215 is
begin
    n1719 <= ( lo0284 );
end Cookbook__fec_check__part215_behav;
