--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1985 is 
  Port (
    lo7014: in std_logic;
    n34745_1: inout std_logic
  );
end IWLS2005__des_perf__part1985;

architecture IWLS2005__des_perf__part1985_behav of IWLS2005__des_perf__part1985 is
begin
    n34745_1 <= ( lo7014 );
end IWLS2005__des_perf__part1985_behav;
