--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part10 is 
  Port (
    lo00417: in std_logic;
    po28: inout std_logic
  );
end IWLS2005__vga_lcd__part10;

architecture IWLS2005__vga_lcd__part10_behav of IWLS2005__vga_lcd__part10 is
begin
    po28 <= ( lo00417 );
end IWLS2005__vga_lcd__part10_behav;
