--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part22 is 
  Port (
    lo21: in std_logic;
    po21: inout std_logic
  );
end Other__idxlat10n_m12__part22;

architecture Other__idxlat10n_m12__part22_behav of Other__idxlat10n_m12__part22 is
begin
    po21 <= ( lo21 );
end Other__idxlat10n_m12__part22_behav;
