--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2040 is 
  Port (
    lo2109: in std_logic;
    n10844: inout std_logic
  );
end Cookbook__fec_check__part2040;

architecture Cookbook__fec_check__part2040_behav of Cookbook__fec_check__part2040 is
begin
    n10844 <= ( lo2109 );
end Cookbook__fec_check__part2040_behav;
