--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part143 is 
  Port (
    lo269: in std_logic;
    po069: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part143;

architecture Cookbook__soft_ecc_ram_64bit__part143_behav of Cookbook__soft_ecc_ram_64bit__part143 is
begin
    po069 <= ( lo269 );
end Cookbook__soft_ecc_ram_64bit__part143_behav;
