--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1855 is 
  Port (
    lo4182: in std_logic;
    n25496: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1855;

architecture Other__ucsb_152_tap_fir__part1855_behav of Other__ucsb_152_tap_fir__part1855 is
begin
    n25496 <= ( lo4182 );
end Other__ucsb_152_tap_fir__part1855_behav;
