--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part875 is 
  Port (
    lo6604: in std_logic;
    n31484_1: inout std_logic
  );
end Other__carpat__part875;

architecture Other__carpat__part875_behav of Other__carpat__part875 is
begin
    n31484_1 <= ( lo6604 );
end Other__carpat__part875_behav;
