--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1104 is 
  Port (
    lo1173: in std_logic;
    n6164: inout std_logic
  );
end Cookbook__fec_check__part1104;

architecture Cookbook__fec_check__part1104_behav of Cookbook__fec_check__part1104 is
begin
    n6164 <= ( lo1173 );
end Cookbook__fec_check__part1104_behav;
