--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part593 is 
  Port (
    lo2152: in std_logic;
    n11979_1: inout std_logic
  );
end Cookbook__ucrypt__part593;

architecture Cookbook__ucrypt__part593_behav of Cookbook__ucrypt__part593 is
begin
    n11979_1 <= ( lo2152 );
end Cookbook__ucrypt__part593_behav;
