--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part86 is 
  Port (
    lo0683: in std_logic;
    n3689: inout std_logic
  );
end ISCAS__s38417__part86;

architecture ISCAS__s38417__part86_behav of ISCAS__s38417__part86 is
begin
    n3689 <= ( lo0683 );
end ISCAS__s38417__part86_behav;
