--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1120 is 
  Port (
    lo7366: in std_logic;
    n40904_1: inout std_logic
  );
end Other__carpat__part1120;

architecture Other__carpat__part1120_behav of Other__carpat__part1120 is
begin
    n40904_1 <= ( lo7366 );
end Other__carpat__part1120_behav;
