--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1187 is 
  Port (
    lo5362: in std_logic;
    n26405: inout std_logic
  );
end IWLS2005__des_perf__part1187;

architecture IWLS2005__des_perf__part1187_behav of IWLS2005__des_perf__part1187 is
begin
    n26405 <= ( lo5362 );
end IWLS2005__des_perf__part1187_behav;
