--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2008 is 
  Port (
    lo4481: in std_logic;
    n26986: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2008;

architecture Other__ucsb_152_tap_fir__part2008_behav of Other__ucsb_152_tap_fir__part2008 is
begin
    n26986 <= ( lo4481 );
end Other__ucsb_152_tap_fir__part2008_behav;
