--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part475 is 
  Port (
    lo4025: in std_logic;
    n20515: inout std_logic
  );
end IWLS2005__des_perf__part475;

architecture IWLS2005__des_perf__part475_behav of IWLS2005__des_perf__part475 is
begin
    n20515 <= ( lo4025 );
end IWLS2005__des_perf__part475_behav;
