--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part887 is 
  Port (
    lo0956: in std_logic;
    n5079: inout std_logic
  );
end Cookbook__fec_check__part887;

architecture Cookbook__fec_check__part887_behav of Cookbook__fec_check__part887 is
begin
    n5079 <= ( lo0956 );
end Cookbook__fec_check__part887_behav;
