--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part768 is 
  Port (
    lo4505: in std_logic;
    n22525: inout std_logic
  );
end IWLS2005__des_perf__part768;

architecture IWLS2005__des_perf__part768_behav of IWLS2005__des_perf__part768 is
begin
    n22525 <= ( lo4505 );
end IWLS2005__des_perf__part768_behav;
