--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part758 is 
  Port (
    lo4493: in std_logic;
    n22390: inout std_logic
  );
end IWLS2005__des_perf__part758;

architecture IWLS2005__des_perf__part758_behav of IWLS2005__des_perf__part758 is
begin
    n22390 <= ( lo4493 );
end IWLS2005__des_perf__part758_behav;
