--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part622 is 
  Port (
    lo3271: in std_logic;
    n11139: inout std_logic
  );
end Other__sudoku_check__part622;

architecture Other__sudoku_check__part622_behav of Other__sudoku_check__part622 is
begin
    n11139 <= ( lo3271 );
end Other__sudoku_check__part622_behav;
