--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_22__part16 is 
  Port (
    lo57: in std_logic;
    po11: inout std_logic
  );
end Cookbook__gearbox_20_22__part16;

architecture Cookbook__gearbox_20_22__part16_behav of Cookbook__gearbox_20_22__part16 is
begin
    po11 <= ( lo57 );
end Cookbook__gearbox_20_22__part16_behav;
