--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2073 is 
  Port (
    lo2142: in std_logic;
    n11009: inout std_logic
  );
end Cookbook__fec_check__part2073;

architecture Cookbook__fec_check__part2073_behav of Cookbook__fec_check__part2073 is
begin
    n11009 <= ( lo2142 );
end Cookbook__fec_check__part2073_behav;
