--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part937 is 
  Port (
    lo6782: in std_logic;
    n34249_1: inout std_logic
  );
end Other__carpat__part937;

architecture Other__carpat__part937_behav of Other__carpat__part937 is
begin
    n34249_1 <= ( lo6782 );
end Other__carpat__part937_behav;
