--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part451 is 
  Port (
    lo05923: in std_logic;
    po1389,po1454,po1720,po1789: inout std_logic
  );
end Other__ray__part451;

architecture Other__ray__part451_behav of Other__ray__part451 is
begin
    po1389 <= ( lo05923 );
    po1454 <= ( lo05923 );
    po1720 <= ( lo05923 );
    po1789 <= ( lo05923 );
end Other__ray__part451_behav;
