--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    lo010: in std_logic;
    po15: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po15 <= ( lo010 );
end top_behav;
