--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part95 is 
  Port (
    lo0635: in std_logic;
    n3449: inout std_logic
  );
end LGSynth91__s38417__part95;

architecture LGSynth91__s38417__part95_behav of LGSynth91__s38417__part95 is
begin
    n3449 <= ( lo0635 );
end LGSynth91__s38417__part95_behav;
