--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part66 is 
  Port (
    lo65: in std_logic;
    po65: inout std_logic
  );
end Other__idxlat10n_m12__part66;

architecture Other__idxlat10n_m12__part66_behav of Other__idxlat10n_m12__part66 is
begin
    po65 <= ( lo65 );
end Other__idxlat10n_m12__part66_behav;
