--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part220 is 
  Port (
    lo324: in std_logic;
    n1132: inout std_logic
  );
end Other__fpu__part220;

architecture Other__fpu__part220_behav of Other__fpu__part220 is
begin
    n1132 <= ( lo324 );
end Other__fpu__part220_behav;
