--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2005 is 
  Port (
    lo2074: in std_logic;
    n10669: inout std_logic
  );
end Cookbook__fec_check__part2005;

architecture Cookbook__fec_check__part2005_behav of Cookbook__fec_check__part2005 is
begin
    n10669 <= ( lo2074 );
end Cookbook__fec_check__part2005_behav;
