--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part253 is 
  Port (
    lo0602: in std_logic;
    n7491: inout std_logic
  );
end Other__ucsb_152_tap_fir__part253;

architecture Other__ucsb_152_tap_fir__part253_behav of Other__ucsb_152_tap_fir__part253 is
begin
    n7491 <= ( lo0602 );
end Other__ucsb_152_tap_fir__part253_behav;
