--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1509 is 
  Port (
    lo1578: in std_logic;
    n8189: inout std_logic
  );
end Cookbook__fec_check__part1509;

architecture Cookbook__fec_check__part1509_behav of Cookbook__fec_check__part1509 is
begin
    n8189 <= ( lo1578 );
end Cookbook__fec_check__part1509_behav;
