--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1477 is 
  Port (
    lo1546: in std_logic;
    n8029: inout std_logic
  );
end Cookbook__fec_check__part1477;

architecture Cookbook__fec_check__part1477_behav of Cookbook__fec_check__part1477 is
begin
    n8029 <= ( lo1546 );
end Cookbook__fec_check__part1477_behav;
