--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part987 is 
  Port (
    lo4356: in std_logic;
    n17269: inout std_logic
  );
end Other__sudoku_check__part987;

architecture Other__sudoku_check__part987_behav of Other__sudoku_check__part987 is
begin
    n17269 <= ( lo4356 );
end Other__sudoku_check__part987_behav;
