--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part85 is 
  Port (
    lo82: in std_logic;
    po02: inout std_logic
  );
end Cookbook__approx_fp_div__part85;

architecture Cookbook__approx_fp_div__part85_behav of Cookbook__approx_fp_div__part85 is
begin
    po02 <= ( lo82 );
end Cookbook__approx_fp_div__part85_behav;
