--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part297 is 
  Port (
    lo0366: in std_logic;
    n2129: inout std_logic
  );
end Cookbook__fec_check__part297;

architecture Cookbook__fec_check__part297_behav of Cookbook__fec_check__part297 is
begin
    n2129 <= ( lo0366 );
end Cookbook__fec_check__part297_behav;
