--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part762 is 
  Port (
    lo06442: in std_logic;
    n48471: inout std_logic
  );
end Other__ray__part762;

architecture Other__ray__part762_behav of Other__ray__part762 is
begin
    n48471 <= ( lo06442 );
end Other__ray__part762_behav;
