--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part623 is 
  Port (
    lo5011: in std_logic;
    n22199: inout std_logic
  );
end Other__carpat__part623;

architecture Other__carpat__part623_behav of Other__carpat__part623 is
begin
    n22199 <= ( lo5011 );
end Other__carpat__part623_behav;
