--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1609 is 
  Port (
    lo1678: in std_logic;
    n8689: inout std_logic
  );
end Cookbook__fec_check__part1609;

architecture Cookbook__fec_check__part1609_behav of Cookbook__fec_check__part1609 is
begin
    n8689 <= ( lo1678 );
end Cookbook__fec_check__part1609_behav;
