--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1634 is 
  Port (
    lo1703: in std_logic;
    n8814: inout std_logic
  );
end Cookbook__fec_check__part1634;

architecture Cookbook__fec_check__part1634_behav of Cookbook__fec_check__part1634 is
begin
    n8814 <= ( lo1703 );
end Cookbook__fec_check__part1634_behav;
