--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2993 is 
  Port (
    lo8306: in std_logic;
    n41855_1: inout std_logic
  );
end IWLS2005__des_perf__part2993;

architecture IWLS2005__des_perf__part2993_behav of IWLS2005__des_perf__part2993 is
begin
    n41855_1 <= ( lo8306 );
end IWLS2005__des_perf__part2993_behav;
