--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part738 is 
  Port (
    lo06418: in std_logic;
    n48186: inout std_logic
  );
end Other__ray__part738;

architecture Other__ray__part738_behav of Other__ray__part738 is
begin
    n48186 <= ( lo06418 );
end Other__ray__part738_behav;
