--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1994 is 
  Port (
    lo4467: in std_logic;
    n26871: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1994;

architecture Other__ucsb_152_tap_fir__part1994_behav of Other__ucsb_152_tap_fir__part1994 is
begin
    n26871 <= ( lo4467 );
end Other__ucsb_152_tap_fir__part1994_behav;
