--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1894 is 
  Port (
    lo4250: in std_logic;
    n25831: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1894;

architecture Other__ucsb_152_tap_fir__part1894_behav of Other__ucsb_152_tap_fir__part1894 is
begin
    n25831 <= ( lo4250 );
end Other__ucsb_152_tap_fir__part1894_behav;
