--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1344 is 
  Port (
    lo1413: in std_logic;
    n7364: inout std_logic
  );
end Cookbook__fec_check__part1344;

architecture Cookbook__fec_check__part1344_behav of Cookbook__fec_check__part1344 is
begin
    n7364 <= ( lo1413 );
end Cookbook__fec_check__part1344_behav;
