--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part181 is 
  Port (
    lo0620: in std_logic;
    n4359: inout std_logic
  );
end Cookbook__ucrypt__part181;

architecture Cookbook__ucrypt__part181_behav of Cookbook__ucrypt__part181 is
begin
    n4359 <= ( lo0620 );
end Cookbook__ucrypt__part181_behav;
