--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1531 is 
  Port (
    lo5733,lo5734,lo5735,lo5736: in std_logic;
    n27309_1,n27314_1,n27319_1,n27324_1,n27329_1,n27334_1,n27339_1,n27344_1,n27359_1: inout std_logic
  );
end Other__sudoku_check__part1531;

architecture Other__sudoku_check__part1531_behav of Other__sudoku_check__part1531 is
begin
    n27309_1 <= ( lo5733 and not lo5734 and not lo5735 and lo5736 );
    n27314_1 <= ( not lo5733 and not lo5734 and not lo5735 and lo5736 );
    n27319_1 <= ( lo5733 and lo5734 and lo5735 and not lo5736 );
    n27324_1 <= ( not lo5733 and lo5734 and lo5735 and not lo5736 );
    n27329_1 <= ( lo5733 and not lo5734 and lo5735 and not lo5736 );
    n27334_1 <= ( not lo5733 and not lo5734 and lo5735 and not lo5736 );
    n27339_1 <= ( lo5733 and lo5734 and not lo5735 and not lo5736 );
    n27344_1 <= ( not lo5733 and lo5734 and not lo5735 and not lo5736 );
    n27359_1 <= ( lo5733 and not lo5734 and not lo5735 and not lo5736 );
end Other__sudoku_check__part1531_behav;
