--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part310 is 
  Port (
    lo1852: in std_logic;
    n8864_1: inout std_logic
  );
end Other__desperf__part310;

architecture Other__desperf__part310_behav of Other__desperf__part310 is
begin
    n8864_1 <= ( lo1852 );
end Other__desperf__part310_behav;
