--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1505 is 
  Port (
    lo5629,lo5630,lo5631,lo5632: in std_logic;
    n27144_1,n29184,n29189,n29194,n29199,n29204,n29209_1,n29214_1,n29219_1: inout std_logic
  );
end Other__sudoku_check__part1505;

architecture Other__sudoku_check__part1505_behav of Other__sudoku_check__part1505 is
begin
    n27144_1 <= ( lo5629 and not lo5630 and not lo5631 and not lo5632 );
    n29184 <= ( lo5629 and not lo5630 and not lo5631 and lo5632 );
    n29189 <= ( not lo5629 and not lo5630 and not lo5631 and lo5632 );
    n29194 <= ( lo5629 and lo5630 and lo5631 and not lo5632 );
    n29199 <= ( not lo5629 and lo5630 and lo5631 and not lo5632 );
    n29204 <= ( lo5629 and not lo5630 and lo5631 and not lo5632 );
    n29209_1 <= ( not lo5629 and not lo5630 and lo5631 and not lo5632 );
    n29214_1 <= ( lo5629 and lo5630 and not lo5631 and not lo5632 );
    n29219_1 <= ( not lo5629 and lo5630 and not lo5631 and not lo5632 );
end Other__sudoku_check__part1505_behav;
