--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2020 is 
  Port (
    lo2089: in std_logic;
    n10744: inout std_logic
  );
end Cookbook__fec_check__part2020;

architecture Cookbook__fec_check__part2020_behav of Cookbook__fec_check__part2020 is
begin
    n10744 <= ( lo2089 );
end Cookbook__fec_check__part2020_behav;
