--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part671 is 
  Port (
    lo0740: in std_logic;
    n3999: inout std_logic
  );
end Cookbook__fec_check__part671;

architecture Cookbook__fec_check__part671_behav of Cookbook__fec_check__part671 is
begin
    n3999 <= ( lo0740 );
end Cookbook__fec_check__part671_behav;
