--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part67 is 
  Port (
    lo081: in std_logic;
    po12: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part67;

architecture Cookbook__approx_fp_invsqrt__part67_behav of Cookbook__approx_fp_invsqrt__part67 is
begin
    po12 <= ( lo081 );
end Cookbook__approx_fp_invsqrt__part67_behav;
