--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2091 is 
  Port (
    lo2160: in std_logic;
    n11099: inout std_logic
  );
end Cookbook__fec_check__part2091;

architecture Cookbook__fec_check__part2091_behav of Cookbook__fec_check__part2091 is
begin
    n11099 <= ( lo2160 );
end Cookbook__fec_check__part2091_behav;
