--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part529 is 
  Port (
    lo3178: in std_logic;
    n10209: inout std_logic
  );
end Other__sudoku_check__part529;

architecture Other__sudoku_check__part529_behav of Other__sudoku_check__part529 is
begin
    n10209 <= ( lo3178 );
end Other__sudoku_check__part529_behav;
