--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1388 is 
  Port (
    lo1457: in std_logic;
    n7584: inout std_logic
  );
end Cookbook__fec_check__part1388;

architecture Cookbook__fec_check__part1388_behav of Cookbook__fec_check__part1388 is
begin
    n7584 <= ( lo1457 );
end Cookbook__fec_check__part1388_behav;
