--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part298 is 
  Port (
    lo03688: in std_logic;
    po6188,po6239,po6494,po6545: inout std_logic
  );
end Other__ray__part298;

architecture Other__ray__part298_behav of Other__ray__part298 is
begin
    po6188 <= ( lo03688 );
    po6239 <= ( lo03688 );
    po6494 <= ( lo03688 );
    po6545 <= ( lo03688 );
end Other__ray__part298_behav;
