--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part94 is 
  Port (
    lo0309: in std_logic;
    n2804: inout std_logic
  );
end Cookbook__ucrypt__part94;

architecture Cookbook__ucrypt__part94_behav of Cookbook__ucrypt__part94 is
begin
    n2804 <= ( lo0309 );
end Cookbook__ucrypt__part94_behav;
