--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part504 is 
  Port (
    lo0573: in std_logic;
    n3164: inout std_logic
  );
end Cookbook__fec_check__part504;

architecture Cookbook__fec_check__part504_behav of Cookbook__fec_check__part504 is
begin
    n3164 <= ( lo0573 );
end Cookbook__fec_check__part504_behav;
