--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1360 is 
  Port (
    lo5784: in std_logic;
    n28875_1: inout std_logic
  );
end IWLS2005__des_perf__part1360;

architecture IWLS2005__des_perf__part1360_behav of IWLS2005__des_perf__part1360 is
begin
    n28875_1 <= ( lo5784 );
end IWLS2005__des_perf__part1360_behav;
