--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__prolog__part5 is 
  Port (
    lo000: in std_logic;
    po01,po00: inout std_logic
  );
end ISCAS__prolog__part5;

architecture ISCAS__prolog__part5_behav of ISCAS__prolog__part5 is
begin
    po01 <= ( lo000 );
    po00 <= ( lo000 );
end ISCAS__prolog__part5_behav;
