--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part57 is 
  Port (
    lo87: in std_logic;
    po12: inout std_logic
  );
end Cookbook__mlab_dcfifo__part57;

architecture Cookbook__mlab_dcfifo__part57_behav of Cookbook__mlab_dcfifo__part57 is
begin
    po12 <= ( lo87 );
end Cookbook__mlab_dcfifo__part57_behav;
