--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part38 is 
  Port (
    lo152: in std_logic;
    po12: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part38;

architecture Cookbook__ycbcr_to_rgb__part38_behav of Cookbook__ycbcr_to_rgb__part38 is
begin
    po12 <= ( lo152 );
end Cookbook__ycbcr_to_rgb__part38_behav;
