--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part139 is 
  Port (
    lo125: in std_logic;
    po141: inout std_logic
  );
end Cookbook__lc_mult_signed__part139;

architecture Cookbook__lc_mult_signed__part139_behav of Cookbook__lc_mult_signed__part139 is
begin
    po141 <= ( lo125 );
end Cookbook__lc_mult_signed__part139_behav;
