--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part239 is 
  Port (
    lo225: in std_logic;
    po041: inout std_logic
  );
end Cookbook__lc_mult_signed__part239;

architecture Cookbook__lc_mult_signed__part239_behav of Cookbook__lc_mult_signed__part239 is
begin
    po041 <= ( lo225 );
end Cookbook__lc_mult_signed__part239_behav;
