--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part577 is 
  Port (
    lo0646: in std_logic;
    n3529: inout std_logic
  );
end Cookbook__fec_check__part577;

architecture Cookbook__fec_check__part577_behav of Cookbook__fec_check__part577 is
begin
    n3529 <= ( lo0646 );
end Cookbook__fec_check__part577_behav;
