--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1783 is 
  Port (
    lo1852: in std_logic;
    n9559: inout std_logic
  );
end Cookbook__fec_check__part1783;

architecture Cookbook__fec_check__part1783_behav of Cookbook__fec_check__part1783 is
begin
    n9559 <= ( lo1852 );
end Cookbook__fec_check__part1783_behav;
