--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part110 is 
  Port (
    pi0955: in std_logic;
    n31309_1: inout std_logic
  );
end Other__carpat__part110;

architecture Other__carpat__part110_behav of Other__carpat__part110 is
begin
    n31309_1 <= ( pi0955 );
end Other__carpat__part110_behav;
