--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr__part18 is 
  Port (
    lo24: in std_logic;
    n190,po07: inout std_logic
  );
end Cookbook__lfsr__part18;

architecture Cookbook__lfsr__part18_behav of Cookbook__lfsr__part18 is
begin
    n190 <= ( lo24 );
    po07 <= ( lo24 );
end Cookbook__lfsr__part18_behav;
