--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part255 is 
  Port (
    lo1132: in std_logic;
    n5294: inout std_logic
  );
end Other__desperf__part255;

architecture Other__desperf__part255_behav of Other__desperf__part255 is
begin
    n5294 <= ( lo1132 );
end Other__desperf__part255_behav;
