--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1983 is 
  Port (
    lo7012: in std_logic;
    n34835_1: inout std_logic
  );
end IWLS2005__des_perf__part1983;

architecture IWLS2005__des_perf__part1983_behav of IWLS2005__des_perf__part1983 is
begin
    n34835_1 <= ( lo7012 );
end IWLS2005__des_perf__part1983_behav;
