--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s5378__part4 is 
  Port (
    lo120: in std_logic;
    n768_1: inout std_logic
  );
end ISCAS__s5378__part4;

architecture ISCAS__s5378__part4_behav of ISCAS__s5378__part4 is
begin
    n768_1 <= ( not lo120 );
end ISCAS__s5378__part4_behav;
