--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part254 is 
  Port (
    lo0917: in std_logic;
    n5844: inout std_logic
  );
end Cookbook__ucrypt__part254;

architecture Cookbook__ucrypt__part254_behav of Cookbook__ucrypt__part254 is
begin
    n5844 <= ( lo0917 );
end Cookbook__ucrypt__part254_behav;
