--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part274 is 
  Port (
    lo0937: in std_logic;
    n5944: inout std_logic
  );
end Cookbook__ucrypt__part274;

architecture Cookbook__ucrypt__part274_behav of Cookbook__ucrypt__part274 is
begin
    n5944 <= ( lo0937 );
end Cookbook__ucrypt__part274_behav;
