--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part838 is 
  Port (
    lo4207: in std_logic;
    n16254: inout std_logic
  );
end Other__sudoku_check__part838;

architecture Other__sudoku_check__part838_behav of Other__sudoku_check__part838 is
begin
    n16254 <= ( lo4207 );
end Other__sudoku_check__part838_behav;
