--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part825 is 
  Port (
    lo0894: in std_logic;
    n4769: inout std_logic
  );
end Cookbook__fec_check__part825;

architecture Cookbook__fec_check__part825_behav of Cookbook__fec_check__part825 is
begin
    n4769 <= ( lo0894 );
end Cookbook__fec_check__part825_behav;
