--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1530 is 
  Port (
    lo1599: in std_logic;
    n8294: inout std_logic
  );
end Cookbook__fec_check__part1530;

architecture Cookbook__fec_check__part1530_behav of Cookbook__fec_check__part1530 is
begin
    n8294 <= ( lo1599 );
end Cookbook__fec_check__part1530_behav;
