--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part157 is 
  Port (
    lo1053: in std_logic;
    n5089_1: inout std_logic
  );
end IWLS93__s38417__part157;

architecture IWLS93__s38417__part157_behav of IWLS93__s38417__part157 is
begin
    n5089_1 <= ( lo1053 );
end IWLS93__s38417__part157_behav;
