--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part400 is 
  Port (
    lo05872: in std_logic;
    po1289,po1354,po1594,po1663: inout std_logic
  );
end Other__ray__part400;

architecture Other__ray__part400_behav of Other__ray__part400 is
begin
    po1289 <= ( lo05872 );
    po1354 <= ( lo05872 );
    po1594 <= ( lo05872 );
    po1663 <= ( lo05872 );
end Other__ray__part400_behav;
