--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part83 is 
  Port (
    lo80: in std_logic;
    po04: inout std_logic
  );
end Cookbook__approx_fp_div__part83;

architecture Cookbook__approx_fp_div__part83_behav of Cookbook__approx_fp_div__part83 is
begin
    po04 <= ( lo80 );
end Cookbook__approx_fp_div__part83_behav;
