--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part874 is 
  Port (
    lo4243: in std_logic;
    n16704: inout std_logic
  );
end Other__sudoku_check__part874;

architecture Other__sudoku_check__part874_behav of Other__sudoku_check__part874 is
begin
    n16704 <= ( lo4243 );
end Other__sudoku_check__part874_behav;
