--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part278 is 
  Port (
    pi1535: in std_logic;
    n44884_1: inout std_logic
  );
end Other__carpat__part278;

architecture Other__carpat__part278_behav of Other__carpat__part278 is
begin
    n44884_1 <= ( pi1535 );
end Other__carpat__part278_behav;
