--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part72 is 
  Port (
    lo0653: in std_logic;
    n4249: inout std_logic
  );
end ISCAS__s38417__part72;

architecture ISCAS__s38417__part72_behav of ISCAS__s38417__part72 is
begin
    n4249 <= ( not lo0653 );
end ISCAS__s38417__part72_behav;
