--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1628 is 
  Port (
    lo1697: in std_logic;
    n8784: inout std_logic
  );
end Cookbook__fec_check__part1628;

architecture Cookbook__fec_check__part1628_behav of Cookbook__fec_check__part1628 is
begin
    n8784 <= ( lo1697 );
end Cookbook__fec_check__part1628_behav;
