--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part556 is 
  Port (
    lo3347: in std_logic;
    n15789: inout std_logic
  );
end Other__carpat__part556;

architecture Other__carpat__part556_behav of Other__carpat__part556 is
begin
    n15789 <= ( lo3347 );
end Other__carpat__part556_behav;
