--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2229 is 
  Port (
    lo2298: in std_logic;
    n11789: inout std_logic
  );
end Cookbook__fec_check__part2229;

architecture Cookbook__fec_check__part2229_behav of Cookbook__fec_check__part2229 is
begin
    n11789 <= ( lo2298 );
end Cookbook__fec_check__part2229_behav;
