--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1556 is 
  Port (
    lo1625: in std_logic;
    n8424: inout std_logic
  );
end Cookbook__fec_check__part1556;

architecture Cookbook__fec_check__part1556_behav of Cookbook__fec_check__part1556 is
begin
    n8424 <= ( lo1625 );
end Cookbook__fec_check__part1556_behav;
