--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part326 is 
  Port (
    lo1193: in std_logic;
    n5630: inout std_logic
  );
end IWLS2005__des_perf__part326;

architecture IWLS2005__des_perf__part326_behav of IWLS2005__des_perf__part326 is
begin
    n5630 <= ( lo1193 );
end IWLS2005__des_perf__part326_behav;
