--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part721 is 
  Port (
    lo3370: in std_logic;
    n12129: inout std_logic
  );
end Other__sudoku_check__part721;

architecture Other__sudoku_check__part721_behav of Other__sudoku_check__part721 is
begin
    n12129 <= ( lo3370 );
end Other__sudoku_check__part721_behav;
