--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part225 is 
  Port (
    lo0776: in std_logic;
    n5139: inout std_logic
  );
end Cookbook__ucrypt__part225;

architecture Cookbook__ucrypt__part225_behav of Cookbook__ucrypt__part225 is
begin
    n5139 <= ( lo0776 );
end Cookbook__ucrypt__part225_behav;
