--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1997 is 
  Port (
    lo4470: in std_logic;
    n26901: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1997;

architecture Other__ucsb_152_tap_fir__part1997_behav of Other__ucsb_152_tap_fir__part1997 is
begin
    n26901 <= ( lo4470 );
end Other__ucsb_152_tap_fir__part1997_behav;
