--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2050 is 
  Port (
    lo4581: in std_logic;
    n27486: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2050;

architecture Other__ucsb_152_tap_fir__part2050_behav of Other__ucsb_152_tap_fir__part2050 is
begin
    n27486 <= ( lo4581 );
end Other__ucsb_152_tap_fir__part2050_behav;
