--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part325 is 
  Port (
    lo0394: in std_logic;
    n2269: inout std_logic
  );
end Cookbook__fec_check__part325;

architecture Cookbook__fec_check__part325_behav of Cookbook__fec_check__part325 is
begin
    n2269 <= ( lo0394 );
end Cookbook__fec_check__part325_behav;
