--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1769 is 
  Port (
    lo8864: in std_logic;
    po299: inout std_logic
  );
end Other__carpat__part1769;

architecture Other__carpat__part1769_behav of Other__carpat__part1769 is
begin
    po299 <= ( lo8864 );
end Other__carpat__part1769_behav;
