--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1234 is 
  Port (
    lo1303: in std_logic;
    n6814: inout std_logic
  );
end Cookbook__fec_check__part1234;

architecture Cookbook__fec_check__part1234_behav of Cookbook__fec_check__part1234 is
begin
    n6814 <= ( lo1303 );
end Cookbook__fec_check__part1234_behav;
