--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part69 is 
  Port (
    pi0798: in std_logic;
    n24849: inout std_logic
  );
end Other__carpat__part69;

architecture Other__carpat__part69_behav of Other__carpat__part69 is
begin
    n24849 <= ( pi0798 );
end Other__carpat__part69_behav;
