--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1806 is 
  Port (
    lo8901: in std_logic;
    po337: inout std_logic
  );
end Other__carpat__part1806;

architecture Other__carpat__part1806_behav of Other__carpat__part1806 is
begin
    po337 <= ( lo8901 );
end Other__carpat__part1806_behav;
