--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part42 is 
  Port (
    lo00917: in std_logic;
    po092: inout std_logic
  );
end IWLS2005__ethernet__part42;

architecture IWLS2005__ethernet__part42_behav of IWLS2005__ethernet__part42 is
begin
    po092 <= ( lo00917 );
end IWLS2005__ethernet__part42_behav;
