--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2130 is 
  Port (
    lo2199: in std_logic;
    n11294: inout std_logic
  );
end Cookbook__fec_check__part2130;

architecture Cookbook__fec_check__part2130_behav of Cookbook__fec_check__part2130 is
begin
    n11294 <= ( lo2199 );
end Cookbook__fec_check__part2130_behav;
