--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part149 is 
  Port (
    lo032: in std_logic;
    po033: inout std_logic
  );
end Other__fpu__part149;

architecture Other__fpu__part149_behav of Other__fpu__part149 is
begin
    po033 <= ( lo032 );
end Other__fpu__part149_behav;
