--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part41 is 
  Port (
    pi041: in std_logic;
    n2432_1: inout std_logic
  );
end Other__fpu__part41;

architecture Other__fpu__part41_behav of Other__fpu__part41 is
begin
    n2432_1 <= ( pi041 );
end Other__fpu__part41_behav;
