--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part138 is 
  Port (
    lo0996: in std_logic;
    po069: inout std_logic
  );
end IWLS2005__mem_ctrl__part138;

architecture IWLS2005__mem_ctrl__part138_behav of IWLS2005__mem_ctrl__part138 is
begin
    po069 <= ( lo0996 );
end IWLS2005__mem_ctrl__part138_behav;
