--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part112 is 
  Port (
    lo184880: in std_logic;
    n924341: inout std_logic
  );
end IWLS2005__leon3__part112;

architecture IWLS2005__leon3__part112_behav of IWLS2005__leon3__part112 is
begin
    n924341 <= ( lo184880 );
end IWLS2005__leon3__part112_behav;
