--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__enc_64_67__part2 is 
  Port (
    lo066: in std_logic;
    n604: inout std_logic
  );
end Cookbook__enc_64_67__part2;

architecture Cookbook__enc_64_67__part2_behav of Cookbook__enc_64_67__part2 is
begin
    n604 <= ( lo066 );
end Cookbook__enc_64_67__part2_behav;
