--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1868 is 
  Port (
    lo6784: in std_logic;
    n33565_1: inout std_logic
  );
end IWLS2005__des_perf__part1868;

architecture IWLS2005__des_perf__part1868_behav of IWLS2005__des_perf__part1868 is
begin
    n33565_1 <= ( lo6784 );
end IWLS2005__des_perf__part1868_behav;
