--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part131 is 
  Port (
    lo0931: in std_logic;
    n4929_1: inout std_logic
  );
end LGSynth91__s38417__part131;

architecture LGSynth91__s38417__part131_behav of LGSynth91__s38417__part131 is
begin
    n4929_1 <= ( lo0931 );
end LGSynth91__s38417__part131_behav;
