--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part143 is 
  Port (
    lo0470: in std_logic;
    n3609: inout std_logic
  );
end Cookbook__ucrypt__part143;

architecture Cookbook__ucrypt__part143_behav of Cookbook__ucrypt__part143 is
begin
    n3609 <= ( lo0470 );
end Cookbook__ucrypt__part143_behav;
