--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part128 is 
  Port (
    lo222: in std_logic;
    po13: inout std_logic
  );
end Cookbook__gearbox_40_67__part128;

architecture Cookbook__gearbox_40_67__part128_behav of Cookbook__gearbox_40_67__part128 is
begin
    po13 <= ( lo222 );
end Cookbook__gearbox_40_67__part128_behav;
