--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part395 is 
  Port (
    lo0009: in std_logic;
    po009: inout std_logic
  );
end Other__carpat__part395;

architecture Other__carpat__part395_behav of Other__carpat__part395 is
begin
    po009 <= ( lo0009 );
end Other__carpat__part395_behav;
