--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part63 is 
  Port (
    lo149311: in std_logic;
    n746662: inout std_logic
  );
end IWLS2005__leon2__part63;

architecture IWLS2005__leon2__part63_behav of IWLS2005__leon2__part63 is
begin
    n746662 <= ( lo149311 );
end IWLS2005__leon2__part63_behav;
