--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1161 is 
  Port (
    lo7408: in std_logic;
    n41119_1: inout std_logic
  );
end Other__carpat__part1161;

architecture Other__carpat__part1161_behav of Other__carpat__part1161 is
begin
    n41119_1 <= ( lo7408 );
end Other__carpat__part1161_behav;
