--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1753 is 
  Port (
    lo3991: in std_logic;
    n24466: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1753;

architecture Other__ucsb_152_tap_fir__part1753_behav of Other__ucsb_152_tap_fir__part1753 is
begin
    n24466 <= ( lo3991 );
end Other__ucsb_152_tap_fir__part1753_behav;
