--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1282 is 
  Port (
    lo5586: in std_logic;
    n27640_1: inout std_logic
  );
end IWLS2005__des_perf__part1282;

architecture IWLS2005__des_perf__part1282_behav of IWLS2005__des_perf__part1282 is
begin
    n27640_1 <= ( lo5586 );
end IWLS2005__des_perf__part1282_behav;
