--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1741 is 
  Port (
    lo3936: in std_logic;
    n24186: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1741;

architecture Other__ucsb_152_tap_fir__part1741_behav of Other__ucsb_152_tap_fir__part1741 is
begin
    n24186 <= ( lo3936 );
end Other__ucsb_152_tap_fir__part1741_behav;
