--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part562 is 
  Port (
    lo3211: in std_logic;
    n10539: inout std_logic
  );
end Other__sudoku_check__part562;

architecture Other__sudoku_check__part562_behav of Other__sudoku_check__part562 is
begin
    n10539 <= ( lo3211 );
end Other__sudoku_check__part562_behav;
