--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part373 is 
  Port (
    pi1739: in std_logic;
    n48329_1: inout std_logic
  );
end Other__carpat__part373;

architecture Other__carpat__part373_behav of Other__carpat__part373 is
begin
    n48329_1 <= ( pi1739 );
end Other__carpat__part373_behav;
