--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part176 is 
  Port (
    lo2825: in std_logic;
    n6679: inout std_logic
  );
end Other__sudoku_check__part176;

architecture Other__sudoku_check__part176_behav of Other__sudoku_check__part176 is
begin
    n6679 <= ( lo2825 );
end Other__sudoku_check__part176_behav;
