--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part20 is 
  Port (
    lo19: in std_logic;
    po19: inout std_logic
  );
end Other__idxlat01n_m12__part20;

architecture Other__idxlat01n_m12__part20_behav of Other__idxlat01n_m12__part20 is
begin
    po19 <= ( lo19 );
end Other__idxlat01n_m12__part20_behav;
