--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part105 is 
  Port (
    pi105: in std_logic;
    n2037: inout std_logic
  );
end Other__fpu__part105;

architecture Other__fpu__part105_behav of Other__fpu__part105 is
begin
    n2037 <= ( pi105 );
end Other__fpu__part105_behav;
