--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2019 is 
  Port (
    lo7058: in std_logic;
    n35595_1: inout std_logic
  );
end IWLS2005__des_perf__part2019;

architecture IWLS2005__des_perf__part2019_behav of IWLS2005__des_perf__part2019 is
begin
    n35595_1 <= ( lo7058 );
end IWLS2005__des_perf__part2019_behav;
