--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part78 is 
  Port (
    lo064: in std_logic;
    po202: inout std_logic
  );
end Cookbook__lc_mult_signed__part78;

architecture Cookbook__lc_mult_signed__part78_behav of Cookbook__lc_mult_signed__part78 is
begin
    po202 <= ( lo064 );
end Cookbook__lc_mult_signed__part78_behav;
