--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part139 is 
  Port (
    lo0902: in std_logic;
    n2879: inout std_logic
  );
end IWLS93__s38417__part139;

architecture IWLS93__s38417__part139_behav of IWLS93__s38417__part139 is
begin
    n2879 <= ( not lo0902 );
end IWLS93__s38417__part139_behav;
