--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part120 is 
  Port (
    lo003: in std_logic;
    po003: inout std_logic
  );
end Other__fpu__part120;

architecture Other__fpu__part120_behav of Other__fpu__part120 is
begin
    po003 <= ( lo003 );
end Other__fpu__part120_behav;
