--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr__part15 is 
  Port (
    lo21: in std_logic;
    n175,po10: inout std_logic
  );
end Cookbook__lfsr__part15;

architecture Cookbook__lfsr__part15_behav of Cookbook__lfsr__part15 is
begin
    n175 <= ( lo21 );
    po10 <= ( lo21 );
end Cookbook__lfsr__part15_behav;
