--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part509 is 
  Port (
    lo4091: in std_logic;
    n20895: inout std_logic
  );
end IWLS2005__des_perf__part509;

architecture IWLS2005__des_perf__part509_behav of IWLS2005__des_perf__part509 is
begin
    n20895 <= ( lo4091 );
end IWLS2005__des_perf__part509_behav;
