--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2545 is 
  Port (
    lo7802: in std_logic;
    n38690_1: inout std_logic
  );
end IWLS2005__des_perf__part2545;

architecture IWLS2005__des_perf__part2545_behav of IWLS2005__des_perf__part2545 is
begin
    n38690_1 <= ( lo7802 );
end IWLS2005__des_perf__part2545_behav;
