--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part4 is 
  Port (
    lo2113: in std_logic;
    n5312: inout std_logic
  );
end Other__top_rs_decode__part4;

architecture Other__top_rs_decode__part4_behav of Other__top_rs_decode__part4 is
begin
    n5312 <= ( lo2113 );
end Other__top_rs_decode__part4_behav;
