--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part66 is 
  Port (
    lo0597: in std_logic;
    po014,n3279,n3259: inout std_logic
  );
end ISCAS__s38417__part66;

architecture ISCAS__s38417__part66_behav of ISCAS__s38417__part66 is
begin
    po014 <= ( lo0597 );
    n3279 <= ( lo0597 );
    n3259 <= ( lo0597 );
end ISCAS__s38417__part66_behav;
