--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1122 is 
  Port (
    lo4491: in std_logic;
    n17944: inout std_logic
  );
end Other__sudoku_check__part1122;

architecture Other__sudoku_check__part1122_behav of Other__sudoku_check__part1122 is
begin
    n17944 <= ( lo4491 );
end Other__sudoku_check__part1122_behav;
