--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part832 is 
  Port (
    lo0901: in std_logic;
    n4804: inout std_logic
  );
end Cookbook__fec_check__part832;

architecture Cookbook__fec_check__part832_behav of Cookbook__fec_check__part832 is
begin
    n4804 <= ( lo0901 );
end Cookbook__fec_check__part832_behav;
