--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1767 is 
  Port (
    lo8838: in std_logic;
    po293: inout std_logic
  );
end Other__carpat__part1767;

architecture Other__carpat__part1767_behav of Other__carpat__part1767 is
begin
    po293 <= ( lo8838 );
end Other__carpat__part1767_behav;
