--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1305 is 
  Port (
    lo4674: in std_logic;
    n18859: inout std_logic
  );
end Other__sudoku_check__part1305;

architecture Other__sudoku_check__part1305_behav of Other__sudoku_check__part1305 is
begin
    n18859 <= ( lo4674 );
end Other__sudoku_check__part1305_behav;
