--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part43 is 
  Port (
    lo40: in std_logic;
    n341: inout std_logic
  );
end Cookbook__approx_fp_div__part43;

architecture Cookbook__approx_fp_div__part43_behav of Cookbook__approx_fp_div__part43 is
begin
    n341 <= ( lo40 );
end Cookbook__approx_fp_div__part43_behav;
