--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1352 is 
  Port (
    lo4721: in std_logic;
    n19094: inout std_logic
  );
end Other__sudoku_check__part1352;

architecture Other__sudoku_check__part1352_behav of Other__sudoku_check__part1352 is
begin
    n19094 <= ( lo4721 );
end Other__sudoku_check__part1352_behav;
