--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1635 is 
  Port (
    lo3712: in std_logic;
    n23136: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1635;

architecture Other__ucsb_152_tap_fir__part1635_behav of Other__ucsb_152_tap_fir__part1635 is
begin
    n23136 <= ( lo3712 );
end Other__ucsb_152_tap_fir__part1635_behav;
