--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part481 is 
  Port (
    lo4032: in std_logic;
    n20420: inout std_logic
  );
end IWLS2005__des_perf__part481;

architecture IWLS2005__des_perf__part481_behav of IWLS2005__des_perf__part481 is
begin
    n20420 <= ( lo4032 );
end IWLS2005__des_perf__part481_behav;
