--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part17 is 
  Port (
    pi23: in std_logic;
    n924176: inout std_logic
  );
end IWLS2005__leon3__part17;

architecture IWLS2005__leon3__part17_behav of IWLS2005__leon3__part17 is
begin
    n924176 <= ( pi23 );
end IWLS2005__leon3__part17_behav;
