--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part142 is 
  Port (
    lo01371: in std_logic;
    po2791,po2887,po2983,po5046,po5094,po5142,n21171: inout std_logic
  );
end Other__ray__part142;

architecture Other__ray__part142_behav of Other__ray__part142 is
begin
    po2791 <= ( lo01371 );
    po2887 <= ( lo01371 );
    po2983 <= ( lo01371 );
    po5046 <= ( lo01371 );
    po5094 <= ( lo01371 );
    po5142 <= ( lo01371 );
    n21171 <= ( lo01371 );
end Other__ray__part142_behav;
