--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1063 is 
  Port (
    lo1132: in std_logic;
    n5959: inout std_logic
  );
end Cookbook__fec_check__part1063;

architecture Cookbook__fec_check__part1063_behav of Cookbook__fec_check__part1063 is
begin
    n5959 <= ( lo1132 );
end Cookbook__fec_check__part1063_behav;
