--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part853 is 
  Port (
    lo06612: in std_logic;
    n49396_1: inout std_logic
  );
end Other__ray__part853;

architecture Other__ray__part853_behav of Other__ray__part853 is
begin
    n49396_1 <= ( lo06612 );
end Other__ray__part853_behav;
