--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part647 is 
  Port (
    lo0716: in std_logic;
    n3879: inout std_logic
  );
end Cookbook__fec_check__part647;

architecture Cookbook__fec_check__part647_behav of Cookbook__fec_check__part647 is
begin
    n3879 <= ( lo0716 );
end Cookbook__fec_check__part647_behav;
