--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part176 is 
  Port (
    lo0245: in std_logic;
    n1524: inout std_logic
  );
end Cookbook__fec_check__part176;

architecture Cookbook__fec_check__part176_behav of Cookbook__fec_check__part176 is
begin
    n1524 <= ( lo0245 );
end Cookbook__fec_check__part176_behav;
