--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part4 is 
  Port (
    pi006: in std_logic;
    n5729_1: inout std_logic
  );
end IWLS2005__mem_ctrl__part4;

architecture IWLS2005__mem_ctrl__part4_behav of IWLS2005__mem_ctrl__part4 is
begin
    n5729_1 <= ( pi006 );
end IWLS2005__mem_ctrl__part4_behav;
