--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part18 is 
  Port (
    lo00192: in std_logic;
    po028: inout std_logic
  );
end IWLS2005__ethernet__part18;

architecture IWLS2005__ethernet__part18_behav of IWLS2005__ethernet__part18 is
begin
    po028 <= ( lo00192 );
end IWLS2005__ethernet__part18_behav;
