--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part107 is 
  Port (
    lo0680: in std_logic;
    po013: inout std_logic
  );
end IWLS2005__mem_ctrl__part107;

architecture IWLS2005__mem_ctrl__part107_behav of IWLS2005__mem_ctrl__part107 is
begin
    po013 <= ( lo0680 );
end IWLS2005__mem_ctrl__part107_behav;
