--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part33 is 
  Port (
    lo32: in std_logic;
    po32: inout std_logic
  );
end Other__idxlat01n_m12__part33;

architecture Other__idxlat01n_m12__part33_behav of Other__idxlat01n_m12__part33 is
begin
    po32 <= ( lo32 );
end Other__idxlat01n_m12__part33_behav;
