--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part41 is 
  Port (
    lo0097: in std_logic;
    n1589: inout std_logic
  );
end Cookbook__ucrypt__part41;

architecture Cookbook__ucrypt__part41_behav of Cookbook__ucrypt__part41 is
begin
    n1589 <= ( lo0097 );
end Cookbook__ucrypt__part41_behav;
