--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1049 is 
  Port (
    lo10795: in std_logic;
    n72416_1: inout std_logic
  );
end Other__ray__part1049;

architecture Other__ray__part1049_behav of Other__ray__part1049 is
begin
    n72416_1 <= ( lo10795 );
end Other__ray__part1049_behav;
