--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part126 is 
  Port (
    lo0461: in std_logic;
    n4705: inout std_logic
  );
end Other__fp_operators__part126;

architecture Other__fp_operators__part126_behav of Other__fp_operators__part126 is
begin
    n4705 <= ( lo0461 );
end Other__fp_operators__part126_behav;
