--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part192 is 
  Port (
    pi0642: in std_logic;
    n44916: inout std_logic
  );
end Other__radar__part192;

architecture Other__radar__part192_behav of Other__radar__part192 is
begin
    n44916 <= ( pi0642 );
end Other__radar__part192_behav;
