--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part101 is 
  Port (
    lo0721: in std_logic;
    n3879: inout std_logic
  );
end ISCAS__s38417__part101;

architecture ISCAS__s38417__part101_behav of ISCAS__s38417__part101 is
begin
    n3879 <= ( lo0721 );
end ISCAS__s38417__part101_behav;
