--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part58 is 
  Port (
    lo0373: in std_logic;
    n2139: inout std_logic
  );
end ISCAS__s38417__part58;

architecture ISCAS__s38417__part58_behav of ISCAS__s38417__part58 is
begin
    n2139 <= ( lo0373 );
end ISCAS__s38417__part58_behav;
