--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part280 is 
  Port (
    lo0943: in std_logic;
    n5974: inout std_logic
  );
end Cookbook__ucrypt__part280;

architecture Cookbook__ucrypt__part280_behav of Cookbook__ucrypt__part280 is
begin
    n5974 <= ( lo0943 );
end Cookbook__ucrypt__part280_behav;
