--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part46 is 
  Port (
    lo213: in std_logic;
    po37: inout std_logic
  );
end Cookbook__gearbox_67_40__part46;

architecture Cookbook__gearbox_67_40__part46_behav of Cookbook__gearbox_67_40__part46 is
begin
    po37 <= ( lo213 );
end Cookbook__gearbox_67_40__part46_behav;
