--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part129 is 
  Port (
    lo0009: in std_logic;
    po09: inout std_logic
  );
end Other__desperf__part129;

architecture Other__desperf__part129_behav of Other__desperf__part129 is
begin
    po09 <= ( lo0009 );
end Other__desperf__part129_behav;
