--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part821 is 
  Port (
    lo4190: in std_logic;
    n15419: inout std_logic
  );
end Other__sudoku_check__part821;

architecture Other__sudoku_check__part821_behav of Other__sudoku_check__part821 is
begin
    n15419 <= ( lo4190 );
end Other__sudoku_check__part821_behav;
