--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part589 is 
  Port (
    lo06070: in std_logic;
    po1606,po1642: inout std_logic
  );
end Other__ray__part589;

architecture Other__ray__part589_behav of Other__ray__part589 is
begin
    po1606 <= ( lo06070 );
    po1642 <= ( lo06070 );
end Other__ray__part589_behav;
