--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part14 is 
  Port (
    lo000: in std_logic;
    po237: inout std_logic
  );
end Cookbook__lc_mult_signed__part14;

architecture Cookbook__lc_mult_signed__part14_behav of Cookbook__lc_mult_signed__part14 is
begin
    po237 <= ( lo000 );
end Cookbook__lc_mult_signed__part14_behav;
