--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part681 is 
  Port (
    lo5203: in std_logic;
    n25029: inout std_logic
  );
end Other__carpat__part681;

architecture Other__carpat__part681_behav of Other__carpat__part681 is
begin
    n25029 <= ( lo5203 );
end Other__carpat__part681_behav;
