--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part136 is 
  Port (
    lo0893: in std_logic;
    n4389: inout std_logic
  );
end IWLS93__s38417__part136;

architecture IWLS93__s38417__part136_behav of IWLS93__s38417__part136 is
begin
    n4389 <= ( lo0893 );
end IWLS93__s38417__part136_behav;
