--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1097 is 
  Port (
    lo2551: in std_logic;
    n17316: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1097;

architecture Other__ucsb_152_tap_fir__part1097_behav of Other__ucsb_152_tap_fir__part1097 is
begin
    n17316 <= ( lo2551 );
end Other__ucsb_152_tap_fir__part1097_behav;
