--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part109 is 
  Port (
    lo0687: in std_logic;
    po024: inout std_logic
  );
end IWLS2005__mem_ctrl__part109;

architecture IWLS2005__mem_ctrl__part109_behav of IWLS2005__mem_ctrl__part109 is
begin
    po024 <= ( lo0687 );
end IWLS2005__mem_ctrl__part109_behav;
