--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1789 is 
  Port (
    lo8884: in std_logic;
    po320: inout std_logic
  );
end Other__carpat__part1789;

architecture Other__carpat__part1789_behav of Other__carpat__part1789 is
begin
    po320 <= ( lo8884 );
end Other__carpat__part1789_behav;
