--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part156 is 
  Port (
    lo01387: in std_logic;
    po2721,po2817,po2913,po5750,po5798,po5846,n21286: inout std_logic
  );
end Other__ray__part156;

architecture Other__ray__part156_behav of Other__ray__part156 is
begin
    po2721 <= ( lo01387 );
    po2817 <= ( lo01387 );
    po2913 <= ( lo01387 );
    po5750 <= ( lo01387 );
    po5798 <= ( lo01387 );
    po5846 <= ( lo01387 );
    n21286 <= ( lo01387 );
end Other__ray__part156_behav;
