--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2194 is 
  Port (
    lo7358: in std_logic;
    n36545_1: inout std_logic
  );
end IWLS2005__des_perf__part2194;

architecture IWLS2005__des_perf__part2194_behav of IWLS2005__des_perf__part2194 is
begin
    n36545_1 <= ( lo7358 );
end IWLS2005__des_perf__part2194_behav;
