--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part163 is 
  Port (
    lo0568: in std_logic;
    n3949: inout std_logic
  );
end Cookbook__ucrypt__part163;

architecture Cookbook__ucrypt__part163_behav of Cookbook__ucrypt__part163 is
begin
    n3949 <= ( lo0568 );
end Cookbook__ucrypt__part163_behav;
