--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ac97_ctrl__part50 is 
  Port (
    lo1868: in std_logic;
    po08: inout std_logic
  );
end IWLS2005__ac97_ctrl__part50;

architecture IWLS2005__ac97_ctrl__part50_behav of IWLS2005__ac97_ctrl__part50 is
begin
    po08 <= ( lo1868 );
end IWLS2005__ac97_ctrl__part50_behav;
