--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part220 is 
  Port (
    lo1465: in std_logic;
    n40906: inout std_logic
  );
end Other__radar__part220;

architecture Other__radar__part220_behav of Other__radar__part220 is
begin
    n40906 <= ( lo1465 );
end Other__radar__part220_behav;
