--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1585 is 
  Port (
    lo3584: in std_logic;
    n22506: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1585;

architecture Other__ucsb_152_tap_fir__part1585_behav of Other__ucsb_152_tap_fir__part1585 is
begin
    n22506 <= ( lo3584 );
end Other__ucsb_152_tap_fir__part1585_behav;
