--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part75 is 
  Port (
    lo309: in std_logic;
    po034: inout std_logic
  );
end IWLS2005__aes_core__part75;

architecture IWLS2005__aes_core__part75_behav of IWLS2005__aes_core__part75 is
begin
    po034 <= ( lo309 );
end IWLS2005__aes_core__part75_behav;
