--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part912 is 
  Port (
    lo4281: in std_logic;
    n16894: inout std_logic
  );
end Other__sudoku_check__part912;

architecture Other__sudoku_check__part912_behav of Other__sudoku_check__part912 is
begin
    n16894 <= ( lo4281 );
end Other__sudoku_check__part912_behav;
