--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part10 is 
  Port (
    pi10,pi26,pi42: in std_logic;
    po10,po26: inout std_logic
  );
end Cookbook__compress_32__part10;

architecture Cookbook__compress_32__part10_behav of Cookbook__compress_32__part10 is
signal n85,n117,n133,n149,n165: std_logic;
begin
    n85 <= ( not pi10 and pi26 )
      or ( pi10 and not pi26 );
    po10 <= ( not n85 and pi42 )
      or ( n85 and not pi42 );
    n117 <= ( pi10 and pi42 );
    n133 <= ( pi10 and pi26 );
    n149 <= not (( not n133 and not n117 ));
    n165 <= ( pi26 and pi42 );
    po26 <= not (( not n149 and not n165 ));
end Cookbook__compress_32__part10_behav;
