--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part16 is 
  Port (
    lo0007: in std_logic;
    n1294: inout std_logic
  );
end Cookbook__ucrypt__part16;

architecture Cookbook__ucrypt__part16_behav of Cookbook__ucrypt__part16 is
begin
    n1294 <= ( lo0007 );
end Cookbook__ucrypt__part16_behav;
