--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part390 is 
  Port (
    lo2216: in std_logic;
    n11555: inout std_logic
  );
end IWLS2005__des_perf__part390;

architecture IWLS2005__des_perf__part390_behav of IWLS2005__des_perf__part390 is
begin
    n11555 <= ( lo2216 );
end IWLS2005__des_perf__part390_behav;
