--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1158 is 
  Port (
    lo4527: in std_logic;
    n18124: inout std_logic
  );
end Other__sudoku_check__part1158;

architecture Other__sudoku_check__part1158_behav of Other__sudoku_check__part1158 is
begin
    n18124 <= ( lo4527 );
end Other__sudoku_check__part1158_behav;
