--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2207 is 
  Port (
    lo2276: in std_logic;
    n11679: inout std_logic
  );
end Cookbook__fec_check__part2207;

architecture Cookbook__fec_check__part2207_behav of Cookbook__fec_check__part2207 is
begin
    n11679 <= ( lo2276 );
end Cookbook__fec_check__part2207_behav;
