--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part205 is 
  Port (
    lo2854: in std_logic;
    n6969: inout std_logic
  );
end Other__sudoku_check__part205;

architecture Other__sudoku_check__part205_behav of Other__sudoku_check__part205 is
begin
    n6969 <= ( lo2854 );
end Other__sudoku_check__part205_behav;
