--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2929 is 
  Port (
    lo8242: in std_logic;
    n41390: inout std_logic
  );
end IWLS2005__des_perf__part2929;

architecture IWLS2005__des_perf__part2929_behav of IWLS2005__des_perf__part2929 is
begin
    n41390 <= ( lo8242 );
end IWLS2005__des_perf__part2929_behav;
