--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1858 is 
  Port (
    lo9131: in std_logic;
    po495: inout std_logic
  );
end Other__carpat__part1858;

architecture Other__carpat__part1858_behav of Other__carpat__part1858 is
begin
    po495 <= ( lo9131 );
end Other__carpat__part1858_behav;
