--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part9 is 
  Port (
    lo21: in std_logic;
    n198: inout std_logic
  );
end Cookbook__mlab_dcfifo__part9;

architecture Cookbook__mlab_dcfifo__part9_behav of Cookbook__mlab_dcfifo__part9 is
begin
    n198 <= ( lo21 );
end Cookbook__mlab_dcfifo__part9_behav;
