--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part86 is 
  Port (
    lo212: in std_logic;
    po126: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part86;

architecture Cookbook__soft_ecc_ram_64bit__part86_behav of Cookbook__soft_ecc_ram_64bit__part86 is
begin
    po126 <= ( lo212 );
end Cookbook__soft_ecc_ram_64bit__part86_behav;
