--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1714 is 
  Port (
    lo3864: in std_logic;
    n23901: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1714;

architecture Other__ucsb_152_tap_fir__part1714_behav of Other__ucsb_152_tap_fir__part1714 is
begin
    n23901 <= ( lo3864 );
end Other__ucsb_152_tap_fir__part1714_behav;
