--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s6669__part7 is 
  Port (
    pi57: in std_logic;
    n792: inout std_logic
  );
end ISCAS__s6669__part7;

architecture ISCAS__s6669__part7_behav of ISCAS__s6669__part7 is
begin
    n792 <= ( pi57 );
end ISCAS__s6669__part7_behav;
