--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part63 is 
  Port (
    lo0360: in std_logic;
    n2074: inout std_logic
  );
end LGSynth91__s38417__part63;

architecture LGSynth91__s38417__part63_behav of LGSynth91__s38417__part63 is
begin
    n2074 <= ( lo0360 );
end LGSynth91__s38417__part63_behav;
