--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part27 is 
  Port (
    lo24: in std_logic;
    n276: inout std_logic
  );
end Cookbook__approx_fp_div__part27;

architecture Cookbook__approx_fp_div__part27_behav of Cookbook__approx_fp_div__part27 is
begin
    n276 <= ( lo24 );
end Cookbook__approx_fp_div__part27_behav;
