--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part424 is 
  Port (
    lo0522: in std_logic;
    n7039: inout std_logic
  );
end Other__carpat__part424;

architecture Other__carpat__part424_behav of Other__carpat__part424 is
begin
    n7039 <= ( lo0522 );
end Other__carpat__part424_behav;
