--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part410 is 
  Port (
    lo2262: in std_logic;
    n11815: inout std_logic
  );
end IWLS2005__des_perf__part410;

architecture IWLS2005__des_perf__part410_behav of IWLS2005__des_perf__part410 is
begin
    n11815 <= ( lo2262 );
end IWLS2005__des_perf__part410_behav;
