--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1102 is 
  Port (
    lo1171: in std_logic;
    n6154: inout std_logic
  );
end Cookbook__fec_check__part1102;

architecture Cookbook__fec_check__part1102_behav of Cookbook__fec_check__part1102 is
begin
    n6154 <= ( lo1171 );
end Cookbook__fec_check__part1102_behav;
