--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1764 is 
  Port (
    lo1833: in std_logic;
    n9464: inout std_logic
  );
end Cookbook__fec_check__part1764;

architecture Cookbook__fec_check__part1764_behav of Cookbook__fec_check__part1764 is
begin
    n9464 <= ( lo1833 );
end Cookbook__fec_check__part1764_behav;
