--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part359 is 
  Port (
    pi1708: in std_logic;
    n48259_1: inout std_logic
  );
end Other__carpat__part359;

architecture Other__carpat__part359_behav of Other__carpat__part359 is
begin
    n48259_1 <= ( pi1708 );
end Other__carpat__part359_behav;
