--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1325 is 
  Port (
    lo1394: in std_logic;
    n7269: inout std_logic
  );
end Cookbook__fec_check__part1325;

architecture Cookbook__fec_check__part1325_behav of Cookbook__fec_check__part1325 is
begin
    n7269 <= ( lo1394 );
end Cookbook__fec_check__part1325_behav;
