--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1185 is 
  Port (
    lo5358: in std_logic;
    n26480: inout std_logic
  );
end IWLS2005__des_perf__part1185;

architecture IWLS2005__des_perf__part1185_behav of IWLS2005__des_perf__part1185 is
begin
    n26480 <= ( lo5358 );
end IWLS2005__des_perf__part1185_behav;
