--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part33 is 
  Port (
    lo75: in std_logic;
    po21: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part33;

architecture Cookbook__soft_ecc_ram_16bit__part33_behav of Cookbook__soft_ecc_ram_16bit__part33 is
begin
    po21 <= ( lo75 );
end Cookbook__soft_ecc_ram_16bit__part33_behav;
