--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1554 is 
  Port (
    lo1623: in std_logic;
    n8414: inout std_logic
  );
end Cookbook__fec_check__part1554;

architecture Cookbook__fec_check__part1554_behav of Cookbook__fec_check__part1554 is
begin
    n8414 <= ( lo1623 );
end Cookbook__fec_check__part1554_behav;
