--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1816 is 
  Port (
    lo6719: in std_logic;
    n33755_1: inout std_logic
  );
end IWLS2005__des_perf__part1816;

architecture IWLS2005__des_perf__part1816_behav of IWLS2005__des_perf__part1816 is
begin
    n33755_1 <= ( lo6719 );
end IWLS2005__des_perf__part1816_behav;
