--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1994 is 
  Port (
    lo2063: in std_logic;
    n10614: inout std_logic
  );
end Cookbook__fec_check__part1994;

architecture Cookbook__fec_check__part1994_behav of Cookbook__fec_check__part1994 is
begin
    n10614 <= ( lo2063 );
end Cookbook__fec_check__part1994_behav;
