--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1988 is 
  Port (
    lo4461: in std_logic;
    n26816: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1988;

architecture Other__ucsb_152_tap_fir__part1988_behav of Other__ucsb_152_tap_fir__part1988 is
begin
    n26816 <= ( lo4461 );
end Other__ucsb_152_tap_fir__part1988_behav;
