--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part49 is 
  Port (
    lo0526: in std_logic;
    po136: inout std_logic
  );
end IWLS2005__pci_bridge32__part49;

architecture IWLS2005__pci_bridge32__part49_behav of IWLS2005__pci_bridge32__part49 is
begin
    po136 <= ( lo0526 );
end IWLS2005__pci_bridge32__part49_behav;
