--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part31 is 
  Port (
    lo094: in std_logic;
    po042: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part31;

architecture Cookbook__soft_ecc_ram_64bit__part31_behav of Cookbook__soft_ecc_ram_64bit__part31 is
begin
    po042 <= ( lo094 );
end Cookbook__soft_ecc_ram_64bit__part31_behav;
