--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1877 is 
  Port (
    lo4233: in std_logic;
    n25746: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1877;

architecture Other__ucsb_152_tap_fir__part1877_behav of Other__ucsb_152_tap_fir__part1877 is
begin
    n25746 <= ( lo4233 );
end Other__ucsb_152_tap_fir__part1877_behav;
