--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part634 is 
  Port (
    lo4280: in std_logic;
    n21555: inout std_logic
  );
end IWLS2005__des_perf__part634;

architecture IWLS2005__des_perf__part634_behav of IWLS2005__des_perf__part634 is
begin
    n21555 <= ( lo4280 );
end IWLS2005__des_perf__part634_behav;
