--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part575 is 
  Port (
    lo0644: in std_logic;
    n3519: inout std_logic
  );
end Cookbook__fec_check__part575;

architecture Cookbook__fec_check__part575_behav of Cookbook__fec_check__part575 is
begin
    n3519 <= ( lo0644 );
end Cookbook__fec_check__part575_behav;
