--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part355 is 
  Port (
    lo3004: in std_logic;
    n8469: inout std_logic
  );
end Other__sudoku_check__part355;

architecture Other__sudoku_check__part355_behav of Other__sudoku_check__part355 is
begin
    n8469 <= ( lo3004 );
end Other__sudoku_check__part355_behav;
