--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2550 is 
  Port (
    lo5622: in std_logic;
    n32696_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2550;

architecture Other__ucsb_152_tap_fir__part2550_behav of Other__ucsb_152_tap_fir__part2550 is
begin
    n32696_1 <= ( lo5622 );
end Other__ucsb_152_tap_fir__part2550_behav;
