--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part8 is 
  Port (
    lo07: in std_logic;
    po07: inout std_logic
  );
end Other__idxlat00n_m12__part8;

architecture Other__idxlat00n_m12__part8_behav of Other__idxlat00n_m12__part8 is
begin
    po07 <= ( lo07 );
end Other__idxlat00n_m12__part8_behav;
