--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part21 is 
  Port (
    lo0090: in std_logic;
    n749: inout std_logic
  );
end Cookbook__fec_check__part21;

architecture Cookbook__fec_check__part21_behav of Cookbook__fec_check__part21 is
begin
    n749 <= ( lo0090 );
end Cookbook__fec_check__part21_behav;
