--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part179 is 
  Port (
    lo2828: in std_logic;
    n6709: inout std_logic
  );
end Other__sudoku_check__part179;

architecture Other__sudoku_check__part179_behav of Other__sudoku_check__part179 is
begin
    n6709 <= ( lo2828 );
end Other__sudoku_check__part179_behav;
