--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1829 is 
  Port (
    lo1898: in std_logic;
    n9789: inout std_logic
  );
end Cookbook__fec_check__part1829;

architecture Cookbook__fec_check__part1829_behav of Cookbook__fec_check__part1829 is
begin
    n9789 <= ( lo1898 );
end Cookbook__fec_check__part1829_behav;
