--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1403 is 
  Port (
    lo7853: in std_logic;
    n44144_1: inout std_logic
  );
end Other__carpat__part1403;

architecture Other__carpat__part1403_behav of Other__carpat__part1403 is
begin
    n44144_1 <= ( lo7853 );
end Other__carpat__part1403_behav;
