--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx_crc__part1 is 
  Port (
    pi65: in std_logic;
    n145: inout std_logic
  );
end Cookbook__lane_rx_crc__part1;

architecture Cookbook__lane_rx_crc__part1_behav of Cookbook__lane_rx_crc__part1 is
begin
    n145 <= ( pi65 );
end Cookbook__lane_rx_crc__part1_behav;
