--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part28 is 
  Port (
    lo27: in std_logic;
    po21: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part28;

architecture Cookbook__x4_decoder_8b10b__part28_behav of Cookbook__x4_decoder_8b10b__part28 is
begin
    po21 <= ( lo27 );
end Cookbook__x4_decoder_8b10b__part28_behav;
