--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part824 is 
  Port (
    lo4620: in std_logic;
    n23070: inout std_logic
  );
end IWLS2005__des_perf__part824;

architecture IWLS2005__des_perf__part824_behav of IWLS2005__des_perf__part824 is
begin
    n23070 <= ( lo4620 );
end IWLS2005__des_perf__part824_behav;
