--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part433 is 
  Port (
    lo3082: in std_logic;
    n9249: inout std_logic
  );
end Other__sudoku_check__part433;

architecture Other__sudoku_check__part433_behav of Other__sudoku_check__part433 is
begin
    n9249 <= ( lo3082 );
end Other__sudoku_check__part433_behav;
