--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part85 is 
  Port (
    lo0681: in std_logic;
    n3679: inout std_logic
  );
end ISCAS__s38417__part85;

architecture ISCAS__s38417__part85_behav of ISCAS__s38417__part85 is
begin
    n3679 <= ( lo0681 );
end ISCAS__s38417__part85_behav;
