--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2386 is 
  Port (
    lo7595: in std_logic;
    n38180_1: inout std_logic
  );
end IWLS2005__des_perf__part2386;

architecture IWLS2005__des_perf__part2386_behav of IWLS2005__des_perf__part2386 is
begin
    n38180_1 <= ( lo7595 );
end IWLS2005__des_perf__part2386_behav;
