--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part950 is 
  Port (
    lo4870: in std_logic;
    n23985: inout std_logic
  );
end IWLS2005__des_perf__part950;

architecture IWLS2005__des_perf__part950_behav of IWLS2005__des_perf__part950 is
begin
    n23985 <= ( lo4870 );
end IWLS2005__des_perf__part950_behav;
