--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1198 is 
  Port (
    lo4567: in std_logic;
    n18324: inout std_logic
  );
end Other__sudoku_check__part1198;

architecture Other__sudoku_check__part1198_behav of Other__sudoku_check__part1198 is
begin
    n18324 <= ( lo4567 );
end Other__sudoku_check__part1198_behav;
