--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1407 is 
  Port (
    lo1476: in std_logic;
    n7679: inout std_logic
  );
end Cookbook__fec_check__part1407;

architecture Cookbook__fec_check__part1407_behav of Cookbook__fec_check__part1407 is
begin
    n7679 <= ( lo1476 );
end Cookbook__fec_check__part1407_behav;
