--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__system_timer__part1 is 
  Port (
    lo53: in std_logic;
    po47: inout std_logic
  );
end Cookbook__system_timer__part1;

architecture Cookbook__system_timer__part1_behav of Cookbook__system_timer__part1 is
begin
    po47 <= ( lo53 );
end Cookbook__system_timer__part1_behav;
