--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1990 is 
  Port (
    lo2059: in std_logic;
    n10594: inout std_logic
  );
end Cookbook__fec_check__part1990;

architecture Cookbook__fec_check__part1990_behav of Cookbook__fec_check__part1990 is
begin
    n10594 <= ( lo2059 );
end Cookbook__fec_check__part1990_behav;
