--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part32 is 
  Port (
    lo037: in std_logic;
    n887: inout std_logic
  );
end Cookbook__gearbox_67_40__part32;

architecture Cookbook__gearbox_67_40__part32_behav of Cookbook__gearbox_67_40__part32 is
begin
    n887 <= ( lo037 );
end Cookbook__gearbox_67_40__part32_behav;
