--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part4 is 
  Port (
    lo042: in std_logic;
    po30: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part4;

architecture Cookbook__soft_ecc_ram_32bit__part4_behav of Cookbook__soft_ecc_ram_32bit__part4 is
begin
    po30 <= ( lo042 );
end Cookbook__soft_ecc_ram_32bit__part4_behav;
