--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part725 is 
  Port (
    lo5451: in std_logic;
    n25744: inout std_logic
  );
end Other__carpat__part725;

architecture Other__carpat__part725_behav of Other__carpat__part725 is
begin
    n25744 <= ( lo5451 );
end Other__carpat__part725_behav;
