--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part452 is 
  Port (
    lo05924: in std_logic;
    po1390,po1455,po1721,po1790: inout std_logic
  );
end Other__ray__part452;

architecture Other__ray__part452_behav of Other__ray__part452 is
begin
    po1390 <= ( lo05924 );
    po1455 <= ( lo05924 );
    po1721 <= ( lo05924 );
    po1790 <= ( lo05924 );
end Other__ray__part452_behav;
