--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part83 is 
  Port (
    pi0884: in std_logic;
    n31149: inout std_logic
  );
end Other__carpat__part83;

architecture Other__carpat__part83_behav of Other__carpat__part83 is
begin
    n31149 <= ( pi0884 );
end Other__carpat__part83_behav;
