--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part6 is 
  Port (
    lo23: in std_logic;
    n188: inout std_logic
  );
end Cookbook__temp_sense_s5__part6;

architecture Cookbook__temp_sense_s5__part6_behav of Cookbook__temp_sense_s5__part6 is
begin
    n188 <= ( lo23 );
end Cookbook__temp_sense_s5__part6_behav;
