--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1481 is 
  Port (
    lo3395: in std_logic;
    n21481: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1481;

architecture Other__ucsb_152_tap_fir__part1481_behav of Other__ucsb_152_tap_fir__part1481 is
begin
    n21481 <= ( lo3395 );
end Other__ucsb_152_tap_fir__part1481_behav;
