--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1725 is 
  Port (
    lo6508: in std_logic;
    n32680_1: inout std_logic
  );
end IWLS2005__des_perf__part1725;

architecture IWLS2005__des_perf__part1725_behav of IWLS2005__des_perf__part1725 is
begin
    n32680_1 <= ( lo6508 );
end IWLS2005__des_perf__part1725_behav;
