--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part59 is 
  Port (
    lo290: in std_logic;
    po124: inout std_logic
  );
end IWLS2005__aes_core__part59;

architecture IWLS2005__aes_core__part59_behav of IWLS2005__aes_core__part59 is
begin
    po124 <= ( lo290 );
end IWLS2005__aes_core__part59_behav;
