--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1784 is 
  Port (
    lo1853: in std_logic;
    n9564: inout std_logic
  );
end Cookbook__fec_check__part1784;

architecture Cookbook__fec_check__part1784_behav of Cookbook__fec_check__part1784 is
begin
    n9564 <= ( lo1853 );
end Cookbook__fec_check__part1784_behav;
