--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part179 is 
  Port (
    lo165: in std_logic;
    po101: inout std_logic
  );
end Cookbook__lc_mult_signed__part179;

architecture Cookbook__lc_mult_signed__part179_behav of Cookbook__lc_mult_signed__part179 is
begin
    po101 <= ( lo165 );
end Cookbook__lc_mult_signed__part179_behav;
