--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3305 is 
  Port (
    lo8674: in std_logic;
    n43605_1: inout std_logic
  );
end IWLS2005__des_perf__part3305;

architecture IWLS2005__des_perf__part3305_behav of IWLS2005__des_perf__part3305 is
begin
    n43605_1 <= ( lo8674 );
end IWLS2005__des_perf__part3305_behav;
