--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part166 is 
  Port (
    lo0368: in std_logic;
    n6291: inout std_logic
  );
end Other__ucsb_152_tap_fir__part166;

architecture Other__ucsb_152_tap_fir__part166_behav of Other__ucsb_152_tap_fir__part166 is
begin
    n6291 <= ( lo0368 );
end Other__ucsb_152_tap_fir__part166_behav;
