--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part426 is 
  Port (
    lo2288: in std_logic;
    n11130: inout std_logic
  );
end IWLS2005__des_perf__part426;

architecture IWLS2005__des_perf__part426_behav of IWLS2005__des_perf__part426 is
begin
    n11130 <= ( lo2288 );
end IWLS2005__des_perf__part426_behav;
