--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part588 is 
  Port (
    lo06069: in std_logic;
    po1605,po1641: inout std_logic
  );
end Other__ray__part588;

architecture Other__ray__part588_behav of Other__ray__part588 is
begin
    po1605 <= ( lo06069 );
    po1641 <= ( lo06069 );
end Other__ray__part588_behav;
