--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part429 is 
  Port (
    lo05901: in std_logic;
    po1318,po1367,po1625,po1687: inout std_logic
  );
end Other__ray__part429;

architecture Other__ray__part429_behav of Other__ray__part429 is
begin
    po1318 <= ( lo05901 );
    po1367 <= ( lo05901 );
    po1625 <= ( lo05901 );
    po1687 <= ( lo05901 );
end Other__ray__part429_behav;
