--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1499 is 
  Port (
    lo8130: in std_logic;
    n44699_1: inout std_logic
  );
end Other__carpat__part1499;

architecture Other__carpat__part1499_behav of Other__carpat__part1499 is
begin
    n44699_1 <= ( lo8130 );
end Other__carpat__part1499_behav;
