--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part16 is 
  Port (
    lo05: in std_logic;
    po18: inout std_logic
  );
end Cookbook__font_rom__part16;

architecture Cookbook__font_rom__part16_behav of Cookbook__font_rom__part16 is
begin
    po18 <= ( lo05 );
end Cookbook__font_rom__part16_behav;
