--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part43 is 
  Port (
    lo42: in std_logic;
    po42: inout std_logic
  );
end Other__idxlat02n_m12__part43;

architecture Other__idxlat02n_m12__part43_behav of Other__idxlat02n_m12__part43 is
begin
    po42 <= ( lo42 );
end Other__idxlat02n_m12__part43_behav;
