--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1076 is 
  Port (
    lo11010: in std_logic;
    n73526_1: inout std_logic
  );
end Other__ray__part1076;

architecture Other__ray__part1076_behav of Other__ray__part1076 is
begin
    n73526_1 <= ( lo11010 );
end Other__ray__part1076_behav;
