--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part231 is 
  Port (
    pi1345: in std_logic;
    n33104_1: inout std_logic
  );
end Other__carpat__part231;

architecture Other__carpat__part231_behav of Other__carpat__part231 is
begin
    n33104_1 <= ( pi1345 );
end Other__carpat__part231_behav;
