--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1340 is 
  Port (
    lo4709: in std_logic;
    n19034: inout std_logic
  );
end Other__sudoku_check__part1340;

architecture Other__sudoku_check__part1340_behav of Other__sudoku_check__part1340 is
begin
    n19034 <= ( lo4709 );
end Other__sudoku_check__part1340_behav;
