--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part97 is 
  Port (
    lo10515: in std_logic;
    n52583_1: inout std_logic
  );
end IWLS2005__ethernet__part97;

architecture IWLS2005__ethernet__part97_behav of IWLS2005__ethernet__part97 is
begin
    n52583_1 <= ( lo10515 );
end IWLS2005__ethernet__part97_behav;
