--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part459 is 
  Port (
    lo1682: in std_logic;
    n9669_1: inout std_logic
  );
end Cookbook__ucrypt__part459;

architecture Cookbook__ucrypt__part459_behav of Cookbook__ucrypt__part459 is
begin
    n9669_1 <= ( lo1682 );
end Cookbook__ucrypt__part459_behav;
