--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1792 is 
  Port (
    lo1861: in std_logic;
    n9604: inout std_logic
  );
end Cookbook__fec_check__part1792;

architecture Cookbook__fec_check__part1792_behav of Cookbook__fec_check__part1792 is
begin
    n9604 <= ( lo1861 );
end Cookbook__fec_check__part1792_behav;
