--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1015 is 
  Port (
    lo4982: in std_logic;
    n24850: inout std_logic
  );
end IWLS2005__des_perf__part1015;

architecture IWLS2005__des_perf__part1015_behav of IWLS2005__des_perf__part1015 is
begin
    n24850 <= ( lo4982 );
end IWLS2005__des_perf__part1015_behav;
