--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part506 is 
  Port (
    lo0575: in std_logic;
    n3174: inout std_logic
  );
end Cookbook__fec_check__part506;

architecture Cookbook__fec_check__part506_behav of Cookbook__fec_check__part506 is
begin
    n3174 <= ( lo0575 );
end Cookbook__fec_check__part506_behav;
