--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part66 is 
  Port (
    lo142: in std_logic;
    po36: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part66;

architecture Cookbook__soft_ecc_ram_32bit__part66_behav of Cookbook__soft_ecc_ram_32bit__part66 is
begin
    po36 <= ( lo142 );
end Cookbook__soft_ecc_ram_32bit__part66_behav;
