--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part193 is 
  Port (
    lo0632: in std_logic;
    n4419: inout std_logic
  );
end Cookbook__ucrypt__part193;

architecture Cookbook__ucrypt__part193_behav of Cookbook__ucrypt__part193 is
begin
    n4419 <= ( lo0632 );
end Cookbook__ucrypt__part193_behav;
