--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part46 is 
  Port (
    lo00921: in std_logic;
    po088: inout std_logic
  );
end IWLS2005__ethernet__part46;

architecture IWLS2005__ethernet__part46_behav of IWLS2005__ethernet__part46 is
begin
    po088 <= ( lo00921 );
end IWLS2005__ethernet__part46_behav;
