--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part44 is 
  Port (
    lo158: in std_logic;
    po22: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part44;

architecture Cookbook__ycbcr_to_rgb__part44_behav of Cookbook__ycbcr_to_rgb__part44 is
begin
    po22 <= ( lo158 );
end Cookbook__ycbcr_to_rgb__part44_behav;
