--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part985 is 
  Port (
    lo10682: in std_logic;
    n71521_1: inout std_logic
  );
end Other__ray__part985;

architecture Other__ray__part985_behav of Other__ray__part985 is
begin
    n71521_1 <= ( lo10682 );
end Other__ray__part985_behav;
