--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part90 is 
  Port (
    lo076: in std_logic;
    po190: inout std_logic
  );
end Cookbook__lc_mult_signed__part90;

architecture Cookbook__lc_mult_signed__part90_behav of Cookbook__lc_mult_signed__part90 is
begin
    po190 <= ( lo076 );
end Cookbook__lc_mult_signed__part90_behav;
