--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part111 is 
  Port (
    lo0326: in std_logic;
    n2889: inout std_logic
  );
end Cookbook__ucrypt__part111;

architecture Cookbook__ucrypt__part111_behav of Cookbook__ucrypt__part111 is
begin
    n2889 <= ( lo0326 );
end Cookbook__ucrypt__part111_behav;
