--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s967__part10 is 
  Port (
    lo15: in std_logic;
    po09: inout std_logic
  );
end ISCAS__s967__part10;

architecture ISCAS__s967__part10_behav of ISCAS__s967__part10 is
begin
    po09 <= ( lo15 );
end ISCAS__s967__part10_behav;
