--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part10 is 
  Port (
    pi10: in std_logic;
    n181: inout std_logic
  );
end Cookbook__approx_fp_div__part10;

architecture Cookbook__approx_fp_div__part10_behav of Cookbook__approx_fp_div__part10 is
begin
    n181 <= ( pi10 );
end Cookbook__approx_fp_div__part10_behav;
