--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1361 is 
  Port (
    lo7811: in std_logic;
    n43934: inout std_logic
  );
end Other__carpat__part1361;

architecture Other__carpat__part1361_behav of Other__carpat__part1361 is
begin
    n43934 <= ( lo7811 );
end Other__carpat__part1361_behav;
