--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part821 is 
  Port (
    lo0890: in std_logic;
    n4749: inout std_logic
  );
end Cookbook__fec_check__part821;

architecture Cookbook__fec_check__part821_behav of Cookbook__fec_check__part821 is
begin
    n4749 <= ( lo0890 );
end Cookbook__fec_check__part821_behav;
