--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part353 is 
  Port (
    lo1240: in std_logic;
    n7459_1: inout std_logic
  );
end Cookbook__ucrypt__part353;

architecture Cookbook__ucrypt__part353_behav of Cookbook__ucrypt__part353 is
begin
    n7459_1 <= ( lo1240 );
end Cookbook__ucrypt__part353_behav;
