--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part539 is 
  Port (
    lo3278: in std_logic;
    n15509: inout std_logic
  );
end Other__carpat__part539;

architecture Other__carpat__part539_behav of Other__carpat__part539 is
begin
    n15509 <= ( lo3278 );
end Other__carpat__part539_behav;
