--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3188 is 
  Port (
    lo8516: in std_logic;
    n42805_1: inout std_logic
  );
end IWLS2005__des_perf__part3188;

architecture IWLS2005__des_perf__part3188_behav of IWLS2005__des_perf__part3188 is
begin
    n42805_1 <= ( lo8516 );
end IWLS2005__des_perf__part3188_behav;
