--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part45 is 
  Port (
    lo0522: in std_logic;
    po141: inout std_logic
  );
end IWLS2005__pci_bridge32__part45;

architecture IWLS2005__pci_bridge32__part45_behav of IWLS2005__pci_bridge32__part45 is
begin
    po141 <= ( lo0522 );
end IWLS2005__pci_bridge32__part45_behav;
