--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part406 is 
  Port (
    lo0475: in std_logic;
    n2674: inout std_logic
  );
end Cookbook__fec_check__part406;

architecture Cookbook__fec_check__part406_behav of Cookbook__fec_check__part406 is
begin
    n2674 <= ( lo0475 );
end Cookbook__fec_check__part406_behav;
