--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part223 is 
  Port (
    lo327: in std_logic;
    n1147: inout std_logic
  );
end Other__fpu__part223;

architecture Other__fpu__part223_behav of Other__fpu__part223 is
begin
    n1147 <= ( lo327 );
end Other__fpu__part223_behav;
