--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part25 is 
  Port (
    lo0063: in std_logic;
    n7504_1: inout std_logic
  );
end IWLS93__s38417__part25;

architecture IWLS93__s38417__part25_behav of IWLS93__s38417__part25 is
begin
    n7504_1 <= ( not lo0063 );
end IWLS93__s38417__part25_behav;
