--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part134 is 
  Port (
    lo0013: in std_logic;
    po14: inout std_logic
  );
end IWLS2005__des_perf__part134;

architecture IWLS2005__des_perf__part134_behav of IWLS2005__des_perf__part134 is
begin
    po14 <= ( lo0013 );
end IWLS2005__des_perf__part134_behav;
