--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part98 is 
  Port (
    lo2681: in std_logic;
    n5899: inout std_logic
  );
end Other__sudoku_check__part98;

architecture Other__sudoku_check__part98_behav of Other__sudoku_check__part98 is
begin
    n5899 <= ( lo2681 );
end Other__sudoku_check__part98_behav;
