--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1735 is 
  Port (
    lo3928: in std_logic;
    n24156: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1735;

architecture Other__ucsb_152_tap_fir__part1735_behav of Other__ucsb_152_tap_fir__part1735 is
begin
    n24156 <= ( lo3928 );
end Other__ucsb_152_tap_fir__part1735_behav;
