--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part583 is 
  Port (
    lo2142: in std_logic;
    n11929_1: inout std_logic
  );
end Cookbook__ucrypt__part583;

architecture Cookbook__ucrypt__part583_behav of Cookbook__ucrypt__part583 is
begin
    n11929_1 <= ( lo2142 );
end Cookbook__ucrypt__part583_behav;
