--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part703 is 
  Port (
    lo4386: in std_logic;
    n22085: inout std_logic
  );
end IWLS2005__des_perf__part703;

architecture IWLS2005__des_perf__part703_behav of IWLS2005__des_perf__part703 is
begin
    n22085 <= ( lo4386 );
end IWLS2005__des_perf__part703_behav;
