--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part526 is 
  Port (
    lo1952: in std_logic;
    n10869_1: inout std_logic
  );
end Cookbook__ucrypt__part526;

architecture Cookbook__ucrypt__part526_behav of Cookbook__ucrypt__part526 is
begin
    n10869_1 <= ( lo1952 );
end Cookbook__ucrypt__part526_behav;
