--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part325 is 
  Port (
    lo2974: in std_logic;
    n8169: inout std_logic
  );
end Other__sudoku_check__part325;

architecture Other__sudoku_check__part325_behav of Other__sudoku_check__part325 is
begin
    n8169 <= ( lo2974 );
end Other__sudoku_check__part325_behav;
