--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part665 is 
  Port (
    lo5186: in std_logic;
    n24744: inout std_logic
  );
end Other__carpat__part665;

architecture Other__carpat__part665_behav of Other__carpat__part665 is
begin
    n24744 <= ( lo5186 );
end Other__carpat__part665_behav;
