--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2263 is 
  Port (
    lo4985: in std_logic;
    n29511: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2263;

architecture Other__ucsb_152_tap_fir__part2263_behav of Other__ucsb_152_tap_fir__part2263 is
begin
    n29511 <= ( lo4985 );
end Other__ucsb_152_tap_fir__part2263_behav;
