--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part743 is 
  Port (
    lo4467: in std_logic;
    n22575: inout std_logic
  );
end IWLS2005__des_perf__part743;

architecture IWLS2005__des_perf__part743_behav of IWLS2005__des_perf__part743 is
begin
    n22575 <= ( lo4467 );
end IWLS2005__des_perf__part743_behav;
