--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part145 is 
  Port (
    lo0975: in std_logic;
    n5149_1: inout std_logic
  );
end LGSynth91__s38417__part145;

architecture LGSynth91__s38417__part145_behav of LGSynth91__s38417__part145 is
begin
    n5149_1 <= ( lo0975 );
end LGSynth91__s38417__part145_behav;
