--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1106 is 
  Port (
    lo5184: in std_logic;
    n25715: inout std_logic
  );
end IWLS2005__des_perf__part1106;

architecture IWLS2005__des_perf__part1106_behav of IWLS2005__des_perf__part1106 is
begin
    n25715 <= ( lo5184 );
end IWLS2005__des_perf__part1106_behav;
