--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2299 is 
  Port (
    lo5081: in std_logic;
    n29981: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2299;

architecture Other__ucsb_152_tap_fir__part2299_behav of Other__ucsb_152_tap_fir__part2299 is
begin
    n29981 <= ( lo5081 );
end Other__ucsb_152_tap_fir__part2299_behav;
