--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1529 is 
  Port (
    lo8160: in std_logic;
    n45869_1: inout std_logic
  );
end Other__carpat__part1529;

architecture Other__carpat__part1529_behav of Other__carpat__part1529 is
begin
    n45869_1 <= ( lo8160 );
end Other__carpat__part1529_behav;
