--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1335 is 
  Port (
    lo4704: in std_logic;
    n19009: inout std_logic
  );
end Other__sudoku_check__part1335;

architecture Other__sudoku_check__part1335_behav of Other__sudoku_check__part1335 is
begin
    n19009 <= ( lo4704 );
end Other__sudoku_check__part1335_behav;
