--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part33 is 
  Port (
    pi033: in std_logic;
    n2392_1: inout std_logic
  );
end Other__fpu__part33;

architecture Other__fpu__part33_behav of Other__fpu__part33 is
begin
    n2392_1 <= ( pi033 );
end Other__fpu__part33_behav;
