--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2808 is 
  Port (
    lo8121: in std_logic;
    n40900_1: inout std_logic
  );
end IWLS2005__des_perf__part2808;

architecture IWLS2005__des_perf__part2808_behav of IWLS2005__des_perf__part2808 is
begin
    n40900_1 <= ( lo8121 );
end IWLS2005__des_perf__part2808_behav;
