--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1180 is 
  Port (
    lo1249: in std_logic;
    n6544: inout std_logic
  );
end Cookbook__fec_check__part1180;

architecture Cookbook__fec_check__part1180_behav of Cookbook__fec_check__part1180 is
begin
    n6544 <= ( lo1249 );
end Cookbook__fec_check__part1180_behav;
