--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part30 is 
  Port (
    lo0475: in std_logic;
    n2768: inout std_logic
  );
end Other__ether__part30;

architecture Other__ether__part30_behav of Other__ether__part30 is
begin
    n2768 <= ( lo0475 );
end Other__ether__part30_behav;
