--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part599 is 
  Port (
    lo3248: in std_logic;
    n10909: inout std_logic
  );
end Other__sudoku_check__part599;

architecture Other__sudoku_check__part599_behav of Other__sudoku_check__part599 is
begin
    n10909 <= ( lo3248 );
end Other__sudoku_check__part599_behav;
