--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part92 is 
  Port (
    pi1187: in std_logic;
    n71991_1: inout std_logic
  );
end Other__ray__part92;

architecture Other__ray__part92_behav of Other__ray__part92 is
begin
    n71991_1 <= ( pi1187 );
end Other__ray__part92_behav;
