--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part200 is 
  Port (
    lo2849: in std_logic;
    n6919: inout std_logic
  );
end Other__sudoku_check__part200;

architecture Other__sudoku_check__part200_behav of Other__sudoku_check__part200 is
begin
    n6919 <= ( lo2849 );
end Other__sudoku_check__part200_behav;
