--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part75 is 
  Port (
    pi0804: in std_logic;
    n24819: inout std_logic
  );
end Other__carpat__part75;

architecture Other__carpat__part75_behav of Other__carpat__part75 is
begin
    n24819 <= ( pi0804 );
end Other__carpat__part75_behav;
