--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1741 is 
  Port (
    lo1810: in std_logic;
    n9349: inout std_logic
  );
end Cookbook__fec_check__part1741;

architecture Cookbook__fec_check__part1741_behav of Cookbook__fec_check__part1741 is
begin
    n9349 <= ( lo1810 );
end Cookbook__fec_check__part1741_behav;
