--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1598 is 
  Port (
    lo8311: in std_logic;
    n46444_1: inout std_logic
  );
end Other__carpat__part1598;

architecture Other__carpat__part1598_behav of Other__carpat__part1598 is
begin
    n46444_1 <= ( lo8311 );
end Other__carpat__part1598_behav;
