--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part79 is 
  Port (
    lo2494: in std_logic;
    n5709: inout std_logic
  );
end Other__sudoku_check__part79;

architecture Other__sudoku_check__part79_behav of Other__sudoku_check__part79 is
begin
    n5709 <= ( lo2494 );
end Other__sudoku_check__part79_behav;
