--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1127 is 
  Port (
    lo4496: in std_logic;
    n17969: inout std_logic
  );
end Other__sudoku_check__part1127;

architecture Other__sudoku_check__part1127_behav of Other__sudoku_check__part1127 is
begin
    n17969 <= ( lo4496 );
end Other__sudoku_check__part1127_behav;
