--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part21 is 
  Port (
    lo0012: in std_logic;
    n1319: inout std_logic
  );
end Cookbook__ucrypt__part21;

architecture Cookbook__ucrypt__part21_behav of Cookbook__ucrypt__part21 is
begin
    n1319 <= ( lo0012 );
end Cookbook__ucrypt__part21_behav;
