--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part230 is 
  Port (
    lo0781: in std_logic;
    n5164: inout std_logic
  );
end Cookbook__ucrypt__part230;

architecture Cookbook__ucrypt__part230_behav of Cookbook__ucrypt__part230 is
begin
    n5164 <= ( lo0781 );
end Cookbook__ucrypt__part230_behav;
