--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part157 is 
  Port (
    lo0226: in std_logic;
    n1429: inout std_logic
  );
end Cookbook__fec_check__part157;

architecture Cookbook__fec_check__part157_behav of Cookbook__fec_check__part157 is
begin
    n1429 <= ( lo0226 );
end Cookbook__fec_check__part157_behav;
