--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part216 is 
  Port (
    lo03264: in std_logic;
    n34076: inout std_logic
  );
end Other__ray__part216;

architecture Other__ray__part216_behav of Other__ray__part216 is
begin
    n34076 <= ( lo03264 );
end Other__ray__part216_behav;
