--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part945 is 
  Port (
    lo1014: in std_logic;
    n5369: inout std_logic
  );
end Cookbook__fec_check__part945;

architecture Cookbook__fec_check__part945_behav of Cookbook__fec_check__part945 is
begin
    n5369 <= ( lo1014 );
end Cookbook__fec_check__part945_behav;
