--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1276 is 
  Port (
    lo1345: in std_logic;
    n7024: inout std_logic
  );
end Cookbook__fec_check__part1276;

architecture Cookbook__fec_check__part1276_behav of Cookbook__fec_check__part1276 is
begin
    n7024 <= ( lo1345 );
end Cookbook__fec_check__part1276_behav;
