--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part126 is 
  Port (
    lo009: in std_logic;
    po009: inout std_logic
  );
end Other__fpu__part126;

architecture Other__fpu__part126_behav of Other__fpu__part126 is
begin
    po009 <= ( lo009 );
end Other__fpu__part126_behav;
