--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part513 is 
  Port (
    lo3162: in std_logic;
    n10049: inout std_logic
  );
end Other__sudoku_check__part513;

architecture Other__sudoku_check__part513_behav of Other__sudoku_check__part513 is
begin
    n10049 <= ( lo3162 );
end Other__sudoku_check__part513_behav;
