--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part568 is 
  Port (
    lo2117: in std_logic;
    n11654: inout std_logic
  );
end Cookbook__ucrypt__part568;

architecture Cookbook__ucrypt__part568_behav of Cookbook__ucrypt__part568 is
begin
    n11654 <= ( lo2117 );
end Cookbook__ucrypt__part568_behav;
