--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part75 is 
  Port (
    pi075: in std_logic;
    n10024_1: inout std_logic
  );
end Other__desperf__part75;

architecture Other__desperf__part75_behav of Other__desperf__part75 is
begin
    n10024_1 <= ( pi075 );
end Other__desperf__part75_behav;
