--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part702 is 
  Port (
    lo0771: in std_logic;
    n4154: inout std_logic
  );
end Cookbook__fec_check__part702;

architecture Cookbook__fec_check__part702_behav of Cookbook__fec_check__part702 is
begin
    n4154 <= ( lo0771 );
end Cookbook__fec_check__part702_behav;
