--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2461 is 
  Port (
    lo5435: in std_logic;
    n31741: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2461;

architecture Other__ucsb_152_tap_fir__part2461_behav of Other__ucsb_152_tap_fir__part2461 is
begin
    n31741 <= ( lo5435 );
end Other__ucsb_152_tap_fir__part2461_behav;
