--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part39 is 
  Port (
    lo97717: in std_logic;
    n488455_1: inout std_logic
  );
end IWLS2005__netcard__part39;

architecture IWLS2005__netcard__part39_behav of IWLS2005__netcard__part39 is
begin
    n488455_1 <= ( lo97717 );
end IWLS2005__netcard__part39_behav;
