--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s967__part1 is 
  Port (
    lo06: in std_logic;
    po00: inout std_logic
  );
end ISCAS__s967__part1;

architecture ISCAS__s967__part1_behav of ISCAS__s967__part1 is
begin
    po00 <= ( lo06 );
end ISCAS__s967__part1_behav;
