--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part56 is 
  Port (
    lo55: in std_logic;
    po55: inout std_logic
  );
end Other__idxlat10n_m12__part56;

architecture Other__idxlat10n_m12__part56_behav of Other__idxlat10n_m12__part56 is
begin
    po55 <= ( lo55 );
end Other__idxlat10n_m12__part56_behav;
