--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part137 is 
  Port (
    lo0995: in std_logic;
    n5339_1: inout std_logic
  );
end IWLS2005__mem_ctrl__part137;

architecture IWLS2005__mem_ctrl__part137_behav of IWLS2005__mem_ctrl__part137 is
begin
    n5339_1 <= ( lo0995 );
end IWLS2005__mem_ctrl__part137_behav;
