--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1144 is 
  Port (
    lo1213: in std_logic;
    n6364: inout std_logic
  );
end Cookbook__fec_check__part1144;

architecture Cookbook__fec_check__part1144_behav of Cookbook__fec_check__part1144 is
begin
    n6364 <= ( lo1213 );
end Cookbook__fec_check__part1144_behav;
