--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1023 is 
  Port (
    lo2416: in std_logic;
    n16661: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1023;

architecture Other__ucsb_152_tap_fir__part1023_behav of Other__ucsb_152_tap_fir__part1023 is
begin
    n16661 <= ( lo2416 );
end Other__ucsb_152_tap_fir__part1023_behav;
