--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1173 is 
  Port (
    lo5333: in std_logic;
    n26460: inout std_logic
  );
end IWLS2005__des_perf__part1173;

architecture IWLS2005__des_perf__part1173_behav of IWLS2005__des_perf__part1173 is
begin
    n26460 <= ( lo5333 );
end IWLS2005__des_perf__part1173_behav;
