--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part30 is 
  Port (
    lo0099: in std_logic;
    n794: inout std_logic
  );
end Cookbook__fec_check__part30;

architecture Cookbook__fec_check__part30_behav of Cookbook__fec_check__part30 is
begin
    n794 <= ( lo0099 );
end Cookbook__fec_check__part30_behav;
