--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part71 is 
  Port (
    lo057: in std_logic;
    po209: inout std_logic
  );
end Cookbook__lc_mult_signed__part71;

architecture Cookbook__lc_mult_signed__part71_behav of Cookbook__lc_mult_signed__part71 is
begin
    po209 <= ( lo057 );
end Cookbook__lc_mult_signed__part71_behav;
