--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part936 is 
  Port (
    lo4855: in std_logic;
    n24060: inout std_logic
  );
end IWLS2005__des_perf__part936;

architecture IWLS2005__des_perf__part936_behav of IWLS2005__des_perf__part936 is
begin
    n24060 <= ( lo4855 );
end IWLS2005__des_perf__part936_behav;
