--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part652 is 
  Port (
    lo3301: in std_logic;
    n11439: inout std_logic
  );
end Other__sudoku_check__part652;

architecture Other__sudoku_check__part652_behav of Other__sudoku_check__part652 is
begin
    n11439 <= ( lo3301 );
end Other__sudoku_check__part652_behav;
