--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part31 is 
  Port (
    lo030: in std_logic;
    n460: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part31;

architecture Cookbook__approx_fp_invsqrt__part31_behav of Cookbook__approx_fp_invsqrt__part31 is
begin
    n460 <= ( lo030 );
end Cookbook__approx_fp_invsqrt__part31_behav;
