--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part734 is 
  Port (
    lo3383: in std_logic;
    n12259: inout std_logic
  );
end Other__sudoku_check__part734;

architecture Other__sudoku_check__part734_behav of Other__sudoku_check__part734 is
begin
    n12259 <= ( lo3383 );
end Other__sudoku_check__part734_behav;
