--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part11 is 
  Port (
    lo23: in std_logic;
    n208: inout std_logic
  );
end Cookbook__mlab_dcfifo__part11;

architecture Cookbook__mlab_dcfifo__part11_behav of Cookbook__mlab_dcfifo__part11 is
begin
    n208 <= ( lo23 );
end Cookbook__mlab_dcfifo__part11_behav;
