--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part429 is 
  Port (
    lo0498: in std_logic;
    n2789: inout std_logic
  );
end Cookbook__fec_check__part429;

architecture Cookbook__fec_check__part429_behav of Cookbook__fec_check__part429 is
begin
    n2789 <= ( lo0498 );
end Cookbook__fec_check__part429_behav;
