--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2312 is 
  Port (
    lo3500,lo3488,lo3476,lo3464,lo3452,lo3440,lo3416,lo3404,lo3428,lo3794: in std_logic;
    n18949: inout std_logic
  );
end Cookbook__fec_check__part2312;

architecture Cookbook__fec_check__part2312_behav of Cookbook__fec_check__part2312 is
signal n13681,n13682,n13683,n13684,n13685,n13686,n13687,n13688: std_logic;
begin
    n13681 <= not (( not lo3500 and not lo3488 ));
    n13682 <= not (( not lo3476 and not lo3464 ));
    n13683 <= not (( not n13681 and not n13682 ));
    n13684 <= not (( not lo3452 and not lo3440 ));
    n13685 <= not (( not lo3416 and not lo3404 ));
    n13686 <= not (( not lo3428 and not n13685 ));
    n13687 <= not (( not n13684 and not n13686 ));
    n13688 <= not (( not n13683 and not n13687 ));
    n18949 <= not (( not n13688 and not lo3794 ));
end Cookbook__fec_check__part2312_behav;
