--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1151 is 
  Port (
    lo2675: in std_logic;
    n17956: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1151;

architecture Other__ucsb_152_tap_fir__part1151_behav of Other__ucsb_152_tap_fir__part1151 is
begin
    n17956 <= ( lo2675 );
end Other__ucsb_152_tap_fir__part1151_behav;
