--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part767 is 
  Port (
    lo4504: in std_logic;
    n22555: inout std_logic
  );
end IWLS2005__des_perf__part767;

architecture IWLS2005__des_perf__part767_behav of IWLS2005__des_perf__part767 is
begin
    n22555 <= ( lo4504 );
end IWLS2005__des_perf__part767_behav;
