--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part586 is 
  Port (
    lo3235: in std_logic;
    n10779: inout std_logic
  );
end Other__sudoku_check__part586;

architecture Other__sudoku_check__part586_behav of Other__sudoku_check__part586 is
begin
    n10779 <= ( lo3235 );
end Other__sudoku_check__part586_behav;
