--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part92 is 
  Port (
    lo0292: in std_logic;
    n4050: inout std_logic
  );
end Other__fp_operators__part92;

architecture Other__fp_operators__part92_behav of Other__fp_operators__part92 is
begin
    n4050 <= ( lo0292 );
end Other__fp_operators__part92_behav;
