--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part583 is 
  Port (
    lo0652: in std_logic;
    n3559: inout std_logic
  );
end Cookbook__fec_check__part583;

architecture Cookbook__fec_check__part583_behav of Cookbook__fec_check__part583 is
begin
    n3559 <= ( lo0652 );
end Cookbook__fec_check__part583_behav;
