--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1710 is 
  Port (
    lo8732: in std_logic;
    po184: inout std_logic
  );
end Other__carpat__part1710;

architecture Other__carpat__part1710_behav of Other__carpat__part1710 is
begin
    po184 <= ( lo8732 );
end Other__carpat__part1710_behav;
