--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part40 is 
  Port (
    lo0745: in std_logic;
    n4883: inout std_logic
  );
end Other__ether__part40;

architecture Other__ether__part40_behav of Other__ether__part40 is
begin
    n4883 <= ( lo0745 );
end Other__ether__part40_behav;
