--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part910 is 
  Port (
    lo4279: in std_logic;
    n16884: inout std_logic
  );
end Other__sudoku_check__part910;

architecture Other__sudoku_check__part910_behav of Other__sudoku_check__part910 is
begin
    n16884 <= ( lo4279 );
end Other__sudoku_check__part910_behav;
