--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1134 is 
  Port (
    lo4503: in std_logic;
    n18004: inout std_logic
  );
end Other__sudoku_check__part1134;

architecture Other__sudoku_check__part1134_behav of Other__sudoku_check__part1134 is
begin
    n18004 <= ( lo4503 );
end Other__sudoku_check__part1134_behav;
