--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part164 is 
  Port (
    lo1115: in std_logic;
    n3929: inout std_logic
  );
end IWLS93__s38417__part164;

architecture IWLS93__s38417__part164_behav of IWLS93__s38417__part164 is
begin
    n3929 <= ( lo1115 );
end IWLS93__s38417__part164_behav;
