--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part43 is 
  Port (
    pi043: in std_logic;
    n9864_1: inout std_logic
  );
end Other__desperf__part43;

architecture Other__desperf__part43_behav of Other__desperf__part43 is
begin
    n9864_1 <= ( pi043 );
end Other__desperf__part43_behav;
