--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part732 is 
  Port (
    lo06412: in std_logic;
    n47991: inout std_logic
  );
end Other__ray__part732;

architecture Other__ray__part732_behav of Other__ray__part732 is
begin
    n47991 <= ( lo06412 );
end Other__ray__part732_behav;
