--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part455 is 
  Port (
    lo0524: in std_logic;
    n2919: inout std_logic
  );
end Cookbook__fec_check__part455;

architecture Cookbook__fec_check__part455_behav of Cookbook__fec_check__part455 is
begin
    n2919 <= ( lo0524 );
end Cookbook__fec_check__part455_behav;
