--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part502 is 
  Port (
    lo3151: in std_logic;
    n9939: inout std_logic
  );
end Other__sudoku_check__part502;

architecture Other__sudoku_check__part502_behav of Other__sudoku_check__part502 is
begin
    n9939 <= ( lo3151 );
end Other__sudoku_check__part502_behav;
