--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part86 is 
  Port (
    pi1181: in std_logic;
    n71931_1: inout std_logic
  );
end Other__ray__part86;

architecture Other__ray__part86_behav of Other__ray__part86 is
begin
    n71931_1 <= ( pi1181 );
end Other__ray__part86_behav;
