--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part714 is 
  Port (
    lo5245: in std_logic;
    n25194: inout std_logic
  );
end Other__carpat__part714;

architecture Other__carpat__part714_behav of Other__carpat__part714 is
begin
    n25194 <= ( lo5245 );
end Other__carpat__part714_behav;
