--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part908 is 
  Port (
    lo6753: in std_logic;
    n34074_1: inout std_logic
  );
end Other__carpat__part908;

architecture Other__carpat__part908_behav of Other__carpat__part908 is
begin
    n34074_1 <= ( lo6753 );
end Other__carpat__part908_behav;
