--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b06_opt__part6 is 
  Port (
    lo8: in std_logic;
    po5: inout std_logic
  );
end ITC99__b06_opt__part6;

architecture ITC99__b06_opt__part6_behav of ITC99__b06_opt__part6 is
begin
    po5 <= ( lo8 );
end ITC99__b06_opt__part6_behav;
