--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part637 is 
  Port (
    lo06134: in std_logic;
    po1700,po1795: inout std_logic
  );
end Other__ray__part637;

architecture Other__ray__part637_behav of Other__ray__part637 is
begin
    po1700 <= ( lo06134 );
    po1795 <= ( lo06134 );
end Other__ray__part637_behav;
