--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3024 is 
  Port (
    lo8337: in std_logic;
    n42140_1: inout std_logic
  );
end IWLS2005__des_perf__part3024;

architecture IWLS2005__des_perf__part3024_behav of IWLS2005__des_perf__part3024 is
begin
    n42140_1 <= ( lo8337 );
end IWLS2005__des_perf__part3024_behav;
