--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2127 is 
  Port (
    lo2196: in std_logic;
    n11279: inout std_logic
  );
end Cookbook__fec_check__part2127;

architecture Cookbook__fec_check__part2127_behav of Cookbook__fec_check__part2127 is
begin
    n11279 <= ( lo2196 );
end Cookbook__fec_check__part2127_behav;
