--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1200 is 
  Port (
    lo1269: in std_logic;
    n6644: inout std_logic
  );
end Cookbook__fec_check__part1200;

architecture Cookbook__fec_check__part1200_behav of Cookbook__fec_check__part1200 is
begin
    n6644 <= ( lo1269 );
end Cookbook__fec_check__part1200_behav;
