--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2615 is 
  Port (
    lo5742: in std_logic;
    n33296_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2615;

architecture Other__ucsb_152_tap_fir__part2615_behav of Other__ucsb_152_tap_fir__part2615 is
begin
    n33296_1 <= ( lo5742 );
end Other__ucsb_152_tap_fir__part2615_behav;
