--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part285 is 
  Port (
    lo1408: in std_logic;
    n9990_1: inout std_logic
  );
end Other__fp_operators__part285;

architecture Other__fp_operators__part285_behav of Other__fp_operators__part285 is
begin
    n9990_1 <= ( lo1408 );
end Other__fp_operators__part285_behav;
