--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part967 is 
  Port (
    lo10653: in std_logic;
    n71206_1: inout std_logic
  );
end Other__ray__part967;

architecture Other__ray__part967_behav of Other__ray__part967 is
begin
    n71206_1 <= ( lo10653 );
end Other__ray__part967_behav;
