--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_20__part19 is 
  Port (
    lo029: in std_logic;
    n742_1: inout std_logic
  );
end Cookbook__gearbox_66_20__part19;

architecture Cookbook__gearbox_66_20__part19_behav of Cookbook__gearbox_66_20__part19 is
begin
    n742_1 <= ( lo029 );
end Cookbook__gearbox_66_20__part19_behav;
