--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1116 is 
  Port (
    lo5198: in std_logic;
    n25905: inout std_logic
  );
end IWLS2005__des_perf__part1116;

architecture IWLS2005__des_perf__part1116_behav of IWLS2005__des_perf__part1116 is
begin
    n25905 <= ( lo5198 );
end IWLS2005__des_perf__part1116_behav;
