--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part100 is 
  Port (
    lo01294: in std_logic;
    po2777,po2873,po2969,po3030,po3078,po3126,n20656: inout std_logic
  );
end Other__ray__part100;

architecture Other__ray__part100_behav of Other__ray__part100 is
begin
    po2777 <= ( lo01294 );
    po2873 <= ( lo01294 );
    po2969 <= ( lo01294 );
    po3030 <= ( lo01294 );
    po3078 <= ( lo01294 );
    po3126 <= ( lo01294 );
    n20656 <= ( lo01294 );
end Other__ray__part100_behav;
