--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part11 is 
  Port (
    pi11: in std_logic;
    n1674_1: inout std_logic
  );
end Cookbook__gearbox_40_67__part11;

architecture Cookbook__gearbox_40_67__part11_behav of Cookbook__gearbox_40_67__part11 is
begin
    n1674_1 <= ( pi11 );
end Cookbook__gearbox_40_67__part11_behav;
