--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1288 is 
  Port (
    lo2962: in std_logic;
    n19311: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1288;

architecture Other__ucsb_152_tap_fir__part1288_behav of Other__ucsb_152_tap_fir__part1288 is
begin
    n19311 <= ( lo2962 );
end Other__ucsb_152_tap_fir__part1288_behav;
