--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part855 is 
  Port (
    lo4224: in std_logic;
    n16609: inout std_logic
  );
end Other__sudoku_check__part855;

architecture Other__sudoku_check__part855_behav of Other__sudoku_check__part855 is
begin
    n16609 <= ( lo4224 );
end Other__sudoku_check__part855_behav;
