--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1176 is 
  Port (
    lo7423: in std_logic;
    n41194_1: inout std_logic
  );
end Other__carpat__part1176;

architecture Other__carpat__part1176_behav of Other__carpat__part1176 is
begin
    n41194_1 <= ( lo7423 );
end Other__carpat__part1176_behav;
