--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1328 is 
  Port (
    lo4697: in std_logic;
    n18974: inout std_logic
  );
end Other__sudoku_check__part1328;

architecture Other__sudoku_check__part1328_behav of Other__sudoku_check__part1328 is
begin
    n18974 <= ( lo4697 );
end Other__sudoku_check__part1328_behav;
