--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1003 is 
  Port (
    lo4372: in std_logic;
    n17349: inout std_logic
  );
end Other__sudoku_check__part1003;

architecture Other__sudoku_check__part1003_behav of Other__sudoku_check__part1003 is
begin
    n17349 <= ( lo4372 );
end Other__sudoku_check__part1003_behav;
