--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2043 is 
  Port (
    lo2112: in std_logic;
    n10859: inout std_logic
  );
end Cookbook__fec_check__part2043;

architecture Cookbook__fec_check__part2043_behav of Cookbook__fec_check__part2043 is
begin
    n10859 <= ( lo2112 );
end Cookbook__fec_check__part2043_behav;
