--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part93 is 
  Port (
    lo1767: in std_logic;
    po086: inout std_logic
  );
end Other__mem__part93;

architecture Other__mem__part93_behav of Other__mem__part93 is
begin
    po086 <= ( lo1767 );
end Other__mem__part93_behav;
