--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2140 is 
  Port (
    lo2209: in std_logic;
    n11344: inout std_logic
  );
end Cookbook__fec_check__part2140;

architecture Cookbook__fec_check__part2140_behav of Cookbook__fec_check__part2140 is
begin
    n11344 <= ( lo2209 );
end Cookbook__fec_check__part2140_behav;
