--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part54 is 
  Port (
    pi054: in std_logic;
    n9919_1: inout std_logic
  );
end Other__desperf__part54;

architecture Other__desperf__part54_behav of Other__desperf__part54 is
begin
    n9919_1 <= ( pi054 );
end Other__desperf__part54_behav;
