--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2072 is 
  Port (
    lo2141: in std_logic;
    n11004: inout std_logic
  );
end Cookbook__fec_check__part2072;

architecture Cookbook__fec_check__part2072_behav of Cookbook__fec_check__part2072 is
begin
    n11004 <= ( lo2141 );
end Cookbook__fec_check__part2072_behav;
