--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1804 is 
  Port (
    lo4103: in std_logic;
    n24941: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1804;

architecture Other__ucsb_152_tap_fir__part1804_behav of Other__ucsb_152_tap_fir__part1804 is
begin
    n24941 <= ( lo4103 );
end Other__ucsb_152_tap_fir__part1804_behav;
