--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1232 is 
  Port (
    lo1301: in std_logic;
    n6804: inout std_logic
  );
end Cookbook__fec_check__part1232;

architecture Cookbook__fec_check__part1232_behav of Cookbook__fec_check__part1232 is
begin
    n6804 <= ( lo1301 );
end Cookbook__fec_check__part1232_behav;
