--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1882 is 
  Port (
    lo1951: in std_logic;
    n10054: inout std_logic
  );
end Cookbook__fec_check__part1882;

architecture Cookbook__fec_check__part1882_behav of Cookbook__fec_check__part1882 is
begin
    n10054 <= ( lo1951 );
end Cookbook__fec_check__part1882_behav;
