--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part180 is 
  Port (
    lo1395: in std_logic;
    n7249: inout std_logic
  );
end ISCAS__s38417__part180;

architecture ISCAS__s38417__part180_behav of ISCAS__s38417__part180 is
begin
    n7249 <= ( lo1395 );
end ISCAS__s38417__part180_behav;
