--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2026 is 
  Port (
    lo2095: in std_logic;
    n10774: inout std_logic
  );
end Cookbook__fec_check__part2026;

architecture Cookbook__fec_check__part2026_behav of Cookbook__fec_check__part2026 is
begin
    n10774 <= ( lo2095 );
end Cookbook__fec_check__part2026_behav;
