--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1103 is 
  Port (
    lo4472: in std_logic;
    n17849: inout std_logic
  );
end Other__sudoku_check__part1103;

architecture Other__sudoku_check__part1103_behav of Other__sudoku_check__part1103 is
begin
    n17849 <= ( lo4472 );
end Other__sudoku_check__part1103_behav;
