--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__eightbyeight_sad__part20 is 
  Port (
    lo327: in std_logic;
    po08: inout std_logic
  );
end Cookbook__eightbyeight_sad__part20;

architecture Cookbook__eightbyeight_sad__part20_behav of Cookbook__eightbyeight_sad__part20 is
begin
    po08 <= ( lo327 );
end Cookbook__eightbyeight_sad__part20_behav;
