--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s5378__part8 is 
  Port (
    lo146: in std_logic;
    n898_1: inout std_logic
  );
end ISCAS__s5378__part8;

architecture ISCAS__s5378__part8_behav of ISCAS__s5378__part8 is
begin
    n898_1 <= ( not lo146 );
end ISCAS__s5378__part8_behav;
