--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part397 is 
  Port (
    lo2233: in std_logic;
    n11680: inout std_logic
  );
end IWLS2005__des_perf__part397;

architecture IWLS2005__des_perf__part397_behav of IWLS2005__des_perf__part397 is
begin
    n11680 <= ( lo2233 );
end IWLS2005__des_perf__part397_behav;
