--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part71 is 
  Port (
    lo0935: in std_logic;
    po138: inout std_logic
  );
end IWLS2005__pci_bridge32__part71;

architecture IWLS2005__pci_bridge32__part71_behav of IWLS2005__pci_bridge32__part71 is
begin
    po138 <= ( lo0935 );
end IWLS2005__pci_bridge32__part71_behav;
