--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part880 is 
  Port (
    lo0949: in std_logic;
    n5044: inout std_logic
  );
end Cookbook__fec_check__part880;

architecture Cookbook__fec_check__part880_behav of Cookbook__fec_check__part880 is
begin
    n5044 <= ( lo0949 );
end Cookbook__fec_check__part880_behav;
