--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part15 is 
  Port (
    pi095: in std_logic;
    n17419_1: inout std_logic
  );
end IWLS2005__pci_bridge32__part15;

architecture IWLS2005__pci_bridge32__part15_behav of IWLS2005__pci_bridge32__part15 is
begin
    n17419_1 <= ( pi095 );
end IWLS2005__pci_bridge32__part15_behav;
