--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2959 is 
  Port (
    lo8272: in std_logic;
    n41805_1: inout std_logic
  );
end IWLS2005__des_perf__part2959;

architecture IWLS2005__des_perf__part2959_behav of IWLS2005__des_perf__part2959 is
begin
    n41805_1 <= ( lo8272 );
end IWLS2005__des_perf__part2959_behav;
