--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part227 is 
  Port (
    lo1123: in std_logic;
    n7070_1: inout std_logic
  );
end Other__fp_operators__part227;

architecture Other__fp_operators__part227_behav of Other__fp_operators__part227 is
begin
    n7070_1 <= ( lo1123 );
end Other__fp_operators__part227_behav;
