--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part385 is 
  Port (
    lo0454: in std_logic;
    n2569: inout std_logic
  );
end Cookbook__fec_check__part385;

architecture Cookbook__fec_check__part385_behav of Cookbook__fec_check__part385 is
begin
    n2569 <= ( lo0454 );
end Cookbook__fec_check__part385_behav;
