--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part262 is 
  Port (
    lo0331: in std_logic;
    n1954: inout std_logic
  );
end Cookbook__fec_check__part262;

architecture Cookbook__fec_check__part262_behav of Cookbook__fec_check__part262 is
begin
    n1954 <= ( lo0331 );
end Cookbook__fec_check__part262_behav;
