--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part382 is 
  Port (
    lo1381: in std_logic;
    n8164_1: inout std_logic
  );
end Cookbook__ucrypt__part382;

architecture Cookbook__ucrypt__part382_behav of Cookbook__ucrypt__part382 is
begin
    n8164_1 <= ( lo1381 );
end Cookbook__ucrypt__part382_behav;
