--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1942 is 
  Port (
    lo6967: in std_logic;
    n34665: inout std_logic
  );
end IWLS2005__des_perf__part1942;

architecture IWLS2005__des_perf__part1942_behav of IWLS2005__des_perf__part1942 is
begin
    n34665 <= ( lo6967 );
end IWLS2005__des_perf__part1942_behav;
