--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1030 is 
  Port (
    lo1099: in std_logic;
    n5794: inout std_logic
  );
end Cookbook__fec_check__part1030;

architecture Cookbook__fec_check__part1030_behav of Cookbook__fec_check__part1030 is
begin
    n5794 <= ( lo1099 );
end Cookbook__fec_check__part1030_behav;
