--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part29 is 
  Port (
    lo71: in std_logic;
    po25: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part29;

architecture Cookbook__soft_ecc_ram_16bit__part29_behav of Cookbook__soft_ecc_ram_16bit__part29 is
begin
    po25 <= ( lo71 );
end Cookbook__soft_ecc_ram_16bit__part29_behav;
