--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part55 is 
  Port (
    lo54: in std_logic;
    po54: inout std_logic
  );
end Other__idxlat02n_m12__part55;

architecture Other__idxlat02n_m12__part55_behav of Other__idxlat02n_m12__part55 is
begin
    po54 <= ( lo54 );
end Other__idxlat02n_m12__part55_behav;
