--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_66__part2 is 
  Port (
    lo025: in std_logic;
    n512: inout std_logic
  );
end Cookbook__gearbox_20_66__part2;

architecture Cookbook__gearbox_20_66__part2_behav of Cookbook__gearbox_20_66__part2 is
begin
    n512 <= ( lo025 );
end Cookbook__gearbox_20_66__part2_behav;
