--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1362 is 
  Port (
    lo4731: in std_logic;
    n19144: inout std_logic
  );
end Other__sudoku_check__part1362;

architecture Other__sudoku_check__part1362_behav of Other__sudoku_check__part1362 is
begin
    n19144 <= ( lo4731 );
end Other__sudoku_check__part1362_behav;
