--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1056 is 
  Port (
    lo2477: in std_logic;
    n16976: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1056;

architecture Other__ucsb_152_tap_fir__part1056_behav of Other__ucsb_152_tap_fir__part1056 is
begin
    n16976 <= ( lo2477 );
end Other__ucsb_152_tap_fir__part1056_behav;
