--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part104 is 
  Port (
    lo0745: in std_logic;
    n3999: inout std_logic
  );
end ISCAS__s38417__part104;

architecture ISCAS__s38417__part104_behav of ISCAS__s38417__part104 is
begin
    n3999 <= ( lo0745 );
end ISCAS__s38417__part104_behav;
