--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1329 is 
  Port (
    lo4698: in std_logic;
    n18979: inout std_logic
  );
end Other__sudoku_check__part1329;

architecture Other__sudoku_check__part1329_behav of Other__sudoku_check__part1329 is
begin
    n18979 <= ( lo4698 );
end Other__sudoku_check__part1329_behav;
