--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1810 is 
  Port (
    lo4109: in std_logic;
    n24986: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1810;

architecture Other__ucsb_152_tap_fir__part1810_behav of Other__ucsb_152_tap_fir__part1810 is
begin
    n24986 <= ( lo4109 );
end Other__ucsb_152_tap_fir__part1810_behav;
