--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2306 is 
  Port (
    lo5092: in std_logic;
    n30016: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2306;

architecture Other__ucsb_152_tap_fir__part2306_behav of Other__ucsb_152_tap_fir__part2306 is
begin
    n30016 <= ( lo5092 );
end Other__ucsb_152_tap_fir__part2306_behav;
