--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__simple_spi__part2 is 
  Port (
    lo067: in std_logic;
    po03: inout std_logic
  );
end IWLS2005__simple_spi__part2;

architecture IWLS2005__simple_spi__part2_behav of IWLS2005__simple_spi__part2 is
begin
    po03 <= ( lo067 );
end IWLS2005__simple_spi__part2_behav;
