--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2067 is 
  Port (
    lo4598: in std_logic;
    n27571: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2067;

architecture Other__ucsb_152_tap_fir__part2067_behav of Other__ucsb_152_tap_fir__part2067 is
begin
    n27571 <= ( lo4598 );
end Other__ucsb_152_tap_fir__part2067_behav;
