--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part730 is 
  Port (
    lo5457: in std_logic;
    n25769: inout std_logic
  );
end Other__carpat__part730;

architecture Other__carpat__part730_behav of Other__carpat__part730 is
begin
    n25769 <= ( lo5457 );
end Other__carpat__part730_behav;
