--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2059 is 
  Port (
    lo7200: in std_logic;
    n35780: inout std_logic
  );
end IWLS2005__des_perf__part2059;

architecture IWLS2005__des_perf__part2059_behav of IWLS2005__des_perf__part2059 is
begin
    n35780 <= ( lo7200 );
end IWLS2005__des_perf__part2059_behav;
