--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part643 is 
  Port (
    lo4289: in std_logic;
    n21545: inout std_logic
  );
end IWLS2005__des_perf__part643;

architecture IWLS2005__des_perf__part643_behav of IWLS2005__des_perf__part643 is
begin
    n21545 <= ( lo4289 );
end IWLS2005__des_perf__part643_behav;
