--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1336 is 
  Port (
    lo3056: in std_logic;
    n19781: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1336;

architecture Other__ucsb_152_tap_fir__part1336_behav of Other__ucsb_152_tap_fir__part1336 is
begin
    n19781 <= ( lo3056 );
end Other__ucsb_152_tap_fir__part1336_behav;
