--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part14 is 
  Port (
    lo45: in std_logic;
    po12: inout std_logic
  );
end Cookbook__temp_sense_s5__part14;

architecture Cookbook__temp_sense_s5__part14_behav of Cookbook__temp_sense_s5__part14 is
begin
    po12 <= ( lo45 );
end Cookbook__temp_sense_s5__part14_behav;
