--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part41 is 
  Port (
    lo0074: in std_logic;
    po054: inout std_logic
  );
end Other__fp_operators__part41;

architecture Other__fp_operators__part41_behav of Other__fp_operators__part41 is
begin
    po054 <= ( lo0074 );
end Other__fp_operators__part41_behav;
