--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part305 is 
  Port (
    lo1080: in std_logic;
    n6659: inout std_logic
  );
end Cookbook__ucrypt__part305;

architecture Cookbook__ucrypt__part305_behav of Cookbook__ucrypt__part305 is
begin
    n6659 <= ( lo1080 );
end Cookbook__ucrypt__part305_behav;
