--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part439 is 
  Port (
    lo0547: in std_logic;
    n7224: inout std_logic
  );
end Other__carpat__part439;

architecture Other__carpat__part439_behav of Other__carpat__part439 is
begin
    n7224 <= ( lo0547 );
end Other__carpat__part439_behav;
