--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part177 is 
  Port (
    lo0246: in std_logic;
    n1529: inout std_logic
  );
end Cookbook__fec_check__part177;

architecture Cookbook__fec_check__part177_behav of Cookbook__fec_check__part177 is
begin
    n1529 <= ( lo0246 );
end Cookbook__fec_check__part177_behav;
