--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s9234__part2 is 
  Port (
    lo002: in std_logic;
    n83: inout std_logic
  );
end ISCAS__s9234__part2;

architecture ISCAS__s9234__part2_behav of ISCAS__s9234__part2 is
begin
    n83 <= ( lo002 );
end ISCAS__s9234__part2_behav;
