--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part18 is 
  Port (
    lo17: in std_logic;
    po11: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part18;

architecture Cookbook__x4_decoder_8b10b__part18_behav of Cookbook__x4_decoder_8b10b__part18 is
begin
    po11 <= ( lo17 );
end Cookbook__x4_decoder_8b10b__part18_behav;
