--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part217 is 
  Port (
    lo03266: in std_logic;
    po1228: inout std_logic
  );
end Other__ray__part217;

architecture Other__ray__part217_behav of Other__ray__part217 is
begin
    po1228 <= ( lo03266 );
end Other__ray__part217_behav;
