--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part322 is 
  Port (
    lo2971: in std_logic;
    n8139: inout std_logic
  );
end Other__sudoku_check__part322;

architecture Other__sudoku_check__part322_behav of Other__sudoku_check__part322 is
begin
    n8139 <= ( lo2971 );
end Other__sudoku_check__part322_behav;
