--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1644 is 
  Port (
    lo8436: in std_logic;
    n47079_1: inout std_logic
  );
end Other__carpat__part1644;

architecture Other__carpat__part1644_behav of Other__carpat__part1644 is
begin
    n47079_1 <= ( lo8436 );
end Other__carpat__part1644_behav;
