--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part111 is 
  Port (
    lo360: in std_logic;
    po064: inout std_logic
  );
end IWLS2005__aes_core__part111;

architecture IWLS2005__aes_core__part111_behav of IWLS2005__aes_core__part111 is
begin
    po064 <= ( lo360 );
end IWLS2005__aes_core__part111_behav;
