--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part166 is 
  Port (
    lo1118: in std_logic;
    n6319_1: inout std_logic
  );
end IWLS93__s38417__part166;

architecture IWLS93__s38417__part166_behav of IWLS93__s38417__part166 is
begin
    n6319_1 <= ( lo1118 );
end IWLS93__s38417__part166_behav;
