--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1382 is 
  Port (
    lo5810: in std_logic;
    n28850_1: inout std_logic
  );
end IWLS2005__des_perf__part1382;

architecture IWLS2005__des_perf__part1382_behav of IWLS2005__des_perf__part1382 is
begin
    n28850_1 <= ( lo5810 );
end IWLS2005__des_perf__part1382_behav;
