--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part526 is 
  Port (
    lo4109: in std_logic;
    n20585: inout std_logic
  );
end IWLS2005__des_perf__part526;

architecture IWLS2005__des_perf__part526_behav of IWLS2005__des_perf__part526 is
begin
    n20585 <= ( lo4109 );
end IWLS2005__des_perf__part526_behav;
