--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part112 is 
  Port (
    lo2761: in std_logic;
    n6039: inout std_logic
  );
end Other__sudoku_check__part112;

architecture Other__sudoku_check__part112_behav of Other__sudoku_check__part112 is
begin
    n6039 <= ( lo2761 );
end Other__sudoku_check__part112_behav;
