--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part245 is 
  Port (
    lo03528: in std_logic;
    n34981: inout std_logic
  );
end Other__ray__part245;

architecture Other__ray__part245_behav of Other__ray__part245 is
begin
    n34981 <= ( lo03528 );
end Other__ray__part245_behav;
