--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part134 is 
  Port (
    lo0482: in std_logic;
    n4765: inout std_logic
  );
end Other__fp_operators__part134;

architecture Other__fp_operators__part134_behav of Other__fp_operators__part134 is
begin
    n4765 <= ( lo0482 );
end Other__fp_operators__part134_behav;
