--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part364 is 
  Port (
    lo2131: in std_logic;
    n11135: inout std_logic
  );
end IWLS2005__des_perf__part364;

architecture IWLS2005__des_perf__part364_behav of IWLS2005__des_perf__part364 is
begin
    n11135 <= ( lo2131 );
end IWLS2005__des_perf__part364_behav;
