--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part565 is 
  Port (
    lo0634: in std_logic;
    n3469: inout std_logic
  );
end Cookbook__fec_check__part565;

architecture Cookbook__fec_check__part565_behav of Cookbook__fec_check__part565 is
begin
    n3469 <= ( lo0634 );
end Cookbook__fec_check__part565_behav;
