--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part71 is 
  Port (
    lo1745: in std_logic;
    n8874: inout std_logic
  );
end IWLS2005__usb_funct__part71;

architecture IWLS2005__usb_funct__part71_behav of IWLS2005__usb_funct__part71 is
begin
    n8874 <= ( lo1745 );
end IWLS2005__usb_funct__part71_behav;
