--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1075 is 
  Port (
    lo2498: in std_logic;
    n17071: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1075;

architecture Other__ucsb_152_tap_fir__part1075_behav of Other__ucsb_152_tap_fir__part1075 is
begin
    n17071 <= ( lo2498 );
end Other__ucsb_152_tap_fir__part1075_behav;
