--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part44 is 
  Port (
    lo2195: in std_logic;
    n5359: inout std_logic
  );
end Other__sudoku_check__part44;

architecture Other__sudoku_check__part44_behav of Other__sudoku_check__part44 is
begin
    n5359 <= ( lo2195 );
end Other__sudoku_check__part44_behav;
