--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part59 is 
  Port (
    lo0128: in std_logic;
    n939: inout std_logic
  );
end Cookbook__fec_check__part59;

architecture Cookbook__fec_check__part59_behav of Cookbook__fec_check__part59 is
begin
    n939 <= ( lo0128 );
end Cookbook__fec_check__part59_behav;
