--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1055 is 
  Port (
    lo10954: in std_logic;
    n72496_1: inout std_logic
  );
end Other__ray__part1055;

architecture Other__ray__part1055_behav of Other__ray__part1055 is
begin
    n72496_1 <= ( lo10954 );
end Other__ray__part1055_behav;
