--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part138 is 
  Port (
    lo0947: in std_logic;
    n5009_1: inout std_logic
  );
end LGSynth91__s38417__part138;

architecture LGSynth91__s38417__part138_behav of LGSynth91__s38417__part138 is
begin
    n5009_1 <= ( lo0947 );
end LGSynth91__s38417__part138_behav;
