--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part95 is 
  Port (
    lo221: in std_logic;
    po117: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part95;

architecture Cookbook__soft_ecc_ram_64bit__part95_behav of Cookbook__soft_ecc_ram_64bit__part95 is
begin
    po117 <= ( lo221 );
end Cookbook__soft_ecc_ram_64bit__part95_behav;
