--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2239 is 
  Port (
    lo7430: in std_logic;
    n37075_1: inout std_logic
  );
end IWLS2005__des_perf__part2239;

architecture IWLS2005__des_perf__part2239_behav of IWLS2005__des_perf__part2239 is
begin
    n37075_1 <= ( lo7430 );
end IWLS2005__des_perf__part2239_behav;
