--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1391 is 
  Port (
    lo3189: in std_logic;
    n20531: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1391;

architecture Other__ucsb_152_tap_fir__part1391_behav of Other__ucsb_152_tap_fir__part1391 is
begin
    n20531 <= ( lo3189 );
end Other__ucsb_152_tap_fir__part1391_behav;
