--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part871 is 
  Port (
    lo0940: in std_logic;
    n4999: inout std_logic
  );
end Cookbook__fec_check__part871;

architecture Cookbook__fec_check__part871_behav of Cookbook__fec_check__part871 is
begin
    n4999 <= ( lo0940 );
end Cookbook__fec_check__part871_behav;
