--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1788 is 
  Port (
    lo8883: in std_logic;
    po318: inout std_logic
  );
end Other__carpat__part1788;

architecture Other__carpat__part1788_behav of Other__carpat__part1788 is
begin
    po318 <= ( lo8883 );
end Other__carpat__part1788_behav;
