--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part215 is 
  Port (
    lo0104: in std_logic;
    n615: inout std_logic
  );
end IWLS2005__des_perf__part215;

architecture IWLS2005__des_perf__part215_behav of IWLS2005__des_perf__part215 is
begin
    n615 <= ( not lo0104 );
end IWLS2005__des_perf__part215_behav;
