--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part202 is 
  Port (
    lo0089: in std_logic;
    n990: inout std_logic
  );
end IWLS2005__des_perf__part202;

architecture IWLS2005__des_perf__part202_behav of IWLS2005__des_perf__part202 is
begin
    n990 <= ( lo0089 );
end IWLS2005__des_perf__part202_behav;
