--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part16 is 
  Port (
    lo002: in std_logic;
    po027: inout std_logic
  );
end Cookbook__lc_mult_signed__part16;

architecture Cookbook__lc_mult_signed__part16_behav of Cookbook__lc_mult_signed__part16 is
begin
    po027 <= ( lo002 );
end Cookbook__lc_mult_signed__part16_behav;
