--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part720 is 
  Port (
    lo3369: in std_logic;
    n12119: inout std_logic
  );
end Other__sudoku_check__part720;

architecture Other__sudoku_check__part720_behav of Other__sudoku_check__part720 is
begin
    n12119 <= ( lo3369 );
end Other__sudoku_check__part720_behav;
