--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1341 is 
  Port (
    lo4710: in std_logic;
    n19039: inout std_logic
  );
end Other__sudoku_check__part1341;

architecture Other__sudoku_check__part1341_behav of Other__sudoku_check__part1341 is
begin
    n19039 <= ( lo4710 );
end Other__sudoku_check__part1341_behav;
