--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1557 is 
  Port (
    lo1626: in std_logic;
    n8429: inout std_logic
  );
end Cookbook__fec_check__part1557;

architecture Cookbook__fec_check__part1557_behav of Cookbook__fec_check__part1557 is
begin
    n8429 <= ( lo1626 );
end Cookbook__fec_check__part1557_behav;
