--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1327 is 
  Port (
    lo1396: in std_logic;
    n7279: inout std_logic
  );
end Cookbook__fec_check__part1327;

architecture Cookbook__fec_check__part1327_behav of Cookbook__fec_check__part1327 is
begin
    n7279 <= ( lo1396 );
end Cookbook__fec_check__part1327_behav;
