--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1705 is 
  Port (
    lo1774: in std_logic;
    n9169: inout std_logic
  );
end Cookbook__fec_check__part1705;

architecture Cookbook__fec_check__part1705_behav of Cookbook__fec_check__part1705 is
begin
    n9169 <= ( lo1774 );
end Cookbook__fec_check__part1705_behav;
