--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part515 is 
  Port (
    lo0584: in std_logic;
    n3219: inout std_logic
  );
end Cookbook__fec_check__part515;

architecture Cookbook__fec_check__part515_behav of Cookbook__fec_check__part515 is
begin
    n3219 <= ( lo0584 );
end Cookbook__fec_check__part515_behav;
