--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part565 is 
  Port (
    lo3405: in std_logic;
    n16199: inout std_logic
  );
end Other__carpat__part565;

architecture Other__carpat__part565_behav of Other__carpat__part565 is
begin
    n16199 <= ( lo3405 );
end Other__carpat__part565_behav;
