--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1958 is 
  Port (
    lo4385: in std_logic;
    n26426: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1958;

architecture Other__ucsb_152_tap_fir__part1958_behav of Other__ucsb_152_tap_fir__part1958 is
begin
    n26426 <= ( lo4385 );
end Other__ucsb_152_tap_fir__part1958_behav;
