--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part94 is 
  Port (
    lo080: in std_logic;
    po186: inout std_logic
  );
end Cookbook__lc_mult_signed__part94;

architecture Cookbook__lc_mult_signed__part94_behav of Cookbook__lc_mult_signed__part94 is
begin
    po186 <= ( lo080 );
end Cookbook__lc_mult_signed__part94_behav;
