--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part58 is 
  Port (
    pi1153: in std_logic;
    n72271_1: inout std_logic
  );
end Other__ray__part58;

architecture Other__ray__part58_behav of Other__ray__part58 is
begin
    n72271_1 <= ( pi1153 );
end Other__ray__part58_behav;
