--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part156 is 
  Port (
    pi1064: in std_logic;
    n31969: inout std_logic
  );
end Other__carpat__part156;

architecture Other__carpat__part156_behav of Other__carpat__part156 is
begin
    n31969 <= ( pi1064 );
end Other__carpat__part156_behav;
