--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part18 is 
  Port (
    lo0479: in std_logic;
    n3409: inout std_logic
  );
end Other__sudoku_check__part18;

architecture Other__sudoku_check__part18_behav of Other__sudoku_check__part18 is
begin
    n3409 <= ( lo0479 );
end Other__sudoku_check__part18_behav;
