--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part548 is 
  Port (
    lo4133: in std_logic;
    n20680: inout std_logic
  );
end IWLS2005__des_perf__part548;

architecture IWLS2005__des_perf__part548_behav of IWLS2005__des_perf__part548 is
begin
    n20680 <= ( lo4133 );
end IWLS2005__des_perf__part548_behav;
