--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1033 is 
  Port (
    lo4402: in std_logic;
    n17499: inout std_logic
  );
end Other__sudoku_check__part1033;

architecture Other__sudoku_check__part1033_behav of Other__sudoku_check__part1033 is
begin
    n17499 <= ( lo4402 );
end Other__sudoku_check__part1033_behav;
