--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part90 is 
  Port (
    lo0278: in std_logic;
    n3985: inout std_logic
  );
end Other__fp_operators__part90;

architecture Other__fp_operators__part90_behav of Other__fp_operators__part90 is
begin
    n3985 <= ( lo0278 );
end Other__fp_operators__part90_behav;
