--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part458 is 
  Port (
    lo0527: in std_logic;
    n2934: inout std_logic
  );
end Cookbook__fec_check__part458;

architecture Cookbook__fec_check__part458_behav of Cookbook__fec_check__part458 is
begin
    n2934 <= ( lo0527 );
end Cookbook__fec_check__part458_behav;
