--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part29 is 
  Port (
    lo18: in std_logic;
    po05: inout std_logic
  );
end Cookbook__font_rom__part29;

architecture Cookbook__font_rom__part29_behav of Cookbook__font_rom__part29 is
begin
    po05 <= ( lo18 );
end Cookbook__font_rom__part29_behav;
