--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part34 is 
  Port (
    lo091: in std_logic;
    n753: inout std_logic
  );
end ISCAS__s13207__part34;

architecture ISCAS__s13207__part34_behav of ISCAS__s13207__part34 is
begin
    n753 <= ( lo091 );
end ISCAS__s13207__part34_behav;
