--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2247 is 
  Port (
    lo2347: in std_logic;
    n12034: inout std_logic
  );
end Cookbook__fec_check__part2247;

architecture Cookbook__fec_check__part2247_behav of Cookbook__fec_check__part2247 is
begin
    n12034 <= ( lo2347 );
end Cookbook__fec_check__part2247_behav;
