--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part615 is 
  Port (
    lo5003: in std_logic;
    n22114: inout std_logic
  );
end Other__carpat__part615;

architecture Other__carpat__part615_behav of Other__carpat__part615 is
begin
    n22114 <= ( lo5003 );
end Other__carpat__part615_behav;
