--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1814 is 
  Port (
    lo9060: in std_logic;
    po445: inout std_logic
  );
end Other__carpat__part1814;

architecture Other__carpat__part1814_behav of Other__carpat__part1814 is
begin
    po445 <= ( lo9060 );
end Other__carpat__part1814_behav;
