--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part23 is 
  Port (
    lo009: in std_logic;
    po020: inout std_logic
  );
end Cookbook__lc_mult_signed__part23;

architecture Cookbook__lc_mult_signed__part23_behav of Cookbook__lc_mult_signed__part23 is
begin
    po020 <= ( lo009 );
end Cookbook__lc_mult_signed__part23_behav;
