--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part146 is 
  Port (
    lo0215: in std_logic;
    n1374: inout std_logic
  );
end Cookbook__fec_check__part146;

architecture Cookbook__fec_check__part146_behav of Cookbook__fec_check__part146 is
begin
    n1374 <= ( lo0215 );
end Cookbook__fec_check__part146_behav;
