--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2204 is 
  Port (
    lo4867: in std_logic;
    n28926: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2204;

architecture Other__ucsb_152_tap_fir__part2204_behav of Other__ucsb_152_tap_fir__part2204 is
begin
    n28926 <= ( lo4867 );
end Other__ucsb_152_tap_fir__part2204_behav;
