--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part947 is 
  Port (
    lo10528: in std_logic;
    n69181_1: inout std_logic
  );
end Other__ray__part947;

architecture Other__ray__part947_behav of Other__ray__part947 is
begin
    n69181_1 <= ( lo10528 );
end Other__ray__part947_behav;
