--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1317 is 
  Port (
    lo3037: in std_logic;
    n19681: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1317;

architecture Other__ucsb_152_tap_fir__part1317_behav of Other__ucsb_152_tap_fir__part1317 is
begin
    n19681 <= ( lo3037 );
end Other__ucsb_152_tap_fir__part1317_behav;
