--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2145 is 
  Port (
    lo2214: in std_logic;
    n11369: inout std_logic
  );
end Cookbook__fec_check__part2145;

architecture Cookbook__fec_check__part2145_behav of Cookbook__fec_check__part2145 is
begin
    n11369 <= ( lo2214 );
end Cookbook__fec_check__part2145_behav;
