--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fifo__part6 is 
  Port (
    lo066: in std_logic;
    po14: inout std_logic
  );
end Cookbook__fifo__part6;

architecture Cookbook__fifo__part6_behav of Cookbook__fifo__part6 is
begin
    po14 <= ( lo066 );
end Cookbook__fifo__part6_behav;
