--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part119 is 
  Port (
    pi119: in std_logic;
    n10244_1: inout std_logic
  );
end Other__desperf__part119;

architecture Other__desperf__part119_behav of Other__desperf__part119 is
begin
    n10244_1 <= ( pi119 );
end Other__desperf__part119_behav;
