--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__min_max__part15 is 
  Port (
    lo14: in std_logic;
    po01: inout std_logic
  );
end Cookbook__min_max__part15;

architecture Cookbook__min_max__part15_behav of Cookbook__min_max__part15 is
begin
    po01 <= ( lo14 );
end Cookbook__min_max__part15_behav;
