--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part66 is 
  Port (
    lo0969: in std_logic;
    n6983_1: inout std_logic
  );
end Other__ether__part66;

architecture Other__ether__part66_behav of Other__ether__part66 is
begin
    n6983_1 <= ( lo0969 );
end Other__ether__part66_behav;
