--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part715 is 
  Port (
    lo06372: in std_logic;
    n47636: inout std_logic
  );
end Other__ray__part715;

architecture Other__ray__part715_behav of Other__ray__part715 is
begin
    n47636 <= ( lo06372 );
end Other__ray__part715_behav;
