--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part532 is 
  Port (
    lo0601: in std_logic;
    n3304: inout std_logic
  );
end Cookbook__fec_check__part532;

architecture Cookbook__fec_check__part532_behav of Cookbook__fec_check__part532 is
begin
    n3304 <= ( lo0601 );
end Cookbook__fec_check__part532_behav;
