--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part0 is 
  Port (
    pi00: in std_logic;
    n544328: inout std_logic
  );
end IWLS2005__leon3mp__part0;

architecture IWLS2005__leon3mp__part0_behav of IWLS2005__leon3mp__part0 is
begin
    n544328 <= ( pi00 );
end IWLS2005__leon3mp__part0_behav;
