--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part37 is 
  Port (
    lo161: in std_logic;
    po44: inout std_logic
  );
end IWLS2005__systemcdes__part37;

architecture IWLS2005__systemcdes__part37_behav of IWLS2005__systemcdes__part37 is
begin
    po44 <= ( lo161 );
end IWLS2005__systemcdes__part37_behav;
