--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part505 is 
  Port (
    lo3154: in std_logic;
    n9969: inout std_logic
  );
end Other__sudoku_check__part505;

architecture Other__sudoku_check__part505_behav of Other__sudoku_check__part505 is
begin
    n9969 <= ( lo3154 );
end Other__sudoku_check__part505_behav;
