--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part1 is 
  Port (
    lo00: in std_logic;
    po00: inout std_logic
  );
end Other__idxlat03n_m12__part1;

architecture Other__idxlat03n_m12__part1_behav of Other__idxlat03n_m12__part1 is
begin
    po00 <= ( lo00 );
end Other__idxlat03n_m12__part1_behav;
