--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part295 is 
  Port (
    pi1576: in std_logic;
    n46754_1: inout std_logic
  );
end Other__carpat__part295;

architecture Other__carpat__part295_behav of Other__carpat__part295 is
begin
    n46754_1 <= ( pi1576 );
end Other__carpat__part295_behav;
