--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1274 is 
  Port (
    lo2939: in std_logic;
    n19236: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1274;

architecture Other__ucsb_152_tap_fir__part1274_behav of Other__ucsb_152_tap_fir__part1274 is
begin
    n19236 <= ( lo2939 );
end Other__ucsb_152_tap_fir__part1274_behav;
