--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part545 is 
  Port (
    lo3194: in std_logic;
    n10369: inout std_logic
  );
end Other__sudoku_check__part545;

architecture Other__sudoku_check__part545_behav of Other__sudoku_check__part545 is
begin
    n10369 <= ( lo3194 );
end Other__sudoku_check__part545_behav;
