--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part31 is 
  Port (
    lo20: in std_logic;
    po03: inout std_logic
  );
end Cookbook__font_rom__part31;

architecture Cookbook__font_rom__part31_behav of Cookbook__font_rom__part31 is
begin
    po03 <= ( lo20 );
end Cookbook__font_rom__part31_behav;
