--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part202 is 
  Port (
    lo03246: in std_logic;
    po0923: inout std_logic
  );
end Other__ray__part202;

architecture Other__ray__part202_behav of Other__ray__part202 is
begin
    po0923 <= ( lo03246 );
end Other__ray__part202_behav;
