--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part213 is 
  Port (
    lo0512: in std_logic;
    n7136: inout std_logic
  );
end Other__ucsb_152_tap_fir__part213;

architecture Other__ucsb_152_tap_fir__part213_behav of Other__ucsb_152_tap_fir__part213 is
begin
    n7136 <= ( lo0512 );
end Other__ucsb_152_tap_fir__part213_behav;
