--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s382__part5 is 
  Port (
    lo07: in std_logic;
    po4: inout std_logic
  );
end IWLS93__s382__part5;

architecture IWLS93__s382__part5_behav of IWLS93__s382__part5 is
begin
    po4 <= ( not lo07 );
end IWLS93__s382__part5_behav;
