--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part50 is 
  Port (
    lo217: in std_logic;
    po33: inout std_logic
  );
end Cookbook__gearbox_67_40__part50;

architecture Cookbook__gearbox_67_40__part50_behav of Cookbook__gearbox_67_40__part50 is
begin
    po33 <= ( lo217 );
end Cookbook__gearbox_67_40__part50_behav;
