--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1270 is 
  Port (
    lo1339: in std_logic;
    n6994: inout std_logic
  );
end Cookbook__fec_check__part1270;

architecture Cookbook__fec_check__part1270_behav of Cookbook__fec_check__part1270 is
begin
    n6994 <= ( lo1339 );
end Cookbook__fec_check__part1270_behav;
