--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part21 is 
  Port (
    lo007: in std_logic;
    po022: inout std_logic
  );
end Cookbook__lc_mult_signed__part21;

architecture Cookbook__lc_mult_signed__part21_behav of Cookbook__lc_mult_signed__part21 is
begin
    po022 <= ( lo007 );
end Cookbook__lc_mult_signed__part21_behav;
