--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part18 is 
  Port (
    lo0005: in std_logic;
    po0005: inout std_logic
  );
end Other__ucsb_152_tap_fir__part18;

architecture Other__ucsb_152_tap_fir__part18_behav of Other__ucsb_152_tap_fir__part18 is
begin
    po0005 <= ( lo0005 );
end Other__ucsb_152_tap_fir__part18_behav;
