--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part56 is 
  Port (
    lo86: in std_logic;
    po13: inout std_logic
  );
end Cookbook__mlab_dcfifo__part56;

architecture Cookbook__mlab_dcfifo__part56_behav of Cookbook__mlab_dcfifo__part56 is
begin
    po13 <= ( lo86 );
end Cookbook__mlab_dcfifo__part56_behav;
