--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part74 is 
  Port (
    pi129: in std_logic;
    n43960: inout std_logic
  );
end IWLS2005__des_perf__part74;

architecture IWLS2005__des_perf__part74_behav of IWLS2005__des_perf__part74 is
begin
    n43960 <= ( pi129 );
end IWLS2005__des_perf__part74_behav;
