--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part299 is 
  Port (
    lo0368: in std_logic;
    n2139: inout std_logic
  );
end Cookbook__fec_check__part299;

architecture Cookbook__fec_check__part299_behav of Cookbook__fec_check__part299 is
begin
    n2139 <= ( lo0368 );
end Cookbook__fec_check__part299_behav;
