--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1476 is 
  Port (
    lo8107: in std_logic;
    n44584_1: inout std_logic
  );
end Other__carpat__part1476;

architecture Other__carpat__part1476_behav of Other__carpat__part1476 is
begin
    n44584_1 <= ( lo8107 );
end Other__carpat__part1476_behav;
