--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part81 is 
  Port (
    lo0662: in std_logic;
    n3584: inout std_logic
  );
end ISCAS__s38417__part81;

architecture ISCAS__s38417__part81_behav of ISCAS__s38417__part81 is
begin
    n3584 <= ( lo0662 );
end ISCAS__s38417__part81_behav;
