--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part47 is 
  Port (
    lo47: in std_logic;
    po39: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part47;

architecture Cookbook__x4_decoder_8b10b__part47_behav of Cookbook__x4_decoder_8b10b__part47 is
begin
    po39 <= ( lo47 );
end Cookbook__x4_decoder_8b10b__part47_behav;
