--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part52 is 
  Port (
    lo0222: in std_logic;
    n2327: inout std_logic
  );
end Other__cfft__part52;

architecture Other__cfft__part52_behav of Other__cfft__part52 is
begin
    n2327 <= ( lo0222 );
end Other__cfft__part52_behav;
