--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part162 is 
  Port (
    lo0042: in std_logic;
    po42: inout std_logic
  );
end Other__desperf__part162;

architecture Other__desperf__part162_behav of Other__desperf__part162 is
begin
    po42 <= ( lo0042 );
end Other__desperf__part162_behav;
