--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part825 is 
  Port (
    lo06584: in std_logic;
    n49256_1: inout std_logic
  );
end Other__ray__part825;

architecture Other__ray__part825_behav of Other__ray__part825 is
begin
    n49256_1 <= ( lo06584 );
end Other__ray__part825_behav;
