--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2190 is 
  Port (
    lo2259: in std_logic;
    n11594: inout std_logic
  );
end Cookbook__fec_check__part2190;

architecture Cookbook__fec_check__part2190_behav of Cookbook__fec_check__part2190 is
begin
    n11594 <= ( lo2259 );
end Cookbook__fec_check__part2190_behav;
