--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1411 is 
  Port (
    lo4780: in std_logic;
    n19389_1: inout std_logic
  );
end Other__sudoku_check__part1411;

architecture Other__sudoku_check__part1411_behav of Other__sudoku_check__part1411 is
begin
    n19389_1 <= ( lo4780 );
end Other__sudoku_check__part1411_behav;
