--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1353 is 
  Port (
    lo3121: in std_logic;
    n20141: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1353;

architecture Other__ucsb_152_tap_fir__part1353_behav of Other__ucsb_152_tap_fir__part1353 is
begin
    n20141 <= ( lo3121 );
end Other__ucsb_152_tap_fir__part1353_behav;
