--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1154 is 
  Port (
    lo5312: in std_logic;
    n26395: inout std_logic
  );
end IWLS2005__des_perf__part1154;

architecture IWLS2005__des_perf__part1154_behav of IWLS2005__des_perf__part1154 is
begin
    n26395 <= ( lo5312 );
end IWLS2005__des_perf__part1154_behav;
