--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part748 is 
  Port (
    lo4472: in std_logic;
    n22620: inout std_logic
  );
end IWLS2005__des_perf__part748;

architecture IWLS2005__des_perf__part748_behav of IWLS2005__des_perf__part748 is
begin
    n22620 <= ( lo4472 );
end IWLS2005__des_perf__part748_behav;
