--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2640 is 
  Port (
    lo7925: in std_logic;
    n39410_1: inout std_logic
  );
end IWLS2005__des_perf__part2640;

architecture IWLS2005__des_perf__part2640_behav of IWLS2005__des_perf__part2640 is
begin
    n39410_1 <= ( lo7925 );
end IWLS2005__des_perf__part2640_behav;
