--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1064 is 
  Port (
    lo10976: in std_logic;
    n73346_1: inout std_logic
  );
end Other__ray__part1064;

architecture Other__ray__part1064_behav of Other__ray__part1064 is
begin
    n73346_1 <= ( lo10976 );
end Other__ray__part1064_behav;
