--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part8 is 
  Port (
    pi12: in std_logic;
    n419: inout std_logic
  );
end LGSynth91__s38417__part8;

architecture LGSynth91__s38417__part8_behav of LGSynth91__s38417__part8 is
begin
    n419 <= ( pi12 );
end LGSynth91__s38417__part8_behav;
