--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx_crc__part6 is 
  Port (
    lo136: in std_logic;
    po0: inout std_logic
  );
end Cookbook__lane_rx_crc__part6;

architecture Cookbook__lane_rx_crc__part6_behav of Cookbook__lane_rx_crc__part6 is
begin
    po0 <= ( lo136 );
end Cookbook__lane_rx_crc__part6_behav;
