--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part94 is 
  Port (
    pi0504: in std_logic;
    n43066_1: inout std_logic
  );
end Other__radar__part94;

architecture Other__radar__part94_behav of Other__radar__part94 is
begin
    n43066_1 <= ( pi0504 );
end Other__radar__part94_behav;
