--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part605 is 
  Port (
    lo4215: in std_logic;
    n21335: inout std_logic
  );
end IWLS2005__des_perf__part605;

architecture IWLS2005__des_perf__part605_behav of IWLS2005__des_perf__part605 is
begin
    n21335 <= ( lo4215 );
end IWLS2005__des_perf__part605_behav;
