--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1095 is 
  Port (
    lo5171: in std_logic;
    n26155: inout std_logic
  );
end IWLS2005__des_perf__part1095;

architecture IWLS2005__des_perf__part1095_behav of IWLS2005__des_perf__part1095 is
begin
    n26155 <= ( lo5171 );
end IWLS2005__des_perf__part1095_behav;
