--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part254 is 
  Port (
    lo432: in std_logic;
    n1497: inout std_logic
  );
end Other__fpu__part254;

architecture Other__fpu__part254_behav of Other__fpu__part254 is
begin
    n1497 <= ( lo432 );
end Other__fpu__part254_behav;
