--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part293 is 
  Port (
    lo1142: in std_logic;
    n6195: inout std_logic
  );
end IWLS2005__des_perf__part293;

architecture IWLS2005__des_perf__part293_behav of IWLS2005__des_perf__part293 is
begin
    n6195 <= ( lo1142 );
end IWLS2005__des_perf__part293_behav;
