--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part24 is 
  Port (
    lo00431: in std_logic;
    po18: inout std_logic
  );
end IWLS2005__vga_lcd__part24;

architecture IWLS2005__vga_lcd__part24_behav of IWLS2005__vga_lcd__part24 is
begin
    po18 <= ( lo00431 );
end IWLS2005__vga_lcd__part24_behav;
