--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part57 is 
  Port (
    lo120: in std_logic;
    po016: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part57;

architecture Cookbook__soft_ecc_ram_64bit__part57_behav of Cookbook__soft_ecc_ram_64bit__part57 is
begin
    po016 <= ( lo120 );
end Cookbook__soft_ecc_ram_64bit__part57_behav;
