--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part55 is 
  Port (
    pi055: in std_logic;
    n43915_1: inout std_logic
  );
end IWLS2005__des_perf__part55;

architecture IWLS2005__des_perf__part55_behav of IWLS2005__des_perf__part55 is
begin
    n43915_1 <= ( pi055 );
end IWLS2005__des_perf__part55_behav;
