--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part102 is 
  Port (
    lo0723: in std_logic;
    n3889: inout std_logic
  );
end ISCAS__s38417__part102;

architecture ISCAS__s38417__part102_behav of ISCAS__s38417__part102 is
begin
    n3889 <= ( lo0723 );
end ISCAS__s38417__part102_behav;
