--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part249 is 
  Port (
    lo1028: in std_logic;
    n5625: inout std_logic
  );
end IWLS2005__des_perf__part249;

architecture IWLS2005__des_perf__part249_behav of IWLS2005__des_perf__part249 is
begin
    n5625 <= ( lo1028 );
end IWLS2005__des_perf__part249_behav;
