--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part774 is 
  Port (
    lo06501: in std_logic;
    n48831: inout std_logic
  );
end Other__ray__part774;

architecture Other__ray__part774_behav of Other__ray__part774 is
begin
    n48831 <= ( lo06501 );
end Other__ray__part774_behav;
