--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part447 is 
  Port (
    lo1652: in std_logic;
    n9369_1: inout std_logic
  );
end Cookbook__ucrypt__part447;

architecture Cookbook__ucrypt__part447_behav of Cookbook__ucrypt__part447 is
begin
    n9369_1 <= ( lo1652 );
end Cookbook__ucrypt__part447_behav;
