--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part412 is 
  Port (
    lo0098: in std_logic;
    po071: inout std_logic
  );
end Other__carpat__part412;

architecture Other__carpat__part412_behav of Other__carpat__part412 is
begin
    po071 <= ( lo0098 );
end Other__carpat__part412_behav;
