--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part3 is 
  Port (
    lo059: in std_logic;
    n929: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part3;

architecture Cookbook__soft_ecc_ram_64bit__part3_behav of Cookbook__soft_ecc_ram_64bit__part3 is
begin
    n929 <= ( lo059 );
end Cookbook__soft_ecc_ram_64bit__part3_behav;
