--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part44 is 
  Port (
    lo211: in std_logic;
    po39: inout std_logic
  );
end Cookbook__gearbox_67_40__part44;

architecture Cookbook__gearbox_67_40__part44_behav of Cookbook__gearbox_67_40__part44 is
begin
    po39 <= ( lo211 );
end Cookbook__gearbox_67_40__part44_behav;
