--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1293 is 
  Port (
    lo3009: in std_logic;
    n19536: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1293;

architecture Other__ucsb_152_tap_fir__part1293_behav of Other__ucsb_152_tap_fir__part1293 is
begin
    n19536 <= ( lo3009 );
end Other__ucsb_152_tap_fir__part1293_behav;
