--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part148 is 
  Port (
    lo0979: in std_logic;
    n624: inout std_logic
  );
end IWLS93__s38417__part148;

architecture IWLS93__s38417__part148_behav of IWLS93__s38417__part148 is
begin
    n624 <= ( not lo0979 );
end IWLS93__s38417__part148_behav;
