--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part50 is 
  Port (
    lo16030: in std_logic;
    po36: inout std_logic
  );
end IWLS2005__vga_lcd__part50;

architecture IWLS2005__vga_lcd__part50_behav of IWLS2005__vga_lcd__part50 is
begin
    po36 <= ( lo16030 );
end IWLS2005__vga_lcd__part50_behav;
