--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1053 is 
  Port (
    lo5087: in std_logic;
    n25255: inout std_logic
  );
end IWLS2005__des_perf__part1053;

architecture IWLS2005__des_perf__part1053_behav of IWLS2005__des_perf__part1053 is
begin
    n25255 <= ( lo5087 );
end IWLS2005__des_perf__part1053_behav;
