--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2416 is 
  Port (
    lo5329: in std_logic;
    n31236: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2416;

architecture Other__ucsb_152_tap_fir__part2416_behav of Other__ucsb_152_tap_fir__part2416 is
begin
    n31236 <= ( lo5329 );
end Other__ucsb_152_tap_fir__part2416_behav;
