--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part689 is 
  Port (
    lo06186: in std_logic;
    po1862,po1898: inout std_logic
  );
end Other__ray__part689;

architecture Other__ray__part689_behav of Other__ray__part689 is
begin
    po1862 <= ( lo06186 );
    po1898 <= ( lo06186 );
end Other__ray__part689_behav;
