--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part17 is 
  Port (
    lo055: in std_logic;
    po15: inout std_logic
  );
end Cookbook__fec_gen__part17;

architecture Cookbook__fec_gen__part17_behav of Cookbook__fec_gen__part17 is
begin
    po15 <= ( lo055 );
end Cookbook__fec_gen__part17_behav;
