--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2487 is 
  Port (
    lo5501: in std_logic;
    n32091_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2487;

architecture Other__ucsb_152_tap_fir__part2487_behav of Other__ucsb_152_tap_fir__part2487 is
begin
    n32091_1 <= ( lo5501 );
end Other__ucsb_152_tap_fir__part2487_behav;
