--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part950 is 
  Port (
    lo4319: in std_logic;
    n17084: inout std_logic
  );
end Other__sudoku_check__part950;

architecture Other__sudoku_check__part950_behav of Other__sudoku_check__part950 is
begin
    n17084 <= ( lo4319 );
end Other__sudoku_check__part950_behav;
