--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part51 is 
  Port (
    lo50: in std_logic;
    po50: inout std_logic
  );
end Other__idxlat00n_m12__part51;

architecture Other__idxlat00n_m12__part51_behav of Other__idxlat00n_m12__part51 is
begin
    po50 <= ( lo50 );
end Other__idxlat00n_m12__part51_behav;
