--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1562 is 
  Port (
    lo3533: in std_logic;
    n22246: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1562;

architecture Other__ucsb_152_tap_fir__part1562_behav of Other__ucsb_152_tap_fir__part1562 is
begin
    n22246 <= ( lo3533 );
end Other__ucsb_152_tap_fir__part1562_behav;
