--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part880 is 
  Port (
    lo07277: in std_logic;
    n50431_1: inout std_logic
  );
end Other__ray__part880;

architecture Other__ray__part880_behav of Other__ray__part880 is
begin
    n50431_1 <= ( lo07277 );
end Other__ray__part880_behav;
