--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part11 is 
  Port (
    pi011: in std_logic;
    n9704_1: inout std_logic
  );
end Other__desperf__part11;

architecture Other__desperf__part11_behav of Other__desperf__part11 is
begin
    n9704_1 <= ( pi011 );
end Other__desperf__part11_behav;
