--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1059 is 
  Port (
    lo7152: in std_logic;
    n37944_1: inout std_logic
  );
end Other__carpat__part1059;

architecture Other__carpat__part1059_behav of Other__carpat__part1059 is
begin
    n37944_1 <= ( lo7152 );
end Other__carpat__part1059_behav;
