--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part535 is 
  Port (
    lo3184: in std_logic;
    n10269: inout std_logic
  );
end Other__sudoku_check__part535;

architecture Other__sudoku_check__part535_behav of Other__sudoku_check__part535 is
begin
    n10269 <= ( lo3184 );
end Other__sudoku_check__part535_behav;
