--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2185 is 
  Port (
    lo4848: in std_logic;
    n28831: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2185;

architecture Other__ucsb_152_tap_fir__part2185_behav of Other__ucsb_152_tap_fir__part2185 is
begin
    n28831 <= ( lo4848 );
end Other__ucsb_152_tap_fir__part2185_behav;
