--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1916 is 
  Port (
    lo1985: in std_logic;
    n10224: inout std_logic
  );
end Cookbook__fec_check__part1916;

architecture Cookbook__fec_check__part1916_behav of Cookbook__fec_check__part1916 is
begin
    n10224 <= ( lo1985 );
end Cookbook__fec_check__part1916_behav;
