--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part3 is 
  Port (
    lo301: in std_logic;
    n1683: inout std_logic
  );
end Cookbook__lane_tx__part3;

architecture Cookbook__lane_tx__part3_behav of Cookbook__lane_tx__part3 is
begin
    n1683 <= ( lo301 );
end Cookbook__lane_tx__part3_behav;
