--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1139 is 
  Port (
    lo12986: in std_logic;
    po1964,po1998,po2144,po2178,n51661_1: inout std_logic
  );
end Other__ray__part1139;

architecture Other__ray__part1139_behav of Other__ray__part1139 is
begin
    po1964 <= ( lo12986 );
    po1998 <= ( lo12986 );
    po2144 <= ( lo12986 );
    po2178 <= ( lo12986 );
    n51661_1 <= ( lo12986 );
end Other__ray__part1139_behav;
