--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1250 is 
  Port (
    lo4619: in std_logic;
    n18584: inout std_logic
  );
end Other__sudoku_check__part1250;

architecture Other__sudoku_check__part1250_behav of Other__sudoku_check__part1250 is
begin
    n18584 <= ( lo4619 );
end Other__sudoku_check__part1250_behav;
