--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1455 is 
  Port (
    lo4824: in std_logic;
    n19609_1: inout std_logic
  );
end Other__sudoku_check__part1455;

architecture Other__sudoku_check__part1455_behav of Other__sudoku_check__part1455 is
begin
    n19609_1 <= ( lo4824 );
end Other__sudoku_check__part1455_behav;
