--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part20 is 
  Port (
    lo019: in std_logic;
    n405_1: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part20;

architecture Cookbook__approx_fp_invsqrt__part20_behav of Cookbook__approx_fp_invsqrt__part20 is
begin
    n405_1 <= ( lo019 );
end Cookbook__approx_fp_invsqrt__part20_behav;
