--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part691 is 
  Port (
    lo06188: in std_logic;
    po1864,po1900: inout std_logic
  );
end Other__ray__part691;

architecture Other__ray__part691_behav of Other__ray__part691 is
begin
    po1864 <= ( lo06188 );
    po1900 <= ( lo06188 );
end Other__ray__part691_behav;
