--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1212 is 
  Port (
    lo4581: in std_logic;
    n18394: inout std_logic
  );
end Other__sudoku_check__part1212;

architecture Other__sudoku_check__part1212_behav of Other__sudoku_check__part1212 is
begin
    n18394 <= ( lo4581 );
end Other__sudoku_check__part1212_behav;
