--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1542 is 
  Port (
    lo1611: in std_logic;
    n8354: inout std_logic
  );
end Cookbook__fec_check__part1542;

architecture Cookbook__fec_check__part1542_behav of Cookbook__fec_check__part1542 is
begin
    n8354 <= ( lo1611 );
end Cookbook__fec_check__part1542_behav;
