--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1061 is 
  Port (
    lo4430: in std_logic;
    n17639: inout std_logic
  );
end Other__sudoku_check__part1061;

architecture Other__sudoku_check__part1061_behav of Other__sudoku_check__part1061 is
begin
    n17639 <= ( lo4430 );
end Other__sudoku_check__part1061_behav;
