--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part388 is 
  Port (
    lo0002: in std_logic;
    po002: inout std_logic
  );
end Other__carpat__part388;

architecture Other__carpat__part388_behav of Other__carpat__part388 is
begin
    po002 <= ( lo0002 );
end Other__carpat__part388_behav;
