--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1310 is 
  Port (
    lo4679: in std_logic;
    n18884: inout std_logic
  );
end Other__sudoku_check__part1310;

architecture Other__sudoku_check__part1310_behav of Other__sudoku_check__part1310 is
begin
    n18884 <= ( lo4679 );
end Other__sudoku_check__part1310_behav;
