--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part619 is 
  Port (
    lo4260: in std_logic;
    n21695: inout std_logic
  );
end IWLS2005__des_perf__part619;

architecture IWLS2005__des_perf__part619_behav of IWLS2005__des_perf__part619 is
begin
    n21695 <= ( lo4260 );
end IWLS2005__des_perf__part619_behav;
