--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1581 is 
  Port (
    lo3580: in std_logic;
    n22486: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1581;

architecture Other__ucsb_152_tap_fir__part1581_behav of Other__ucsb_152_tap_fir__part1581 is
begin
    n22486 <= ( lo3580 );
end Other__ucsb_152_tap_fir__part1581_behav;
