--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part908 is 
  Port (
    lo4817: in std_logic;
    n24025: inout std_logic
  );
end IWLS2005__des_perf__part908;

architecture IWLS2005__des_perf__part908_behav of IWLS2005__des_perf__part908 is
begin
    n24025 <= ( lo4817 );
end IWLS2005__des_perf__part908_behav;
