--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part799 is 
  Port (
    lo4168: in std_logic;
    n14529: inout std_logic
  );
end Other__sudoku_check__part799;

architecture Other__sudoku_check__part799_behav of Other__sudoku_check__part799 is
begin
    n14529 <= ( lo4168 );
end Other__sudoku_check__part799_behav;
