--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part728 is 
  Port (
    lo5454: in std_logic;
    n25759: inout std_logic
  );
end Other__carpat__part728;

architecture Other__carpat__part728_behav of Other__carpat__part728 is
begin
    n25759 <= ( lo5454 );
end Other__carpat__part728_behav;
