--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part5 is 
  Port (
    pi07: in std_logic;
    po28: inout std_logic
  );
end IWLS2005__leon3__part5;

architecture IWLS2005__leon3__part5_behav of IWLS2005__leon3__part5 is
begin
    po28 <= ( not pi07 );
end IWLS2005__leon3__part5_behav;
