--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2620 is 
  Port (
    lo5747: in std_logic;
    n33321_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2620;

architecture Other__ucsb_152_tap_fir__part2620_behav of Other__ucsb_152_tap_fir__part2620 is
begin
    n33321_1 <= ( lo5747 );
end Other__ucsb_152_tap_fir__part2620_behav;
