--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part446 is 
  Port (
    lo05918: in std_logic;
    po1384,po1449,po1715,po1784: inout std_logic
  );
end Other__ray__part446;

architecture Other__ray__part446_behav of Other__ray__part446 is
begin
    po1384 <= ( lo05918 );
    po1449 <= ( lo05918 );
    po1715 <= ( lo05918 );
    po1784 <= ( lo05918 );
end Other__ray__part446_behav;
