--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1107 is 
  Port (
    lo7313: in std_logic;
    po740: inout std_logic
  );
end Other__carpat__part1107;

architecture Other__carpat__part1107_behav of Other__carpat__part1107 is
begin
    po740 <= ( lo7313 );
end Other__carpat__part1107_behav;
