--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_crossing_fifo is 
  Port (
    pi0,lo0: in std_logic;
    po0,n5_1: inout std_logic
  );
end Cookbook__clock_crossing_fifo;

architecture Cookbook__clock_crossing_fifo_behav of Cookbook__clock_crossing_fifo is
signal n5,n6: std_logic;
begin
    n5 <= not (( lo0 and not pi0 ));
    n6 <= ( lo0 and not pi0 );
    n5_1 <= not (( not n6 and not n5 ));
    po0 <= ( lo0 );
end Cookbook__clock_crossing_fifo_behav;
