--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part94 is 
  Port (
    lo3202: in std_logic;
    n16589_1: inout std_logic
  );
end IWLS2005__pci_bridge32__part94;

architecture IWLS2005__pci_bridge32__part94_behav of IWLS2005__pci_bridge32__part94 is
begin
    n16589_1 <= ( lo3202 );
end IWLS2005__pci_bridge32__part94_behav;
