--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part82 is 
  Port (
    pi082: in std_logic;
    n2152: inout std_logic
  );
end Other__fpu__part82;

architecture Other__fpu__part82_behav of Other__fpu__part82 is
begin
    n2152 <= ( pi082 );
end Other__fpu__part82_behav;
