--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part114 is 
  Port (
    lo184897: in std_logic;
    n924536: inout std_logic
  );
end IWLS2005__leon3__part114;

architecture IWLS2005__leon3__part114_behav of IWLS2005__leon3__part114 is
begin
    n924536 <= ( lo184897 );
end IWLS2005__leon3__part114_behav;
