--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part452 is 
  Port (
    lo0521: in std_logic;
    n2904: inout std_logic
  );
end Cookbook__fec_check__part452;

architecture Cookbook__fec_check__part452_behav of Cookbook__fec_check__part452 is
begin
    n2904 <= ( lo0521 );
end Cookbook__fec_check__part452_behav;
