--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s6669__part9 is 
  Port (
    pi59: in std_logic;
    n807: inout std_logic
  );
end ISCAS__s6669__part9;

architecture ISCAS__s6669__part9_behav of ISCAS__s6669__part9 is
begin
    n807 <= ( pi59 );
end ISCAS__s6669__part9_behav;
