--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part487 is 
  Port (
    lo05959: in std_logic;
    po1425,po1474,po1758,po1820: inout std_logic
  );
end Other__ray__part487;

architecture Other__ray__part487_behav of Other__ray__part487 is
begin
    po1425 <= ( lo05959 );
    po1474 <= ( lo05959 );
    po1758 <= ( lo05959 );
    po1820 <= ( lo05959 );
end Other__ray__part487_behav;
