--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part147 is 
  Port (
    lo0980: in std_logic;
    n5174_1: inout std_logic
  );
end LGSynth91__s38417__part147;

architecture LGSynth91__s38417__part147_behav of LGSynth91__s38417__part147 is
begin
    n5174_1 <= ( lo0980 );
end LGSynth91__s38417__part147_behav;
