--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part195 is 
  Port (
    lo299: in std_logic;
    n1007: inout std_logic
  );
end Other__fpu__part195;

architecture Other__fpu__part195_behav of Other__fpu__part195 is
begin
    n1007 <= ( lo299 );
end Other__fpu__part195_behav;
