--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part969 is 
  Port (
    lo4338: in std_logic;
    n17179: inout std_logic
  );
end Other__sudoku_check__part969;

architecture Other__sudoku_check__part969_behav of Other__sudoku_check__part969 is
begin
    n17179 <= ( lo4338 );
end Other__sudoku_check__part969_behav;
