--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part882 is 
  Port (
    lo4728: in std_logic;
    n23400: inout std_logic
  );
end IWLS2005__des_perf__part882;

architecture IWLS2005__des_perf__part882_behav of IWLS2005__des_perf__part882 is
begin
    n23400 <= ( lo4728 );
end IWLS2005__des_perf__part882_behav;
