--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1664 is 
  Port (
    lo6369: in std_logic;
    n32085_1: inout std_logic
  );
end IWLS2005__des_perf__part1664;

architecture IWLS2005__des_perf__part1664_behav of IWLS2005__des_perf__part1664 is
begin
    n32085_1 <= ( lo6369 );
end IWLS2005__des_perf__part1664_behav;
