--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1070 is 
  Port (
    lo5111: in std_logic;
    n25460: inout std_logic
  );
end IWLS2005__des_perf__part1070;

architecture IWLS2005__des_perf__part1070_behav of IWLS2005__des_perf__part1070 is
begin
    n25460 <= ( lo5111 );
end IWLS2005__des_perf__part1070_behav;
