--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part373 is 
  Port (
    lo05693: in std_logic;
    po6085,po6136,po6391,po6442: inout std_logic
  );
end Other__ray__part373;

architecture Other__ray__part373_behav of Other__ray__part373 is
begin
    po6085 <= ( lo05693 );
    po6136 <= ( lo05693 );
    po6391 <= ( lo05693 );
    po6442 <= ( lo05693 );
end Other__ray__part373_behav;
