--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part9 is 
  Port (
    pi09: in std_logic;
    n746887: inout std_logic
  );
end IWLS2005__leon2__part9;

architecture IWLS2005__leon2__part9_behav of IWLS2005__leon2__part9 is
begin
    n746887 <= ( pi09 );
end IWLS2005__leon2__part9_behav;
