--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2343 is 
  Port (
    lo7546: in std_logic;
    n37720_1: inout std_logic
  );
end IWLS2005__des_perf__part2343;

architecture IWLS2005__des_perf__part2343_behav of IWLS2005__des_perf__part2343 is
begin
    n37720_1 <= ( lo7546 );
end IWLS2005__des_perf__part2343_behav;
