--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part218 is 
  Port (
    lo0517: in std_logic;
    n7161: inout std_logic
  );
end Other__ucsb_152_tap_fir__part218;

architecture Other__ucsb_152_tap_fir__part218_behav of Other__ucsb_152_tap_fir__part218 is
begin
    n7161 <= ( lo0517 );
end Other__ucsb_152_tap_fir__part218_behav;
