--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1586 is 
  Port (
    lo1655: in std_logic;
    n8574: inout std_logic
  );
end Cookbook__fec_check__part1586;

architecture Cookbook__fec_check__part1586_behav of Cookbook__fec_check__part1586 is
begin
    n8574 <= ( lo1655 );
end Cookbook__fec_check__part1586_behav;
