--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1026 is 
  Port (
    lo5058: in std_logic;
    n25195: inout std_logic
  );
end IWLS2005__des_perf__part1026;

architecture IWLS2005__des_perf__part1026_behav of IWLS2005__des_perf__part1026 is
begin
    n25195 <= ( lo5058 );
end IWLS2005__des_perf__part1026_behav;
