--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1069 is 
  Port (
    lo5110: in std_logic;
    n25290: inout std_logic
  );
end IWLS2005__des_perf__part1069;

architecture IWLS2005__des_perf__part1069_behav of IWLS2005__des_perf__part1069 is
begin
    n25290 <= ( lo5110 );
end IWLS2005__des_perf__part1069_behav;
