--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part68 is 
  Port (
    pi0797: in std_logic;
    n24854: inout std_logic
  );
end Other__carpat__part68;

architecture Other__carpat__part68_behav of Other__carpat__part68 is
begin
    n24854 <= ( pi0797 );
end Other__carpat__part68_behav;
