--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_20__part15 is 
  Port (
    lo025: in std_logic;
    n722_1: inout std_logic
  );
end Cookbook__gearbox_66_20__part15;

architecture Cookbook__gearbox_66_20__part15_behav of Cookbook__gearbox_66_20__part15 is
begin
    n722_1 <= ( lo025 );
end Cookbook__gearbox_66_20__part15_behav;
