--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part489 is 
  Port (
    lo1824: in std_logic;
    n10379_1: inout std_logic
  );
end Cookbook__ucrypt__part489;

architecture Cookbook__ucrypt__part489_behav of Cookbook__ucrypt__part489 is
begin
    n10379_1 <= ( lo1824 );
end Cookbook__ucrypt__part489_behav;
