--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2927 is 
  Port (
    lo8240: in std_logic;
    n41395: inout std_logic
  );
end IWLS2005__des_perf__part2927;

architecture IWLS2005__des_perf__part2927_behav of IWLS2005__des_perf__part2927 is
begin
    n41395 <= ( lo8240 );
end IWLS2005__des_perf__part2927_behav;
