--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part199 is 
  Port (
    lo0796: in std_logic;
    n6120: inout std_logic
  );
end Other__fp_operators__part199;

architecture Other__fp_operators__part199_behav of Other__fp_operators__part199 is
begin
    n6120 <= ( lo0796 );
end Other__fp_operators__part199_behav;
