--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part31 is 
  Port (
    lo0022: in std_logic;
    n1369: inout std_logic
  );
end Cookbook__ucrypt__part31;

architecture Cookbook__ucrypt__part31_behav of Cookbook__ucrypt__part31 is
begin
    n1369 <= ( lo0022 );
end Cookbook__ucrypt__part31_behav;
