--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part46 is 
  Port (
    lo46: in std_logic;
    po43: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part46;

architecture Cookbook__x4_decoder_8b10b__part46_behav of Cookbook__x4_decoder_8b10b__part46 is
begin
    po43 <= ( lo46 );
end Cookbook__x4_decoder_8b10b__part46_behav;
