--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2806 is 
  Port (
    lo8119: in std_logic;
    n40885_1: inout std_logic
  );
end IWLS2005__des_perf__part2806;

architecture IWLS2005__des_perf__part2806_behav of IWLS2005__des_perf__part2806 is
begin
    n40885_1 <= ( lo8119 );
end IWLS2005__des_perf__part2806_behav;
