--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part306 is 
  Port (
    lo0375: in std_logic;
    n2174: inout std_logic
  );
end Cookbook__fec_check__part306;

architecture Cookbook__fec_check__part306_behav of Cookbook__fec_check__part306 is
begin
    n2174 <= ( lo0375 );
end Cookbook__fec_check__part306_behav;
