--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part808 is 
  Port (
    lo4581: in std_logic;
    n23200: inout std_logic
  );
end IWLS2005__des_perf__part808;

architecture IWLS2005__des_perf__part808_behav of IWLS2005__des_perf__part808 is
begin
    n23200 <= ( lo4581 );
end IWLS2005__des_perf__part808_behav;
