--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2140 is 
  Port (
    lo4746: in std_logic;
    n28231: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2140;

architecture Other__ucsb_152_tap_fir__part2140_behav of Other__ucsb_152_tap_fir__part2140 is
begin
    n28231 <= ( lo4746 );
end Other__ucsb_152_tap_fir__part2140_behav;
