--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1656 is 
  Port (
    lo8601: in std_logic;
    n48504_1: inout std_logic
  );
end Other__carpat__part1656;

architecture Other__carpat__part1656_behav of Other__carpat__part1656 is
begin
    n48504_1 <= ( lo8601 );
end Other__carpat__part1656_behav;
