--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part18 is 
  Port (
    lo83: in std_logic;
    po02: inout std_logic
  );
end Cookbook__gearbox_67_20__part18;

architecture Cookbook__gearbox_67_20__part18_behav of Cookbook__gearbox_67_20__part18 is
begin
    po02 <= ( lo83 );
end Cookbook__gearbox_67_20__part18_behav;
