--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part86 is 
  Port (
    lo0155: in std_logic;
    n1074: inout std_logic
  );
end Cookbook__fec_check__part86;

architecture Cookbook__fec_check__part86_behav of Cookbook__fec_check__part86 is
begin
    n1074 <= ( lo0155 );
end Cookbook__fec_check__part86_behav;
