--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part128 is 
  Port (
    lo0837: in std_logic;
    n5679_1: inout std_logic
  );
end IWLS93__s38417__part128;

architecture IWLS93__s38417__part128_behav of IWLS93__s38417__part128 is
begin
    n5679_1 <= ( lo0837 );
end IWLS93__s38417__part128_behav;
