--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part101 is 
  Port (
    pi101: in std_logic;
    n10154_1: inout std_logic
  );
end Other__desperf__part101;

architecture Other__desperf__part101_behav of Other__desperf__part101 is
begin
    n10154_1 <= ( pi101 );
end Other__desperf__part101_behav;
