--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1091 is 
  Port (
    lo2545: in std_logic;
    n17286: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1091;

architecture Other__ucsb_152_tap_fir__part1091_behav of Other__ucsb_152_tap_fir__part1091 is
begin
    n17286 <= ( lo2545 );
end Other__ucsb_152_tap_fir__part1091_behav;
