--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2544 is 
  Port (
    lo5607: in std_logic;
    n32621: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2544;

architecture Other__ucsb_152_tap_fir__part2544_behav of Other__ucsb_152_tap_fir__part2544 is
begin
    n32621 <= ( lo5607 );
end Other__ucsb_152_tap_fir__part2544_behav;
