--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part69 is 
  Port (
    lo17058: in std_logic;
    n85602: inout std_logic
  );
end IWLS2005__vga_lcd__part69;

architecture IWLS2005__vga_lcd__part69_behav of IWLS2005__vga_lcd__part69 is
begin
    n85602 <= ( lo17058 );
end IWLS2005__vga_lcd__part69_behav;
