--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part967 is 
  Port (
    lo4930: in std_logic;
    n24845: inout std_logic
  );
end IWLS2005__des_perf__part967;

architecture IWLS2005__des_perf__part967_behav of IWLS2005__des_perf__part967 is
begin
    n24845 <= ( lo4930 );
end IWLS2005__des_perf__part967_behav;
