--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part13 is 
  Port (
    pi13: in std_logic;
    n604: inout std_logic
  );
end ISCAS__s3384__part13;

architecture ISCAS__s3384__part13_behav of ISCAS__s3384__part13 is
begin
    n604 <= ( pi13 );
end ISCAS__s3384__part13_behav;
