--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part130 is 
  Port (
    lo0465: in std_logic;
    n4725: inout std_logic
  );
end Other__fp_operators__part130;

architecture Other__fp_operators__part130_behav of Other__fp_operators__part130 is
begin
    n4725 <= ( lo0465 );
end Other__fp_operators__part130_behav;
