--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part738 is 
  Port (
    lo0807: in std_logic;
    n4334: inout std_logic
  );
end Cookbook__fec_check__part738;

architecture Cookbook__fec_check__part738_behav of Cookbook__fec_check__part738 is
begin
    n4334 <= ( lo0807 );
end Cookbook__fec_check__part738_behav;
