--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_40__part42 is 
  Port (
    lo111: in std_logic;
    po01: inout std_logic
  );
end Cookbook__gearbox_66_40__part42;

architecture Cookbook__gearbox_66_40__part42_behav of Cookbook__gearbox_66_40__part42 is
begin
    po01 <= ( lo111 );
end Cookbook__gearbox_66_40__part42_behav;
