--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part15 is 
  Port (
    pi18: in std_logic;
    n122: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part15;

architecture Cookbook__ycbcr_to_rgb__part15_behav of Cookbook__ycbcr_to_rgb__part15 is
begin
    n122 <= ( pi18 );
end Cookbook__ycbcr_to_rgb__part15_behav;
