--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1924 is 
  Port (
    lo1993: in std_logic;
    n10264: inout std_logic
  );
end Cookbook__fec_check__part1924;

architecture Cookbook__fec_check__part1924_behav of Cookbook__fec_check__part1924 is
begin
    n10264 <= ( lo1993 );
end Cookbook__fec_check__part1924_behav;
