--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part24 is 
  Port (
    lo0041: in std_logic;
    n964: inout std_logic
  );
end IWLS93__s38417__part24;

architecture IWLS93__s38417__part24_behav of IWLS93__s38417__part24 is
begin
    n964 <= ( lo0041 );
end IWLS93__s38417__part24_behav;
