--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part81 is 
  Port (
    lo80: in std_logic;
    po80: inout std_logic
  );
end Other__idxlat03n_m12__part81;

architecture Other__idxlat03n_m12__part81_behav of Other__idxlat03n_m12__part81 is
begin
    po80 <= ( lo80 );
end Other__idxlat03n_m12__part81_behav;
