--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part58 is 
  Port (
    pi64: in std_logic;
    n869616: inout std_logic
  );
end IWLS2005__leon3__part58;

architecture IWLS2005__leon3__part58_behav of IWLS2005__leon3__part58 is
begin
    n869616 <= ( pi64 );
end IWLS2005__leon3__part58_behav;
