--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1847 is 
  Port (
    lo1916: in std_logic;
    n9879: inout std_logic
  );
end Cookbook__fec_check__part1847;

architecture Cookbook__fec_check__part1847_behav of Cookbook__fec_check__part1847 is
begin
    n9879 <= ( lo1916 );
end Cookbook__fec_check__part1847_behav;
