--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part235 is 
  Port (
    lo03506: in std_logic;
    n34751: inout std_logic
  );
end Other__ray__part235;

architecture Other__ray__part235_behav of Other__ray__part235 is
begin
    n34751 <= ( lo03506 );
end Other__ray__part235_behav;
