--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1497 is 
  Port (
    lo1566: in std_logic;
    n8129: inout std_logic
  );
end Cookbook__fec_check__part1497;

architecture Cookbook__fec_check__part1497_behav of Cookbook__fec_check__part1497 is
begin
    n8129 <= ( lo1566 );
end Cookbook__fec_check__part1497_behav;
