--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part253 is 
  Port (
    lo1126: in std_logic;
    n5179: inout std_logic
  );
end Other__desperf__part253;

architecture Other__desperf__part253_behav of Other__desperf__part253 is
begin
    n5179 <= ( lo1126 );
end Other__desperf__part253_behav;
