--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_dcfifo__part50 is 
  Port (
    lo74: in std_logic;
    po06: inout std_logic
  );
end Cookbook__mlab_dcfifo__part50;

architecture Cookbook__mlab_dcfifo__part50_behav of Cookbook__mlab_dcfifo__part50 is
begin
    po06 <= ( lo74 );
end Cookbook__mlab_dcfifo__part50_behav;
