--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part67 is 
  Port (
    lo17013: in std_logic;
    n85397_1: inout std_logic
  );
end IWLS2005__vga_lcd__part67;

architecture IWLS2005__vga_lcd__part67_behav of IWLS2005__vga_lcd__part67 is
begin
    n85397_1 <= ( lo17013 );
end IWLS2005__vga_lcd__part67_behav;
