--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part259 is 
  Port (
    lo03625: in std_logic;
    n36131: inout std_logic
  );
end Other__ray__part259;

architecture Other__ray__part259_behav of Other__ray__part259 is
begin
    n36131 <= ( lo03625 );
end Other__ray__part259_behav;
