--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part1 is 
  Port (
    pi073: in std_logic;
    n1431: inout std_logic
  );
end Other__mem__part1;

architecture Other__mem__part1_behav of Other__mem__part1 is
begin
    n1431 <= ( pi073 );
end Other__mem__part1_behav;
