--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1892 is 
  Port (
    lo1961: in std_logic;
    n10104: inout std_logic
  );
end Cookbook__fec_check__part1892;

architecture Cookbook__fec_check__part1892_behav of Cookbook__fec_check__part1892 is
begin
    n10104 <= ( lo1961 );
end Cookbook__fec_check__part1892_behav;
