--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part181 is 
  Port (
    lo0061: in std_logic;
    po61: inout std_logic
  );
end Other__desperf__part181;

architecture Other__desperf__part181_behav of Other__desperf__part181 is
begin
    po61 <= ( lo0061 );
end Other__desperf__part181_behav;
