--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1985 is 
  Port (
    lo2054: in std_logic;
    n10569: inout std_logic
  );
end Cookbook__fec_check__part1985;

architecture Cookbook__fec_check__part1985_behav of Cookbook__fec_check__part1985 is
begin
    n10569 <= ( lo2054 );
end Cookbook__fec_check__part1985_behav;
