--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2233 is 
  Port (
    lo7424: in std_logic;
    n37010_1: inout std_logic
  );
end IWLS2005__des_perf__part2233;

architecture IWLS2005__des_perf__part2233_behav of IWLS2005__des_perf__part2233 is
begin
    n37010_1 <= ( lo7424 );
end IWLS2005__des_perf__part2233_behav;
