--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2344 is 
  Port (
    lo5183: in std_logic;
    n30421: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2344;

architecture Other__ucsb_152_tap_fir__part2344_behav of Other__ucsb_152_tap_fir__part2344 is
begin
    n30421 <= ( lo5183 );
end Other__ucsb_152_tap_fir__part2344_behav;
