--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2107 is 
  Port (
    lo7253: in std_logic;
    n36190_1: inout std_logic
  );
end IWLS2005__des_perf__part2107;

architecture IWLS2005__des_perf__part2107_behav of IWLS2005__des_perf__part2107 is
begin
    n36190_1 <= ( lo7253 );
end IWLS2005__des_perf__part2107_behav;
