--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s953__part15 is 
  Port (
    lo20: in std_logic;
    po16: inout std_logic
  );
end IWLS93__s953__part15;

architecture IWLS93__s953__part15_behav of IWLS93__s953__part15 is
begin
    po16 <= ( lo20 );
end IWLS93__s953__part15_behav;
