--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1708 is 
  Port (
    lo3858: in std_logic;
    n23871: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1708;

architecture Other__ucsb_152_tap_fir__part1708_behav of Other__ucsb_152_tap_fir__part1708 is
begin
    n23871 <= ( lo3858 );
end Other__ucsb_152_tap_fir__part1708_behav;
