--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1297 is 
  Port (
    lo3017: in std_logic;
    n19581: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1297;

architecture Other__ucsb_152_tap_fir__part1297_behav of Other__ucsb_152_tap_fir__part1297 is
begin
    n19581 <= ( lo3017 );
end Other__ucsb_152_tap_fir__part1297_behav;
