--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1576 is 
  Port (
    lo3575: in std_logic;
    n22461: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1576;

architecture Other__ucsb_152_tap_fir__part1576_behav of Other__ucsb_152_tap_fir__part1576 is
begin
    n22461 <= ( lo3575 );
end Other__ucsb_152_tap_fir__part1576_behav;
