--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ac97_ctrl__part75 is 
  Port (
    lo2012: in std_logic;
    n9973_1: inout std_logic
  );
end IWLS2005__ac97_ctrl__part75;

architecture IWLS2005__ac97_ctrl__part75_behav of IWLS2005__ac97_ctrl__part75 is
begin
    n9973_1 <= ( lo2012 );
end IWLS2005__ac97_ctrl__part75_behav;
