--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part103 is 
  Port (
    lo089: in std_logic;
    po177: inout std_logic
  );
end Cookbook__lc_mult_signed__part103;

architecture Cookbook__lc_mult_signed__part103_behav of Cookbook__lc_mult_signed__part103 is
begin
    po177 <= ( lo089 );
end Cookbook__lc_mult_signed__part103_behav;
