--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part840 is 
  Port (
    lo4644: in std_logic;
    n23245: inout std_logic
  );
end IWLS2005__des_perf__part840;

architecture IWLS2005__des_perf__part840_behav of IWLS2005__des_perf__part840 is
begin
    n23245 <= ( lo4644 );
end IWLS2005__des_perf__part840_behav;
