--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part701 is 
  Port (
    lo06198: in std_logic;
    n46911: inout std_logic
  );
end Other__ray__part701;

architecture Other__ray__part701_behav of Other__ray__part701 is
begin
    n46911 <= ( lo06198 );
end Other__ray__part701_behav;
