--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part423 is 
  Port (
    lo3072: in std_logic;
    n9149: inout std_logic
  );
end Other__sudoku_check__part423;

architecture Other__sudoku_check__part423_behav of Other__sudoku_check__part423 is
begin
    n9149 <= ( lo3072 );
end Other__sudoku_check__part423_behav;
