--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part947 is 
  Port (
    lo4867: in std_logic;
    n24095: inout std_logic
  );
end IWLS2005__des_perf__part947;

architecture IWLS2005__des_perf__part947_behav of IWLS2005__des_perf__part947 is
begin
    n24095 <= ( lo4867 );
end IWLS2005__des_perf__part947_behav;
