--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part140 is 
  Port (
    lo266: in std_logic;
    po072: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part140;

architecture Cookbook__soft_ecc_ram_64bit__part140_behav of Cookbook__soft_ecc_ram_64bit__part140 is
begin
    po072 <= ( lo266 );
end Cookbook__soft_ecc_ram_64bit__part140_behav;
