--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part43 is 
  Port (
    lo108: in std_logic;
    n838: inout std_logic
  );
end ISCAS__s13207__part43;

architecture ISCAS__s13207__part43_behav of ISCAS__s13207__part43 is
begin
    n838 <= ( lo108 );
end ISCAS__s13207__part43_behav;
