--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2098 is 
  Port (
    lo7244: in std_logic;
    n35770: inout std_logic
  );
end IWLS2005__des_perf__part2098;

architecture IWLS2005__des_perf__part2098_behav of IWLS2005__des_perf__part2098 is
begin
    n35770 <= ( lo7244 );
end IWLS2005__des_perf__part2098_behav;
