--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part30 is 
  Port (
    pi30: in std_logic;
    n544163: inout std_logic
  );
end IWLS2005__leon3mp__part30;

architecture IWLS2005__leon3mp__part30_behav of IWLS2005__leon3mp__part30 is
begin
    n544163 <= ( pi30 );
end IWLS2005__leon3mp__part30_behav;
