--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part43 is 
  Port (
    lo0520: in std_logic;
    po144: inout std_logic
  );
end IWLS2005__pci_bridge32__part43;

architecture IWLS2005__pci_bridge32__part43_behav of IWLS2005__pci_bridge32__part43 is
begin
    po144 <= ( lo0520 );
end IWLS2005__pci_bridge32__part43_behav;
