--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1153 is 
  Port (
    lo2677: in std_logic;
    n17966: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1153;

architecture Other__ucsb_152_tap_fir__part1153_behav of Other__ucsb_152_tap_fir__part1153 is
begin
    n17966 <= ( lo2677 );
end Other__ucsb_152_tap_fir__part1153_behav;
