--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part889 is 
  Port (
    lo0958: in std_logic;
    n5089: inout std_logic
  );
end Cookbook__fec_check__part889;

architecture Cookbook__fec_check__part889_behav of Cookbook__fec_check__part889 is
begin
    n5089 <= ( lo0958 );
end Cookbook__fec_check__part889_behav;
