--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part899 is 
  Port (
    lo4268: in std_logic;
    n16829: inout std_logic
  );
end Other__sudoku_check__part899;

architecture Other__sudoku_check__part899_behav of Other__sudoku_check__part899 is
begin
    n16829 <= ( lo4268 );
end Other__sudoku_check__part899_behav;
