--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2008 is 
  Port (
    lo2077: in std_logic;
    n10684: inout std_logic
  );
end Cookbook__fec_check__part2008;

architecture Cookbook__fec_check__part2008_behav of Cookbook__fec_check__part2008 is
begin
    n10684 <= ( lo2077 );
end Cookbook__fec_check__part2008_behav;
