--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2004 is 
  Port (
    lo4477: in std_logic;
    n26966: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2004;

architecture Other__ucsb_152_tap_fir__part2004_behav of Other__ucsb_152_tap_fir__part2004 is
begin
    n26966 <= ( lo4477 );
end Other__ucsb_152_tap_fir__part2004_behav;
