--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part242 is 
  Port (
    lo0591: in std_logic;
    n7436: inout std_logic
  );
end Other__ucsb_152_tap_fir__part242;

architecture Other__ucsb_152_tap_fir__part242_behav of Other__ucsb_152_tap_fir__part242 is
begin
    n7436 <= ( lo0591 );
end Other__ucsb_152_tap_fir__part242_behav;
