--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part309 is 
  Port (
    lo1171: in std_logic;
    n6150: inout std_logic
  );
end IWLS2005__des_perf__part309;

architecture IWLS2005__des_perf__part309_behav of IWLS2005__des_perf__part309 is
begin
    n6150 <= ( lo1171 );
end IWLS2005__des_perf__part309_behav;
