--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part249 is 
  Port (
    lo1214: in std_logic;
    n8130_1: inout std_logic
  );
end Other__fp_operators__part249;

architecture Other__fp_operators__part249_behav of Other__fp_operators__part249 is
begin
    n8130_1 <= ( lo1214 );
end Other__fp_operators__part249_behav;
