--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1321 is 
  Port (
    lo1390: in std_logic;
    n7249: inout std_logic
  );
end Cookbook__fec_check__part1321;

architecture Cookbook__fec_check__part1321_behav of Cookbook__fec_check__part1321 is
begin
    n7249 <= ( lo1390 );
end Cookbook__fec_check__part1321_behav;
