--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1096 is 
  Port (
    lo5172: in std_logic;
    n26150: inout std_logic
  );
end IWLS2005__des_perf__part1096;

architecture IWLS2005__des_perf__part1096_behav of IWLS2005__des_perf__part1096 is
begin
    n26150 <= ( lo5172 );
end IWLS2005__des_perf__part1096_behav;
