--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part197 is 
  Port (
    lo0794: in std_logic;
    n6110: inout std_logic
  );
end Other__fp_operators__part197;

architecture Other__fp_operators__part197_behav of Other__fp_operators__part197 is
begin
    n6110 <= ( lo0794 );
end Other__fp_operators__part197_behav;
