--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2595 is 
  Port (
    lo5698: in std_logic;
    n33076_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2595;

architecture Other__ucsb_152_tap_fir__part2595_behav of Other__ucsb_152_tap_fir__part2595 is
begin
    n33076_1 <= ( lo5698 );
end Other__ucsb_152_tap_fir__part2595_behav;
