--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part346 is 
  Port (
    lo2995: in std_logic;
    n8379: inout std_logic
  );
end Other__sudoku_check__part346;

architecture Other__sudoku_check__part346_behav of Other__sudoku_check__part346 is
begin
    n8379 <= ( lo2995 );
end Other__sudoku_check__part346_behav;
