--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part863 is 
  Port (
    lo4232: in std_logic;
    n16649: inout std_logic
  );
end Other__sudoku_check__part863;

architecture Other__sudoku_check__part863_behav of Other__sudoku_check__part863 is
begin
    n16649 <= ( lo4232 );
end Other__sudoku_check__part863_behav;
