--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part171 is 
  Port (
    pi0601: in std_logic;
    n44051_1: inout std_logic
  );
end Other__radar__part171;

architecture Other__radar__part171_behav of Other__radar__part171 is
begin
    n44051_1 <= ( pi0601 );
end Other__radar__part171_behav;
