--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8,pi9,lo0,lo1,lo2,lo3,lo4,lo5,lo6,lo7: in std_logic;
    po0,n23,n28,n33,n38,n43,n48_1,n53_1,n58_1: inout std_logic
  );
end top;

architecture top_behav of top is
signal n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100: std_logic;
begin
    po0 <= not (( not n94 and not n80 ));
    n23 <= not (( n81 and n95 ));
    n28 <= not (( not n55 and not n56 ));
    n33 <= ( not n57 and not n58 );
    n38 <= not (( not n59 and not n60 ));
    n43 <= not (( n85 and n96 ));
    n48_1 <= not (( n86 and not n48 ));
    n53_1 <= ( not n61 and not n62 );
    n58_1 <= not (( not n63 and not n64 ));
    n44 <= ( not n82 and pi0 );
    n45 <= not (( lo3 and pi0 ));
    n46 <= not (( lo7 and n47 ));
    n47 <= ( n66 and pi0 );
    n48 <= ( lo5 and not n65 );
    n49 <= not (( not lo3 and pi0 ));
    n50 <= not (( not lo7 and pi0 ));
    n51 <= ( lo2 and not n49 );
    n52 <= ( lo1 and not n97 );
    n53 <= ( n67 and n70 );
    n54 <= ( n67 and n71 );
    n55 <= ( n44 and not lo1 );
    n56 <= ( lo1 and not n44 );
    n57 <= ( n45 and not lo2 );
    n58 <= ( lo2 and not n45 );
    n59 <= ( lo3 and not pi0 );
    n60 <= ( pi0 and not lo3 );
    n61 <= ( n46 and not lo6 );
    n62 <= ( lo6 and not n46 );
    n63 <= ( lo7 and not n47 );
    n64 <= ( n47 and not lo7 );
    n65 <= ( not n46 and lo6 );
    n66 <= ( not n82 and lo0 and lo1 );
    n67 <= ( not lo0 and not lo2 and not lo1 and not lo3 );
    n68 <= ( pi0 and lo7 );
    n69 <= ( n67 and n68 );
    n70 <= ( lo6 and not n50 );
    n71 <= ( lo5 and not n98 );
    n72 <= ( not lo5 and not n98 and lo4 );
    n73 <= ( n67 and n72 );
    n74 <= ( pi0 and lo3 );
    n75 <= ( n74 and pi8 );
    n76 <= ( pi0 and pi9 );
    n77 <= ( n69 and pi4 );
    n78 <= ( not lo1 and not n97 and lo0 );
    n79 <= ( n78 and pi5 );
    n80 <= ( n73 and pi1 );
    n81 <= not (( n44 and not lo0 and lo1 ));
    n82 <= not (( lo3 and lo2 ));
    n83 <= not (( not n82 and lo1 and pi0 ));
    n84 <= not (( not n46 and lo6 ));
    n85 <= not (( not n84 and not lo4 and lo5 ));
    n86 <= not (( not n84 and not lo5 ));
    n87 <= not (( not n46 and lo6 and lo5 ));
    n88 <= not (( n52 and pi6 ));
    n89 <= not (( n51 and pi7 ));
    n90 <= not (( n54 and pi2 ));
    n91 <= not (( n53 and pi3 ));
    n92 <= not (( n88 and n89 and n99 ));
    n93 <= not (( n90 and n91 and n100 ));
    n94 <= not (( not n92 and not n93 ));
    n95 <= not (( n83 and lo0 ));
    n96 <= not (( n87 and lo4 ));
    n97 <= not (( not n49 and not lo2 ));
    n98 <= not (( not n50 and not lo6 ));
    n99 <= ( not n75 and not n76 );
    n100 <= ( not n77 and not n79 );
end top_behav;
