--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part63 is 
  Port (
    lo3731,lo3719,lo3695,lo3683,lo3707,lo3659,lo3647,lo3671,lo3623,lo3611,lo3635: in std_logic;
    n19054: inout std_logic
  );
end Cookbook__fec_check__part63;

architecture Cookbook__fec_check__part63_behav of Cookbook__fec_check__part63 is
signal n13472,n13473,n13474,n13475,n13476,n13477,n13478,n13479,n13480: std_logic;
begin
    n13472 <= not (( not lo3731 and not lo3719 ));
    n13473 <= not (( not lo3695 and not lo3683 ));
    n13474 <= not (( not lo3707 and not n13473 ));
    n13475 <= not (( not n13472 and not n13474 ));
    n13476 <= not (( not lo3659 and not lo3647 ));
    n13477 <= not (( not lo3671 and not n13476 ));
    n13478 <= not (( not lo3623 and not lo3611 ));
    n13479 <= not (( not lo3635 and not n13478 ));
    n13480 <= not (( not n13477 and not n13479 ));
    n19054 <= not (( not n13475 and not n13480 ));
end Cookbook__fec_check__part63_behav;
