--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part21 is 
  Port (
    lo04260,lo04261,lo04262,lo04259,lo04263: in std_logic;
    n27711,n27721,n27706,n27716,n27726: inout std_logic
  );
end QUIP__uoft_raytracer__part21;

architecture QUIP__uoft_raytracer__part21_behav of QUIP__uoft_raytracer__part21 is
signal n53254,n53255,n77435,n77436: std_logic;
begin
    n53254 <= ( not lo04260 and not lo04261 and not lo04262 );
    n53255 <= ( not lo04259 and lo04263 and n53254 )
      or ( lo04263 and n77436 );
    n27711 <= ( not lo04260 and lo04259 and not n53255 )
      or ( lo04260 and not lo04259 and not n53255 );
    n27721 <= ( not lo04262 and n77435 and not n53255 )
      or ( lo04262 and not n77435 and not n53255 );
    n77435 <= ( lo04260 and lo04259 and lo04261 );
    n77436 <= ( lo04260 and lo04259 and lo04261 and lo04262 );
    n27706 <= ( not lo04259 and not lo04263 )
      or ( not lo04259 and not n77436 and not n53254 );
    n27716 <= ( not lo04260 and lo04261 and not n53255 )
      or ( lo04260 and lo04259 and not lo04261 and not n53255 )
      or ( not lo04259 and lo04261 and not n53255 );
    n27726 <= ( lo04259 and lo04263 and not n77436 )
      or ( not lo04263 and n77436 )
      or ( lo04263 and not n77436 and not n53254 );
end QUIP__uoft_raytracer__part21_behav;
