--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b06 is 
  Port (
    pi0,pi1,lo1,lo2,lo3: in std_logic;
    n17,n22,n27,n32,n37,n42,n47_1,n52_1,n57_1: inout std_logic
  );
end ITC99__b06;

architecture ITC99__b06_behav of ITC99__b06 is
signal n35,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66: std_logic;
begin
    n35 <= ( n64 and n63 );
    n32 <= not (( n35 and n52 ));
    n27 <= not (( n56 and n55 and n48 and n45 ));
    n22 <= not (( n54 and n53 ));
    n42 <= not (( n62 and n46 and n66 and n65 ));
    n37 <= not (( n60 and n47 and n59 ));
    n52_1 <= not (( pi0 and n50 and n35 ));
    n47_1 <= not (( n48 and n49 ));
    n17 <= not (( n58 and n57 ));
    n44 <= ( lo1 and lo2 and lo3 );
    n45 <= not (( pi0 and lo2 ));
    n46 <= not (( not lo1 and not lo3 ));
    n47 <= not (( not lo2 and not lo1 and lo3 ));
    n48 <= not (( lo1 and not lo3 and not lo2 and not pi0 ));
    n49 <= not (( lo1 and not n45 ));
    n50 <= not (( lo1 and lo2 ));
    n51 <= not (( not lo2 and not lo3 ));
    n52 <= not (( not pi0 and n51 ));
    n53 <= not (( not n47 and not pi0 ));
    n54 <= not (( lo1 and n52 ));
    n55 <= not (( pi0 and not lo1 and lo3 ));
    n56 <= not (( not n46 and lo2 ));
    n57 <= not (( lo2 and not pi0 and not n46 ));
    n58 <= not (( not pi1 and not n44 ));
    n59 <= not (( not n45 and not lo3 ));
    n60 <= not (( lo1 and n52 ));
    n61 <= not (( pi0 and not lo3 ));
    n62 <= not (( lo3 and lo1 ));
    n63 <= not (( not n46 and not lo2 ));
    n64 <= not (( lo3 and lo2 ));
    n65 <= not (( pi0 and not lo2 ));
    n66 <= not (( lo2 and n61 ));
    n57_1 <= ( n17 );
end ITC99__b06_behav;
