--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__radar20__part4 is 
  Port (
    lo0707,lo0859,lo0944,lo0945,lo0946,lo0947: in std_logic;
    n9682,n10107,n10112,n10117,n10122: inout std_logic
  );
end QUIP__radar20__part4;

architecture QUIP__radar20__part4_behav of QUIP__radar20__part4 is
signal n22495,n22673,n33347,n33389,n33390: std_logic;
begin
    n9682 <= ( not lo0707 and lo0859 )
      or ( lo0707 and n22495 );
    n10107 <= ( not lo0707 and lo0944 )
      or ( lo0707 and n33389 );
    n10112 <= ( not lo0707 and lo0945 )
      or ( lo0707 and n33390 );
    n10117 <= ( not lo0707 and lo0946 )
      or ( lo0707 and n22673 );
    n22495 <= ( not lo0944 and lo0859 )
      or ( lo0944 and n33347 and not lo0859 )
      or ( not n33347 and lo0859 );
    n22673 <= ( not lo0946 and lo0947 )
      or ( lo0946 and not lo0947 );
    n10122 <= ( not lo0707 and lo0947 )
      or ( lo0707 and not lo0947 );
    n33347 <= ( lo0946 and lo0947 and lo0945 );
    n33389 <= ( not lo0946 and lo0944 )
      or ( lo0946 and lo0947 and lo0945 and not lo0944 )
      or ( not lo0947 and lo0944 )
      or ( not lo0945 and lo0944 );
    n33390 <= ( not lo0946 and lo0945 )
      or ( lo0946 and lo0947 and not lo0945 )
      or ( not lo0947 and lo0945 );
end QUIP__radar20__part4_behav;
