--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part24 is 
  Port (
    lo5633,lo5634,lo5635,lo5636: in std_logic;
    n27149_1,n28784,n28789_1,n28794,n28799_1,n28804_1,n28809_1,n28814_1,n28819: inout std_logic
  );
end Other__sudoku_check__part24;

architecture Other__sudoku_check__part24_behav of Other__sudoku_check__part24 is
begin
    n27149_1 <= ( lo5633 and not lo5634 and not lo5635 and not lo5636 );
    n28784 <= ( lo5633 and not lo5634 and not lo5635 and lo5636 );
    n28789_1 <= ( not lo5633 and not lo5634 and not lo5635 and lo5636 );
    n28794 <= ( lo5633 and lo5634 and lo5635 and not lo5636 );
    n28799_1 <= ( not lo5633 and lo5634 and lo5635 and not lo5636 );
    n28804_1 <= ( lo5633 and not lo5634 and lo5635 and not lo5636 );
    n28809_1 <= ( not lo5633 and not lo5634 and lo5635 and not lo5636 );
    n28814_1 <= ( lo5633 and lo5634 and not lo5635 and not lo5636 );
    n28819 <= ( not lo5633 and lo5634 and not lo5635 and not lo5636 );
end Other__sudoku_check__part24_behav;
