--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part35 is 
  Port (
    lo3511,lo3499,lo3475,lo3463,lo3487,lo3451,lo3439,lo3415,lo3403,lo3427,lo3795: in std_logic;
    n18954: inout std_logic
  );
end Cookbook__fec_check__part35;

architecture Cookbook__fec_check__part35_behav of Cookbook__fec_check__part35 is
signal n13672,n13673,n13674,n13675,n13676,n13677,n13678,n13679,n13680: std_logic;
begin
    n13672 <= not (( not lo3511 and not lo3499 ));
    n13673 <= not (( not lo3475 and not lo3463 ));
    n13674 <= not (( not lo3487 and not n13673 ));
    n13675 <= not (( not n13672 and not n13674 ));
    n13676 <= not (( not lo3451 and not lo3439 ));
    n13677 <= not (( not lo3415 and not lo3403 ));
    n13678 <= not (( not lo3427 and not n13677 ));
    n13679 <= not (( not n13676 and not n13678 ));
    n13680 <= not (( not n13675 and not n13679 ));
    n18954 <= not (( not n13680 and not lo3795 ));
end Cookbook__fec_check__part35_behav;
