--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part7 is 
  Port (
    lo127,lo128,lo119,lo120,lo121,lo122,lo123,lo124,lo125,lo126,lo129: in std_logic;
    n842_1,n847,n852_1,n857_1,n862_1,n867_1,n872_1,n877: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part7;

architecture Cookbook__ycbcr_to_rgb__part7_behav of Cookbook__ycbcr_to_rgb__part7 is
signal n1223,n1224,n1225,n1226,n1227,n1228,n1229,n1230,n1231: std_logic;
begin
    n1223 <= not (( not lo127 and not lo128 ));
    n1224 <= not (( not lo119 and not n1223 ));
    n1225 <= not (( not lo120 and not n1223 ));
    n1226 <= not (( not lo121 and not n1223 ));
    n1227 <= not (( not lo122 and not n1223 ));
    n1228 <= not (( not lo123 and not n1223 ));
    n1229 <= not (( not lo124 and not n1223 ));
    n1230 <= not (( not lo125 and not n1223 ));
    n1231 <= not (( not lo126 and not n1223 ));
    n842_1 <= ( n1224 and not lo129 );
    n847 <= ( n1225 and not lo129 );
    n852_1 <= ( n1226 and not lo129 );
    n857_1 <= ( n1227 and not lo129 );
    n862_1 <= ( n1228 and not lo129 );
    n867_1 <= ( n1229 and not lo129 );
    n872_1 <= ( n1230 and not lo129 );
    n877 <= ( n1231 and not lo129 );
end Cookbook__ycbcr_to_rgb__part7_behav;
