--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part6 is 
  Port (
    lo04057,lo04056,lo04058,lo04059,lo04060,lo04061: in std_logic;
    n26691,n26696,n26706,n26701,n26711,n26716: inout std_logic
  );
end QUIP__uoft_raytracer__part6;

architecture QUIP__uoft_raytracer__part6_behav of QUIP__uoft_raytracer__part6 is
signal n51954,n77291,n77292,n77293: std_logic;
begin
    n51954 <= ( lo04057 and not lo04056 and not lo04058 and not lo04059 );
    n26691 <= ( not lo04056 and not n77293 );
    n26696 <= ( not lo04057 and lo04056 and not n77293 )
      or ( lo04057 and not lo04056 and not n77293 );
    n26706 <= ( not lo04059 and n77291 and not n77293 )
      or ( lo04059 and not n77291 and not n77293 );
    n77291 <= ( lo04057 and lo04056 and lo04058 );
    n77292 <= ( lo04057 and lo04056 and lo04058 and lo04059 );
    n77293 <= ( not lo04060 and lo04061 and n51954 )
      or ( lo04060 and n77292 and lo04061 );
    n26701 <= ( not lo04057 and lo04058 and not n77293 )
      or ( lo04057 and lo04056 and not lo04058 and not n77293 )
      or ( not lo04056 and lo04058 and not n77293 );
    n26711 <= ( not lo04060 and n77292 and not lo04061 )
      or ( not lo04060 and n77292 and not n51954 )
      or ( lo04060 and not n77292 );
    n26716 <= ( not lo04060 and lo04061 and not n51954 )
      or ( lo04060 and not n77292 and lo04061 )
      or ( lo04060 and n77292 and not lo04061 );
end QUIP__uoft_raytracer__part6_behav;
