--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part65 is 
  Port (
    lo5797,lo5798,lo5799,lo5800: in std_logic;
    n27629_1,n29309,n29494,n29674,n29854_1,n30034,n30214,n30394,n30574: inout std_logic
  );
end Other__sudoku_check__part65;

architecture Other__sudoku_check__part65_behav of Other__sudoku_check__part65 is
begin
    n27629_1 <= ( lo5797 and not lo5798 and not lo5799 and not lo5800 );
    n29309 <= ( lo5797 and not lo5798 and not lo5799 and lo5800 );
    n29494 <= ( not lo5797 and not lo5798 and not lo5799 and lo5800 );
    n29674 <= ( lo5797 and lo5798 and lo5799 and not lo5800 );
    n29854_1 <= ( not lo5797 and lo5798 and lo5799 and not lo5800 );
    n30034 <= ( lo5797 and not lo5798 and lo5799 and not lo5800 );
    n30214 <= ( not lo5797 and not lo5798 and lo5799 and not lo5800 );
    n30394 <= ( lo5797 and lo5798 and not lo5799 and not lo5800 );
    n30574 <= ( not lo5797 and lo5798 and not lo5799 and not lo5800 );
end Other__sudoku_check__part65_behav;
