--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part86 is 
  Port (
    lo5881,lo5882,lo5883,lo5884: in std_logic;
    n27974_1,n28084_1,n28089_1,n28094_1,n28099_1,n28104_1,n28109_1,n28114_1,n28119_1: inout std_logic
  );
end Other__sudoku_check__part86;

architecture Other__sudoku_check__part86_behav of Other__sudoku_check__part86 is
begin
    n27974_1 <= ( lo5881 and not lo5882 and not lo5883 and not lo5884 );
    n28084_1 <= ( lo5881 and not lo5882 and not lo5883 and lo5884 );
    n28089_1 <= ( not lo5881 and not lo5882 and not lo5883 and lo5884 );
    n28094_1 <= ( lo5881 and lo5882 and lo5883 and not lo5884 );
    n28099_1 <= ( not lo5881 and lo5882 and lo5883 and not lo5884 );
    n28104_1 <= ( lo5881 and not lo5882 and lo5883 and not lo5884 );
    n28109_1 <= ( not lo5881 and not lo5882 and lo5883 and not lo5884 );
    n28114_1 <= ( lo5881 and lo5882 and not lo5883 and not lo5884 );
    n28119_1 <= ( not lo5881 and lo5882 and not lo5883 and not lo5884 );
end Other__sudoku_check__part86_behav;
