--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part15 is 
  Port (
    pi045,pi109,pi044,pi108,pi043,pi107: in std_logic;
    n319_1: inout std_logic
  );
end Cookbook__pipe_equal__part15;

architecture Cookbook__pipe_equal__part15_behav of Cookbook__pipe_equal__part15 is
signal n243,n244,n245,n246: std_logic;
begin
    n243 <= ( not pi045 and pi109 )
      or ( pi045 and not pi109 );
    n244 <= ( not pi044 and pi108 )
      or ( pi044 and not pi108 );
    n245 <= ( not pi043 and pi107 )
      or ( pi043 and not pi107 );
    n246 <= not (( not n244 and not n245 ));
    n319_1 <= ( not n243 and not n246 );
end Cookbook__pipe_equal__part15_behav;
