--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part54 is 
  Port (
    lo5753,lo5754,lo5755,lo5756: in std_logic;
    n27414_1,n29344,n29529_1,n29709_1,n29889_1,n30069_1,n30249,n30429,n30609: inout std_logic
  );
end Other__sudoku_check__part54;

architecture Other__sudoku_check__part54_behav of Other__sudoku_check__part54 is
begin
    n27414_1 <= ( lo5753 and not lo5754 and not lo5755 and not lo5756 );
    n29344 <= ( lo5753 and not lo5754 and not lo5755 and lo5756 );
    n29529_1 <= ( not lo5753 and not lo5754 and not lo5755 and lo5756 );
    n29709_1 <= ( lo5753 and lo5754 and lo5755 and not lo5756 );
    n29889_1 <= ( not lo5753 and lo5754 and lo5755 and not lo5756 );
    n30069_1 <= ( lo5753 and not lo5754 and lo5755 and not lo5756 );
    n30249 <= ( not lo5753 and not lo5754 and lo5755 and not lo5756 );
    n30429 <= ( lo5753 and lo5754 and not lo5755 and not lo5756 );
    n30609 <= ( not lo5753 and lo5754 and not lo5755 and not lo5756 );
end Other__sudoku_check__part54_behav;
