--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part45 is 
  Port (
    lo5717,lo5718,lo5719,lo5720: in std_logic;
    n27289_1,n27549_1,n27554_1,n27559_1,n27564_1,n27569_1,n27574_1,n27579_1,n27584_1: inout std_logic
  );
end Other__sudoku_check__part45;

architecture Other__sudoku_check__part45_behav of Other__sudoku_check__part45 is
begin
    n27289_1 <= ( lo5717 and not lo5718 and not lo5719 and not lo5720 );
    n27549_1 <= ( lo5717 and not lo5718 and not lo5719 and lo5720 );
    n27554_1 <= ( not lo5717 and not lo5718 and not lo5719 and lo5720 );
    n27559_1 <= ( lo5717 and lo5718 and lo5719 and not lo5720 );
    n27564_1 <= ( not lo5717 and lo5718 and lo5719 and not lo5720 );
    n27569_1 <= ( lo5717 and not lo5718 and lo5719 and not lo5720 );
    n27574_1 <= ( not lo5717 and not lo5718 and lo5719 and not lo5720 );
    n27579_1 <= ( lo5717 and lo5718 and not lo5719 and not lo5720 );
    n27584_1 <= ( not lo5717 and lo5718 and not lo5719 and not lo5720 );
end Other__sudoku_check__part45_behav;
