--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part136 is 
  Port (
    lo8763,lo8764,lo8765: in std_logic;
    n49324_1,n49329_1,n49334: inout std_logic
  );
end Other__carpat__part136;

architecture Other__carpat__part136_behav of Other__carpat__part136 is
signal n37410,n37411,n135160,n135161,n135162,n135163: std_logic;
begin
    n37410 <= ( lo8763 and not lo8764 and lo8765 );
    n37411 <= not (( not n135163 and not n37410 ));
    n49324_1 <= ( not lo8763 and not n37411 );
    n49329_1 <= ( not n37411 and n135160 );
    n49334 <= ( not n37411 and n135162 );
    n135160 <= ( not lo8764 and lo8763 )
      or ( lo8764 and not lo8763 );
    n135161 <= ( lo8764 and lo8763 );
    n135162 <= ( not lo8765 and n135161 )
      or ( lo8765 and not n135161 );
    n135163 <= ( lo8765 and n135161 );
end Other__carpat__part136_behav;
