--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part17 is 
  Port (
    lo04236,lo04237,lo04238,lo04235,lo04239: in std_logic;
    n27591,n27601,n27586,n27596,n27606: inout std_logic
  );
end QUIP__uoft_raytracer__part17;

architecture QUIP__uoft_raytracer__part17_behav of QUIP__uoft_raytracer__part17 is
signal n53039,n53040,n77394,n77395: std_logic;
begin
    n53039 <= ( not lo04236 and lo04237 and not lo04238 );
    n53040 <= ( not lo04235 and lo04239 and n53039 )
      or ( lo04239 and n77395 );
    n27591 <= ( not lo04236 and lo04235 and not n53040 )
      or ( lo04236 and not lo04235 and not n53040 );
    n27601 <= ( not lo04238 and n77394 and not n53040 )
      or ( lo04238 and not n77394 and not n53040 );
    n77394 <= ( lo04236 and lo04235 and lo04237 );
    n77395 <= ( lo04236 and lo04235 and lo04237 and lo04238 );
    n27586 <= ( not lo04235 and not lo04239 )
      or ( not lo04235 and not n77395 and not n53039 );
    n27596 <= ( not lo04236 and lo04237 and not n53040 )
      or ( lo04236 and lo04235 and not lo04237 and not n53040 )
      or ( not lo04235 and lo04237 and not n53040 );
    n27606 <= ( lo04235 and lo04239 and not n77395 )
      or ( not lo04239 and n77395 )
      or ( lo04239 and not n77395 and not n53039 );
end QUIP__uoft_raytracer__part17_behav;
