--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__nut_000__part1 is 
  Port (
    lo062,lo001,lo060,lo061: in std_logic;
    n391,n86,n381,n386: inout std_logic
  );
end QUIP__nut_000__part1;

architecture QUIP__nut_000__part1_behav of QUIP__nut_000__part1 is
begin
    n391 <= ( not lo062 );
    n86 <= ( not lo001 and lo060 and lo061 and lo062 )
      or ( lo001 and not lo060 )
      or ( lo001 and not lo061 )
      or ( lo001 and not lo062 );
    n381 <= ( not lo060 and lo061 and lo062 )
      or ( lo060 and not lo061 )
      or ( lo060 and not lo062 );
    n386 <= ( not lo061 and lo062 )
      or ( lo061 and not lo062 );
end QUIP__nut_000__part1_behav;
