--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part70 is 
  Port (
    lo5817,lo5818,lo5819,lo5820: in std_logic;
    n27654_1,n29459,n29644,n29824_1,n30004,n30184,n30364,n30544,n30724: inout std_logic
  );
end Other__sudoku_check__part70;

architecture Other__sudoku_check__part70_behav of Other__sudoku_check__part70 is
begin
    n27654_1 <= ( lo5817 and not lo5818 and not lo5819 and not lo5820 );
    n29459 <= ( lo5817 and not lo5818 and not lo5819 and lo5820 );
    n29644 <= ( not lo5817 and not lo5818 and not lo5819 and lo5820 );
    n29824_1 <= ( lo5817 and lo5818 and lo5819 and not lo5820 );
    n30004 <= ( not lo5817 and lo5818 and lo5819 and not lo5820 );
    n30184 <= ( lo5817 and not lo5818 and lo5819 and not lo5820 );
    n30364 <= ( not lo5817 and not lo5818 and lo5819 and not lo5820 );
    n30544 <= ( lo5817 and lo5818 and not lo5819 and not lo5820 );
    n30724 <= ( not lo5817 and lo5818 and not lo5819 and not lo5820 );
end Other__sudoku_check__part70_behav;
