--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__delay_reg is 
  Port (
    pi0,lo0,lo1,lo2,lo3: in std_logic;
    n3,n8,n13_1,n18: inout std_logic
  );
end Cookbook__delay_reg;

architecture Cookbook__delay_reg_behav of Cookbook__delay_reg is
signal n13,n14,n15,n16,n17: std_logic;
begin
    n13 <= ( not lo0 and lo1 )
      or ( lo0 and not lo1 );
    n14 <= ( lo0 and lo1 );
    n15 <= ( not n14 and lo2 )
      or ( n14 and not lo2 );
    n16 <= ( n14 and lo2 );
    n17 <= ( not n16 and lo3 )
      or ( n16 and not lo3 );
    n3 <= ( not lo0 and pi0 )
      or ( lo0 and not pi0 );
    n8 <= ( lo1 and not pi0 )
      or ( n13 and pi0 );
    n13_1 <= ( lo2 and not pi0 )
      or ( n15 and pi0 );
    n18 <= ( lo3 and not pi0 )
      or ( n17 and pi0 );
end Cookbook__delay_reg_behav;
