--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part57 is 
  Port (
    lo5765,lo5766,lo5767,lo5768: in std_logic;
    n27429_1,n29434_1,n29619_1,n29799_1,n29979_1,n30159,n30339,n30519,n30699: inout std_logic
  );
end Other__sudoku_check__part57;

architecture Other__sudoku_check__part57_behav of Other__sudoku_check__part57 is
begin
    n27429_1 <= ( lo5765 and not lo5766 and not lo5767 and not lo5768 );
    n29434_1 <= ( lo5765 and not lo5766 and not lo5767 and lo5768 );
    n29619_1 <= ( not lo5765 and not lo5766 and not lo5767 and lo5768 );
    n29799_1 <= ( lo5765 and lo5766 and lo5767 and not lo5768 );
    n29979_1 <= ( not lo5765 and lo5766 and lo5767 and not lo5768 );
    n30159 <= ( lo5765 and not lo5766 and lo5767 and not lo5768 );
    n30339 <= ( not lo5765 and not lo5766 and lo5767 and not lo5768 );
    n30519 <= ( lo5765 and lo5766 and not lo5767 and not lo5768 );
    n30699 <= ( not lo5765 and lo5766 and not lo5767 and not lo5768 );
end Other__sudoku_check__part57_behav;
