--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part18 is 
  Port (
    lo5609,lo5610,lo5611,lo5612: in std_logic;
    n27119_1,n28624_1,n28629_1,n28634_1,n28639_1,n28644_1,n28649,n28654_1,n28659_1: inout std_logic
  );
end Other__sudoku_check__part18;

architecture Other__sudoku_check__part18_behav of Other__sudoku_check__part18 is
begin
    n27119_1 <= ( lo5609 and not lo5610 and not lo5611 and not lo5612 );
    n28624_1 <= ( lo5609 and not lo5610 and not lo5611 and lo5612 );
    n28629_1 <= ( not lo5609 and not lo5610 and not lo5611 and lo5612 );
    n28634_1 <= ( lo5609 and lo5610 and lo5611 and not lo5612 );
    n28639_1 <= ( not lo5609 and lo5610 and lo5611 and not lo5612 );
    n28644_1 <= ( lo5609 and not lo5610 and lo5611 and not lo5612 );
    n28649 <= ( not lo5609 and not lo5610 and lo5611 and not lo5612 );
    n28654_1 <= ( lo5609 and lo5610 and not lo5611 and not lo5612 );
    n28659_1 <= ( not lo5609 and lo5610 and not lo5611 and not lo5612 );
end Other__sudoku_check__part18_behav;
