--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part47 is 
  Port (
    lo5725,lo5726,lo5727,lo5728: in std_logic;
    n27299_1,n27479_1,n27484_1,n27489_1,n27494_1,n27499_1,n27504_1,n27509_1,n27514_1: inout std_logic
  );
end Other__sudoku_check__part47;

architecture Other__sudoku_check__part47_behav of Other__sudoku_check__part47 is
begin
    n27299_1 <= ( lo5725 and not lo5726 and not lo5727 and not lo5728 );
    n27479_1 <= ( lo5725 and not lo5726 and not lo5727 and lo5728 );
    n27484_1 <= ( not lo5725 and not lo5726 and not lo5727 and lo5728 );
    n27489_1 <= ( lo5725 and lo5726 and lo5727 and not lo5728 );
    n27494_1 <= ( not lo5725 and lo5726 and lo5727 and not lo5728 );
    n27499_1 <= ( lo5725 and not lo5726 and lo5727 and not lo5728 );
    n27504_1 <= ( not lo5725 and not lo5726 and lo5727 and not lo5728 );
    n27509_1 <= ( lo5725 and lo5726 and not lo5727 and not lo5728 );
    n27514_1 <= ( not lo5725 and lo5726 and not lo5727 and not lo5728 );
end Other__sudoku_check__part47_behav;
