--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    lo020,lo101,lo619,lo155,lo597,lo314,lo084,lo200,lo564,lo578,lo236,lo159,lo521: in std_logic;
    po042: inout std_logic
  );
end top;

architecture top_behav of top is
signal n4107,n4132,n4190: std_logic;
begin
    po042 <= ( not lo020 and not n4107 and not n4190 and not n4132 );
    n4107 <= not (( not lo101 and not lo619 and not lo155 and not lo597 ));
    n4132 <= not (( not lo314 and not lo084 and not lo200 and not lo564 ));
    n4190 <= not (( not lo578 and not lo236 and not lo159 and not lo521 ));
end top_behav;
