--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part57 is 
  Port (
    lo3665,lo3653,lo3629,lo3617,lo3641,lo3593,lo3581,lo3605,lo3557,lo3545,lo3569: in std_logic;
    n19024: inout std_logic
  );
end Cookbook__fec_check__part57;

architecture Cookbook__fec_check__part57_behav of Cookbook__fec_check__part57 is
signal n13532,n13533,n13534,n13535,n13536,n13537,n13538,n13539,n13540: std_logic;
begin
    n13532 <= not (( not lo3665 and not lo3653 ));
    n13533 <= not (( not lo3629 and not lo3617 ));
    n13534 <= not (( not lo3641 and not n13533 ));
    n13535 <= not (( not n13532 and not n13534 ));
    n13536 <= not (( not lo3593 and not lo3581 ));
    n13537 <= not (( not lo3605 and not n13536 ));
    n13538 <= not (( not lo3557 and not lo3545 ));
    n13539 <= not (( not lo3569 and not n13538 ));
    n13540 <= not (( not n13537 and not n13539 ));
    n19024 <= not (( not n13535 and not n13540 ));
end Cookbook__fec_check__part57_behav;
