--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part51 is 
  Port (
    lo3599,lo3587,lo3563,lo3551,lo3575,lo3527,lo3515,lo3539,lo3491,lo3479,lo3503: in std_logic;
    n18994: inout std_logic
  );
end Cookbook__fec_check__part51;

architecture Cookbook__fec_check__part51_behav of Cookbook__fec_check__part51 is
signal n13592,n13593,n13594,n13595,n13596,n13597,n13598,n13599,n13600: std_logic;
begin
    n13592 <= not (( not lo3599 and not lo3587 ));
    n13593 <= not (( not lo3563 and not lo3551 ));
    n13594 <= not (( not lo3575 and not n13593 ));
    n13595 <= not (( not n13592 and not n13594 ));
    n13596 <= not (( not lo3527 and not lo3515 ));
    n13597 <= not (( not lo3539 and not n13596 ));
    n13598 <= not (( not lo3491 and not lo3479 ));
    n13599 <= not (( not lo3503 and not n13598 ));
    n13600 <= not (( not n13597 and not n13599 ));
    n18994 <= not (( not n13595 and not n13600 ));
end Cookbook__fec_check__part51_behav;
