--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__daio is 
  Port (
    pi0,lo0,lo1,lo2,lo3: in std_logic;
    po0,n7,n12: inout std_logic
  );
end IWLS93__daio;

architecture IWLS93__daio_behav of IWLS93__daio is
signal n18,n19,n20,n21,n22,n23,n24,n25: std_logic;
begin
    n7 <= ( not lo0 )
      or ( po0 );
    n12 <= ( n20 )
      or ( n21 );
    po0 <= ( n18 and n19 );
    n18 <= ( n24 )
      or ( n25 );
    n19 <= ( n22 )
      or ( n23 );
    n20 <= ( not lo0 and not n18 );
    n21 <= ( lo0 and lo1 );
    n22 <= ( pi0 and lo2 );
    n23 <= ( not pi0 and not lo2 );
    n24 <= ( lo2 and lo3 );
    n25 <= ( not lo2 and not lo3 );
end IWLS93__daio_behav;
