--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s5378__part1 is 
  Port (
    lo037,lo057,lo081,lo015,lo091,lo027,lo047,pi25: in std_logic;
    n623: inout std_logic
  );
end ISCAS__s5378__part1;

architecture ISCAS__s5378__part1_behav of ISCAS__s5378__part1 is
signal n821,n844,n1230: std_logic;
begin
    n623 <= not (( not n821 and n844 ));
    n821 <= not (( lo037 and lo057 and not n1230 ));
    n844 <= ( lo081 and lo015 and lo091 );
    n1230 <= not (( lo027 and lo047 and not pi25 ));
end ISCAS__s5378__part1_behav;
