--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part18 is 
  Port (
    pi2148,pi2149,pi2150: in std_logic;
    n34311_1,n34316_1,n34321_1: inout std_logic
  );
end Other__umass_weather__part18;

architecture Other__umass_weather__part18_behav of Other__umass_weather__part18 is
signal n47518: std_logic;
begin
    n34311_1 <= ( not pi2148 );
    n34316_1 <= ( not pi2148 and not pi2149 )
      or ( pi2148 and pi2149 );
    n47518 <= not (( not pi2148 and not pi2149 ));
    n34321_1 <= ( not pi2150 and not n47518 )
      or ( pi2150 and n47518 );
end Other__umass_weather__part18_behav;
