--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part12 is 
  Port (
    lo04206,lo04208,lo04207,lo04205,lo04209: in std_logic;
    n27441,n27451,n27436,n27446,n27456: inout std_logic
  );
end QUIP__uoft_raytracer__part12;

architecture QUIP__uoft_raytracer__part12_behav of QUIP__uoft_raytracer__part12 is
signal n52770,n52771,n77354,n77355: std_logic;
begin
    n52770 <= ( not lo04206 and lo04208 and not lo04207 );
    n52771 <= ( lo04205 and lo04209 and n52770 )
      or ( lo04209 and n77355 );
    n27441 <= ( not lo04206 and lo04205 and not n52771 )
      or ( lo04206 and not lo04205 and not n52771 );
    n27451 <= ( not lo04208 and n77354 and not n52771 )
      or ( lo04208 and not n77354 and not n52771 );
    n77354 <= ( lo04206 and lo04205 and lo04207 );
    n77355 <= ( lo04206 and lo04205 and lo04207 and lo04208 );
    n27436 <= ( not lo04205 and not lo04209 )
      or ( not lo04205 and not n77355 );
    n27446 <= ( not lo04206 and lo04207 and not n52771 )
      or ( lo04206 and lo04205 and not lo04207 and not n52771 )
      or ( not lo04205 and lo04207 and not n52771 );
    n27456 <= ( not lo04205 and lo04209 and not n77355 )
      or ( not lo04209 and n77355 )
      or ( lo04209 and not n77355 and not n52770 );
end QUIP__uoft_raytracer__part12_behav;
