--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part60 is 
  Port (
    lo5777,lo5778,lo5779,lo5780: in std_logic;
    n27524_1,n29349_1,n29534_1,n29714,n29894_1,n30074,n30254,n30434,n30614: inout std_logic
  );
end Other__sudoku_check__part60;

architecture Other__sudoku_check__part60_behav of Other__sudoku_check__part60 is
begin
    n27524_1 <= ( lo5777 and not lo5778 and not lo5779 and not lo5780 );
    n29349_1 <= ( lo5777 and not lo5778 and not lo5779 and lo5780 );
    n29534_1 <= ( not lo5777 and not lo5778 and not lo5779 and lo5780 );
    n29714 <= ( lo5777 and lo5778 and lo5779 and not lo5780 );
    n29894_1 <= ( not lo5777 and lo5778 and lo5779 and not lo5780 );
    n30074 <= ( lo5777 and not lo5778 and lo5779 and not lo5780 );
    n30254 <= ( not lo5777 and not lo5778 and lo5779 and not lo5780 );
    n30434 <= ( lo5777 and lo5778 and not lo5779 and not lo5780 );
    n30614 <= ( not lo5777 and lo5778 and not lo5779 and not lo5780 );
end Other__sudoku_check__part60_behav;
