--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part32 is 
  Port (
    lo5665,lo5666,lo5667,lo5668: in std_logic;
    n27189_1,n28904_1,n28909_1,n28914_1,n28919_1,n28924,n28929_1,n28934_1,n28939: inout std_logic
  );
end Other__sudoku_check__part32;

architecture Other__sudoku_check__part32_behav of Other__sudoku_check__part32 is
begin
    n27189_1 <= ( lo5665 and not lo5666 and not lo5667 and not lo5668 );
    n28904_1 <= ( lo5665 and not lo5666 and not lo5667 and lo5668 );
    n28909_1 <= ( not lo5665 and not lo5666 and not lo5667 and lo5668 );
    n28914_1 <= ( lo5665 and lo5666 and lo5667 and not lo5668 );
    n28919_1 <= ( not lo5665 and lo5666 and lo5667 and not lo5668 );
    n28924 <= ( lo5665 and not lo5666 and lo5667 and not lo5668 );
    n28929_1 <= ( not lo5665 and not lo5666 and lo5667 and not lo5668 );
    n28934_1 <= ( lo5665 and lo5666 and not lo5667 and not lo5668 );
    n28939 <= ( not lo5665 and lo5666 and not lo5667 and not lo5668 );
end Other__sudoku_check__part32_behav;
