--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part82 is 
  Port (
    lo2584,lo2602,lo2603,lo2604,lo2605,lo2606: in std_logic;
    n21651,n21741,n21746,n21751,n21756,n21761: inout std_logic
  );
end Other__umass_weather__part82;

architecture Other__umass_weather__part82_behav of Other__umass_weather__part82 is
signal n34889,n34891,n34893,n34895: std_logic;
begin
    n21651 <= ( not lo2584 );
    n21741 <= ( not lo2584 and not lo2602 )
      or ( lo2584 and lo2602 );
    n34889 <= ( not lo2584 and lo2602 );
    n21746 <= ( not lo2603 and n34889 )
      or ( lo2603 and not n34889 );
    n34891 <= ( lo2603 and n34889 );
    n21751 <= ( not lo2604 and n34891 )
      or ( lo2604 and not n34891 );
    n34893 <= ( lo2604 and n34891 );
    n21756 <= ( not lo2605 and n34893 )
      or ( lo2605 and not n34893 );
    n34895 <= ( lo2605 and n34893 );
    n21761 <= ( not lo2606 and n34895 )
      or ( lo2606 and not n34895 );
end Other__umass_weather__part82_behav;
