--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part65 is 
  Port (
    lo1425,lo1442,lo1443,lo1444,lo1445,lo1446: in std_logic;
    n15856,n15941,n15946,n15951,n15956,n15961: inout std_logic
  );
end Other__umass_weather__part65;

architecture Other__umass_weather__part65_behav of Other__umass_weather__part65 is
signal n28255,n28257,n28259,n28261: std_logic;
begin
    n15856 <= ( not lo1425 );
    n15941 <= ( not lo1425 and lo1442 )
      or ( lo1425 and not lo1442 );
    n28255 <= ( lo1425 and lo1442 );
    n15946 <= ( not lo1443 and n28255 )
      or ( lo1443 and not n28255 );
    n28257 <= ( lo1443 and n28255 );
    n15951 <= ( not lo1444 and n28257 )
      or ( lo1444 and not n28257 );
    n28259 <= ( lo1444 and n28257 );
    n15956 <= ( not lo1445 and n28259 )
      or ( lo1445 and not n28259 );
    n28261 <= ( lo1445 and n28259 );
    n15961 <= ( not lo1446 and n28261 )
      or ( lo1446 and not n28261 );
end Other__umass_weather__part65_behav;
