--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part56 is 
  Port (
    lo5761,lo5762,lo5763,lo5764: in std_logic;
    n27424_1,n29404_1,n29589,n29769_1,n29949,n30129,n30309,n30489,n30669: inout std_logic
  );
end Other__sudoku_check__part56;

architecture Other__sudoku_check__part56_behav of Other__sudoku_check__part56 is
begin
    n27424_1 <= ( lo5761 and not lo5762 and not lo5763 and not lo5764 );
    n29404_1 <= ( lo5761 and not lo5762 and not lo5763 and lo5764 );
    n29589 <= ( not lo5761 and not lo5762 and not lo5763 and lo5764 );
    n29769_1 <= ( lo5761 and lo5762 and lo5763 and not lo5764 );
    n29949 <= ( not lo5761 and lo5762 and lo5763 and not lo5764 );
    n30129 <= ( lo5761 and not lo5762 and lo5763 and not lo5764 );
    n30309 <= ( not lo5761 and not lo5762 and lo5763 and not lo5764 );
    n30489 <= ( lo5761 and lo5762 and not lo5763 and not lo5764 );
    n30669 <= ( not lo5761 and lo5762 and not lo5763 and not lo5764 );
end Other__sudoku_check__part56_behav;
