--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part133 is 
  Port (
    lo8756,lo8757,lo8758: in std_logic;
    n49289_1,n49294_1,n49299_1: inout std_logic
  );
end Other__carpat__part133;

architecture Other__carpat__part133_behav of Other__carpat__part133 is
signal n37339,n37340,n135153,n135154,n135155,n135156: std_logic;
begin
    n37339 <= ( not lo8756 and not lo8757 and lo8758 );
    n37340 <= not (( not n135156 and not n37339 ));
    n49289_1 <= ( not lo8756 and not n37340 );
    n49294_1 <= ( not n37340 and n135153 );
    n49299_1 <= ( not n37340 and n135155 );
    n135153 <= ( not lo8757 and lo8756 )
      or ( lo8757 and not lo8756 );
    n135154 <= ( lo8757 and lo8756 );
    n135155 <= ( not lo8758 and n135154 )
      or ( lo8758 and not n135154 );
    n135156 <= ( lo8758 and n135154 );
end Other__carpat__part133_behav;
