--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi34,lo298,lo389: in std_logic;
    po120,n2312,n1857: inout std_logic
  );
end top;

architecture top_behav of top is
signal n2481,n3328,n3359,n4324,n4325,n4641: std_logic;
begin
    po120 <= ( not pi34 );
    n2312 <= not (( not n3328 and not n3359 ));
    n2481 <= ( lo298 and pi34 );
    n1857 <= ( n4641 and n4325 );
    n3328 <= ( lo389 and not n2481 );
    n3359 <= ( not lo389 and n2481 );
    n4324 <= not (( not lo298 and pi34 ));
    n4325 <= not (( pi34 and n4324 ));
    n4641 <= not (( not lo298 and n4324 ));
end top_behav;
