--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part58 is 
  Port (
    lo5769,lo5770,lo5771,lo5772: in std_logic;
    n27434_1,n29464_1,n29649,n29829,n30009,n30189,n30369,n30549,n30729: inout std_logic
  );
end Other__sudoku_check__part58;

architecture Other__sudoku_check__part58_behav of Other__sudoku_check__part58 is
begin
    n27434_1 <= ( lo5769 and not lo5770 and not lo5771 and not lo5772 );
    n29464_1 <= ( lo5769 and not lo5770 and not lo5771 and lo5772 );
    n29649 <= ( not lo5769 and not lo5770 and not lo5771 and lo5772 );
    n29829 <= ( lo5769 and lo5770 and lo5771 and not lo5772 );
    n30009 <= ( not lo5769 and lo5770 and lo5771 and not lo5772 );
    n30189 <= ( lo5769 and not lo5770 and lo5771 and not lo5772 );
    n30369 <= ( not lo5769 and not lo5770 and lo5771 and not lo5772 );
    n30549 <= ( lo5769 and lo5770 and not lo5771 and not lo5772 );
    n30729 <= ( not lo5769 and lo5770 and not lo5771 and not lo5772 );
end Other__sudoku_check__part58_behav;
