--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part67 is 
  Port (
    lo1603,lo1602: in std_logic;
    n5645,n11385_1,n11390_1: inout std_logic
  );
end Other__fp_operators__part67;

architecture Other__fp_operators__part67_behav of Other__fp_operators__part67 is
signal n23105,n23106,n37130,n37131: std_logic;
begin
    n5645 <= ( not lo1603 );
    n23105 <= ( not lo1602 and lo1603 );
    n23106 <= not (( not n37131 and not n23105 ));
    n11385_1 <= ( not lo1602 and not n23106 );
    n11390_1 <= ( not n23106 and n37130 );
    n37130 <= ( not lo1603 and lo1602 )
      or ( lo1603 and not lo1602 );
    n37131 <= ( lo1603 and lo1602 );
end Other__fp_operators__part67_behav;
