--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_des_des3perf__part2 is 
  Port (
    lo5846,lo5847,lo5848,lo5849: in std_logic;
    n30069_1,n30074_1,n30079_1,n30084_1: inout std_logic
  );
end QUIP__oc_des_des3perf__part2;

architecture QUIP__oc_des_des3perf__part2_behav of QUIP__oc_des_des3perf__part2 is
signal n38293,n38295: std_logic;
begin
    n30069_1 <= ( not lo5846 );
    n30074_1 <= ( not lo5847 and lo5846 )
      or ( lo5847 and not lo5846 );
    n38293 <= ( lo5847 and lo5846 );
    n30079_1 <= ( not lo5848 and n38293 )
      or ( lo5848 and not n38293 );
    n38295 <= ( lo5848 and n38293 );
    n30084_1 <= ( not lo5849 and n38295 )
      or ( lo5849 and not n38295 );
end QUIP__oc_des_des3perf__part2_behav;
