--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part48 is 
  Port (
    lo3566,lo3554,lo3530,lo3518,lo3542,lo3494,lo3482,lo3506,lo3458,lo3446,lo3470: in std_logic;
    n18979: inout std_logic
  );
end Cookbook__fec_check__part48;

architecture Cookbook__fec_check__part48_behav of Cookbook__fec_check__part48 is
signal n13622,n13623,n13624,n13625,n13626,n13627,n13628,n13629,n13630: std_logic;
begin
    n13622 <= not (( not lo3566 and not lo3554 ));
    n13623 <= not (( not lo3530 and not lo3518 ));
    n13624 <= not (( not lo3542 and not n13623 ));
    n13625 <= not (( not n13622 and not n13624 ));
    n13626 <= not (( not lo3494 and not lo3482 ));
    n13627 <= not (( not lo3506 and not n13626 ));
    n13628 <= not (( not lo3458 and not lo3446 ));
    n13629 <= not (( not lo3470 and not n13628 ));
    n13630 <= not (( not n13627 and not n13629 ));
    n18979 <= not (( not n13625 and not n13630 ));
end Cookbook__fec_check__part48_behav;
