--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part50 is 
  Port (
    lo5737,lo5738,lo5739,lo5740: in std_logic;
    n27349_1,n27809_1,n27814_1,n27819_1,n27824_1,n27829_1,n27834_1,n27839_1,n27844_1: inout std_logic
  );
end Other__sudoku_check__part50;

architecture Other__sudoku_check__part50_behav of Other__sudoku_check__part50 is
begin
    n27349_1 <= ( lo5737 and not lo5738 and not lo5739 and not lo5740 );
    n27809_1 <= ( lo5737 and not lo5738 and not lo5739 and lo5740 );
    n27814_1 <= ( not lo5737 and not lo5738 and not lo5739 and lo5740 );
    n27819_1 <= ( lo5737 and lo5738 and lo5739 and not lo5740 );
    n27824_1 <= ( not lo5737 and lo5738 and lo5739 and not lo5740 );
    n27829_1 <= ( lo5737 and not lo5738 and lo5739 and not lo5740 );
    n27834_1 <= ( not lo5737 and not lo5738 and lo5739 and not lo5740 );
    n27839_1 <= ( lo5737 and lo5738 and not lo5739 and not lo5740 );
    n27844_1 <= ( not lo5737 and lo5738 and not lo5739 and not lo5740 );
end Other__sudoku_check__part50_behav;
