--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part58 is 
  Port (
    lo3676,lo3664,lo3640,lo3628,lo3652,lo3604,lo3592,lo3616,lo3568,lo3556,lo3580: in std_logic;
    n19029: inout std_logic
  );
end Cookbook__fec_check__part58;

architecture Cookbook__fec_check__part58_behav of Cookbook__fec_check__part58 is
signal n13522,n13523,n13524,n13525,n13526,n13527,n13528,n13529,n13530: std_logic;
begin
    n13522 <= not (( not lo3676 and not lo3664 ));
    n13523 <= not (( not lo3640 and not lo3628 ));
    n13524 <= not (( not lo3652 and not n13523 ));
    n13525 <= not (( not n13522 and not n13524 ));
    n13526 <= not (( not lo3604 and not lo3592 ));
    n13527 <= not (( not lo3616 and not n13526 ));
    n13528 <= not (( not lo3568 and not lo3556 ));
    n13529 <= not (( not lo3580 and not n13528 ));
    n13530 <= not (( not n13527 and not n13529 ));
    n19029 <= not (( not n13525 and not n13530 ));
end Cookbook__fec_check__part58_behav;
