--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part1 is 
  Port (
    pi003,pi067,pi002,pi066,pi001,pi065: in std_logic;
    n389: inout std_logic
  );
end Cookbook__pipe_equal__part1;

architecture Cookbook__pipe_equal__part1_behav of Cookbook__pipe_equal__part1 is
signal n313,n314,n315,n316: std_logic;
begin
    n313 <= ( not pi003 and pi067 )
      or ( pi003 and not pi067 );
    n314 <= ( not pi002 and pi066 )
      or ( pi002 and not pi066 );
    n315 <= ( not pi001 and pi065 )
      or ( pi001 and not pi065 );
    n316 <= not (( not n314 and not n315 ));
    n389 <= ( not n313 and not n316 );
end Cookbook__pipe_equal__part1_behav;
