--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part19 is 
  Port (
    lo5613,lo5614,lo5615,lo5616: in std_logic;
    n27124_1,n29024_1,n29029,n29034_1,n29039_1,n29044,n29049_1,n29054_1,n29059: inout std_logic
  );
end Other__sudoku_check__part19;

architecture Other__sudoku_check__part19_behav of Other__sudoku_check__part19 is
begin
    n27124_1 <= ( lo5613 and not lo5614 and not lo5615 and not lo5616 );
    n29024_1 <= ( lo5613 and not lo5614 and not lo5615 and lo5616 );
    n29029 <= ( not lo5613 and not lo5614 and not lo5615 and lo5616 );
    n29034_1 <= ( lo5613 and lo5614 and lo5615 and not lo5616 );
    n29039_1 <= ( not lo5613 and lo5614 and lo5615 and not lo5616 );
    n29044 <= ( lo5613 and not lo5614 and lo5615 and not lo5616 );
    n29049_1 <= ( not lo5613 and not lo5614 and lo5615 and not lo5616 );
    n29054_1 <= ( lo5613 and lo5614 and not lo5615 and not lo5616 );
    n29059 <= ( not lo5613 and lo5614 and not lo5615 and not lo5616 );
end Other__sudoku_check__part19_behav;
