--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_hdlc__part4 is 
  Port (
    lo317,lo318,lo319,lo316,lo320,lo321,lo322,lo323: in std_logic;
    n1731,n1736: inout std_logic
  );
end QUIP__oc_hdlc__part4;

architecture QUIP__oc_hdlc__part4_behav of QUIP__oc_hdlc__part4 is
signal n1888,n1889: std_logic;
begin
    n1888 <= ( lo317 and lo318 and lo319 and not lo316 );
    n1889 <= ( n1888 and lo320 and lo321 and lo322 );
    n1731 <= ( n1889 and not lo323 );
    n1736 <= ( lo323 and n1889 );
end QUIP__oc_hdlc__part4_behav;
