--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part20 is 
  Port (
    pi060,pi124,pi059,pi123,pi058,pi122: in std_logic;
    n294_1: inout std_logic
  );
end Cookbook__pipe_equal__part20;

architecture Cookbook__pipe_equal__part20_behav of Cookbook__pipe_equal__part20 is
signal n218,n219,n220,n221: std_logic;
begin
    n218 <= ( not pi060 and pi124 )
      or ( pi060 and not pi124 );
    n219 <= ( not pi059 and pi123 )
      or ( pi059 and not pi123 );
    n220 <= ( not pi058 and pi122 )
      or ( pi058 and not pi122 );
    n221 <= not (( not n219 and not n220 ));
    n294_1 <= ( not n218 and not n221 );
end Cookbook__pipe_equal__part20_behav;
