--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__xor5 is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0: inout std_logic
  );
end IWLS93__xor5;

architecture IWLS93__xor5_behav of IWLS93__xor5 is
signal n7,n8,n9,n10,n11,n12,n13,n14,n15,n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41: std_logic;
begin
    po0 <= ( n41 )
      or ( n33 );
    n7 <= ( not pi1 and pi2 and pi3 );
    n8 <= ( pi1 and not pi2 and pi3 );
    n9 <= ( pi0 and pi4 );
    n10 <= ( pi1 and not pi2 and not pi3 );
    n11 <= ( n9 and n10 );
    n12 <= ( pi0 and not pi4 );
    n13 <= ( n12 and n7 );
    n14 <= ( pi1 and pi2 and pi3 );
    n15 <= ( pi1 and pi2 and not pi3 );
    n16 <= ( n12 and n15 );
    n17 <= ( n12 and n8 );
    n18 <= ( n9 and n14 );
    n19 <= ( n9 and n24 );
    n20 <= ( n9 and n35 );
    n21 <= ( n19 )
      or ( n13 )
      or ( n20 );
    n22 <= ( not pi0 and not pi4 );
    n23 <= ( n22 and n10 );
    n24 <= ( not pi1 and pi2 and not pi3 );
    n25 <= ( n22 and n14 );
    n26 <= ( n12 and n39 );
    n27 <= ( n29 and n15 );
    n28 <= ( n25 )
      or ( n26 )
      or ( n27 );
    n29 <= ( not pi0 and pi4 );
    n30 <= ( n29 and n8 );
    n31 <= ( n23 )
      or ( n30 )
      or ( n37 );
    n32 <= ( n38 )
      or ( n34 )
      or ( n40 );
    n33 <= ( n31 )
      or ( n28 )
      or ( n32 );
    n34 <= ( n22 and n24 );
    n35 <= ( not pi1 and not pi2 and pi3 );
    n36 <= ( n17 )
      or ( n16 )
      or ( n11 );
    n37 <= ( n29 and n7 );
    n38 <= ( n22 and n35 );
    n39 <= ( not pi1 and not pi2 and not pi3 );
    n40 <= ( n29 and n39 );
    n41 <= ( n36 )
      or ( n18 )
      or ( n21 );
end IWLS93__xor5_behav;
