--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part138 is 
  Port (
    lo8794,lo8795,lo8796: in std_logic;
    n49479_1,n49484_1,n49489_1: inout std_logic
  );
end Other__carpat__part138;

architecture Other__carpat__part138_behav of Other__carpat__part138 is
signal n37758,n37759,n135296,n135297,n135298,n135299: std_logic;
begin
    n37758 <= ( not lo8794 and lo8795 and lo8796 );
    n37759 <= not (( not n135299 and not n37758 ));
    n49479_1 <= ( not lo8794 and not n37759 );
    n49484_1 <= ( not n37759 and n135296 );
    n49489_1 <= ( not n37759 and n135298 );
    n135296 <= ( not lo8795 and lo8794 )
      or ( lo8795 and not lo8794 );
    n135297 <= ( lo8795 and lo8794 );
    n135298 <= ( not lo8796 and n135297 )
      or ( lo8796 and not n135297 );
    n135299 <= ( lo8796 and n135297 );
end Other__carpat__part138_behav;
