--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part64 is 
  Port (
    lo1581,lo1582,lo1583: in std_logic;
    n11280_1,n11285_1,n11290_1: inout std_logic
  );
end Other__fp_operators__part64;

architecture Other__fp_operators__part64_behav of Other__fp_operators__part64 is
signal n20953,n20954,n37104,n37105,n37106,n37107: std_logic;
begin
    n20953 <= ( not lo1581 and not lo1582 and lo1583 );
    n20954 <= not (( not n37107 and not n20953 ));
    n11280_1 <= ( not lo1581 and not n20954 );
    n11285_1 <= ( not n20954 and n37104 );
    n11290_1 <= ( not n20954 and n37106 );
    n37104 <= ( not lo1582 and lo1581 )
      or ( lo1582 and not lo1581 );
    n37105 <= ( lo1582 and lo1581 );
    n37106 <= ( not lo1583 and n37105 )
      or ( lo1583 and not n37105 );
    n37107 <= ( lo1583 and n37105 );
end Other__fp_operators__part64_behav;
