--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part8 is 
  Port (
    pi024,pi088,pi023,pi087,pi022,pi086: in std_logic;
    n354: inout std_logic
  );
end Cookbook__pipe_equal__part8;

architecture Cookbook__pipe_equal__part8_behav of Cookbook__pipe_equal__part8 is
signal n278,n279,n280,n281: std_logic;
begin
    n278 <= ( not pi024 and pi088 )
      or ( pi024 and not pi088 );
    n279 <= ( not pi023 and pi087 )
      or ( pi023 and not pi087 );
    n280 <= ( not pi022 and pi086 )
      or ( pi022 and not pi086 );
    n281 <= not (( not n279 and not n280 ));
    n354 <= ( not n278 and not n281 );
end Cookbook__pipe_equal__part8_behav;
