--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part3 is 
  Port (
    pi009,pi073,pi008,pi072,pi007,pi071: in std_logic;
    n379: inout std_logic
  );
end Cookbook__pipe_equal__part3;

architecture Cookbook__pipe_equal__part3_behav of Cookbook__pipe_equal__part3 is
signal n303,n304,n305,n306: std_logic;
begin
    n303 <= ( not pi009 and pi073 )
      or ( pi009 and not pi073 );
    n304 <= ( not pi008 and pi072 )
      or ( pi008 and not pi072 );
    n305 <= ( not pi007 and pi071 )
      or ( pi007 and not pi071 );
    n306 <= not (( not n304 and not n305 ));
    n379 <= ( not n303 and not n306 );
end Cookbook__pipe_equal__part3_behav;
