--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part21 is 
  Port (
    pi063,pi127,pi062,pi126,pi061,pi125: in std_logic;
    n289_1: inout std_logic
  );
end Cookbook__pipe_equal__part21;

architecture Cookbook__pipe_equal__part21_behav of Cookbook__pipe_equal__part21 is
signal n213,n214,n215,n216: std_logic;
begin
    n213 <= ( not pi063 and pi127 )
      or ( pi063 and not pi127 );
    n214 <= ( not pi062 and pi126 )
      or ( pi062 and not pi126 );
    n215 <= ( not pi061 and pi125 )
      or ( pi061 and not pi125 );
    n216 <= not (( not n214 and not n215 ));
    n289_1 <= ( not n213 and not n216 );
end Cookbook__pipe_equal__part21_behav;
