--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part62 is 
  Port (
    lo5785,lo5786,lo5787,lo5788: in std_logic;
    n27534_1,n29409_1,n29594_1,n29774_1,n29954,n30134,n30314,n30494,n30674: inout std_logic
  );
end Other__sudoku_check__part62;

architecture Other__sudoku_check__part62_behav of Other__sudoku_check__part62 is
begin
    n27534_1 <= ( lo5785 and not lo5786 and not lo5787 and not lo5788 );
    n29409_1 <= ( lo5785 and not lo5786 and not lo5787 and lo5788 );
    n29594_1 <= ( not lo5785 and not lo5786 and not lo5787 and lo5788 );
    n29774_1 <= ( lo5785 and lo5786 and lo5787 and not lo5788 );
    n29954 <= ( not lo5785 and lo5786 and lo5787 and not lo5788 );
    n30134 <= ( lo5785 and not lo5786 and lo5787 and not lo5788 );
    n30314 <= ( not lo5785 and not lo5786 and lo5787 and not lo5788 );
    n30494 <= ( lo5785 and lo5786 and not lo5787 and not lo5788 );
    n30674 <= ( not lo5785 and lo5786 and not lo5787 and not lo5788 );
end Other__sudoku_check__part62_behav;
