--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part48 is 
  Port (
    lo0913,lo0914: in std_logic;
    n6435,n6445,n6475,n6525,n6535,n6580: inout std_logic
  );
end Other__fp_operators__part48;

architecture Other__fp_operators__part48_behav of Other__fp_operators__part48 is
signal n6545,n24959,n24962: std_logic;
begin
    n6435 <= ( not lo0913 and lo0914 )
      or ( lo0913 and not lo0914 );
    n6545 <= ( lo0913 and lo0914 );
    n6445 <= ( not lo0913 and not lo0914 and n6545 )
      or ( not lo0913 and lo0914 and not n6545 )
      or ( lo0913 and not lo0914 and not n6545 )
      or ( lo0913 and lo0914 and n6545 );
    n6475 <= ( lo0913 and not n6545 );
    n24959 <= ( lo0913 and n6545 );
    n6525 <= ( lo0914 and not n24959 );
    n24962 <= ( lo0914 and n24959 );
    n6535 <= ( lo0913 and not n24962 );
    n6580 <= ( lo0914 and not n6545 );
end Other__fp_operators__part48_behav;
