--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__insert_parity__part1 is 
  Port (
    pi17,pi16,pi15,pi14,pi13,pi12,pi10,pi09,pi11: in std_logic;
    po1: inout std_logic
  );
end Cookbook__insert_parity__part1;

architecture Cookbook__insert_parity__part1_behav of Cookbook__insert_parity__part1 is
signal n74,n75,n76,n77,n78,n79,n80: std_logic;
begin
    n74 <= ( not pi17 and pi16 )
      or ( pi17 and not pi16 );
    n75 <= ( not pi15 and pi14 )
      or ( pi15 and not pi14 );
    n76 <= ( not n74 and n75 )
      or ( n74 and not n75 );
    n77 <= ( not pi13 and pi12 )
      or ( pi13 and not pi12 );
    n78 <= ( not pi10 and pi09 )
      or ( pi10 and not pi09 );
    n79 <= ( not pi11 and n78 )
      or ( pi11 and not n78 );
    n80 <= ( not n77 and n79 )
      or ( n77 and not n79 );
    po1 <= ( not n76 and not n80 )
      or ( n76 and n80 );
end Cookbook__insert_parity__part1_behav;
