--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    lo018,lo086,lo474,lo128,lo458,lo442,lo186,lo131,lo400,lo245,lo072,lo158,lo429: in std_logic;
    po042: inout std_logic
  );
end top;

architecture top_behav of top is
signal n2678,n2679,n2680: std_logic;
begin
    po042 <= ( not lo018 and not n2678 and not n2679 and not n2680 );
    n2678 <= ( lo086 )
      or ( lo474 )
      or ( lo128 )
      or ( lo458 );
    n2679 <= ( lo442 )
      or ( lo186 )
      or ( lo131 )
      or ( lo400 );
    n2680 <= ( lo245 )
      or ( lo072 )
      or ( lo158 )
      or ( lo429 );
end top_behav;
