--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part87 is 
  Port (
    lo5885,lo5886,lo5887,lo5888: in std_logic;
    n27979_1,n28219_1,n28224_1,n28229_1,n28234_1,n28239_1,n28244_1,n28249_1,n28254_1: inout std_logic
  );
end Other__sudoku_check__part87;

architecture Other__sudoku_check__part87_behav of Other__sudoku_check__part87 is
begin
    n27979_1 <= ( lo5885 and not lo5886 and not lo5887 and not lo5888 );
    n28219_1 <= ( lo5885 and not lo5886 and not lo5887 and lo5888 );
    n28224_1 <= ( not lo5885 and not lo5886 and not lo5887 and lo5888 );
    n28229_1 <= ( lo5885 and lo5886 and lo5887 and not lo5888 );
    n28234_1 <= ( not lo5885 and lo5886 and lo5887 and not lo5888 );
    n28239_1 <= ( lo5885 and not lo5886 and lo5887 and not lo5888 );
    n28244_1 <= ( not lo5885 and not lo5886 and lo5887 and not lo5888 );
    n28249_1 <= ( lo5885 and lo5886 and not lo5887 and not lo5888 );
    n28254_1 <= ( not lo5885 and lo5886 and not lo5887 and not lo5888 );
end Other__sudoku_check__part87_behav;
