--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10: in std_logic;
    po0,po1,po2,po3,po4,po5: inout std_logic
  );
end top;

architecture top_behav of top is
signal n18,n20,n22,n24: std_logic;
begin
    po5 <= ( not pi10 and not pi08 and pi09 )
      or ( not pi10 and pi08 and not pi09 )
      or ( pi10 and not pi08 and not pi09 )
      or ( pi10 and pi08 and pi09 );
    n18 <= ( pi10 and pi08 )
      or ( pi10 and pi09 )
      or ( pi08 and pi09 );
    po4 <= ( not n18 and not pi03 and pi07 )
      or ( not n18 and pi03 and not pi07 )
      or ( n18 and not pi03 and not pi07 )
      or ( n18 and pi03 and pi07 );
    n20 <= ( n18 and pi03 )
      or ( n18 and pi07 )
      or ( pi03 and pi07 );
    po3 <= ( not n20 and not pi02 and pi06 )
      or ( not n20 and pi02 and not pi06 )
      or ( n20 and not pi02 and not pi06 )
      or ( n20 and pi02 and pi06 );
    n22 <= ( n20 and pi02 )
      or ( n20 and pi06 )
      or ( pi02 and pi06 );
    po2 <= ( not n22 and not pi01 and pi05 )
      or ( not n22 and pi01 and not pi05 )
      or ( n22 and not pi01 and not pi05 )
      or ( n22 and pi01 and pi05 );
    n24 <= ( n22 and pi01 )
      or ( n22 and pi05 )
      or ( pi01 and pi05 );
    po1 <= ( not n24 and not pi00 and pi04 )
      or ( not n24 and pi00 and not pi04 )
      or ( n24 and not pi00 and not pi04 )
      or ( n24 and pi00 and pi04 );
    po0 <= ( n24 and pi00 )
      or ( n24 and pi04 )
      or ( pi00 and pi04 );
end top_behav;
