--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part19 is 
  Port (
    lo04247,lo04249,lo04250,lo04248,lo04251: in std_logic;
    n27646,n27651,n27661,n27656,n27666: inout std_logic
  );
end QUIP__uoft_raytracer__part19;

architecture QUIP__uoft_raytracer__part19_behav of QUIP__uoft_raytracer__part19 is
signal n53146,n53147,n77414,n77415: std_logic;
begin
    n53146 <= ( not lo04247 and not lo04249 and not lo04250 );
    n53147 <= ( lo04248 and lo04251 and n53146 )
      or ( lo04251 and n77415 );
    n27646 <= ( not lo04247 and not n53147 );
    n27651 <= ( not lo04248 and lo04247 and not n53147 )
      or ( lo04248 and not lo04247 and not n53147 );
    n27661 <= ( not lo04250 and n77414 and not n53147 )
      or ( lo04250 and not n77414 and not n53147 );
    n77414 <= ( lo04248 and lo04247 and lo04249 );
    n77415 <= ( lo04248 and lo04247 and lo04249 and lo04250 );
    n27656 <= ( not lo04248 and lo04249 and not n53147 )
      or ( lo04248 and lo04247 and not lo04249 and not n53147 )
      or ( not lo04247 and lo04249 and not n53147 );
    n27666 <= ( not lo04248 and lo04251 and not n77415 )
      or ( not lo04251 and n77415 )
      or ( lo04251 and not n77415 and not n53146 );
end QUIP__uoft_raytracer__part19_behav;
