--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part4 is 
  Port (
    lo58,lo59,lo60,lo61,lo62,lo63,lo64,lo65,lo66,lo67,lo68,lo69: in std_logic;
    n323_1,n328_1,n333_1,n338_1,n343,n348_1,n353,n358,n363,n368,n373,n378: inout std_logic
  );
end Cookbook__temp_sense_s5__part4;

architecture Cookbook__temp_sense_s5__part4_behav of Cookbook__temp_sense_s5__part4 is
signal n228,n230,n232,n234,n236,n238,n240,n242,n244,n246: std_logic;
begin
    n323_1 <= ( not lo58 );
    n328_1 <= ( not lo58 and lo59 )
      or ( lo58 and not lo59 );
    n228 <= ( lo58 and lo59 );
    n333_1 <= ( not n228 and lo60 )
      or ( n228 and not lo60 );
    n230 <= ( n228 and lo60 );
    n338_1 <= ( not n230 and lo61 )
      or ( n230 and not lo61 );
    n232 <= ( n230 and lo61 );
    n343 <= ( not n232 and lo62 )
      or ( n232 and not lo62 );
    n234 <= ( n232 and lo62 );
    n348_1 <= ( not n234 and lo63 )
      or ( n234 and not lo63 );
    n236 <= ( n234 and lo63 );
    n353 <= ( not n236 and lo64 )
      or ( n236 and not lo64 );
    n238 <= ( n236 and lo64 );
    n358 <= ( not n238 and lo65 )
      or ( n238 and not lo65 );
    n240 <= ( n238 and lo65 );
    n363 <= ( not n240 and lo66 )
      or ( n240 and not lo66 );
    n242 <= ( n240 and lo66 );
    n368 <= ( not n242 and lo67 )
      or ( n242 and not lo67 );
    n244 <= ( n242 and lo67 );
    n373 <= ( not n244 and lo68 )
      or ( n244 and not lo68 );
    n246 <= ( n244 and lo68 );
    n378 <= ( not n246 and lo69 )
      or ( n246 and not lo69 );
end Cookbook__temp_sense_s5__part4_behav;
