--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part55 is 
  Port (
    lo3643,lo3631,lo3607,lo3595,lo3619,lo3571,lo3559,lo3583,lo3535,lo3523,lo3547: in std_logic;
    n19014: inout std_logic
  );
end Cookbook__fec_check__part55;

architecture Cookbook__fec_check__part55_behav of Cookbook__fec_check__part55 is
signal n13552,n13553,n13554,n13555,n13556,n13557,n13558,n13559,n13560: std_logic;
begin
    n13552 <= not (( not lo3643 and not lo3631 ));
    n13553 <= not (( not lo3607 and not lo3595 ));
    n13554 <= not (( not lo3619 and not n13553 ));
    n13555 <= not (( not n13552 and not n13554 ));
    n13556 <= not (( not lo3571 and not lo3559 ));
    n13557 <= not (( not lo3583 and not n13556 ));
    n13558 <= not (( not lo3535 and not lo3523 ));
    n13559 <= not (( not lo3547 and not n13558 ));
    n13560 <= not (( not n13557 and not n13559 ));
    n19014 <= not (( not n13555 and not n13560 ));
end Cookbook__fec_check__part55_behav;
