--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part68 is 
  Port (
    lo5809,lo5810,lo5811,lo5812: in std_logic;
    n27644_1,n29399_1,n29584,n29764,n29944_1,n30124,n30304,n30484,n30664: inout std_logic
  );
end Other__sudoku_check__part68;

architecture Other__sudoku_check__part68_behav of Other__sudoku_check__part68 is
begin
    n27644_1 <= ( lo5809 and not lo5810 and not lo5811 and not lo5812 );
    n29399_1 <= ( lo5809 and not lo5810 and not lo5811 and lo5812 );
    n29584 <= ( not lo5809 and not lo5810 and not lo5811 and lo5812 );
    n29764 <= ( lo5809 and lo5810 and lo5811 and not lo5812 );
    n29944_1 <= ( not lo5809 and lo5810 and lo5811 and not lo5812 );
    n30124 <= ( lo5809 and not lo5810 and lo5811 and not lo5812 );
    n30304 <= ( not lo5809 and not lo5810 and lo5811 and not lo5812 );
    n30484 <= ( lo5809 and lo5810 and not lo5811 and not lo5812 );
    n30664 <= ( not lo5809 and lo5810 and not lo5811 and not lo5812 );
end Other__sudoku_check__part68_behav;
