--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part143 is 
  Port (
    lo9233,lo9234,lo9235: in std_logic;
    n51674_1,n51679_1,n51684_1: inout std_logic
  );
end Other__carpat__part143;

architecture Other__carpat__part143_behav of Other__carpat__part143 is
signal n136720: std_logic;
begin
    n51674_1 <= ( not lo9233 );
    n51679_1 <= ( not lo9234 and lo9233 )
      or ( lo9234 and not lo9233 );
    n136720 <= ( lo9234 and lo9233 );
    n51684_1 <= ( not lo9235 and n136720 )
      or ( lo9235 and not n136720 );
end Other__carpat__part143_behav;
