--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26,pi27,pi28,pi29,pi30: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15: inout std_logic
  );
end top;

architecture top_behav of top is
signal n48,n50,n52,n54,n56,n58,n60,n62,n64,n66,n68,n70,n72,n74: std_logic;
begin
    po15 <= ( not pi30 and not pi14 and pi29 )
      or ( not pi30 and pi14 and not pi29 )
      or ( pi30 and not pi14 and not pi29 )
      or ( pi30 and pi14 and pi29 );
    n48 <= ( pi30 and pi14 )
      or ( pi30 and pi29 )
      or ( pi14 and pi29 );
    po14 <= ( not n48 and not pi13 and pi28 )
      or ( not n48 and pi13 and not pi28 )
      or ( n48 and not pi13 and not pi28 )
      or ( n48 and pi13 and pi28 );
    n50 <= ( n48 and pi13 )
      or ( n48 and pi28 )
      or ( pi13 and pi28 );
    po13 <= ( not n50 and not pi12 and pi27 )
      or ( not n50 and pi12 and not pi27 )
      or ( n50 and not pi12 and not pi27 )
      or ( n50 and pi12 and pi27 );
    n52 <= ( n50 and pi12 )
      or ( n50 and pi27 )
      or ( pi12 and pi27 );
    po12 <= ( not n52 and not pi11 and pi26 )
      or ( not n52 and pi11 and not pi26 )
      or ( n52 and not pi11 and not pi26 )
      or ( n52 and pi11 and pi26 );
    n54 <= ( n52 and pi11 )
      or ( n52 and pi26 )
      or ( pi11 and pi26 );
    po11 <= ( not n54 and not pi10 and pi25 )
      or ( not n54 and pi10 and not pi25 )
      or ( n54 and not pi10 and not pi25 )
      or ( n54 and pi10 and pi25 );
    n56 <= ( n54 and pi10 )
      or ( n54 and pi25 )
      or ( pi10 and pi25 );
    po10 <= ( not n56 and not pi09 and pi24 )
      or ( not n56 and pi09 and not pi24 )
      or ( n56 and not pi09 and not pi24 )
      or ( n56 and pi09 and pi24 );
    n58 <= ( n56 and pi09 )
      or ( n56 and pi24 )
      or ( pi09 and pi24 );
    po09 <= ( not n58 and not pi08 and pi23 )
      or ( not n58 and pi08 and not pi23 )
      or ( n58 and not pi08 and not pi23 )
      or ( n58 and pi08 and pi23 );
    n60 <= ( n58 and pi08 )
      or ( n58 and pi23 )
      or ( pi08 and pi23 );
    po08 <= ( not n60 and not pi07 and pi22 )
      or ( not n60 and pi07 and not pi22 )
      or ( n60 and not pi07 and not pi22 )
      or ( n60 and pi07 and pi22 );
    n62 <= ( n60 and pi07 )
      or ( n60 and pi22 )
      or ( pi07 and pi22 );
    po07 <= ( not n62 and not pi06 and pi21 )
      or ( not n62 and pi06 and not pi21 )
      or ( n62 and not pi06 and not pi21 )
      or ( n62 and pi06 and pi21 );
    n64 <= ( n62 and pi06 )
      or ( n62 and pi21 )
      or ( pi06 and pi21 );
    po06 <= ( not n64 and not pi05 and pi20 )
      or ( not n64 and pi05 and not pi20 )
      or ( n64 and not pi05 and not pi20 )
      or ( n64 and pi05 and pi20 );
    n66 <= ( n64 and pi05 )
      or ( n64 and pi20 )
      or ( pi05 and pi20 );
    po05 <= ( not n66 and not pi04 and pi19 )
      or ( not n66 and pi04 and not pi19 )
      or ( n66 and not pi04 and not pi19 )
      or ( n66 and pi04 and pi19 );
    n68 <= ( n66 and pi04 )
      or ( n66 and pi19 )
      or ( pi04 and pi19 );
    po04 <= ( not n68 and not pi03 and pi18 )
      or ( not n68 and pi03 and not pi18 )
      or ( n68 and not pi03 and not pi18 )
      or ( n68 and pi03 and pi18 );
    n70 <= ( n68 and pi03 )
      or ( n68 and pi18 )
      or ( pi03 and pi18 );
    po03 <= ( not n70 and not pi02 and pi17 )
      or ( not n70 and pi02 and not pi17 )
      or ( n70 and not pi02 and not pi17 )
      or ( n70 and pi02 and pi17 );
    n72 <= ( n70 and pi02 )
      or ( n70 and pi17 )
      or ( pi02 and pi17 );
    po02 <= ( not n72 and not pi01 and pi16 )
      or ( not n72 and pi01 and not pi16 )
      or ( n72 and not pi01 and not pi16 )
      or ( n72 and pi01 and pi16 );
    n74 <= ( n72 and pi01 )
      or ( n72 and pi16 )
      or ( pi01 and pi16 );
    po01 <= ( not n74 and not pi00 and pi15 )
      or ( not n74 and pi00 and not pi15 )
      or ( n74 and not pi00 and not pi15 )
      or ( n74 and pi00 and pi15 );
    po00 <= ( n74 and pi00 )
      or ( n74 and pi15 )
      or ( pi00 and pi15 );
end top_behav;
