--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__majority is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0: inout std_logic
  );
end IWLS93__majority;

architecture IWLS93__majority_behav of IWLS93__majority is
signal n7,n8,n9,n10,n11,n12,n13: std_logic;
begin
    po0 <= ( not n11 );
    n7 <= ( not pi1 and not pi2 and not pi3 );
    n8 <= ( not pi2 and not pi3 and not pi4 );
    n9 <= ( not pi1 and not pi3 and not pi4 );
    n10 <= ( not pi0 and not pi3 and not pi4 );
    n11 <= ( n10 )
      or ( n9 )
      or ( n12 )
      or ( n7 )
      or ( n13 )
      or ( n8 );
    n12 <= ( not pi0 and not pi2 and not pi3 );
    n13 <= ( not pi0 and not pi1 and not pi3 );
end IWLS93__majority_behav;
