--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_3 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10: inout std_logic
  );
end Cookbook__fec_rot_3;

architecture Cookbook__fec_rot_3_behav of Cookbook__fec_rot_3 is
signal n24: std_logic;
begin
    n24 <= ( not pi05 and pi02 )
      or ( pi05 and not pi02 );
    po10 <= ( not pi02 and pi00 )
      or ( pi02 and not pi00 );
    po09 <= ( not pi12 and pi01 )
      or ( pi12 and not pi01 );
    po08 <= ( not pi11 and pi00 )
      or ( pi11 and not pi00 );
    po07 <= ( not pi10 and pi02 )
      or ( pi10 and not pi02 );
    po06 <= ( not pi09 and pi01 )
      or ( pi09 and not pi01 );
    po05 <= ( not pi08 and pi00 )
      or ( pi08 and not pi00 );
    po04 <= ( not pi07 and pi02 )
      or ( pi07 and not pi02 );
    po03 <= ( not pi06 and pi01 )
      or ( pi06 and not pi01 );
    po02 <= ( not n24 and pi00 )
      or ( n24 and not pi00 );
    po01 <= ( not pi04 and pi01 )
      or ( pi04 and not pi01 );
    po00 <= ( not pi03 and pi00 )
      or ( pi03 and not pi00 );
end Cookbook__fec_rot_3_behav;
