--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__daio is 
  Port (
    pi0, CLK: in std_logic;
    po0,po1: inout std_logic
  );
end IWLS93__daio;

architecture IWLS93__daio_behav of IWLS93__daio is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,li0,li1,n18,n19,n20,n21,n22,n23,n24,n25,li2,li3: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    li0 <= ( not lo0 )
      or ( po0 );
    li1 <= ( n20 )
      or ( n21 );
    po0 <= ( n18 and n19 );
    n18 <= ( n24 )
      or ( n25 );
    n19 <= ( n22 )
      or ( n23 );
    n20 <= ( not lo0 and not n18 );
    n21 <= ( lo0 and lo1 );
    n22 <= ( pi0 and lo2 );
    n23 <= ( not pi0 and not lo2 );
    n24 <= ( lo2 and lo3 );
    n25 <= ( not lo2 and not lo3 );
    li2 <= ( pi0 );
    li3 <= ( lo2 );
    po1 <= ( lo1 );
end IWLS93__daio_behav;
