--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part11 is 
  Port (
    pi27, CLK: in std_logic;
    po027: inout std_logic
  );
end Cookbook__lc_mult_signed__part11;

architecture Cookbook__lc_mult_signed__part11_behav of Cookbook__lc_mult_signed__part11 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo002,li002: std_logic;
begin
    DFF0: DFF port map (li002, CLK, lo002);
    li002 <= ( pi27 );
    po027 <= ( lo002 );
end Cookbook__lc_mult_signed__part11_behav;
