--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part91 is 
  Port (
    pi0215, CLK: in std_logic;
    po0507: inout std_logic
  );
end Other__umass_weather__part91;

architecture Other__umass_weather__part91_behav of Other__umass_weather__part91 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0593,li0593: std_logic;
begin
    DFF0: DFF port map (li0593, CLK, lo0593);
    li0593 <= ( pi0215 );
    po0507 <= ( lo0593 );
end Other__umass_weather__part91_behav;
