--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense__part1 is 
  Port (
    , CLK: in std_logic;
    po28: inout std_logic
  );
end Cookbook__temp_sense__part1;

architecture Cookbook__temp_sense__part1_behav of Cookbook__temp_sense__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo21,lo78,li78,li21: std_logic;
begin
    DFF0: DFF port map (li21, CLK, lo21);
    DFF1: DFF port map (li78, CLK, lo78);
    li78 <= ( not lo78 );
    li21 <= '0';
    po28 <= ( lo21 );
end Cookbook__temp_sense__part1_behav;
