--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_9__part0 is 
  Port (
    pi17,pi08,pi15,pi06,pi13,pi04,pi11,pi02,pi00,pi29,pi28,pi26,pi24,pi22,pi20,pi19,pi09: in std_logic;
    po28,po26,po24,po22,po20,po19,po17,po15,po13,po11,po10,po08,po06,po04,po02,po00: inout std_logic
  );
end Cookbook__fec_rot_9__part0;

architecture Cookbook__fec_rot_9__part0_behav of Cookbook__fec_rot_9__part0 is
signal n60,n62,n64,n66: std_logic;
begin
    n60 <= ( not pi17 and pi08 )
      or ( pi17 and not pi08 );
    n62 <= ( not pi15 and pi06 )
      or ( pi15 and not pi06 );
    n64 <= ( not pi13 and pi04 )
      or ( pi13 and not pi04 );
    n66 <= ( not pi11 and pi02 )
      or ( pi11 and not pi02 );
    po28 <= ( not pi08 and pi06 )
      or ( pi08 and not pi06 );
    po26 <= ( not pi06 and pi04 )
      or ( pi06 and not pi04 );
    po24 <= ( not pi04 and pi02 )
      or ( pi04 and not pi02 );
    po22 <= ( not pi02 and pi00 )
      or ( pi02 and not pi00 );
    po20 <= ( not pi29 and pi00 )
      or ( pi29 and not pi00 );
    po19 <= ( not pi28 and pi08 )
      or ( pi28 and not pi08 );
    po17 <= ( not pi26 and pi06 )
      or ( pi26 and not pi06 );
    po15 <= ( not pi24 and pi04 )
      or ( pi24 and not pi04 );
    po13 <= ( not pi22 and pi02 )
      or ( pi22 and not pi02 );
    po11 <= ( not pi20 and pi00 )
      or ( pi20 and not pi00 );
    po10 <= ( not pi19 and pi08 )
      or ( pi19 and not pi08 );
    po08 <= ( not n60 and pi06 )
      or ( n60 and not pi06 );
    po06 <= ( not n62 and pi04 )
      or ( n62 and not pi04 );
    po04 <= ( not n64 and pi02 )
      or ( n64 and not pi02 );
    po02 <= ( not n66 and pi00 )
      or ( n66 and not pi00 );
    po00 <= ( not pi09 and pi00 )
      or ( pi09 and not pi00 );
end Cookbook__fec_rot_9__part0_behav;
