--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_8bit is 
  Port (
    , CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17,po18,po19,po20,po21: inout std_logic
  );
end Cookbook__soft_ecc_ram_8bit;

architecture Cookbook__soft_ecc_ram_8bit_behav of Cookbook__soft_ecc_ram_8bit is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,lo12,lo13,lo14,lo15,lo16,lo17,lo18,lo19,lo20,lo21,lo22,lo23,lo24,lo25,lo26,lo27,lo28,lo29,lo30,lo31,lo32,lo33,lo34,lo35,lo36,lo37,lo38,lo39,lo40,lo41,lo42,lo43,lo44,lo45,lo46,lo47,li11,li10,li09,li08,li12,n171,n172,n173,n174,n175,n176,n177,n178,n179,n180,n181,n182,n183,n184,n185,n186,n187,n188,n189,n190,n191,n192,n193,n194,n195,n196,n197,n198,n199,n200,li14,n202,n203,n204,li23,li15,li16,li17,li18,li19,li20,li21,li22,li00,li01,li02,li03,li04,li05,li06,li07,li35,li34,li33,li32,li36,n227,n228,n229,n230,n231,n232,n233,n234,n235,n236,n237,n238,n239,n240,n241,n242,n243,n244,n245,n246,n247,n248,n249,n250,n251,n252,n253,n254,n255,n256,li38,n258,n259,n260,li47,li39,li40,li41,li42,li43,li44,li45,li46,li24,li25,li26,li27,li28,li29,li30,li31,li13,li37: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    DFF12: DFF port map (li12, CLK, lo12);
    DFF13: DFF port map (li13, CLK, lo13);
    DFF14: DFF port map (li14, CLK, lo14);
    DFF15: DFF port map (li15, CLK, lo15);
    DFF16: DFF port map (li16, CLK, lo16);
    DFF17: DFF port map (li17, CLK, lo17);
    DFF18: DFF port map (li18, CLK, lo18);
    DFF19: DFF port map (li19, CLK, lo19);
    DFF20: DFF port map (li20, CLK, lo20);
    DFF21: DFF port map (li21, CLK, lo21);
    DFF22: DFF port map (li22, CLK, lo22);
    DFF23: DFF port map (li23, CLK, lo23);
    DFF24: DFF port map (li24, CLK, lo24);
    DFF25: DFF port map (li25, CLK, lo25);
    DFF26: DFF port map (li26, CLK, lo26);
    DFF27: DFF port map (li27, CLK, lo27);
    DFF28: DFF port map (li28, CLK, lo28);
    DFF29: DFF port map (li29, CLK, lo29);
    DFF30: DFF port map (li30, CLK, lo30);
    DFF31: DFF port map (li31, CLK, lo31);
    DFF32: DFF port map (li32, CLK, lo32);
    DFF33: DFF port map (li33, CLK, lo33);
    DFF34: DFF port map (li34, CLK, lo34);
    DFF35: DFF port map (li35, CLK, lo35);
    DFF36: DFF port map (li36, CLK, lo36);
    DFF37: DFF port map (li37, CLK, lo37);
    DFF38: DFF port map (li38, CLK, lo38);
    DFF39: DFF port map (li39, CLK, lo39);
    DFF40: DFF port map (li40, CLK, lo40);
    DFF41: DFF port map (li41, CLK, lo41);
    DFF42: DFF port map (li42, CLK, lo42);
    DFF43: DFF port map (li43, CLK, lo43);
    DFF44: DFF port map (li44, CLK, lo44);
    DFF45: DFF port map (li45, CLK, lo45);
    DFF46: DFF port map (li46, CLK, lo46);
    DFF47: DFF port map (li47, CLK, lo47);
    li11 <= '0';
    li10 <= '0';
    li09 <= '0';
    li08 <= '0';
    li12 <= '0';
    n171 <= ( not lo08 and lo09 );
    n172 <= ( not lo08 and not lo09 );
    n173 <= ( lo08 and lo09 );
    n174 <= ( lo08 and not lo09 );
    n175 <= ( n172 and lo10 );
    n176 <= ( n174 and lo10 );
    n177 <= ( n174 and not lo10 );
    n178 <= ( n171 and lo10 );
    n179 <= ( n171 and not lo10 );
    n180 <= ( n173 and lo10 );
    n181 <= ( n173 and not lo10 );
    n182 <= ( n177 and lo11 );
    n183 <= ( n179 and lo11 );
    n184 <= ( n181 and lo11 );
    n185 <= ( n181 and not lo11 );
    n186 <= ( n175 and lo11 );
    n187 <= ( n176 and not lo11 );
    n188 <= ( n178 and not lo11 );
    n189 <= ( n180 and not lo11 );
    n190 <= ( n185 and lo12 );
    n191 <= ( n187 and lo12 );
    n192 <= ( n188 and lo12 );
    n193 <= ( n189 and lo12 );
    n194 <= ( n182 and lo12 );
    n195 <= ( n183 and lo12 );
    n196 <= ( n184 and lo12 );
    n197 <= ( n186 and lo12 );
    n198 <= not (( not lo08 and not lo09 ));
    n199 <= not (( not lo10 and not lo11 ));
    n200 <= not (( not n198 and not n199 ));
    li14 <= ( n200 and not lo12 );
    n202 <= not (( not lo08 and not lo09 ));
    n203 <= not (( not lo11 and not lo12 ));
    n204 <= not (( not lo10 and not n203 ));
    li23 <= ( not n202 and not n204 );
    li15 <= ( not n190 and lo00 )
      or ( n190 and not lo00 );
    li16 <= ( not n191 and lo01 )
      or ( n191 and not lo01 );
    li17 <= ( not n192 and lo02 )
      or ( n192 and not lo02 );
    li18 <= ( not n193 and lo03 )
      or ( n193 and not lo03 );
    li19 <= ( not n194 and lo04 )
      or ( n194 and not lo04 );
    li20 <= ( not n195 and lo05 )
      or ( n195 and not lo05 );
    li21 <= ( not n196 and lo06 )
      or ( n196 and not lo06 );
    li22 <= ( not n197 and lo07 )
      or ( n197 and not lo07 );
    li00 <= '0';
    li01 <= '0';
    li02 <= '0';
    li03 <= '0';
    li04 <= '0';
    li05 <= '0';
    li06 <= '0';
    li07 <= '0';
    li35 <= '0';
    li34 <= '0';
    li33 <= '0';
    li32 <= '0';
    li36 <= '0';
    n227 <= ( not lo32 and lo33 );
    n228 <= ( not lo32 and not lo33 );
    n229 <= ( lo32 and lo33 );
    n230 <= ( lo32 and not lo33 );
    n231 <= ( n228 and lo34 );
    n232 <= ( n230 and lo34 );
    n233 <= ( n230 and not lo34 );
    n234 <= ( n227 and lo34 );
    n235 <= ( n227 and not lo34 );
    n236 <= ( n229 and lo34 );
    n237 <= ( n229 and not lo34 );
    n238 <= ( n233 and lo35 );
    n239 <= ( n235 and lo35 );
    n240 <= ( n237 and lo35 );
    n241 <= ( n237 and not lo35 );
    n242 <= ( n231 and lo35 );
    n243 <= ( n232 and not lo35 );
    n244 <= ( n234 and not lo35 );
    n245 <= ( n236 and not lo35 );
    n246 <= ( n241 and lo36 );
    n247 <= ( n243 and lo36 );
    n248 <= ( n244 and lo36 );
    n249 <= ( n245 and lo36 );
    n250 <= ( n238 and lo36 );
    n251 <= ( n239 and lo36 );
    n252 <= ( n240 and lo36 );
    n253 <= ( n242 and lo36 );
    n254 <= not (( not lo32 and not lo33 ));
    n255 <= not (( not lo34 and not lo35 ));
    n256 <= not (( not n254 and not n255 ));
    li38 <= ( n256 and not lo36 );
    n258 <= not (( not lo32 and not lo33 ));
    n259 <= not (( not lo35 and not lo36 ));
    n260 <= not (( not lo34 and not n259 ));
    li47 <= ( not n258 and not n260 );
    li39 <= ( not n246 and lo24 )
      or ( n246 and not lo24 );
    li40 <= ( not n247 and lo25 )
      or ( n247 and not lo25 );
    li41 <= ( not n248 and lo26 )
      or ( n248 and not lo26 );
    li42 <= ( not n249 and lo27 )
      or ( n249 and not lo27 );
    li43 <= ( not n250 and lo28 )
      or ( n250 and not lo28 );
    li44 <= ( not n251 and lo29 )
      or ( n251 and not lo29 );
    li45 <= ( not n252 and lo30 )
      or ( n252 and not lo30 );
    li46 <= ( not n253 and lo31 )
      or ( n253 and not lo31 );
    li24 <= '0';
    li25 <= '0';
    li26 <= '0';
    li27 <= '0';
    li28 <= '0';
    li29 <= '0';
    li30 <= '0';
    li31 <= '0';
    li13 <= ( lo12 );
    li37 <= ( lo36 );
    po00 <= ( lo22 );
    po01 <= ( lo21 );
    po02 <= ( lo20 );
    po03 <= ( lo19 );
    po04 <= ( lo18 );
    po05 <= ( lo17 );
    po06 <= ( lo16 );
    po07 <= ( lo15 );
    po08 <= ( lo46 );
    po09 <= ( lo45 );
    po10 <= ( lo44 );
    po11 <= ( lo43 );
    po12 <= ( lo42 );
    po13 <= ( lo41 );
    po14 <= ( lo40 );
    po15 <= ( lo39 );
    po16 <= ( lo14 );
    po17 <= ( lo13 );
    po18 <= ( lo23 );
    po19 <= ( lo38 );
    po20 <= ( lo37 );
    po21 <= ( lo47 );
end Cookbook__soft_ecc_ram_8bit_behav;
