--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C2670__part1 is 
  Port (
    pi073,pi114: in std_logic;
    po10: inout std_logic
  );
end LGSynth91__C2670__part1;

architecture LGSynth91__C2670__part1_behav of LGSynth91__C2670__part1 is
begin
    po10 <= ( pi073 and pi114 );
end LGSynth91__C2670__part1_behav;
