--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1: inout std_logic
  );
end top;

architecture top_behav of top is
signal n9: std_logic;
begin
    po0 <= ( pi0 and pi2 )
      or ( pi1 and n9 );
    po1 <= ( pi1 and n9 )
      or ( pi4 and n9 );
    n9 <= ( not pi2 )
      or ( not pi3 );
end top_behav;
