--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part231 is 
  Port (
    pi2132, CLK: in std_logic;
    po2023: inout std_logic
  );
end Other__umass_weather__part231;

architecture Other__umass_weather__part231_behav of Other__umass_weather__part231 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4898,lo4970,lo5042,li4898,li4970,li5042: std_logic;
begin
    DFF0: DFF port map (li4898, CLK, lo4898);
    DFF1: DFF port map (li4970, CLK, lo4970);
    DFF2: DFF port map (li5042, CLK, lo5042);
    li4898 <= ( lo4970 );
    li4970 <= ( lo5042 );
    li5042 <= ( pi2132 );
    po2023 <= ( lo4898 );
end Other__umass_weather__part231_behav;
