--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__jtag_to_c_probe__part1 is 
  Port (
    pi6, CLK: in std_logic;
    po1: inout std_logic
  );
end Cookbook__jtag_to_c_probe__part1;

architecture Cookbook__jtag_to_c_probe__part1_behav of Cookbook__jtag_to_c_probe__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo17,n181,n182,li17: std_logic;
begin
    DFF0: DFF port map (li17, CLK, lo17);
    n181 <= not (( lo17 and not pi6 ));
    n182 <= ( lo17 and not pi6 );
    li17 <= not (( not n182 and not n181 ));
    po1 <= ( lo17 );
end Cookbook__jtag_to_c_probe__part1_behav;
