--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__radar20__part1 is 
  Port (
    , CLK: in std_logic;
    po001: inout std_logic
  );
end QUIP__radar20__part1;

architecture QUIP__radar20__part1_behav of QUIP__radar20__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0002,lo0003,li0002,li0003: std_logic;
begin
    DFF0: DFF port map (li0002, CLK, lo0002);
    DFF1: DFF port map (li0003, CLK, lo0003);
    po001 <= ( li0003 );
    li0002 <= ( not lo0002 );
    li0003 <= ( not lo0002 and lo0003 )
      or ( lo0002 and not lo0003 );
end QUIP__radar20__part1_behav;
