--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part217 is 
  Port (
    pi2118, CLK: in std_logic;
    po2009: inout std_logic
  );
end Other__umass_weather__part217;

architecture Other__umass_weather__part217_behav of Other__umass_weather__part217 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4884,lo4913,lo4985,li4884,li4913,li4985: std_logic;
begin
    DFF0: DFF port map (li4884, CLK, lo4884);
    DFF1: DFF port map (li4913, CLK, lo4913);
    DFF2: DFF port map (li4985, CLK, lo4985);
    li4884 <= ( lo4913 );
    li4913 <= ( lo4985 );
    li4985 <= ( pi2118 );
    po2009 <= ( lo4884 );
end Other__umass_weather__part217_behav;
