--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi14, CLK: in std_logic;
    po04,po10: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo129,lo502,li129,li502: std_logic;
begin
    DFF0: DFF port map (li129, CLK, lo129);
    DFF1: DFF port map (li502, CLK, lo502);
    po04 <= ( lo129 );
    po10 <= ( lo502 );
    li129 <= ( pi14 );
    li502 <= ( pi14 );
end top_behav;
