--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__ex4__part4 is 
  Port (
    pi04,pi11,pi18,pi28,pi35,pi42,pi52,pi59,pi66: in std_logic;
    po04,po11: inout std_logic
  );
end Espresso__ex4__part4;

architecture Espresso__ex4__part4_behav of Espresso__ex4__part4 is
begin
    po04 <= ( not pi28 and pi35 and not pi42 )
      or ( not pi11 and pi35 and not pi59 )
      or ( pi11 and not pi18 and pi35 and pi42 and not pi52 )
      or ( not pi18 and pi28 and pi35 and pi42 and not pi52 )
      or ( pi11 and not pi18 and pi35 and not pi52 and pi59 )
      or ( not pi18 and pi28 and pi35 and not pi52 and pi59 )
      or ( not pi04 and pi11 and pi28 and pi35 and not pi66 )
      or ( not pi04 and pi28 and pi35 and pi42 and not pi66 )
      or ( not pi04 and pi11 and pi35 and pi59 and not pi66 )
      or ( not pi04 and pi35 and pi42 and pi59 and not pi66 );
    po11 <= ( pi28 and not pi35 and pi42 )
      or ( pi11 and not pi35 and pi59 )
      or ( not pi11 and pi18 and not pi35 and not pi42 and pi52 )
      or ( pi18 and not pi28 and not pi35 and not pi42 and pi52 )
      or ( not pi11 and pi18 and not pi35 and pi52 and not pi59 )
      or ( pi18 and not pi28 and not pi35 and pi52 and not pi59 )
      or ( pi04 and not pi11 and not pi28 and not pi35 and pi66 )
      or ( pi04 and not pi28 and not pi35 and not pi42 and pi66 )
      or ( pi04 and not pi11 and not pi35 and not pi59 and pi66 )
      or ( pi04 and not pi35 and not pi42 and not pi59 and pi66 );
end Espresso__ex4__part4_behav;
