--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part137 is 
  Port (
    pi0316, CLK: in std_logic;
    po0253: inout std_logic
  );
end Other__umass_weather__part137;

architecture Other__umass_weather__part137_behav of Other__umass_weather__part137 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0358,li0358: std_logic;
begin
    DFF0: DFF port map (li0358, CLK, lo0358);
    li0358 <= ( pi0316 );
    po0253 <= ( lo0358 );
end Other__umass_weather__part137_behav;
