--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi46,pi48,pi51: in std_logic;
    po104,po106: inout std_logic
  );
end top;

architecture top_behav of top is
signal n2290,n2291,n2292: std_logic;
begin
    n2290 <= ( not pi46 and pi48 );
    n2291 <= ( pi46 and pi51 );
    n2292 <= ( n2290 )
      or ( n2291 );
    po104 <= ( n2292 );
    po106 <= ( n2292 );
end top_behav;
