--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part228 is 
  Port (
    pi2129, CLK: in std_logic;
    po2020: inout std_logic
  );
end Other__umass_weather__part228;

architecture Other__umass_weather__part228_behav of Other__umass_weather__part228 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4895,lo4924,lo4996,li4895,li4924,li4996: std_logic;
begin
    DFF0: DFF port map (li4895, CLK, lo4895);
    DFF1: DFF port map (li4924, CLK, lo4924);
    DFF2: DFF port map (li4996, CLK, lo4996);
    li4895 <= ( lo4924 );
    li4924 <= ( lo4996 );
    li4996 <= ( pi2129 );
    po2020 <= ( lo4895 );
end Other__umass_weather__part228_behav;
