--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C5315__part3 is 
  Port (
    pi062,pi164: in std_logic;
    po015: inout std_logic
  );
end LGSynth91__C5315__part3;

architecture LGSynth91__C5315__part3_behav of LGSynth91__C5315__part3 is
begin
    po015 <= ( pi062 and not pi164 );
end LGSynth91__C5315__part3_behav;
