--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__b9__part1 is 
  Port (
    pi01,pi29,pi31,pi33: in std_logic;
    po16,po17: inout std_logic
  );
end IWLS93__b9__part1;

architecture IWLS93__b9__part1_behav of IWLS93__b9__part1 is
signal n114,n158: std_logic;
begin
    po16 <= ( not n158 );
    po17 <= ( not n114 );
    n114 <= ( not pi01 )
      or ( not pi29 )
      or ( pi31 );
    n158 <= ( not pi01 )
      or ( not pi29 )
      or ( not pi31 )
      or ( pi33 );
end IWLS93__b9__part1_behav;
