--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__cps__part1 is 
  Port (
    : in std_logic;
    po000,po003,po008,po009,po087,po097,po103: inout std_logic
  );
end IWLS93__cps__part1;

architecture IWLS93__cps__part1_behav of IWLS93__cps__part1 is
signal n131: std_logic;
begin
    n131 <= '0';
    po000 <= ( n131 );
    po003 <= ( n131 );
    po008 <= ( n131 );
    po009 <= ( n131 );
    po087 <= ( n131 );
    po097 <= ( n131 );
    po103 <= ( n131 );
end IWLS93__cps__part1_behav;
