--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part235 is 
  Port (
    pi2136, CLK: in std_logic;
    po2027: inout std_logic
  );
end Other__umass_weather__part235;

architecture Other__umass_weather__part235_behav of Other__umass_weather__part235 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4902,lo4974,lo5046,li4902,li4974,li5046: std_logic;
begin
    DFF0: DFF port map (li4902, CLK, lo4902);
    DFF1: DFF port map (li4974, CLK, lo4974);
    DFF2: DFF port map (li5046, CLK, lo5046);
    li4902 <= ( lo4974 );
    li4974 <= ( lo5046 );
    li5046 <= ( pi2136 );
    po2027 <= ( lo4902 );
end Other__umass_weather__part235_behav;
