--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part6 is 
  Port (
    pi23,pi24: in std_logic;
    po09: inout std_logic
  );
end Espresso__misg__part6;

architecture Espresso__misg__part6_behav of Espresso__misg__part6 is
begin
    po09 <= ( not pi23 )
      or ( not pi24 );
end Espresso__misg__part6_behav;
