--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__c880__part2 is 
  Port (
    pi19,pi20,pi21,pi22: in std_logic;
    po14,po09: inout std_logic
  );
end ISCAS__c880__part2;

architecture ISCAS__c880__part2_behav of ISCAS__c880__part2 is
signal n104: std_logic;
begin
    n104 <= not (( not pi19 and not pi20 ));
    po14 <= ( pi21 and n104 );
    po09 <= ( pi22 and n104 );
end ISCAS__c880__part2_behav;
