--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part7 is 
  Port (
    pi25,pi26: in std_logic;
    po11: inout std_logic
  );
end Espresso__misg__part7;

architecture Espresso__misg__part7_behav of Espresso__misg__part7 is
begin
    po11 <= ( not pi25 )
      or ( not pi26 );
end Espresso__misg__part7_behav;
