--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C5315__part4 is 
  Port (
    pi150: in std_logic;
    po000,po005,po006: inout std_logic
  );
end LGSynth91__C5315__part4;

architecture LGSynth91__C5315__part4_behav of LGSynth91__C5315__part4 is
begin
    po000 <= ( not pi150 );
    po005 <= ( not pi150 );
    po006 <= ( not pi150 );
end LGSynth91__C5315__part4_behav;
