--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part149 is 
  Port (
    pi0346, CLK: in std_logic;
    po0299: inout std_logic
  );
end Other__umass_weather__part149;

architecture Other__umass_weather__part149_behav of Other__umass_weather__part149 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0401,li0401: std_logic;
begin
    DFF0: DFF port map (li0401, CLK, lo0401);
    li0401 <= ( pi0346 );
    po0299 <= ( lo0401 );
end Other__umass_weather__part149_behav;
