--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4, CLK: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,li0,li1,li2,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    po0 <= ( not n33 );
    po1 <= ( not n34 );
    po2 <= ( not n35 );
    po3 <= ( not n36 );
    po4 <= ( not n37 );
    po5 <= ( not n38 );
    po6 <= ( not n39 );
    po7 <= ( not n40 );
    li0 <= ( not n41 );
    li1 <= ( not n42 );
    li2 <= ( not n43 );
    n33 <= ( not n45 and not n49 and not n52 and not n54 and not n56 and not n60 and not n61 and not n62 and not n63 and not n64 and not n66 and not n67 and not n68 );
    n34 <= ( not n61 and not n63 and not n64 and not n66 and not n67 and not n68 );
    n35 <= ( not n44 and not n45 and not n46 and not n47 and not n50 and not n52 and not n53 and not n55 and not n58 and not n59 and not n60 and not n62 );
    n36 <= ( not n45 and not n48 and not n52 and not n60 and not n62 );
    n37 <= ( not n44 and not n45 and not n46 and not n52 and not n55 and not n57 and not n58 and not n59 and not n60 and not n62 and not n65 );
    n38 <= ( not n47 and not n49 and not n50 and not n53 and not n54 and not n56 and not n57 and not n65 );
    n39 <= ( not n57 and not n65 );
    n40 <= ( not n50 and not n51 and not n53 );
    n41 <= ( not n44 and not n49 and not n54 and not n56 and not n57 and not n58 and not n59 and not n61 and not n63 and not n64 and not n65 and not n66 and not n67 and not n68 );
    n42 <= ( not n47 and not n50 and not n53 and not n57 and not n61 and not n63 and not n64 and not n65 and not n66 and not n67 and not n68 );
    n43 <= ( not n46 and not n47 and not n49 and not n50 and not n53 and not n54 and not n55 and not n56 and not n57 and not n65 );
    n44 <= ( pi0 and not pi1 and not pi4 and not lo0 and lo1 );
    n45 <= ( pi0 and pi1 and not pi4 and not lo0 and lo1 );
    n46 <= ( pi0 and not pi1 and pi2 and not lo1 and lo2 );
    n47 <= ( not pi0 and pi1 and not pi4 and not lo0 and lo1 );
    n48 <= ( not lo0 and not lo1 and not lo2 );
    n49 <= ( pi2 and pi3 and lo0 and lo1 and lo2 );
    n50 <= ( not pi0 and pi1 and not pi2 and not lo1 and not lo2 );
    n51 <= ( not lo0 and lo1 and lo2 );
    n52 <= ( pi0 and pi1 and pi2 and not lo1 and lo2 );
    n53 <= ( not pi0 and pi1 and pi2 and not lo0 and not lo1 );
    n54 <= ( not pi0 and pi2 and lo0 and not lo1 and lo2 );
    n55 <= ( pi2 and lo0 and not lo1 and not lo2 );
    n56 <= ( pi0 and pi2 and lo0 and lo1 and lo2 );
    n57 <= ( not pi0 and pi2 and not pi3 and lo0 and lo1 );
    n58 <= ( pi0 and not pi1 and not pi2 and not lo2 );
    n59 <= ( pi0 and not pi1 and not lo0 and not lo2 );
    n60 <= ( pi0 and pi1 and not pi2 and not lo2 );
    n61 <= ( pi4 and not lo0 and lo1 and lo2 );
    n62 <= ( pi0 and pi1 and not lo0 and not lo2 );
    n63 <= ( not pi0 and not pi2 and lo1 and not lo2 );
    n64 <= ( not pi0 and not pi1 and not pi2 );
    n65 <= ( pi2 and lo0 and lo1 and not lo2 );
    n66 <= ( not pi0 and not pi1 and not lo0 );
    n67 <= ( not pi2 and lo0 and lo2 );
    n68 <= ( not pi2 and not lo1 and lo2 );
end top_behav;
