--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part6 is 
  Port (
    pi22, CLK: in std_logic;
    po022: inout std_logic
  );
end Cookbook__lc_mult_signed__part6;

architecture Cookbook__lc_mult_signed__part6_behav of Cookbook__lc_mult_signed__part6 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo007,li007: std_logic;
begin
    DFF0: DFF port map (li007, CLK, lo007);
    li007 <= ( pi22 );
    po022 <= ( lo007 );
end Cookbook__lc_mult_signed__part6_behav;
