--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__cm151a is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11: in std_logic;
    po0,po1: inout std_logic
  );
end IWLS93__cm151a;

architecture IWLS93__cm151a_behav of IWLS93__cm151a is
signal n16,n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43: std_logic;
begin
    po0 <= ( not pi11 and not n16 );
    po1 <= ( not po0 );
    n16 <= ( n22 )
      or ( n24 )
      or ( n26 );
    n17 <= ( not pi03 and pi08 );
    n18 <= ( not pi02 and not pi08 );
    n19 <= ( not pi02 and not pi03 );
    n20 <= ( n17 )
      or ( n18 )
      or ( n19 );
    n21 <= ( not pi06 and not pi08 );
    n22 <= ( pi10 and not n41 );
    n23 <= ( not pi07 and pi08 );
    n24 <= ( not n29 and not n41 );
    n25 <= ( not pi09 and not n30 );
    n26 <= ( not pi10 and not n29 );
    n27 <= ( pi09 and not n20 );
    n28 <= ( not n20 and not n30 );
    n29 <= ( n27 )
      or ( n28 )
      or ( n25 );
    n30 <= ( n31 )
      or ( n32 )
      or ( n33 );
    n31 <= ( not pi01 and pi08 );
    n32 <= ( not pi00 and not pi08 );
    n33 <= ( not pi00 and not pi01 );
    n34 <= ( not pi04 and not pi08 );
    n35 <= ( pi09 and not n38 );
    n36 <= ( not pi05 and pi08 );
    n37 <= ( not n38 and not n42 );
    n38 <= ( n23 )
      or ( n21 )
      or ( n39 );
    n39 <= ( not pi06 and not pi07 );
    n40 <= ( not pi09 and not n42 );
    n41 <= ( n35 )
      or ( n37 )
      or ( n40 );
    n42 <= ( n36 )
      or ( n34 )
      or ( n43 );
    n43 <= ( not pi04 and not pi05 );
end IWLS93__cm151a_behav;
