--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12: in std_logic;
    po0,po1,po2,po3,po4,po5,po6: inout std_logic
  );
end top;

architecture top_behav of top is
signal n21,n23,n25,n27,n29: std_logic;
begin
    po6 <= ( not pi12 and not pi10 and pi11 )
      or ( not pi12 and pi10 and not pi11 )
      or ( pi12 and not pi10 and not pi11 )
      or ( pi12 and pi10 and pi11 );
    n21 <= ( pi12 and pi10 )
      or ( pi12 and pi11 )
      or ( pi10 and pi11 );
    po5 <= ( not n21 and not pi04 and pi09 )
      or ( not n21 and pi04 and not pi09 )
      or ( n21 and not pi04 and not pi09 )
      or ( n21 and pi04 and pi09 );
    n23 <= ( n21 and pi04 )
      or ( n21 and pi09 )
      or ( pi04 and pi09 );
    po4 <= ( not n23 and not pi03 and pi08 )
      or ( not n23 and pi03 and not pi08 )
      or ( n23 and not pi03 and not pi08 )
      or ( n23 and pi03 and pi08 );
    n25 <= ( n23 and pi03 )
      or ( n23 and pi08 )
      or ( pi03 and pi08 );
    po3 <= ( not n25 and not pi02 and pi07 )
      or ( not n25 and pi02 and not pi07 )
      or ( n25 and not pi02 and not pi07 )
      or ( n25 and pi02 and pi07 );
    n27 <= ( n25 and pi02 )
      or ( n25 and pi07 )
      or ( pi02 and pi07 );
    po2 <= ( not n27 and not pi01 and pi06 )
      or ( not n27 and pi01 and not pi06 )
      or ( n27 and not pi01 and not pi06 )
      or ( n27 and pi01 and pi06 );
    n29 <= ( n27 and pi01 )
      or ( n27 and pi06 )
      or ( pi01 and pi06 );
    po1 <= ( not n29 and not pi00 and pi05 )
      or ( not n29 and pi00 and not pi05 )
      or ( n29 and not pi00 and not pi05 )
      or ( n29 and pi00 and pi05 );
    po0 <= ( n29 and pi00 )
      or ( n29 and pi05 )
      or ( pi00 and pi05 );
end top_behav;
