--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__rot__part1 is 
  Port (
    pi014,pi102,pi007,pi025,pi069,pi098: in std_logic;
    po33,po35: inout std_logic
  );
end IWLS93__rot__part1;

architecture IWLS93__rot__part1_behav of IWLS93__rot__part1 is
signal n433,n507,n549: std_logic;
begin
    po33 <= ( pi014 and pi102 );
    po35 <= ( n507 )
      or ( n549 )
      or ( n433 );
    n433 <= ( pi007 and pi025 );
    n507 <= ( pi069 and pi098 );
    n549 <= ( not pi014 and pi069 );
end IWLS93__rot__part1_behav;
