--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12: inout std_logic
  );
end top;

architecture top_behav of top is
signal n39,n41,n43,n45,n47,n49,n51,n53,n55,n57,n59: std_logic;
begin
    po12 <= ( not pi24 and not pi11 and pi23 )
      or ( not pi24 and pi11 and not pi23 )
      or ( pi24 and not pi11 and not pi23 )
      or ( pi24 and pi11 and pi23 );
    n39 <= ( pi24 and pi11 )
      or ( pi24 and pi23 )
      or ( pi11 and pi23 );
    po11 <= ( not n39 and not pi10 and pi22 )
      or ( not n39 and pi10 and not pi22 )
      or ( n39 and not pi10 and not pi22 )
      or ( n39 and pi10 and pi22 );
    n41 <= ( n39 and pi10 )
      or ( n39 and pi22 )
      or ( pi10 and pi22 );
    po10 <= ( not n41 and not pi09 and pi21 )
      or ( not n41 and pi09 and not pi21 )
      or ( n41 and not pi09 and not pi21 )
      or ( n41 and pi09 and pi21 );
    n43 <= ( n41 and pi09 )
      or ( n41 and pi21 )
      or ( pi09 and pi21 );
    po09 <= ( not n43 and not pi08 and pi20 )
      or ( not n43 and pi08 and not pi20 )
      or ( n43 and not pi08 and not pi20 )
      or ( n43 and pi08 and pi20 );
    n45 <= ( n43 and pi08 )
      or ( n43 and pi20 )
      or ( pi08 and pi20 );
    po08 <= ( not n45 and not pi07 and pi19 )
      or ( not n45 and pi07 and not pi19 )
      or ( n45 and not pi07 and not pi19 )
      or ( n45 and pi07 and pi19 );
    n47 <= ( n45 and pi07 )
      or ( n45 and pi19 )
      or ( pi07 and pi19 );
    po07 <= ( not n47 and not pi06 and pi18 )
      or ( not n47 and pi06 and not pi18 )
      or ( n47 and not pi06 and not pi18 )
      or ( n47 and pi06 and pi18 );
    n49 <= ( n47 and pi06 )
      or ( n47 and pi18 )
      or ( pi06 and pi18 );
    po06 <= ( not n49 and not pi05 and pi17 )
      or ( not n49 and pi05 and not pi17 )
      or ( n49 and not pi05 and not pi17 )
      or ( n49 and pi05 and pi17 );
    n51 <= ( n49 and pi05 )
      or ( n49 and pi17 )
      or ( pi05 and pi17 );
    po05 <= ( not n51 and not pi04 and pi16 )
      or ( not n51 and pi04 and not pi16 )
      or ( n51 and not pi04 and not pi16 )
      or ( n51 and pi04 and pi16 );
    n53 <= ( n51 and pi04 )
      or ( n51 and pi16 )
      or ( pi04 and pi16 );
    po04 <= ( not n53 and not pi03 and pi15 )
      or ( not n53 and pi03 and not pi15 )
      or ( n53 and not pi03 and not pi15 )
      or ( n53 and pi03 and pi15 );
    n55 <= ( n53 and pi03 )
      or ( n53 and pi15 )
      or ( pi03 and pi15 );
    po03 <= ( not n55 and not pi02 and pi14 )
      or ( not n55 and pi02 and not pi14 )
      or ( n55 and not pi02 and not pi14 )
      or ( n55 and pi02 and pi14 );
    n57 <= ( n55 and pi02 )
      or ( n55 and pi14 )
      or ( pi02 and pi14 );
    po02 <= ( not n57 and not pi01 and pi13 )
      or ( not n57 and pi01 and not pi13 )
      or ( n57 and not pi01 and not pi13 )
      or ( n57 and pi01 and pi13 );
    n59 <= ( n57 and pi01 )
      or ( n57 and pi13 )
      or ( pi01 and pi13 );
    po01 <= ( not n59 and not pi00 and pi12 )
      or ( not n59 and pi00 and not pi12 )
      or ( n59 and not pi00 and not pi12 )
      or ( n59 and pi00 and pi12 );
    po00 <= ( n59 and pi00 )
      or ( n59 and pi12 )
      or ( pi00 and pi12 );
end top_behav;
