--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part5 is 
  Port (
    pi05,pi21,pi37: in std_logic;
    po05,po21: inout std_logic
  );
end Cookbook__compress_32__part5;

architecture Cookbook__compress_32__part5_behav of Cookbook__compress_32__part5 is
signal n90,n122,n138,n154,n170: std_logic;
begin
    n90 <= ( not pi05 and pi21 )
      or ( pi05 and not pi21 );
    po05 <= ( not n90 and pi37 )
      or ( n90 and not pi37 );
    n122 <= ( pi05 and pi37 );
    n138 <= ( pi05 and pi21 );
    n154 <= not (( not n138 and not n122 ));
    n170 <= ( pi21 and pi37 );
    po21 <= not (( not n154 and not n170 ));
end Cookbook__compress_32__part5_behav;
