--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C7552__part1 is 
  Port (
    pi001,pi020,pi164,pi067,pi066: in std_logic;
    po01,po06,po08,po09,po11: inout std_logic
  );
end LGSynth91__C7552__part1;

architecture LGSynth91__C7552__part1_behav of LGSynth91__C7552__part1 is
signal n338,n347: std_logic;
begin
    po01 <= ( pi001 )
      or ( pi020 );
    po06 <= ( pi001 )
      or ( not pi164 );
    po08 <= ( pi001 )
      or ( not pi164 );
    po09 <= ( pi001 )
      or ( not n338 );
    po11 <= ( not n347 );
    n338 <= ( pi067 and pi066 );
    n347 <= ( not pi001 and n338 );
end LGSynth91__C7552__part1_behav;
