--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__c17 is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1: inout std_logic
  );
end ISCAS__c17;

architecture ISCAS__c17_behav of ISCAS__c17 is
signal n7,n8,n9,n10: std_logic;
begin
    n7 <= not (( pi2 and pi3 ));
    n8 <= not (( pi0 and pi2 ));
    n9 <= not (( n7 and pi4 ));
    n10 <= not (( pi1 and n7 ));
    po1 <= not (( n10 and n9 ));
    po0 <= not (( n8 and n10 ));
end ISCAS__c17_behav;
