--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__al2__part1 is 
  Port (
    pi12,pi13,pi14,pi15: in std_logic;
    po15,po16,po17,po18,po19,po20,po21,po22,po23,po24,po25,po26,po27,po28,po29,po30: inout std_logic
  );
end Espresso__al2__part1;

architecture Espresso__al2__part1_behav of Espresso__al2__part1 is
begin
    po15 <= ( not pi12 and not pi13 and not pi14 and not pi15 );
    po16 <= ( not pi12 and not pi13 and not pi14 and pi15 );
    po17 <= ( not pi12 and not pi13 and pi14 and not pi15 );
    po18 <= ( not pi12 and not pi13 and pi14 and pi15 );
    po19 <= ( not pi12 and pi13 and not pi14 and not pi15 );
    po20 <= ( not pi12 and pi13 and not pi14 and pi15 );
    po21 <= ( not pi12 and pi13 and pi14 and not pi15 );
    po22 <= ( not pi12 and pi13 and pi14 and pi15 );
    po23 <= ( pi12 and not pi13 and not pi14 and not pi15 );
    po24 <= ( pi12 and not pi13 and not pi14 and pi15 );
    po25 <= ( pi12 and not pi13 and pi14 and not pi15 );
    po26 <= ( pi12 and not pi13 and pi14 and pi15 );
    po27 <= ( pi12 and pi13 and not pi14 and not pi15 );
    po28 <= ( pi12 and pi13 and not pi14 and pi15 );
    po29 <= ( pi12 and pi13 and pi14 and not pi15 );
    po30 <= ( pi12 and pi13 and pi14 and pi15 );
end Espresso__al2__part1_behav;
