--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__74181 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7: inout std_logic
  );
end Other__74181;

architecture Other__74181_behav of Other__74181 is
signal n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n48,n49,n50,n51,n53,n55,n56,n57,n59,n60,n61,n62,n63,n65,n66,n67,n68,n69,n70,n72,n73,n74,n75,n76,n77,n78: std_logic;
begin
    n22 <= ( not pi00 and not n23 and not n24 );
    n23 <= ( pi01 and pi09 );
    n24 <= ( not pi01 and pi10 );
    n25 <= ( not n26 and not n27 );
    n26 <= ( not pi01 and pi11 and pi00 );
    n27 <= ( pi01 and pi12 and pi00 );
    n28 <= ( not pi02 and not n29 and not n30 );
    n29 <= ( pi03 and pi09 );
    n30 <= ( not pi03 and pi10 );
    n31 <= ( not n32 and not n33 );
    n32 <= ( not pi03 and pi11 and pi02 );
    n33 <= ( pi03 and pi12 and pi02 );
    n34 <= ( not pi04 and not n35 and not n36 );
    n35 <= ( pi05 and pi09 );
    n36 <= ( not pi05 and pi10 );
    n37 <= ( not n38 and not n39 );
    n38 <= ( not pi05 and pi11 and pi04 );
    n39 <= ( pi05 and pi12 and pi04 );
    n40 <= ( not pi04 and not n41 and not n42 );
    n41 <= ( pi07 and pi09 );
    n42 <= ( not pi07 and pi10 );
    n43 <= ( not n44 and not n45 );
    n44 <= ( not pi07 and pi11 and pi06 );
    n45 <= ( pi07 and pi12 and pi06 );
    po5 <= not (( n25 and n31 and n37 and n43 ));
    po6 <= ( n48 );
    n48 <= ( not n40 and not n49 and not n50 and not n51 );
    n49 <= ( n34 and n43 );
    n50 <= ( n28 and n37 and n43 );
    n51 <= ( n22 and n31 and n37 and n43 );
    po4 <= not (( not n53 and n48 ));
    n53 <= ( pi08 and n25 and n31 and n37 and n43 );
    po0 <= ( n55 );
    n55 <= ( not n57 and n56 )
      or ( n57 and not n56 );
    n56 <= ( not n22 and n25 )
      or ( n22 and not n25 );
    n57 <= not (( not pi13 and pi08 ));
    po1 <= ( n59 );
    n59 <= ( not n61 and n60 )
      or ( n61 and not n60 );
    n60 <= ( not n28 and n31 )
      or ( n28 and not n31 );
    n61 <= ( not n62 and not n63 );
    n62 <= ( not pi13 and n22 );
    n63 <= ( not pi13 and n25 and pi08 );
    po2 <= ( n65 );
    n65 <= ( not n67 and n66 )
      or ( n67 and not n66 );
    n66 <= ( not n34 and n37 )
      or ( n34 and not n37 );
    n67 <= ( not n68 and not n69 and not n70 );
    n68 <= ( not pi13 and n28 );
    n69 <= ( not pi13 and n22 and n31 );
    n70 <= ( not pi13 and n31 and n25 and pi08 );
    po3 <= ( n72 );
    n72 <= ( not n74 and n73 )
      or ( n74 and not n73 );
    n73 <= ( not n40 and n43 )
      or ( n40 and not n43 );
    n74 <= ( not n75 and not n76 and not n77 and not n78 );
    n75 <= ( not pi13 and n34 );
    n76 <= ( not pi13 and n28 and n37 );
    n77 <= ( not pi13 and n22 and n31 and n37 );
    n78 <= ( not pi13 and n25 and n31 and n37 and pi08 );
    po7 <= ( n55 and n59 and n65 and n72 );
end Other__74181_behav;
