--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_2__part0 is 
  Port (
    pi8,pi0,pi6,pi4,pi2: in std_logic;
    po6,po4,po2,po0: inout std_logic
  );
end Cookbook__fec_rot_2__part0;

architecture Cookbook__fec_rot_2__part0_behav of Cookbook__fec_rot_2__part0 is
begin
    po6 <= ( not pi8 and pi0 )
      or ( pi8 and not pi0 );
    po4 <= ( not pi6 and pi0 )
      or ( pi6 and not pi0 );
    po2 <= ( not pi4 and pi0 )
      or ( pi4 and not pi0 );
    po0 <= ( not pi2 and pi0 )
      or ( pi2 and not pi0 );
end Cookbook__fec_rot_2__part0_behav;
