--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_mux is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7, CLK: in std_logic;
    po0: inout std_logic
  );
end Cookbook__clock_mux;

architecture Cookbook__clock_mux_behav of Cookbook__clock_mux is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,n45,n46,n47,n48,n49,n50,n51,n52,li11,li02,li05,li08,n57,n58,n60,n61,n62,n63,li00,li01,li03,li04,li06,li07,li09,li10: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    n45 <= not (( not lo07 and not lo10 ));
    n46 <= not (( not lo04 and not n45 ));
    n47 <= not (( not lo07 and not lo10 ));
    n48 <= not (( not lo01 and not n47 ));
    n49 <= not (( not lo01 and not lo04 ));
    n50 <= not (( not n49 and not lo10 ));
    n51 <= not (( not lo01 and not lo04 ));
    n52 <= not (( not n51 and not lo07 ));
    li11 <= ( pi7 and not n46 );
    li02 <= ( pi6 and not n48 );
    li05 <= ( pi5 and not n50 );
    li08 <= ( pi4 and not n52 );
    n57 <= not (( not n60 and not n61 ));
    n58 <= not (( not n62 and not n63 ));
    po0 <= not (( not n57 and not n58 ));
    n60 <= ( pi3 and lo01 );
    n61 <= ( pi2 and lo04 );
    n62 <= ( pi1 and lo07 );
    n63 <= ( pi0 and lo10 );
    li00 <= ( lo11 );
    li01 <= ( lo00 );
    li03 <= ( lo02 );
    li04 <= ( lo03 );
    li06 <= ( lo05 );
    li07 <= ( lo06 );
    li09 <= ( lo08 );
    li10 <= ( lo09 );
end Cookbook__clock_mux_behav;
