--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b02 is 
  Port (
    pi0,lo0,lo1,lo2,lo3: in std_logic;
    po0,n5,n10,n15,n20_1: inout std_logic
  );
end ITC99__b02;

architecture ITC99__b02_behav of ITC99__b02 is
signal n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31: std_logic;
begin
    n5 <= ( not lo3 and not lo2 and lo1 );
    n20_1 <= not (( n27 and n26 ));
    n10 <= not (( n21 and n20 ));
    n15 <= not (( n31 and n30 ));
    n18 <= not (( n29 and n28 and not lo3 ));
    n19 <= not (( not lo1 and not pi0 ));
    n20 <= not (( lo3 and n19 ));
    n21 <= not (( lo2 and n18 ));
    n22 <= not (( not pi0 and not lo2 ));
    n23 <= not (( not lo1 and n22 ));
    n24 <= not (( pi0 and not lo1 ));
    n25 <= not (( lo3 and n24 ));
    n26 <= not (( not pi0 and not lo3 and not lo1 ));
    n27 <= not (( n25 and not lo2 ));
    n28 <= not (( pi0 and not lo1 ));
    n29 <= not (( lo1 and not pi0 ));
    n30 <= not (( lo3 and n23 ));
    n31 <= not (( lo2 and not lo1 and not lo3 ));
    po0 <= ( lo0 );
end ITC99__b02_behav;
