--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part212 is 
  Port (
    lo0195,lo0196: in std_logic;
    n34226,n34711: inout std_logic
  );
end Other__radar__part212;

architecture Other__radar__part212_behav of Other__radar__part212 is
begin
    n34226 <= ( lo0195 and not lo0196 );
    n34711 <= ( lo0195 );
end Other__radar__part212_behav;
