--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1275 is 
  Port (
    lo4644: in std_logic;
    n18709: inout std_logic
  );
end Other__sudoku_check__part1275;

architecture Other__sudoku_check__part1275_behav of Other__sudoku_check__part1275 is
begin
    n18709 <= ( lo4644 );
end Other__sudoku_check__part1275_behav;
