--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part34 is 
  Port (
    lo039: in std_logic;
    n897: inout std_logic
  );
end Cookbook__gearbox_67_40__part34;

architecture Cookbook__gearbox_67_40__part34_behav of Cookbook__gearbox_67_40__part34 is
begin
    n897 <= ( lo039 );
end Cookbook__gearbox_67_40__part34_behav;
