--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1075 is 
  Port (
    lo11009: in std_logic;
    n73521_1: inout std_logic
  );
end Other__ray__part1075;

architecture Other__ray__part1075_behav of Other__ray__part1075 is
begin
    n73521_1 <= ( lo11009 );
end Other__ray__part1075_behav;
