--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part891 is 
  Port (
    lo08197: in std_logic;
    n54141_1: inout std_logic
  );
end Other__ray__part891;

architecture Other__ray__part891_behav of Other__ray__part891 is
begin
    n54141_1 <= ( lo08197 );
end Other__ray__part891_behav;
