--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part39 is 
  Port (
    lo0072: in std_logic;
    po052: inout std_logic
  );
end Other__fp_operators__part39;

architecture Other__fp_operators__part39_behav of Other__fp_operators__part39 is
begin
    po052 <= ( lo0072 );
end Other__fp_operators__part39_behav;
