--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2038 is 
  Port (
    lo2107: in std_logic;
    n10834: inout std_logic
  );
end Cookbook__fec_check__part2038;

architecture Cookbook__fec_check__part2038_behav of Cookbook__fec_check__part2038 is
begin
    n10834 <= ( lo2107 );
end Cookbook__fec_check__part2038_behav;
