--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part803 is 
  Port (
    lo6371: in std_logic;
    po531: inout std_logic
  );
end Other__carpat__part803;

architecture Other__carpat__part803_behav of Other__carpat__part803 is
begin
    po531 <= ( lo6371 );
end Other__carpat__part803_behav;
