--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1033 is 
  Port (
    lo1102: in std_logic;
    n5809: inout std_logic
  );
end Cookbook__fec_check__part1033;

architecture Cookbook__fec_check__part1033_behav of Cookbook__fec_check__part1033 is
begin
    n5809 <= ( lo1102 );
end Cookbook__fec_check__part1033_behav;
