--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1075 is 
  Port (
    lo4444: in std_logic;
    n17709: inout std_logic
  );
end Other__sudoku_check__part1075;

architecture Other__sudoku_check__part1075_behav of Other__sudoku_check__part1075 is
begin
    n17709 <= ( lo4444 );
end Other__sudoku_check__part1075_behav;
