--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1460 is 
  Port (
    lo8091: in std_logic;
    n44504_1: inout std_logic
  );
end Other__carpat__part1460;

architecture Other__carpat__part1460_behav of Other__carpat__part1460 is
begin
    n44504_1 <= ( lo8091 );
end Other__carpat__part1460_behav;
