--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part10 is 
  Port (
    pi14: in std_logic;
    n404: inout std_logic
  );
end LGSynth91__s38417__part10;

architecture LGSynth91__s38417__part10_behav of LGSynth91__s38417__part10 is
begin
    n404 <= ( pi14 );
end LGSynth91__s38417__part10_behav;
