--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part37 is 
  Port (
    lo34: in std_logic;
    po36: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part37;

architecture Cookbook__x4_encoder_8b10b__part37_behav of Cookbook__x4_encoder_8b10b__part37 is
begin
    po36 <= ( lo34 );
end Cookbook__x4_encoder_8b10b__part37_behav;
