--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part19 is 
  Port (
    pi25: in std_logic;
    n923991: inout std_logic
  );
end IWLS2005__leon3__part19;

architecture IWLS2005__leon3__part19_behav of IWLS2005__leon3__part19 is
begin
    n923991 <= ( pi25 );
end IWLS2005__leon3__part19_behav;
