--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part34 is 
  Port (
    pi34: in std_logic;
    n1559: inout std_logic
  );
end Cookbook__gearbox_40_67__part34;

architecture Cookbook__gearbox_40_67__part34_behav of Cookbook__gearbox_40_67__part34 is
begin
    n1559 <= ( pi34 );
end Cookbook__gearbox_40_67__part34_behav;
