--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part352 is 
  Port (
    lo0421: in std_logic;
    n2404: inout std_logic
  );
end Cookbook__fec_check__part352;

architecture Cookbook__fec_check__part352_behav of Cookbook__fec_check__part352 is
begin
    n2404 <= ( lo0421 );
end Cookbook__fec_check__part352_behav;
