--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part40 is 
  Port (
    lo0108: in std_logic;
    po116: inout std_logic
  );
end Other__mem__part40;

architecture Other__mem__part40_behav of Other__mem__part40 is
begin
    po116 <= ( lo0108 );
end Other__mem__part40_behav;
