--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part169 is 
  Port (
    lo1362: in std_logic;
    n7084_1: inout std_logic
  );
end ISCAS__s38417__part169;

architecture ISCAS__s38417__part169_behav of ISCAS__s38417__part169 is
begin
    n7084_1 <= ( lo1362 );
end ISCAS__s38417__part169_behav;
