--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part92 is 
  Port (
    lo2639: in std_logic;
    n5839: inout std_logic
  );
end Other__sudoku_check__part92;

architecture Other__sudoku_check__part92_behav of Other__sudoku_check__part92 is
begin
    n5839 <= ( lo2639 );
end Other__sudoku_check__part92_behav;
