--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part72 is 
  Port (
    lo041: in std_logic;
    n689: inout std_logic
  );
end Cookbook__gearbox_40_67__part72;

architecture Cookbook__gearbox_40_67__part72_behav of Cookbook__gearbox_40_67__part72 is
begin
    n689 <= ( lo041 );
end Cookbook__gearbox_40_67__part72_behav;
