--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2217 is 
  Port (
    lo2286: in std_logic;
    n11729: inout std_logic
  );
end Cookbook__fec_check__part2217;

architecture Cookbook__fec_check__part2217_behav of Cookbook__fec_check__part2217 is
begin
    n11729 <= ( lo2286 );
end Cookbook__fec_check__part2217_behav;
