--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part19 is 
  Port (
    lo0006: in std_logic;
    po0006: inout std_logic
  );
end Other__ucsb_152_tap_fir__part19;

architecture Other__ucsb_152_tap_fir__part19_behav of Other__ucsb_152_tap_fir__part19 is
begin
    po0006 <= ( lo0006 );
end Other__ucsb_152_tap_fir__part19_behav;
