--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part302 is 
  Port (
    lo03692: in std_logic;
    po6243,po6310,po6549,po6616: inout std_logic
  );
end Other__ray__part302;

architecture Other__ray__part302_behav of Other__ray__part302 is
begin
    po6243 <= ( lo03692 );
    po6310 <= ( lo03692 );
    po6549 <= ( lo03692 );
    po6616 <= ( lo03692 );
end Other__ray__part302_behav;
