--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1235 is 
  Port (
    lo7674: in std_logic;
    n42359_1: inout std_logic
  );
end Other__carpat__part1235;

architecture Other__carpat__part1235_behav of Other__carpat__part1235 is
begin
    n42359_1 <= ( lo7674 );
end Other__carpat__part1235_behav;
