--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1781 is 
  Port (
    lo1850: in std_logic;
    n9549: inout std_logic
  );
end Cookbook__fec_check__part1781;

architecture Cookbook__fec_check__part1781_behav of Cookbook__fec_check__part1781 is
begin
    n9549 <= ( lo1850 );
end Cookbook__fec_check__part1781_behav;
