--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1267 is 
  Port (
    lo4636: in std_logic;
    n18669: inout std_logic
  );
end Other__sudoku_check__part1267;

architecture Other__sudoku_check__part1267_behav of Other__sudoku_check__part1267 is
begin
    n18669 <= ( lo4636 );
end Other__sudoku_check__part1267_behav;
