--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part102 is 
  Port (
    lo0171: in std_logic;
    n1154: inout std_logic
  );
end Cookbook__fec_check__part102;

architecture Cookbook__fec_check__part102_behav of Cookbook__fec_check__part102 is
begin
    n1154 <= ( lo0171 );
end Cookbook__fec_check__part102_behav;
