--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1291 is 
  Port (
    lo2966: in std_logic;
    n19331: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1291;

architecture Other__ucsb_152_tap_fir__part1291_behav of Other__ucsb_152_tap_fir__part1291 is
begin
    n19331 <= ( lo2966 );
end Other__ucsb_152_tap_fir__part1291_behav;
