--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s5378__part10 is 
  Port (
    lo166: in std_logic;
    n998: inout std_logic
  );
end ISCAS__s5378__part10;

architecture ISCAS__s5378__part10_behav of ISCAS__s5378__part10 is
begin
    n998 <= ( not lo166 );
end ISCAS__s5378__part10_behav;
