--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part252 is 
  Port (
    lo0915: in std_logic;
    n5834: inout std_logic
  );
end Cookbook__ucrypt__part252;

architecture Cookbook__ucrypt__part252_behav of Cookbook__ucrypt__part252 is
begin
    n5834 <= ( lo0915 );
end Cookbook__ucrypt__part252_behav;
