--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s400__part3 is 
  Port (
    lo04: in std_logic;
    po2: inout std_logic
  );
end LGSynth91__s400__part3;

architecture LGSynth91__s400__part3_behav of LGSynth91__s400__part3 is
begin
    po2 <= ( not lo04 );
end LGSynth91__s400__part3_behav;
