--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part124 is 
  Port (
    lo0241: in std_logic;
    n5671: inout std_logic
  );
end Other__ucsb_152_tap_fir__part124;

architecture Other__ucsb_152_tap_fir__part124_behav of Other__ucsb_152_tap_fir__part124 is
begin
    n5671 <= ( lo0241 );
end Other__ucsb_152_tap_fir__part124_behav;
