--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1371 is 
  Port (
    lo4740: in std_logic;
    n19189: inout std_logic
  );
end Other__sudoku_check__part1371;

architecture Other__sudoku_check__part1371_behav of Other__sudoku_check__part1371 is
begin
    n19189 <= ( lo4740 );
end Other__sudoku_check__part1371_behav;
