--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part36 is 
  Port (
    lo0162: in std_logic;
    n1549: inout std_logic
  );
end IWLS93__s38417__part36;

architecture IWLS93__s38417__part36_behav of IWLS93__s38417__part36 is
begin
    n1549 <= ( lo0162 );
end IWLS93__s38417__part36_behav;
