--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1274 is 
  Port (
    lo7713: in std_logic;
    n42554_1: inout std_logic
  );
end Other__carpat__part1274;

architecture Other__carpat__part1274_behav of Other__carpat__part1274 is
begin
    n42554_1 <= ( lo7713 );
end Other__carpat__part1274_behav;
