--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1997 is 
  Port (
    lo7032: in std_logic;
    n35655_1: inout std_logic
  );
end IWLS2005__des_perf__part1997;

architecture IWLS2005__des_perf__part1997_behav of IWLS2005__des_perf__part1997 is
begin
    n35655_1 <= ( lo7032 );
end IWLS2005__des_perf__part1997_behav;
