--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part9 is 
  Port (
    lo74: in std_logic;
    po11: inout std_logic
  );
end Cookbook__gearbox_67_20__part9;

architecture Cookbook__gearbox_67_20__part9_behav of Cookbook__gearbox_67_20__part9 is
begin
    po11 <= ( lo74 );
end Cookbook__gearbox_67_20__part9_behav;
