--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part29 is 
  Port (
    pi29: in std_logic;
    n746687: inout std_logic
  );
end IWLS2005__leon2__part29;

architecture IWLS2005__leon2__part29_behav of IWLS2005__leon2__part29 is
begin
    n746687 <= ( pi29 );
end IWLS2005__leon2__part29_behav;
