--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part55 is 
  Port (
    lo0096: in std_logic;
    po076: inout std_logic
  );
end Other__fp_operators__part55;

architecture Other__fp_operators__part55_behav of Other__fp_operators__part55 is
begin
    po076 <= ( lo0096 );
end Other__fp_operators__part55_behav;
