--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part11 is 
  Port (
    lo10: in std_logic;
    po10: inout std_logic
  );
end Other__idxlat01n_m12__part11;

architecture Other__idxlat01n_m12__part11_behav of Other__idxlat01n_m12__part11 is
begin
    po10 <= ( lo10 );
end Other__idxlat01n_m12__part11_behav;
