--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part378 is 
  Port (
    lo05798: in std_logic;
    n36506: inout std_logic
  );
end Other__ray__part378;

architecture Other__ray__part378_behav of Other__ray__part378 is
begin
    n36506 <= ( lo05798 );
end Other__ray__part378_behav;
