--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2218 is 
  Port (
    lo2287: in std_logic;
    n11734: inout std_logic
  );
end Cookbook__fec_check__part2218;

architecture Cookbook__fec_check__part2218_behav of Cookbook__fec_check__part2218 is
begin
    n11734 <= ( lo2287 );
end Cookbook__fec_check__part2218_behav;
