--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1801 is 
  Port (
    lo4100: in std_logic;
    n24921: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1801;

architecture Other__ucsb_152_tap_fir__part1801_behav of Other__ucsb_152_tap_fir__part1801 is
begin
    n24921 <= ( lo4100 );
end Other__ucsb_152_tap_fir__part1801_behav;
