--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part428 is 
  Port (
    lo3077: in std_logic;
    n9199: inout std_logic
  );
end Other__sudoku_check__part428;

architecture Other__sudoku_check__part428_behav of Other__sudoku_check__part428 is
begin
    n9199 <= ( lo3077 );
end Other__sudoku_check__part428_behav;
