--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part34 is 
  Port (
    pi034: in std_logic;
    n9819_1: inout std_logic
  );
end Other__desperf__part34;

architecture Other__desperf__part34_behav of Other__desperf__part34 is
begin
    n9819_1 <= ( pi034 );
end Other__desperf__part34_behav;
