--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2051 is 
  Port (
    lo4582: in std_logic;
    n27491: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2051;

architecture Other__ucsb_152_tap_fir__part2051_behav of Other__ucsb_152_tap_fir__part2051 is
begin
    n27491 <= ( lo4582 );
end Other__ucsb_152_tap_fir__part2051_behav;
