--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1634 is 
  Port (
    lo3710: in std_logic;
    n23131: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1634;

architecture Other__ucsb_152_tap_fir__part1634_behav of Other__ucsb_152_tap_fir__part1634 is
begin
    n23131 <= ( lo3710 );
end Other__ucsb_152_tap_fir__part1634_behav;
