--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part279 is 
  Port (
    lo0942: in std_logic;
    n5969: inout std_logic
  );
end Cookbook__ucrypt__part279;

architecture Cookbook__ucrypt__part279_behav of Cookbook__ucrypt__part279 is
begin
    n5969 <= ( lo0942 );
end Cookbook__ucrypt__part279_behav;
