--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1592 is 
  Port (
    lo1661: in std_logic;
    n8604: inout std_logic
  );
end Cookbook__fec_check__part1592;

architecture Cookbook__fec_check__part1592_behav of Cookbook__fec_check__part1592 is
begin
    n8604 <= ( lo1661 );
end Cookbook__fec_check__part1592_behav;
