--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part186 is 
  Port (
    lo0255: in std_logic;
    n1574: inout std_logic
  );
end Cookbook__fec_check__part186;

architecture Cookbook__fec_check__part186_behav of Cookbook__fec_check__part186 is
begin
    n1574 <= ( lo0255 );
end Cookbook__fec_check__part186_behav;
