--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part828 is 
  Port (
    lo0897: in std_logic;
    n4784: inout std_logic
  );
end Cookbook__fec_check__part828;

architecture Cookbook__fec_check__part828_behav of Cookbook__fec_check__part828 is
begin
    n4784 <= ( lo0897 );
end Cookbook__fec_check__part828_behav;
