--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part17 is 
  Port (
    lo016: in std_logic;
    n390: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part17;

architecture Cookbook__approx_fp_invsqrt__part17_behav of Cookbook__approx_fp_invsqrt__part17 is
begin
    n390 <= ( lo016 );
end Cookbook__approx_fp_invsqrt__part17_behav;
