--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part750 is 
  Port (
    lo06430: in std_logic;
    n48246: inout std_logic
  );
end Other__ray__part750;

architecture Other__ray__part750_behav of Other__ray__part750 is
begin
    n48246 <= ( lo06430 );
end Other__ray__part750_behav;
