--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2295 is 
  Port (
    lo5071: in std_logic;
    n29931: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2295;

architecture Other__ucsb_152_tap_fir__part2295_behav of Other__ucsb_152_tap_fir__part2295 is
begin
    n29931 <= ( lo5071 );
end Other__ucsb_152_tap_fir__part2295_behav;
