--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1450 is 
  Port (
    lo1519: in std_logic;
    n7894: inout std_logic
  );
end Cookbook__fec_check__part1450;

architecture Cookbook__fec_check__part1450_behav of Cookbook__fec_check__part1450 is
begin
    n7894 <= ( lo1519 );
end Cookbook__fec_check__part1450_behav;
