--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part72 is 
  Port (
    lo0593: in std_logic;
    n3809: inout std_logic
  );
end LGSynth91__s38417__part72;

architecture LGSynth91__s38417__part72_behav of LGSynth91__s38417__part72 is
begin
    n3809 <= ( not lo0593 );
end LGSynth91__s38417__part72_behav;
