--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1235 is 
  Port (
    lo1304: in std_logic;
    n6819: inout std_logic
  );
end Cookbook__fec_check__part1235;

architecture Cookbook__fec_check__part1235_behav of Cookbook__fec_check__part1235 is
begin
    n6819 <= ( lo1304 );
end Cookbook__fec_check__part1235_behav;
