--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part505 is 
  Port (
    lo0574: in std_logic;
    n3169: inout std_logic
  );
end Cookbook__fec_check__part505;

architecture Cookbook__fec_check__part505_behav of Cookbook__fec_check__part505 is
begin
    n3169 <= ( lo0574 );
end Cookbook__fec_check__part505_behav;
