--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part372 is 
  Port (
    lo2139: in std_logic;
    n11225: inout std_logic
  );
end IWLS2005__des_perf__part372;

architecture IWLS2005__des_perf__part372_behav of IWLS2005__des_perf__part372 is
begin
    n11225 <= ( lo2139 );
end IWLS2005__des_perf__part372_behav;
