--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1496 is 
  Port (
    lo3410: in std_logic;
    n21556: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1496;

architecture Other__ucsb_152_tap_fir__part1496_behav of Other__ucsb_152_tap_fir__part1496 is
begin
    n21556 <= ( lo3410 );
end Other__ucsb_152_tap_fir__part1496_behav;
