--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part573 is 
  Port (
    lo06054: in std_logic;
    po1575,po1670: inout std_logic
  );
end Other__ray__part573;

architecture Other__ray__part573_behav of Other__ray__part573 is
begin
    po1575 <= ( lo06054 );
    po1670 <= ( lo06054 );
end Other__ray__part573_behav;
