--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3121 is 
  Port (
    lo8434: in std_logic;
    n42550: inout std_logic
  );
end IWLS2005__des_perf__part3121;

architecture IWLS2005__des_perf__part3121_behav of IWLS2005__des_perf__part3121 is
begin
    n42550 <= ( lo8434 );
end IWLS2005__des_perf__part3121_behav;
