--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part545 is 
  Port (
    lo0614: in std_logic;
    n3369: inout std_logic
  );
end Cookbook__fec_check__part545;

architecture Cookbook__fec_check__part545_behav of Cookbook__fec_check__part545 is
begin
    n3369 <= ( lo0614 );
end Cookbook__fec_check__part545_behav;
