--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part16 is 
  Port (
    lo463: in std_logic;
    po08: inout std_logic
  );
end Cookbook__lane_tx__part16;

architecture Cookbook__lane_tx__part16_behav of Cookbook__lane_tx__part16 is
begin
    po08 <= ( lo463 );
end Cookbook__lane_tx__part16_behav;
