--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1003 is 
  Port (
    lo2359: in std_logic;
    n16336: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1003;

architecture Other__ucsb_152_tap_fir__part1003_behav of Other__ucsb_152_tap_fir__part1003 is
begin
    n16336 <= ( lo2359 );
end Other__ucsb_152_tap_fir__part1003_behav;
