--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part52 is 
  Port (
    lo128: in std_logic;
    po50: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part52;

architecture Cookbook__soft_ecc_ram_32bit__part52_behav of Cookbook__soft_ecc_ram_32bit__part52 is
begin
    po50 <= ( lo128 );
end Cookbook__soft_ecc_ram_32bit__part52_behav;
