--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1049 is 
  Port (
    lo1118: in std_logic;
    n5889: inout std_logic
  );
end Cookbook__fec_check__part1049;

architecture Cookbook__fec_check__part1049_behav of Cookbook__fec_check__part1049 is
begin
    n5889 <= ( lo1118 );
end Cookbook__fec_check__part1049_behav;
