--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part661 is 
  Port (
    lo06158: in std_logic;
    po1739,po1775: inout std_logic
  );
end Other__ray__part661;

architecture Other__ray__part661_behav of Other__ray__part661 is
begin
    po1739 <= ( lo06158 );
    po1775 <= ( lo06158 );
end Other__ray__part661_behav;
