--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part378 is 
  Port (
    lo2183: in std_logic;
    n11415: inout std_logic
  );
end IWLS2005__des_perf__part378;

architecture IWLS2005__des_perf__part378_behav of IWLS2005__des_perf__part378 is
begin
    n11415 <= ( lo2183 );
end IWLS2005__des_perf__part378_behav;
