--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part8 is 
  Port (
    pi008: in std_logic;
    n2267_1: inout std_logic
  );
end Other__fpu__part8;

architecture Other__fpu__part8_behav of Other__fpu__part8 is
begin
    n2267_1 <= ( pi008 );
end Other__fpu__part8_behav;
