--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part797 is 
  Port (
    lo6246: in std_logic;
    n28044: inout std_logic
  );
end Other__carpat__part797;

architecture Other__carpat__part797_behav of Other__carpat__part797 is
begin
    n28044 <= ( lo6246 );
end Other__carpat__part797_behav;
