--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1124 is 
  Port (
    lo5208: in std_logic;
    n25900: inout std_logic
  );
end IWLS2005__des_perf__part1124;

architecture IWLS2005__des_perf__part1124_behav of IWLS2005__des_perf__part1124 is
begin
    n25900 <= ( lo5208 );
end IWLS2005__des_perf__part1124_behav;
