--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part278 is 
  Port (
    lo0347: in std_logic;
    n2034: inout std_logic
  );
end Cookbook__fec_check__part278;

architecture Cookbook__fec_check__part278_behav of Cookbook__fec_check__part278 is
begin
    n2034 <= ( lo0347 );
end Cookbook__fec_check__part278_behav;
