--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part23 is 
  Port (
    pi023: in std_logic;
    n9764_1: inout std_logic
  );
end Other__desperf__part23;

architecture Other__desperf__part23_behav of Other__desperf__part23 is
begin
    n9764_1 <= ( pi023 );
end Other__desperf__part23_behav;
