--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1084 is 
  Port (
    lo7177: in std_logic;
    n38259_1: inout std_logic
  );
end Other__carpat__part1084;

architecture Other__carpat__part1084_behav of Other__carpat__part1084 is
begin
    n38259_1 <= ( lo7177 );
end Other__carpat__part1084_behav;
