--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1204 is 
  Port (
    lo2788: in std_logic;
    n18506: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1204;

architecture Other__ucsb_152_tap_fir__part1204_behav of Other__ucsb_152_tap_fir__part1204 is
begin
    n18506 <= ( lo2788 );
end Other__ucsb_152_tap_fir__part1204_behav;
