--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part279 is 
  Port (
    lo1362: in std_logic;
    n9745_1: inout std_logic
  );
end Other__fp_operators__part279;

architecture Other__fp_operators__part279_behav of Other__fp_operators__part279 is
begin
    n9745_1 <= ( lo1362 );
end Other__fp_operators__part279_behav;
