--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2199 is 
  Port (
    lo4862: in std_logic;
    n28901: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2199;

architecture Other__ucsb_152_tap_fir__part2199_behav of Other__ucsb_152_tap_fir__part2199 is
begin
    n28901 <= ( lo4862 );
end Other__ucsb_152_tap_fir__part2199_behav;
