--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part861 is 
  Port (
    lo0930: in std_logic;
    n4949: inout std_logic
  );
end Cookbook__fec_check__part861;

architecture Cookbook__fec_check__part861_behav of Cookbook__fec_check__part861 is
begin
    n4949 <= ( lo0930 );
end Cookbook__fec_check__part861_behav;
