--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part90 is 
  Port (
    lo604,lo605,lo606: in std_logic;
    n3313_1,n3318_1,n3323_1: inout std_logic
  );
end ISCAS__s13207__part90;

architecture ISCAS__s13207__part90_behav of ISCAS__s13207__part90 is
signal n2493,n2994,n3036,n4493,n4494,n4495: std_logic;
begin
    n3313_1 <= ( not lo604 );
    n2493 <= ( lo605 and lo604 );
    n3318_1 <= ( n4494 and n4495 );
    n3323_1 <= not (( not n3036 and not n2994 ));
    n2994 <= ( not lo606 and n2493 );
    n3036 <= ( lo606 and not n2493 );
    n4493 <= not (( not lo605 and lo604 ));
    n4494 <= not (( not lo605 and n4493 ));
    n4495 <= not (( lo604 and n4493 ));
end ISCAS__s13207__part90_behav;
