--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part258 is 
  Port (
    pi1515: in std_logic;
    n44374_1: inout std_logic
  );
end Other__carpat__part258;

architecture Other__carpat__part258_behav of Other__carpat__part258 is
begin
    n44374_1 <= ( pi1515 );
end Other__carpat__part258_behav;
