--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part38 is 
  Port (
    lo043: in std_logic;
    n917: inout std_logic
  );
end Cookbook__gearbox_67_40__part38;

architecture Cookbook__gearbox_67_40__part38_behav of Cookbook__gearbox_67_40__part38 is
begin
    n917 <= ( lo043 );
end Cookbook__gearbox_67_40__part38_behav;
