--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3198 is 
  Port (
    lo8531: in std_logic;
    n42775_1: inout std_logic
  );
end IWLS2005__des_perf__part3198;

architecture IWLS2005__des_perf__part3198_behav of IWLS2005__des_perf__part3198 is
begin
    n42775_1 <= ( lo8531 );
end IWLS2005__des_perf__part3198_behav;
