--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_8bit__part17 is 
  Port (
    lo41: in std_logic;
    po13: inout std_logic
  );
end Cookbook__soft_ecc_ram_8bit__part17;

architecture Cookbook__soft_ecc_ram_8bit__part17_behav of Cookbook__soft_ecc_ram_8bit__part17 is
begin
    po13 <= ( lo41 );
end Cookbook__soft_ecc_ram_8bit__part17_behav;
