--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1183 is 
  Port (
    lo2734: in std_logic;
    n18261: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1183;

architecture Other__ucsb_152_tap_fir__part1183_behav of Other__ucsb_152_tap_fir__part1183 is
begin
    n18261 <= ( lo2734 );
end Other__ucsb_152_tap_fir__part1183_behav;
