--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1205 is 
  Port (
    lo1274: in std_logic;
    n6669: inout std_logic
  );
end Cookbook__fec_check__part1205;

architecture Cookbook__fec_check__part1205_behav of Cookbook__fec_check__part1205 is
begin
    n6669 <= ( lo1274 );
end Cookbook__fec_check__part1205_behav;
