--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part925 is 
  Port (
    lo6770: in std_logic;
    n34159_1: inout std_logic
  );
end Other__carpat__part925;

architecture Other__carpat__part925_behav of Other__carpat__part925 is
begin
    n34159_1 <= ( lo6770 );
end Other__carpat__part925_behav;
