--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1715 is 
  Port (
    lo8741: in std_logic;
    po193: inout std_logic
  );
end Other__carpat__part1715;

architecture Other__carpat__part1715_behav of Other__carpat__part1715 is
begin
    po193 <= ( lo8741 );
end Other__carpat__part1715_behav;
