--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part17 is 
  Port (
    pi17: in std_logic;
    n1644_1: inout std_logic
  );
end Cookbook__gearbox_40_67__part17;

architecture Cookbook__gearbox_40_67__part17_behav of Cookbook__gearbox_40_67__part17 is
begin
    n1644_1 <= ( pi17 );
end Cookbook__gearbox_40_67__part17_behav;
