--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part828 is 
  Port (
    lo6457: in std_logic;
    n30539: inout std_logic
  );
end Other__carpat__part828;

architecture Other__carpat__part828_behav of Other__carpat__part828 is
begin
    n30539 <= ( lo6457 );
end Other__carpat__part828_behav;
