--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part666 is 
  Port (
    lo06163: in std_logic;
    po1824,po1919: inout std_logic
  );
end Other__ray__part666;

architecture Other__ray__part666_behav of Other__ray__part666 is
begin
    po1824 <= ( lo06163 );
    po1919 <= ( lo06163 );
end Other__ray__part666_behav;
