--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part804 is 
  Port (
    lo4577: in std_logic;
    n23175: inout std_logic
  );
end IWLS2005__des_perf__part804;

architecture IWLS2005__des_perf__part804_behav of IWLS2005__des_perf__part804 is
begin
    n23175 <= ( lo4577 );
end IWLS2005__des_perf__part804_behav;
