--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3288 is 
  Port (
    lo8637: in std_logic;
    n43540_1: inout std_logic
  );
end IWLS2005__des_perf__part3288;

architecture IWLS2005__des_perf__part3288_behav of IWLS2005__des_perf__part3288 is
begin
    n43540_1 <= ( lo8637 );
end IWLS2005__des_perf__part3288_behav;
