--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part37 is 
  Port (
    lo113: in std_logic;
    po68: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part37;

architecture Cookbook__soft_ecc_ram_32bit__part37_behav of Cookbook__soft_ecc_ram_32bit__part37 is
begin
    po68 <= ( lo113 );
end Cookbook__soft_ecc_ram_32bit__part37_behav;
