--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part5 is 
  Port (
    pi09: in std_logic;
    n434: inout std_logic
  );
end LGSynth91__s38417__part5;

architecture LGSynth91__s38417__part5_behav of LGSynth91__s38417__part5 is
begin
    n434 <= ( pi09 );
end LGSynth91__s38417__part5_behav;
