--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1134 is 
  Port (
    lo2629: in std_logic;
    n17666: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1134;

architecture Other__ucsb_152_tap_fir__part1134_behav of Other__ucsb_152_tap_fir__part1134 is
begin
    n17666 <= ( lo2629 );
end Other__ucsb_152_tap_fir__part1134_behav;
