--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2496 is 
  Port (
    lo5510: in std_logic;
    n32136_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2496;

architecture Other__ucsb_152_tap_fir__part2496_behav of Other__ucsb_152_tap_fir__part2496 is
begin
    n32136_1 <= ( lo5510 );
end Other__ucsb_152_tap_fir__part2496_behav;
