--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part562 is 
  Port (
    lo3402: in std_logic;
    n16184: inout std_logic
  );
end Other__carpat__part562;

architecture Other__carpat__part562_behav of Other__carpat__part562 is
begin
    n16184 <= ( lo3402 );
end Other__carpat__part562_behav;
