--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part81 is 
  Port (
    pi081: in std_logic;
    n10054_1: inout std_logic
  );
end Other__desperf__part81;

architecture Other__desperf__part81_behav of Other__desperf__part81 is
begin
    n10054_1 <= ( pi081 );
end Other__desperf__part81_behav;
