--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part46 is 
  Port (
    lo0201: in std_logic;
    n2192: inout std_logic
  );
end Other__cfft__part46;

architecture Other__cfft__part46_behav of Other__cfft__part46 is
begin
    n2192 <= ( lo0201 );
end Other__cfft__part46_behav;
