--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part58 is 
  Port (
    lo0016: in std_logic;
    po151: inout std_logic
  );
end IWLS2005__mem_ctrl__part58;

architecture IWLS2005__mem_ctrl__part58_behav of IWLS2005__mem_ctrl__part58 is
begin
    po151 <= ( lo0016 );
end IWLS2005__mem_ctrl__part58_behav;
