--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part150 is 
  Port (
    lo033: in std_logic;
    po035: inout std_logic
  );
end Other__fpu__part150;

architecture Other__fpu__part150_behav of Other__fpu__part150 is
begin
    po035 <= ( lo033 );
end Other__fpu__part150_behav;
