--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__k2__part1 is 
  Port (
    : in std_logic;
    po15,po35: inout std_logic
  );
end IWLS93__k2__part1;

architecture IWLS93__k2__part1_behav of IWLS93__k2__part1 is
signal n105: std_logic;
begin
    n105 <= '0';
    po15 <= ( n105 );
    po35 <= ( n105 );
end IWLS93__k2__part1_behav;
