--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part421 is 
  Port (
    lo2280: in std_logic;
    n11145: inout std_logic
  );
end IWLS2005__des_perf__part421;

architecture IWLS2005__des_perf__part421_behav of IWLS2005__des_perf__part421 is
begin
    n11145 <= ( not lo2280 );
end IWLS2005__des_perf__part421_behav;
