--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1174 is 
  Port (
    lo1243: in std_logic;
    n6514: inout std_logic
  );
end Cookbook__fec_check__part1174;

architecture Cookbook__fec_check__part1174_behav of Cookbook__fec_check__part1174 is
begin
    n6514 <= ( lo1243 );
end Cookbook__fec_check__part1174_behav;
