--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part124 is 
  Port (
    lo110: in std_logic;
    po156: inout std_logic
  );
end Cookbook__lc_mult_signed__part124;

architecture Cookbook__lc_mult_signed__part124_behav of Cookbook__lc_mult_signed__part124 is
begin
    po156 <= ( lo110 );
end Cookbook__lc_mult_signed__part124_behav;
