--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1655 is 
  Port (
    lo1724: in std_logic;
    n8919: inout std_logic
  );
end Cookbook__fec_check__part1655;

architecture Cookbook__fec_check__part1655_behav of Cookbook__fec_check__part1655 is
begin
    n8919 <= ( lo1724 );
end Cookbook__fec_check__part1655_behav;
