--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part7 is 
  Port (
    lo012: in std_logic;
    n762: inout std_logic
  );
end Cookbook__gearbox_67_40__part7;

architecture Cookbook__gearbox_67_40__part7_behav of Cookbook__gearbox_67_40__part7 is
begin
    n762 <= ( lo012 );
end Cookbook__gearbox_67_40__part7_behav;
