--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part180 is 
  Port (
    lo2829: in std_logic;
    n6719: inout std_logic
  );
end Other__sudoku_check__part180;

architecture Other__sudoku_check__part180_behav of Other__sudoku_check__part180 is
begin
    n6719 <= ( lo2829 );
end Other__sudoku_check__part180_behav;
