--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1401 is 
  Port (
    lo1470: in std_logic;
    n7649: inout std_logic
  );
end Cookbook__fec_check__part1401;

architecture Cookbook__fec_check__part1401_behav of Cookbook__fec_check__part1401 is
begin
    n7649 <= ( lo1470 );
end Cookbook__fec_check__part1401_behav;
