--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1245 is 
  Port (
    lo1314: in std_logic;
    n6869: inout std_logic
  );
end Cookbook__fec_check__part1245;

architecture Cookbook__fec_check__part1245_behav of Cookbook__fec_check__part1245 is
begin
    n6869 <= ( lo1314 );
end Cookbook__fec_check__part1245_behav;
