--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part174 is 
  Port (
    lo273: in std_logic;
    n877: inout std_logic
  );
end Other__fpu__part174;

architecture Other__fpu__part174_behav of Other__fpu__part174 is
begin
    n877 <= ( lo273 );
end Other__fpu__part174_behav;
