--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part4 is 
  Port (
    lo03: in std_logic;
    po03: inout std_logic
  );
end Other__idxlat00n_m12__part4;

architecture Other__idxlat00n_m12__part4_behav of Other__idxlat00n_m12__part4 is
begin
    po03 <= ( lo03 );
end Other__idxlat00n_m12__part4_behav;
