--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part53 is 
  Port (
    lo0122: in std_logic;
    n909: inout std_logic
  );
end Cookbook__fec_check__part53;

architecture Cookbook__fec_check__part53_behav of Cookbook__fec_check__part53 is
begin
    n909 <= ( lo0122 );
end Cookbook__fec_check__part53_behav;
