--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1881 is 
  Port (
    lo4237: in std_logic;
    n25766: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1881;

architecture Other__ucsb_152_tap_fir__part1881_behav of Other__ucsb_152_tap_fir__part1881 is
begin
    n25766 <= ( lo4237 );
end Other__ucsb_152_tap_fir__part1881_behav;
