--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2435 is 
  Port (
    lo7678: in std_logic;
    n38020: inout std_logic
  );
end IWLS2005__des_perf__part2435;

architecture IWLS2005__des_perf__part2435_behav of IWLS2005__des_perf__part2435 is
begin
    n38020 <= ( lo7678 );
end IWLS2005__des_perf__part2435_behav;
