--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part5 is 
  Port (
    lo04: in std_logic;
    po04: inout std_logic
  );
end Other__idxlat02n_m12__part5;

architecture Other__idxlat02n_m12__part5_behav of Other__idxlat02n_m12__part5 is
begin
    po04 <= ( lo04 );
end Other__idxlat02n_m12__part5_behav;
