--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part44 is 
  Port (
    lo043: in std_logic;
    n525: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part44;

architecture Cookbook__approx_fp_invsqrt__part44_behav of Cookbook__approx_fp_invsqrt__part44 is
begin
    n525 <= ( lo043 );
end Cookbook__approx_fp_invsqrt__part44_behav;
