--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part50 is 
  Port (
    lo036: in std_logic;
    po230: inout std_logic
  );
end Cookbook__lc_mult_signed__part50;

architecture Cookbook__lc_mult_signed__part50_behav of Cookbook__lc_mult_signed__part50 is
begin
    po230 <= ( lo036 );
end Cookbook__lc_mult_signed__part50_behav;
