--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1436 is 
  Port (
    lo3293: in std_logic;
    n21046: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1436;

architecture Other__ucsb_152_tap_fir__part1436_behav of Other__ucsb_152_tap_fir__part1436 is
begin
    n21046 <= ( lo3293 );
end Other__ucsb_152_tap_fir__part1436_behav;
