--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part673 is 
  Port (
    lo0742: in std_logic;
    n4009: inout std_logic
  );
end Cookbook__fec_check__part673;

architecture Cookbook__fec_check__part673_behav of Cookbook__fec_check__part673 is
begin
    n4009 <= ( lo0742 );
end Cookbook__fec_check__part673_behav;
