--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part719 is 
  Port (
    lo4404: in std_logic;
    n21990: inout std_logic
  );
end IWLS2005__des_perf__part719;

architecture IWLS2005__des_perf__part719_behav of IWLS2005__des_perf__part719 is
begin
    n21990 <= ( lo4404 );
end IWLS2005__des_perf__part719_behav;
