--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part38 is 
  Port (
    lo35: in std_logic;
    po35: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part38;

architecture Cookbook__x4_encoder_8b10b__part38_behav of Cookbook__x4_encoder_8b10b__part38 is
begin
    po35 <= ( lo35 );
end Cookbook__x4_encoder_8b10b__part38_behav;
