--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1148 is 
  Port (
    lo12995: in std_logic;
    po1973,po2007,po2153,po2187,n51706_1: inout std_logic
  );
end Other__ray__part1148;

architecture Other__ray__part1148_behav of Other__ray__part1148 is
begin
    po1973 <= ( lo12995 );
    po2007 <= ( lo12995 );
    po2153 <= ( lo12995 );
    po2187 <= ( lo12995 );
    n51706_1 <= ( lo12995 );
end Other__ray__part1148_behav;
