--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part70 is 
  Port (
    lo237: in std_logic;
    po13: inout std_logic
  );
end Cookbook__gearbox_67_40__part70;

architecture Cookbook__gearbox_67_40__part70_behav of Cookbook__gearbox_67_40__part70 is
begin
    po13 <= ( lo237 );
end Cookbook__gearbox_67_40__part70_behav;
