--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part882 is 
  Port (
    lo6649: in std_logic;
    n31709_1: inout std_logic
  );
end Other__carpat__part882;

architecture Other__carpat__part882_behav of Other__carpat__part882 is
begin
    n31709_1 <= ( lo6649 );
end Other__carpat__part882_behav;
