--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part870 is 
  Port (
    lo4239: in std_logic;
    n16684: inout std_logic
  );
end Other__sudoku_check__part870;

architecture Other__sudoku_check__part870_behav of Other__sudoku_check__part870 is
begin
    n16684 <= ( lo4239 );
end Other__sudoku_check__part870_behav;
