--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part172 is 
  Port (
    lo0664: in std_logic;
    n5705: inout std_logic
  );
end Other__fp_operators__part172;

architecture Other__fp_operators__part172_behav of Other__fp_operators__part172 is
begin
    n5705 <= ( lo0664 );
end Other__fp_operators__part172_behav;
