--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1626 is 
  Port (
    lo8418: in std_logic;
    n46989_1: inout std_logic
  );
end Other__carpat__part1626;

architecture Other__carpat__part1626_behav of Other__carpat__part1626 is
begin
    n46989_1 <= ( lo8418 );
end Other__carpat__part1626_behav;
