--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part48 is 
  Port (
    lo47: in std_logic;
    po47: inout std_logic
  );
end Other__idxlat10n_m12__part48;

architecture Other__idxlat10n_m12__part48_behav of Other__idxlat10n_m12__part48 is
begin
    po47 <= ( lo47 );
end Other__idxlat10n_m12__part48_behav;
