--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part183 is 
  Port (
    lo0435: in std_logic;
    n6646: inout std_logic
  );
end Other__ucsb_152_tap_fir__part183;

architecture Other__ucsb_152_tap_fir__part183_behav of Other__ucsb_152_tap_fir__part183 is
begin
    n6646 <= ( lo0435 );
end Other__ucsb_152_tap_fir__part183_behav;
