--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2244 is 
  Port (
    lo7435: in std_logic;
    n36865: inout std_logic
  );
end IWLS2005__des_perf__part2244;

architecture IWLS2005__des_perf__part2244_behav of IWLS2005__des_perf__part2244 is
begin
    n36865 <= ( lo7435 );
end IWLS2005__des_perf__part2244_behav;
