--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part361 is 
  Port (
    lo1312: in std_logic;
    n7669_1: inout std_logic
  );
end Cookbook__ucrypt__part361;

architecture Cookbook__ucrypt__part361_behav of Cookbook__ucrypt__part361 is
begin
    n7669_1 <= ( lo1312 );
end Cookbook__ucrypt__part361_behav;
