--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part381 is 
  Port (
    pi1747: in std_logic;
    n48369_1: inout std_logic
  );
end Other__carpat__part381;

architecture Other__carpat__part381_behav of Other__carpat__part381 is
begin
    n48369_1 <= ( pi1747 );
end Other__carpat__part381_behav;
