--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1670 is 
  Port (
    lo1739: in std_logic;
    n8994: inout std_logic
  );
end Cookbook__fec_check__part1670;

architecture Cookbook__fec_check__part1670_behav of Cookbook__fec_check__part1670 is
begin
    n8994 <= ( lo1739 );
end Cookbook__fec_check__part1670_behav;
