--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part42 is 
  Port (
    lo2181: in std_logic;
    n5339: inout std_logic
  );
end Other__sudoku_check__part42;

architecture Other__sudoku_check__part42_behav of Other__sudoku_check__part42 is
begin
    n5339 <= ( lo2181 );
end Other__sudoku_check__part42_behav;
