--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part102 is 
  Port (
    lo3251: in std_logic;
    n16659: inout std_logic
  );
end IWLS2005__pci_bridge32__part102;

architecture IWLS2005__pci_bridge32__part102_behav of IWLS2005__pci_bridge32__part102 is
begin
    n16659 <= ( lo3251 );
end IWLS2005__pci_bridge32__part102_behav;
