--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part845 is 
  Port (
    lo4669: in std_logic;
    n23265: inout std_logic
  );
end IWLS2005__des_perf__part845;

architecture IWLS2005__des_perf__part845_behav of IWLS2005__des_perf__part845 is
begin
    n23265 <= ( lo4669 );
end IWLS2005__des_perf__part845_behav;
