--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1444 is 
  Port (
    lo1513: in std_logic;
    n7864: inout std_logic
  );
end Cookbook__fec_check__part1444;

architecture Cookbook__fec_check__part1444_behav of Cookbook__fec_check__part1444 is
begin
    n7864 <= ( lo1513 );
end Cookbook__fec_check__part1444_behav;
