--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part132 is 
  Port (
    lo118: in std_logic;
    po148: inout std_logic
  );
end Cookbook__lc_mult_signed__part132;

architecture Cookbook__lc_mult_signed__part132_behav of Cookbook__lc_mult_signed__part132 is
begin
    po148 <= ( lo118 );
end Cookbook__lc_mult_signed__part132_behav;
