--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part32 is 
  Port (
    lo30: in std_logic;
    po09: inout std_logic
  );
end Cookbook__pipeline_add__part32;

architecture Cookbook__pipeline_add__part32_behav of Cookbook__pipeline_add__part32 is
begin
    po09 <= ( lo30 );
end Cookbook__pipeline_add__part32_behav;
