--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1189 is 
  Port (
    lo4558: in std_logic;
    n18279: inout std_logic
  );
end Other__sudoku_check__part1189;

architecture Other__sudoku_check__part1189_behav of Other__sudoku_check__part1189 is
begin
    n18279 <= ( lo4558 );
end Other__sudoku_check__part1189_behav;
