--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2964 is 
  Port (
    lo8277: in std_logic;
    n41630_1: inout std_logic
  );
end IWLS2005__des_perf__part2964;

architecture IWLS2005__des_perf__part2964_behav of IWLS2005__des_perf__part2964 is
begin
    n41630_1 <= ( lo8277 );
end IWLS2005__des_perf__part2964_behav;
