--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1363 is 
  Port (
    lo5788: in std_logic;
    n29170_1: inout std_logic
  );
end IWLS2005__des_perf__part1363;

architecture IWLS2005__des_perf__part1363_behav of IWLS2005__des_perf__part1363 is
begin
    n29170_1 <= ( lo5788 );
end IWLS2005__des_perf__part1363_behav;
