--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part322 is 
  Port (
    lo0391: in std_logic;
    n2254: inout std_logic
  );
end Cookbook__fec_check__part322;

architecture Cookbook__fec_check__part322_behav of Cookbook__fec_check__part322 is
begin
    n2254 <= ( lo0391 );
end Cookbook__fec_check__part322_behav;
