--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part58 is 
  Port (
    lo027: in std_logic;
    n619: inout std_logic
  );
end Cookbook__gearbox_40_67__part58;

architecture Cookbook__gearbox_40_67__part58_behav of Cookbook__gearbox_40_67__part58 is
begin
    n619 <= ( lo027 );
end Cookbook__gearbox_40_67__part58_behav;
