--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1370 is 
  Port (
    lo3165: in std_logic;
    n20411: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1370;

architecture Other__ucsb_152_tap_fir__part1370_behav of Other__ucsb_152_tap_fir__part1370 is
begin
    n20411 <= ( lo3165 );
end Other__ucsb_152_tap_fir__part1370_behav;
