--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part12 is 
  Port (
    lo012: in std_logic;
    n353: inout std_logic
  );
end ISCAS__s13207__part12;

architecture ISCAS__s13207__part12_behav of ISCAS__s13207__part12 is
begin
    n353 <= ( lo012 );
end ISCAS__s13207__part12_behav;
