--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part756 is 
  Port (
    lo3405: in std_logic;
    n12479: inout std_logic
  );
end Other__sudoku_check__part756;

architecture Other__sudoku_check__part756_behav of Other__sudoku_check__part756 is
begin
    n12479 <= ( lo3405 );
end Other__sudoku_check__part756_behav;
