--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3196 is 
  Port (
    lo8528: in std_logic;
    n43015_1: inout std_logic
  );
end IWLS2005__des_perf__part3196;

architecture IWLS2005__des_perf__part3196_behav of IWLS2005__des_perf__part3196 is
begin
    n43015_1 <= ( lo8528 );
end IWLS2005__des_perf__part3196_behav;
