--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part182 is 
  Port (
    lo0621: in std_logic;
    n4364: inout std_logic
  );
end Cookbook__ucrypt__part182;

architecture Cookbook__ucrypt__part182_behav of Cookbook__ucrypt__part182 is
begin
    n4364 <= ( lo0621 );
end Cookbook__ucrypt__part182_behav;
