--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1365 is 
  Port (
    lo4734: in std_logic;
    n19159: inout std_logic
  );
end Other__sudoku_check__part1365;

architecture Other__sudoku_check__part1365_behav of Other__sudoku_check__part1365 is
begin
    n19159 <= ( lo4734 );
end Other__sudoku_check__part1365_behav;
