--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part445 is 
  Port (
    lo3094: in std_logic;
    n9369: inout std_logic
  );
end Other__sudoku_check__part445;

architecture Other__sudoku_check__part445_behav of Other__sudoku_check__part445 is
begin
    n9369 <= ( lo3094 );
end Other__sudoku_check__part445_behav;
