--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part330 is 
  Port (
    lo1552: in std_logic;
    n11115_1: inout std_logic
  );
end Other__fp_operators__part330;

architecture Other__fp_operators__part330_behav of Other__fp_operators__part330 is
begin
    n11115_1 <= ( lo1552 );
end Other__fp_operators__part330_behav;
