--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part21 is 
  Port (
    lo63: in std_logic;
    po36: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part21;

architecture Cookbook__soft_ecc_ram_16bit__part21_behav of Cookbook__soft_ecc_ram_16bit__part21 is
begin
    po36 <= ( lo63 );
end Cookbook__soft_ecc_ram_16bit__part21_behav;
