--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1524 is 
  Port (
    lo3466: in std_logic;
    n21916: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1524;

architecture Other__ucsb_152_tap_fir__part1524_behav of Other__ucsb_152_tap_fir__part1524 is
begin
    n21916 <= ( lo3466 );
end Other__ucsb_152_tap_fir__part1524_behav;
