--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part30 is 
  Port (
    pi030: in std_logic;
    n2377_1: inout std_logic
  );
end Other__fpu__part30;

architecture Other__fpu__part30_behav of Other__fpu__part30 is
begin
    n2377_1 <= ( pi030 );
end Other__fpu__part30_behav;
