--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1167 is 
  Port (
    lo4536: in std_logic;
    n18169: inout std_logic
  );
end Other__sudoku_check__part1167;

architecture Other__sudoku_check__part1167_behav of Other__sudoku_check__part1167 is
begin
    n18169 <= ( lo4536 );
end Other__sudoku_check__part1167_behav;
