--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part982 is 
  Port (
    lo4351: in std_logic;
    n17244: inout std_logic
  );
end Other__sudoku_check__part982;

architecture Other__sudoku_check__part982_behav of Other__sudoku_check__part982 is
begin
    n17244 <= ( lo4351 );
end Other__sudoku_check__part982_behav;
