--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2880 is 
  Port (
    lo8193: in std_logic;
    n41120_1: inout std_logic
  );
end IWLS2005__des_perf__part2880;

architecture IWLS2005__des_perf__part2880_behav of IWLS2005__des_perf__part2880 is
begin
    n41120_1 <= ( lo8193 );
end IWLS2005__des_perf__part2880_behav;
