--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part581 is 
  Port (
    lo3230: in std_logic;
    n10729: inout std_logic
  );
end Other__sudoku_check__part581;

architecture Other__sudoku_check__part581_behav of Other__sudoku_check__part581 is
begin
    n10729 <= ( lo3230 );
end Other__sudoku_check__part581_behav;
