--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1031 is 
  Port (
    lo10752: in std_logic;
    n72066: inout std_logic
  );
end Other__ray__part1031;

architecture Other__ray__part1031_behav of Other__ray__part1031 is
begin
    n72066 <= ( lo10752 );
end Other__ray__part1031_behav;
