--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1699 is 
  Port (
    lo8703: in std_logic;
    n49019_1: inout std_logic
  );
end Other__carpat__part1699;

architecture Other__carpat__part1699_behav of Other__carpat__part1699 is
begin
    n49019_1 <= ( lo8703 );
end Other__carpat__part1699_behav;
