--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part333 is 
  Port (
    lo1201: in std_logic;
    n5665: inout std_logic
  );
end IWLS2005__des_perf__part333;

architecture IWLS2005__des_perf__part333_behav of IWLS2005__des_perf__part333 is
begin
    n5665 <= ( not lo1201 );
end IWLS2005__des_perf__part333_behav;
