--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1204 is 
  Port (
    lo7451: in std_logic;
    n41434_1: inout std_logic
  );
end Other__carpat__part1204;

architecture Other__carpat__part1204_behav of Other__carpat__part1204 is
begin
    n41434_1 <= ( lo7451 );
end Other__carpat__part1204_behav;
