--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part86 is 
  Port (
    lo10487: in std_logic;
    n52678_1: inout std_logic
  );
end IWLS2005__ethernet__part86;

architecture IWLS2005__ethernet__part86_behav of IWLS2005__ethernet__part86 is
begin
    n52678_1 <= ( lo10487 );
end IWLS2005__ethernet__part86_behav;
