--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1146 is 
  Port (
    lo2670: in std_logic;
    n17931: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1146;

architecture Other__ucsb_152_tap_fir__part1146_behav of Other__ucsb_152_tap_fir__part1146 is
begin
    n17931 <= ( lo2670 );
end Other__ucsb_152_tap_fir__part1146_behav;
