--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2563 is 
  Port (
    lo7820: in std_logic;
    n39070_1: inout std_logic
  );
end IWLS2005__des_perf__part2563;

architecture IWLS2005__des_perf__part2563_behav of IWLS2005__des_perf__part2563 is
begin
    n39070_1 <= ( lo7820 );
end IWLS2005__des_perf__part2563_behav;
