--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1929 is 
  Port (
    lo4312: in std_logic;
    n26146: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1929;

architecture Other__ucsb_152_tap_fir__part1929_behav of Other__ucsb_152_tap_fir__part1929 is
begin
    n26146 <= ( lo4312 );
end Other__ucsb_152_tap_fir__part1929_behav;
