--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1838 is 
  Port (
    lo9111: in std_logic;
    po475: inout std_logic
  );
end Other__carpat__part1838;

architecture Other__carpat__part1838_behav of Other__carpat__part1838 is
begin
    po475 <= ( lo9111 );
end Other__carpat__part1838_behav;
