--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part79 is 
  Port (
    lo0660: in std_logic;
    n3574: inout std_logic
  );
end ISCAS__s38417__part79;

architecture ISCAS__s38417__part79_behav of ISCAS__s38417__part79 is
begin
    n3574 <= ( lo0660 );
end ISCAS__s38417__part79_behav;
