--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part22 is 
  Port (
    lo0017: in std_logic;
    n844: inout std_logic
  );
end IWLS93__s38417__part22;

architecture IWLS93__s38417__part22_behav of IWLS93__s38417__part22 is
begin
    n844 <= ( lo0017 );
end IWLS93__s38417__part22_behav;
