--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part45 is 
  Port (
    pi045: in std_logic;
    n44175_1: inout std_logic
  );
end IWLS2005__des_perf__part45;

architecture IWLS2005__des_perf__part45_behav of IWLS2005__des_perf__part45 is
begin
    n44175_1 <= ( pi045 );
end IWLS2005__des_perf__part45_behav;
