--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part108 is 
  Port (
    lo0209: in std_logic;
    n5486: inout std_logic
  );
end Other__ucsb_152_tap_fir__part108;

architecture Other__ucsb_152_tap_fir__part108_behav of Other__ucsb_152_tap_fir__part108 is
begin
    n5486 <= ( lo0209 );
end Other__ucsb_152_tap_fir__part108_behav;
