--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1604 is 
  Port (
    lo8317: in std_logic;
    n46474_1: inout std_logic
  );
end Other__carpat__part1604;

architecture Other__carpat__part1604_behav of Other__carpat__part1604 is
begin
    n46474_1 <= ( lo8317 );
end Other__carpat__part1604_behav;
