--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2209 is 
  Port (
    lo7396: in std_logic;
    n36530_1: inout std_logic
  );
end IWLS2005__des_perf__part2209;

architecture IWLS2005__des_perf__part2209_behav of IWLS2005__des_perf__part2209 is
begin
    n36530_1 <= ( lo7396 );
end IWLS2005__des_perf__part2209_behav;
