--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part83 is 
  Port (
    pi138: in std_logic;
    n44015: inout std_logic
  );
end IWLS2005__des_perf__part83;

architecture IWLS2005__des_perf__part83_behav of IWLS2005__des_perf__part83 is
begin
    n44015 <= ( pi138 );
end IWLS2005__des_perf__part83_behav;
