--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1795 is 
  Port (
    lo1864: in std_logic;
    n9619: inout std_logic
  );
end Cookbook__fec_check__part1795;

architecture Cookbook__fec_check__part1795_behav of Cookbook__fec_check__part1795 is
begin
    n9619 <= ( lo1864 );
end Cookbook__fec_check__part1795_behav;
