--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part7 is 
  Port (
    lo0005: in std_logic;
    po0005: inout std_logic
  );
end Other__ether__part7;

architecture Other__ether__part7_behav of Other__ether__part7 is
begin
    po0005 <= ( lo0005 );
end Other__ether__part7_behav;
