--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part566 is 
  Port (
    lo3215: in std_logic;
    n10579: inout std_logic
  );
end Other__sudoku_check__part566;

architecture Other__sudoku_check__part566_behav of Other__sudoku_check__part566 is
begin
    n10579 <= ( lo3215 );
end Other__sudoku_check__part566_behav;
