--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1616 is 
  Port (
    lo3662: in std_logic;
    n22806: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1616;

architecture Other__ucsb_152_tap_fir__part1616_behav of Other__ucsb_152_tap_fir__part1616 is
begin
    n22806 <= ( lo3662 );
end Other__ucsb_152_tap_fir__part1616_behav;
