--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1591 is 
  Port (
    lo6259: in std_logic;
    n31475_1: inout std_logic
  );
end IWLS2005__des_perf__part1591;

architecture IWLS2005__des_perf__part1591_behav of IWLS2005__des_perf__part1591 is
begin
    n31475_1 <= ( lo6259 );
end IWLS2005__des_perf__part1591_behav;
