--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part274 is 
  Port (
    pi1531: in std_logic;
    n44864_1: inout std_logic
  );
end Other__carpat__part274;

architecture Other__carpat__part274_behav of Other__carpat__part274 is
begin
    n44864_1 <= ( pi1531 );
end Other__carpat__part274_behav;
