--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part78 is 
  Port (
    lo270: in std_logic;
    n1648: inout std_logic
  );
end ISCAS__s13207__part78;

architecture ISCAS__s13207__part78_behav of ISCAS__s13207__part78 is
begin
    n1648 <= ( lo270 );
end ISCAS__s13207__part78_behav;
