--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part28 is 
  Port (
    pi028: in std_logic;
    n2367_1: inout std_logic
  );
end Other__fpu__part28;

architecture Other__fpu__part28_behav of Other__fpu__part28 is
begin
    n2367_1 <= ( pi028 );
end Other__fpu__part28_behav;
