--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part192 is 
  Port (
    lo1451: in std_logic;
    po083: inout std_logic
  );
end LGSynth91__s38417__part192;

architecture LGSynth91__s38417__part192_behav of LGSynth91__s38417__part192 is
begin
    po083 <= ( lo1451 );
end LGSynth91__s38417__part192_behav;
