--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part361 is 
  Port (
    lo3010: in std_logic;
    n8529: inout std_logic
  );
end Other__sudoku_check__part361;

architecture Other__sudoku_check__part361_behav of Other__sudoku_check__part361 is
begin
    n8529 <= ( lo3010 );
end Other__sudoku_check__part361_behav;
