--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2162 is 
  Port (
    lo2231: in std_logic;
    n11454: inout std_logic
  );
end Cookbook__fec_check__part2162;

architecture Cookbook__fec_check__part2162_behav of Cookbook__fec_check__part2162 is
begin
    n11454 <= ( lo2231 );
end Cookbook__fec_check__part2162_behav;
