--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part465 is 
  Port (
    lo05937: in std_logic;
    po1403,po1437: inout std_logic
  );
end Other__ray__part465;

architecture Other__ray__part465_behav of Other__ray__part465 is
begin
    po1403 <= ( lo05937 );
    po1437 <= ( lo05937 );
end Other__ray__part465_behav;
