--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part604 is 
  Port (
    lo0673: in std_logic;
    n3664: inout std_logic
  );
end Cookbook__fec_check__part604;

architecture Cookbook__fec_check__part604_behav of Cookbook__fec_check__part604 is
begin
    n3664 <= ( lo0673 );
end Cookbook__fec_check__part604_behav;
