--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1926 is 
  Port (
    lo6878: in std_logic;
    n34445_1: inout std_logic
  );
end IWLS2005__des_perf__part1926;

architecture IWLS2005__des_perf__part1926_behav of IWLS2005__des_perf__part1926 is
begin
    n34445_1 <= ( lo6878 );
end IWLS2005__des_perf__part1926_behav;
