--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1357 is 
  Port (
    lo4726: in std_logic;
    n19119: inout std_logic
  );
end Other__sudoku_check__part1357;

architecture Other__sudoku_check__part1357_behav of Other__sudoku_check__part1357 is
begin
    n19119 <= ( lo4726 );
end Other__sudoku_check__part1357_behav;
