--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part275 is 
  Port (
    lo0344: in std_logic;
    n2019: inout std_logic
  );
end Cookbook__fec_check__part275;

architecture Cookbook__fec_check__part275_behav of Cookbook__fec_check__part275 is
begin
    n2019 <= ( lo0344 );
end Cookbook__fec_check__part275_behav;
