--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2429 is 
  Port (
    lo5369: in std_logic;
    n31441: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2429;

architecture Other__ucsb_152_tap_fir__part2429_behav of Other__ucsb_152_tap_fir__part2429 is
begin
    n31441 <= ( lo5369 );
end Other__ucsb_152_tap_fir__part2429_behav;
