--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1760 is 
  Port (
    lo8831: in std_logic;
    po286: inout std_logic
  );
end Other__carpat__part1760;

architecture Other__carpat__part1760_behav of Other__carpat__part1760 is
begin
    po286 <= ( lo8831 );
end Other__carpat__part1760_behav;
