--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part236 is 
  Port (
    lo0881: in std_logic;
    n3884: inout std_logic
  );
end Other__desperf__part236;

architecture Other__desperf__part236_behav of Other__desperf__part236 is
begin
    n3884 <= ( lo0881 );
end Other__desperf__part236_behav;
