--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part220 is 
  Port (
    lo0652: in std_logic;
    n2864: inout std_logic
  );
end Other__desperf__part220;

architecture Other__desperf__part220_behav of Other__desperf__part220 is
begin
    n2864 <= ( lo0652 );
end Other__desperf__part220_behav;
