--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part189 is 
  Port (
    lo0258: in std_logic;
    n1589: inout std_logic
  );
end Cookbook__fec_check__part189;

architecture Cookbook__fec_check__part189_behav of Cookbook__fec_check__part189 is
begin
    n1589 <= ( lo0258 );
end Cookbook__fec_check__part189_behav;
