--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part255 is 
  Port (
    lo2904: in std_logic;
    n7469: inout std_logic
  );
end Other__sudoku_check__part255;

architecture Other__sudoku_check__part255_behav of Other__sudoku_check__part255 is
begin
    n7469 <= ( lo2904 );
end Other__sudoku_check__part255_behav;
