--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2336 is 
  Port (
    lo5175: in std_logic;
    n30381: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2336;

architecture Other__ucsb_152_tap_fir__part2336_behav of Other__ucsb_152_tap_fir__part2336 is
begin
    n30381 <= ( lo5175 );
end Other__ucsb_152_tap_fir__part2336_behav;
