--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1743 is 
  Port (
    lo8811: in std_logic;
    po264: inout std_logic
  );
end Other__carpat__part1743;

architecture Other__carpat__part1743_behav of Other__carpat__part1743 is
begin
    po264 <= ( lo8811 );
end Other__carpat__part1743_behav;
