--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1572 is 
  Port (
    lo1641: in std_logic;
    n8504: inout std_logic
  );
end Cookbook__fec_check__part1572;

architecture Cookbook__fec_check__part1572_behav of Cookbook__fec_check__part1572 is
begin
    n8504 <= ( lo1641 );
end Cookbook__fec_check__part1572_behav;
