--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part782 is 
  Port (
    lo06509: in std_logic;
    n48871_1: inout std_logic
  );
end Other__ray__part782;

architecture Other__ray__part782_behav of Other__ray__part782 is
begin
    n48871_1 <= ( lo06509 );
end Other__ray__part782_behav;
