--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1489 is 
  Port (
    lo3403: in std_logic;
    n21521: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1489;

architecture Other__ucsb_152_tap_fir__part1489_behav of Other__ucsb_152_tap_fir__part1489 is
begin
    n21521 <= ( lo3403 );
end Other__ucsb_152_tap_fir__part1489_behav;
