--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part824 is 
  Port (
    lo6453: in std_logic;
    n30519_1: inout std_logic
  );
end Other__carpat__part824;

architecture Other__carpat__part824_behav of Other__carpat__part824 is
begin
    n30519_1 <= ( lo6453 );
end Other__carpat__part824_behav;
