--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part225 is 
  Port (
    lo0766: in std_logic;
    n3404: inout std_logic
  );
end Other__desperf__part225;

architecture Other__desperf__part225_behav of Other__desperf__part225 is
begin
    n3404 <= ( lo0766 );
end Other__desperf__part225_behav;
