--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part19 is 
  Port (
    lo2880: in std_logic;
    n13667: inout std_logic
  );
end Other__top_rs_decode__part19;

architecture Other__top_rs_decode__part19_behav of Other__top_rs_decode__part19 is
begin
    n13667 <= ( lo2880 );
end Other__top_rs_decode__part19_behav;
