--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2123 is 
  Port (
    lo4729: in std_logic;
    n28146: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2123;

architecture Other__ucsb_152_tap_fir__part2123_behav of Other__ucsb_152_tap_fir__part2123 is
begin
    n28146 <= ( lo4729 );
end Other__ucsb_152_tap_fir__part2123_behav;
