--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part63 is 
  Port (
    pi0758: in std_logic;
    n24894: inout std_logic
  );
end Other__carpat__part63;

architecture Other__carpat__part63_behav of Other__carpat__part63 is
begin
    n24894 <= ( pi0758 );
end Other__carpat__part63_behav;
