--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part606 is 
  Port (
    lo0675: in std_logic;
    n3674: inout std_logic
  );
end Cookbook__fec_check__part606;

architecture Cookbook__fec_check__part606_behav of Cookbook__fec_check__part606 is
begin
    n3674 <= ( lo0675 );
end Cookbook__fec_check__part606_behav;
