--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part37 is 
  Port (
    pi1129: in std_logic;
    n56161_1: inout std_logic
  );
end Other__ray__part37;

architecture Other__ray__part37_behav of Other__ray__part37 is
begin
    n56161_1 <= ( pi1129 );
end Other__ray__part37_behav;
