--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part654 is 
  Port (
    lo5096: in std_logic;
    n23064: inout std_logic
  );
end Other__carpat__part654;

architecture Other__carpat__part654_behav of Other__carpat__part654 is
begin
    n23064 <= ( lo5096 );
end Other__carpat__part654_behav;
