--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part993 is 
  Port (
    lo10690: in std_logic;
    n71561_1: inout std_logic
  );
end Other__ray__part993;

architecture Other__ray__part993_behav of Other__ray__part993 is
begin
    n71561_1 <= ( lo10690 );
end Other__ray__part993_behav;
