--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2224 is 
  Port (
    lo4916: in std_logic;
    n29166: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2224;

architecture Other__ucsb_152_tap_fir__part2224_behav of Other__ucsb_152_tap_fir__part2224 is
begin
    n29166 <= ( lo4916 );
end Other__ucsb_152_tap_fir__part2224_behav;
