--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part45 is 
  Port (
    lo169: in std_logic;
    po38: inout std_logic
  );
end IWLS2005__systemcdes__part45;

architecture IWLS2005__systemcdes__part45_behav of IWLS2005__systemcdes__part45 is
begin
    po38 <= ( lo169 );
end IWLS2005__systemcdes__part45_behav;
