--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part413 is 
  Port (
    lo0482: in std_logic;
    n2709: inout std_logic
  );
end Cookbook__fec_check__part413;

architecture Cookbook__fec_check__part413_behav of Cookbook__fec_check__part413 is
begin
    n2709 <= ( lo0482 );
end Cookbook__fec_check__part413_behav;
