--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part629 is 
  Port (
    lo0698: in std_logic;
    n3789: inout std_logic
  );
end Cookbook__fec_check__part629;

architecture Cookbook__fec_check__part629_behav of Cookbook__fec_check__part629 is
begin
    n3789 <= ( lo0698 );
end Cookbook__fec_check__part629_behav;
