--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part283 is 
  Port (
    lo1493: in std_logic;
    n7119_1: inout std_logic
  );
end Other__desperf__part283;

architecture Other__desperf__part283_behav of Other__desperf__part283 is
begin
    n7119_1 <= ( lo1493 );
end Other__desperf__part283_behav;
