--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part148 is 
  Port (
    lo0982: in std_logic;
    n5184_1: inout std_logic
  );
end LGSynth91__s38417__part148;

architecture LGSynth91__s38417__part148_behav of LGSynth91__s38417__part148 is
begin
    n5184_1 <= ( lo0982 );
end LGSynth91__s38417__part148_behav;
