--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part531 is 
  Port (
    lo06003: in std_logic;
    po1518,po1567,po1877,po1939: inout std_logic
  );
end Other__ray__part531;

architecture Other__ray__part531_behav of Other__ray__part531 is
begin
    po1518 <= ( lo06003 );
    po1567 <= ( lo06003 );
    po1877 <= ( lo06003 );
    po1939 <= ( lo06003 );
end Other__ray__part531_behav;
