--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part148 is 
  Port (
    lo1095: in std_logic;
    n5749_1: inout std_logic
  );
end ISCAS__s38417__part148;

architecture ISCAS__s38417__part148_behav of ISCAS__s38417__part148 is
begin
    n5749_1 <= ( lo1095 );
end ISCAS__s38417__part148_behav;
