--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part23 is 
  Port (
    lo028: in std_logic;
    n842: inout std_logic
  );
end Cookbook__gearbox_67_40__part23;

architecture Cookbook__gearbox_67_40__part23_behav of Cookbook__gearbox_67_40__part23 is
begin
    n842 <= ( lo028 );
end Cookbook__gearbox_67_40__part23_behav;
