--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part817 is 
  Port (
    lo06576: in std_logic;
    n49216_1: inout std_logic
  );
end Other__ray__part817;

architecture Other__ray__part817_behav of Other__ray__part817 is
begin
    n49216_1 <= ( lo06576 );
end Other__ray__part817_behav;
