--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part118 is 
  Port (
    lo0715: in std_logic;
    po025: inout std_logic
  );
end IWLS2005__mem_ctrl__part118;

architecture IWLS2005__mem_ctrl__part118_behav of IWLS2005__mem_ctrl__part118 is
begin
    po025 <= ( lo0715 );
end IWLS2005__mem_ctrl__part118_behav;
