--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1754 is 
  Port (
    lo6550: in std_logic;
    n32425_1: inout std_logic
  );
end IWLS2005__des_perf__part1754;

architecture IWLS2005__des_perf__part1754_behav of IWLS2005__des_perf__part1754 is
begin
    n32425_1 <= ( lo6550 );
end IWLS2005__des_perf__part1754_behav;
