--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1835 is 
  Port (
    lo1904: in std_logic;
    n9819: inout std_logic
  );
end Cookbook__fec_check__part1835;

architecture Cookbook__fec_check__part1835_behav of Cookbook__fec_check__part1835 is
begin
    n9819 <= ( lo1904 );
end Cookbook__fec_check__part1835_behav;
