--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part73 is 
  Port (
    pi073: in std_logic;
    n10014_1: inout std_logic
  );
end Other__desperf__part73;

architecture Other__desperf__part73_behav of Other__desperf__part73 is
begin
    n10014_1 <= ( pi073 );
end Other__desperf__part73_behav;
