--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part211 is 
  Port (
    lo0510: in std_logic;
    n7126: inout std_logic
  );
end Other__ucsb_152_tap_fir__part211;

architecture Other__ucsb_152_tap_fir__part211_behav of Other__ucsb_152_tap_fir__part211 is
begin
    n7126 <= ( lo0510 );
end Other__ucsb_152_tap_fir__part211_behav;
