--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1246 is 
  Port (
    lo2873: in std_logic;
    n18931: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1246;

architecture Other__ucsb_152_tap_fir__part1246_behav of Other__ucsb_152_tap_fir__part1246 is
begin
    n18931 <= ( lo2873 );
end Other__ucsb_152_tap_fir__part1246_behav;
