--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part431 is 
  Port (
    lo0500: in std_logic;
    n2799: inout std_logic
  );
end Cookbook__fec_check__part431;

architecture Cookbook__fec_check__part431_behav of Cookbook__fec_check__part431 is
begin
    n2799 <= ( lo0500 );
end Cookbook__fec_check__part431_behav;
