--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1611 is 
  Port (
    lo8403: in std_logic;
    n46914_1: inout std_logic
  );
end Other__carpat__part1611;

architecture Other__carpat__part1611_behav of Other__carpat__part1611 is
begin
    n46914_1 <= ( lo8403 );
end Other__carpat__part1611_behav;
