--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1873 is 
  Port (
    lo4225: in std_logic;
    n25711: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1873;

architecture Other__ucsb_152_tap_fir__part1873_behav of Other__ucsb_152_tap_fir__part1873 is
begin
    n25711 <= ( lo4225 );
end Other__ucsb_152_tap_fir__part1873_behav;
