--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1724 is 
  Port (
    lo6507: in std_logic;
    n32360: inout std_logic
  );
end IWLS2005__des_perf__part1724;

architecture IWLS2005__des_perf__part1724_behav of IWLS2005__des_perf__part1724 is
begin
    n32360 <= ( lo6507 );
end IWLS2005__des_perf__part1724_behav;
