--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part905 is 
  Port (
    lo09305: in std_logic;
    po0953: inout std_logic
  );
end Other__ray__part905;

architecture Other__ray__part905_behav of Other__ray__part905 is
begin
    po0953 <= ( lo09305 );
end Other__ray__part905_behav;
