--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part141 is 
  Port (
    lo0210: in std_logic;
    n1349: inout std_logic
  );
end Cookbook__fec_check__part141;

architecture Cookbook__fec_check__part141_behav of Cookbook__fec_check__part141 is
begin
    n1349 <= ( lo0210 );
end Cookbook__fec_check__part141_behav;
