--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part87 is 
  Port (
    pi087: in std_logic;
    n2127: inout std_logic
  );
end Other__fpu__part87;

architecture Other__fpu__part87_behav of Other__fpu__part87 is
begin
    n2127 <= ( pi087 );
end Other__fpu__part87_behav;
