--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part86 is 
  Port (
    lo3137: in std_logic;
    n16349: inout std_logic
  );
end IWLS2005__pci_bridge32__part86;

architecture IWLS2005__pci_bridge32__part86_behav of IWLS2005__pci_bridge32__part86 is
begin
    n16349 <= ( lo3137 );
end IWLS2005__pci_bridge32__part86_behav;
