--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part339 is 
  Port (
    lo2988: in std_logic;
    n8309: inout std_logic
  );
end Other__sudoku_check__part339;

architecture Other__sudoku_check__part339_behav of Other__sudoku_check__part339 is
begin
    n8309 <= ( lo2988 );
end Other__sudoku_check__part339_behav;
