--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part968 is 
  Port (
    lo4931: in std_logic;
    n24855: inout std_logic
  );
end IWLS2005__des_perf__part968;

architecture IWLS2005__des_perf__part968_behav of IWLS2005__des_perf__part968 is
begin
    n24855 <= ( lo4931 );
end IWLS2005__des_perf__part968_behav;
