--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1334 is 
  Port (
    lo1403: in std_logic;
    n7314: inout std_logic
  );
end Cookbook__fec_check__part1334;

architecture Cookbook__fec_check__part1334_behav of Cookbook__fec_check__part1334 is
begin
    n7314 <= ( lo1403 );
end Cookbook__fec_check__part1334_behav;
