--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part753 is 
  Port (
    lo5487: in std_logic;
    n25884: inout std_logic
  );
end Other__carpat__part753;

architecture Other__carpat__part753_behav of Other__carpat__part753 is
begin
    n25884 <= ( lo5487 );
end Other__carpat__part753_behav;
