--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1479 is 
  Port (
    lo1548: in std_logic;
    n8039: inout std_logic
  );
end Cookbook__fec_check__part1479;

architecture Cookbook__fec_check__part1479_behav of Cookbook__fec_check__part1479 is
begin
    n8039 <= ( lo1548 );
end Cookbook__fec_check__part1479_behav;
