--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part117 is 
  Port (
    lo0769: in std_logic;
    n3804: inout std_logic
  );
end IWLS93__s38417__part117;

architecture IWLS93__s38417__part117_behav of IWLS93__s38417__part117 is
begin
    n3804 <= ( lo0769 );
end IWLS93__s38417__part117_behav;
