--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part911 is 
  Port (
    lo4280: in std_logic;
    n16889: inout std_logic
  );
end Other__sudoku_check__part911;

architecture Other__sudoku_check__part911_behav of Other__sudoku_check__part911 is
begin
    n16889 <= ( lo4280 );
end Other__sudoku_check__part911_behav;
