--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part127 is 
  Port (
    lo0007: in std_logic;
    po07: inout std_logic
  );
end Other__desperf__part127;

architecture Other__desperf__part127_behav of Other__desperf__part127 is
begin
    po07 <= ( lo0007 );
end Other__desperf__part127_behav;
