--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part44 is 
  Port (
    lo43: in std_logic;
    po25: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part44;

architecture Cookbook__x4_decoder_8b10b__part44_behav of Cookbook__x4_decoder_8b10b__part44 is
begin
    po25 <= ( lo43 );
end Cookbook__x4_decoder_8b10b__part44_behav;
