--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part889 is 
  Port (
    lo08195: in std_logic;
    n53296_1: inout std_logic
  );
end Other__ray__part889;

architecture Other__ray__part889_behav of Other__ray__part889 is
begin
    n53296_1 <= ( lo08195 );
end Other__ray__part889_behav;
