--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1347 is 
  Port (
    lo1416: in std_logic;
    n7379: inout std_logic
  );
end Cookbook__fec_check__part1347;

architecture Cookbook__fec_check__part1347_behav of Cookbook__fec_check__part1347 is
begin
    n7379 <= ( lo1416 );
end Cookbook__fec_check__part1347_behav;
