--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part32 is 
  Port (
    lo484: in std_logic;
    n2598_1: inout std_logic
  );
end Cookbook__lane_tx__part32;

architecture Cookbook__lane_tx__part32_behav of Cookbook__lane_tx__part32 is
begin
    n2598_1 <= ( lo484 );
end Cookbook__lane_tx__part32_behav;
