--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part149 is 
  Port (
    lo2798: in std_logic;
    n6409: inout std_logic
  );
end Other__sudoku_check__part149;

architecture Other__sudoku_check__part149_behav of Other__sudoku_check__part149 is
begin
    n6409 <= ( lo2798 );
end Other__sudoku_check__part149_behav;
