--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2099 is 
  Port (
    lo2168: in std_logic;
    n11139: inout std_logic
  );
end Cookbook__fec_check__part2099;

architecture Cookbook__fec_check__part2099_behav of Cookbook__fec_check__part2099 is
begin
    n11139 <= ( lo2168 );
end Cookbook__fec_check__part2099_behav;
