--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1574 is 
  Port (
    lo1643: in std_logic;
    n8514: inout std_logic
  );
end Cookbook__fec_check__part1574;

architecture Cookbook__fec_check__part1574_behav of Cookbook__fec_check__part1574 is
begin
    n8514 <= ( lo1643 );
end Cookbook__fec_check__part1574_behav;
