--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ternary_sum_nine__part13 is 
  Port (
    lo39: in std_logic;
    po02: inout std_logic
  );
end Cookbook__ternary_sum_nine__part13;

architecture Cookbook__ternary_sum_nine__part13_behav of Cookbook__ternary_sum_nine__part13 is
begin
    po02 <= ( lo39 );
end Cookbook__ternary_sum_nine__part13_behav;
