--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part10 is 
  Port (
    pi15: in std_logic;
    n7254_1: inout std_logic
  );
end IWLS93__s38417__part10;

architecture IWLS93__s38417__part10_behav of IWLS93__s38417__part10 is
begin
    n7254_1 <= ( pi15 );
end IWLS93__s38417__part10_behav;
