--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part905 is 
  Port (
    lo4813: in std_logic;
    n24240: inout std_logic
  );
end IWLS2005__des_perf__part905;

architecture IWLS2005__des_perf__part905_behav of IWLS2005__des_perf__part905 is
begin
    n24240 <= ( lo4813 );
end IWLS2005__des_perf__part905_behav;
