--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part58 is 
  Port (
    lo16993: in std_logic;
    po08: inout std_logic
  );
end IWLS2005__vga_lcd__part58;

architecture IWLS2005__vga_lcd__part58_behav of IWLS2005__vga_lcd__part58 is
begin
    po08 <= ( lo16993 );
end IWLS2005__vga_lcd__part58_behav;
