--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part184 is 
  Port (
    lo0253: in std_logic;
    n1564: inout std_logic
  );
end Cookbook__fec_check__part184;

architecture Cookbook__fec_check__part184_behav of Cookbook__fec_check__part184 is
begin
    n1564 <= ( lo0253 );
end Cookbook__fec_check__part184_behav;
