--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part21 is 
  Port (
    lo0246: in std_logic;
    n1504: inout std_logic
  );
end ISCAS__s38417__part21;

architecture ISCAS__s38417__part21_behav of ISCAS__s38417__part21 is
begin
    n1504 <= ( lo0246 );
end ISCAS__s38417__part21_behav;
