--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part75 is 
  Port (
    lo0596: in std_logic;
    n3254: inout std_logic
  );
end LGSynth91__s38417__part75;

architecture LGSynth91__s38417__part75_behav of LGSynth91__s38417__part75 is
begin
    n3254 <= ( lo0596 );
end LGSynth91__s38417__part75_behav;
