--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part35 is 
  Port (
    pi35: in std_logic;
    n746692: inout std_logic
  );
end IWLS2005__leon2__part35;

architecture IWLS2005__leon2__part35_behav of IWLS2005__leon2__part35 is
begin
    n746692 <= ( pi35 );
end IWLS2005__leon2__part35_behav;
