--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part523 is 
  Port (
    lo4105: in std_logic;
    n20815: inout std_logic
  );
end IWLS2005__des_perf__part523;

architecture IWLS2005__des_perf__part523_behav of IWLS2005__des_perf__part523 is
begin
    n20815 <= ( lo4105 );
end IWLS2005__des_perf__part523_behav;
