--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part44 is 
  Port (
    lo0190: in std_logic;
    n2177: inout std_logic
  );
end Other__cfft__part44;

architecture Other__cfft__part44_behav of Other__cfft__part44 is
begin
    n2177 <= ( lo0190 );
end Other__cfft__part44_behav;
