--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1497 is 
  Port (
    lo3411: in std_logic;
    n21561: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1497;

architecture Other__ucsb_152_tap_fir__part1497_behav of Other__ucsb_152_tap_fir__part1497 is
begin
    n21561 <= ( lo3411 );
end Other__ucsb_152_tap_fir__part1497_behav;
