--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part87 is 
  Port (
    lo10488: in std_logic;
    n52568_1: inout std_logic
  );
end IWLS2005__ethernet__part87;

architecture IWLS2005__ethernet__part87_behav of IWLS2005__ethernet__part87 is
begin
    n52568_1 <= ( lo10488 );
end IWLS2005__ethernet__part87_behav;
