--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part24 is 
  Port (
    lo23: in std_logic;
    po23: inout std_logic
  );
end Other__idxlat02n_m12__part24;

architecture Other__idxlat02n_m12__part24_behav of Other__idxlat02n_m12__part24 is
begin
    po23 <= ( lo23 );
end Other__idxlat02n_m12__part24_behav;
