--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part461 is 
  Port (
    lo0530: in std_logic;
    n2949: inout std_logic
  );
end Cookbook__fec_check__part461;

architecture Cookbook__fec_check__part461_behav of Cookbook__fec_check__part461 is
begin
    n2949 <= ( lo0530 );
end Cookbook__fec_check__part461_behav;
