--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part417 is 
  Port (
    lo0486: in std_logic;
    n2729: inout std_logic
  );
end Cookbook__fec_check__part417;

architecture Cookbook__fec_check__part417_behav of Cookbook__fec_check__part417 is
begin
    n2729 <= ( lo0486 );
end Cookbook__fec_check__part417_behav;
