--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part67 is 
  Port (
    lo149316: in std_logic;
    n746602: inout std_logic
  );
end IWLS2005__leon2__part67;

architecture IWLS2005__leon2__part67_behav of IWLS2005__leon2__part67 is
begin
    n746602 <= ( lo149316 );
end IWLS2005__leon2__part67_behav;
