--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part411 is 
  Port (
    lo0097: in std_logic;
    po070: inout std_logic
  );
end Other__carpat__part411;

architecture Other__carpat__part411_behav of Other__carpat__part411 is
begin
    po070 <= ( lo0097 );
end Other__carpat__part411_behav;
