--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part167 is 
  Port (
    lo0588: in std_logic;
    n4049: inout std_logic
  );
end Cookbook__ucrypt__part167;

architecture Cookbook__ucrypt__part167_behav of Cookbook__ucrypt__part167 is
begin
    n4049 <= ( lo0588 );
end Cookbook__ucrypt__part167_behav;
