--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1146 is 
  Port (
    lo5304: in std_logic;
    n26585_1: inout std_logic
  );
end IWLS2005__des_perf__part1146;

architecture IWLS2005__des_perf__part1146_behav of IWLS2005__des_perf__part1146 is
begin
    n26585_1 <= ( lo5304 );
end IWLS2005__des_perf__part1146_behav;
