--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part840 is 
  Port (
    lo0909: in std_logic;
    n4844: inout std_logic
  );
end Cookbook__fec_check__part840;

architecture Cookbook__fec_check__part840_behav of Cookbook__fec_check__part840 is
begin
    n4844 <= ( lo0909 );
end Cookbook__fec_check__part840_behav;
