--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part943 is 
  Port (
    lo4312: in std_logic;
    n17049: inout std_logic
  );
end Other__sudoku_check__part943;

architecture Other__sudoku_check__part943_behav of Other__sudoku_check__part943 is
begin
    n17049 <= ( lo4312 );
end Other__sudoku_check__part943_behav;
