--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part576 is 
  Port (
    lo0645: in std_logic;
    n3524: inout std_logic
  );
end Cookbook__fec_check__part576;

architecture Cookbook__fec_check__part576_behav of Cookbook__fec_check__part576 is
begin
    n3524 <= ( lo0645 );
end Cookbook__fec_check__part576_behav;
