--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part477 is 
  Port (
    lo0546: in std_logic;
    n3029: inout std_logic
  );
end Cookbook__fec_check__part477;

architecture Cookbook__fec_check__part477_behav of Cookbook__fec_check__part477 is
begin
    n3029 <= ( lo0546 );
end Cookbook__fec_check__part477_behav;
