--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part133 is 
  Port (
    lo184944: in std_logic;
    n924701: inout std_logic
  );
end IWLS2005__leon3__part133;

architecture IWLS2005__leon3__part133_behav of IWLS2005__leon3__part133 is
begin
    n924701 <= ( lo184944 );
end IWLS2005__leon3__part133_behav;
