--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part801 is 
  Port (
    lo6369: in std_logic;
    po529: inout std_logic
  );
end Other__carpat__part801;

architecture Other__carpat__part801_behav of Other__carpat__part801 is
begin
    po529 <= ( lo6369 );
end Other__carpat__part801_behav;
