--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2177 is 
  Port (
    lo7330: in std_logic;
    n36725_1: inout std_logic
  );
end IWLS2005__des_perf__part2177;

architecture IWLS2005__des_perf__part2177_behav of IWLS2005__des_perf__part2177 is
begin
    n36725_1 <= ( lo7330 );
end IWLS2005__des_perf__part2177_behav;
