--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__reg_cam_cell__part1 is 
  Port (
    lo64: in std_logic;
    po0: inout std_logic
  );
end Cookbook__reg_cam_cell__part1;

architecture Cookbook__reg_cam_cell__part1_behav of Cookbook__reg_cam_cell__part1 is
begin
    po0 <= ( lo64 );
end Cookbook__reg_cam_cell__part1_behav;
