--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1815 is 
  Port (
    lo9061: in std_logic;
    po446: inout std_logic
  );
end Other__carpat__part1815;

architecture Other__carpat__part1815_behav of Other__carpat__part1815 is
begin
    po446 <= ( lo9061 );
end Other__carpat__part1815_behav;
