--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part51 is 
  Port (
    lo156: in std_logic;
    n1078: inout std_logic
  );
end ISCAS__s13207__part51;

architecture ISCAS__s13207__part51_behav of ISCAS__s13207__part51 is
begin
    n1078 <= ( lo156 );
end ISCAS__s13207__part51_behav;
