--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part206 is 
  Port (
    pi1266: in std_logic;
    n33249_1: inout std_logic
  );
end Other__carpat__part206;

architecture Other__carpat__part206_behav of Other__carpat__part206 is
begin
    n33249_1 <= ( pi1266 );
end Other__carpat__part206_behav;
