--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_22__part8 is 
  Port (
    lo49: in std_logic;
    po19: inout std_logic
  );
end Cookbook__gearbox_20_22__part8;

architecture Cookbook__gearbox_20_22__part8_behav of Cookbook__gearbox_20_22__part8 is
begin
    po19 <= ( lo49 );
end Cookbook__gearbox_20_22__part8_behav;
