--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2341 is 
  Port (
    lo3753,lo3741,lo3717,lo3705,lo3729,lo3681,lo3669,lo3693,lo3645,lo3633,lo3657: in std_logic;
    n19064: inout std_logic
  );
end Cookbook__fec_check__part2341;

architecture Cookbook__fec_check__part2341_behav of Cookbook__fec_check__part2341 is
signal n13452,n13453,n13454,n13455,n13456,n13457,n13458,n13459,n13460: std_logic;
begin
    n13452 <= not (( not lo3753 and not lo3741 ));
    n13453 <= not (( not lo3717 and not lo3705 ));
    n13454 <= not (( not lo3729 and not n13453 ));
    n13455 <= not (( not n13452 and not n13454 ));
    n13456 <= not (( not lo3681 and not lo3669 ));
    n13457 <= not (( not lo3693 and not n13456 ));
    n13458 <= not (( not lo3645 and not lo3633 ));
    n13459 <= not (( not lo3657 and not n13458 ));
    n13460 <= not (( not n13457 and not n13459 ));
    n19064 <= not (( not n13455 and not n13460 ));
end Cookbook__fec_check__part2341_behav;
