--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part20 is 
  Port (
    pi020: in std_logic;
    n9749_1: inout std_logic
  );
end Other__desperf__part20;

architecture Other__desperf__part20_behav of Other__desperf__part20 is
begin
    n9749_1 <= ( pi020 );
end Other__desperf__part20_behav;
