--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part673 is 
  Port (
    lo5194: in std_logic;
    n24989: inout std_logic
  );
end Other__carpat__part673;

architecture Other__carpat__part673_behav of Other__carpat__part673 is
begin
    n24989 <= ( lo5194 );
end Other__carpat__part673_behav;
