--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1318 is 
  Port (
    lo4687: in std_logic;
    n18924: inout std_logic
  );
end Other__sudoku_check__part1318;

architecture Other__sudoku_check__part1318_behav of Other__sudoku_check__part1318 is
begin
    n18924 <= ( lo4687 );
end Other__sudoku_check__part1318_behav;
