--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1864 is 
  Port (
    lo9137: in std_logic;
    po501: inout std_logic
  );
end Other__carpat__part1864;

architecture Other__carpat__part1864_behav of Other__carpat__part1864 is
begin
    po501 <= ( lo9137 );
end Other__carpat__part1864_behav;
