--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2436 is 
  Port (
    lo5376: in std_logic;
    n31476_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2436;

architecture Other__ucsb_152_tap_fir__part2436_behav of Other__ucsb_152_tap_fir__part2436 is
begin
    n31476_1 <= ( lo5376 );
end Other__ucsb_152_tap_fir__part2436_behav;
