--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part36 is 
  Port (
    lo35: in std_logic;
    po35: inout std_logic
  );
end Other__idxlat10n_m12__part36;

architecture Other__idxlat10n_m12__part36_behav of Other__idxlat10n_m12__part36 is
begin
    po35 <= ( lo35 );
end Other__idxlat10n_m12__part36_behav;
