--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1216 is 
  Port (
    lo7632: in std_logic;
    n42049_1: inout std_logic
  );
end Other__carpat__part1216;

architecture Other__carpat__part1216_behav of Other__carpat__part1216 is
begin
    n42049_1 <= ( lo7632 );
end Other__carpat__part1216_behav;
