--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part729 is 
  Port (
    lo5456: in std_logic;
    n25764: inout std_logic
  );
end Other__carpat__part729;

architecture Other__carpat__part729_behav of Other__carpat__part729 is
begin
    n25764 <= ( lo5456 );
end Other__carpat__part729_behav;
