--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part338 is 
  Port (
    lo0407: in std_logic;
    n2334: inout std_logic
  );
end Cookbook__fec_check__part338;

architecture Cookbook__fec_check__part338_behav of Cookbook__fec_check__part338 is
begin
    n2334 <= ( lo0407 );
end Cookbook__fec_check__part338_behav;
