--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part90 is 
  Port (
    lo0628: in std_logic;
    n3074: inout std_logic
  );
end IWLS93__s38417__part90;

architecture IWLS93__s38417__part90_behav of IWLS93__s38417__part90 is
begin
    n3074 <= ( lo0628 );
end IWLS93__s38417__part90_behav;
