--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part433 is 
  Port (
    lo3025: in std_logic;
    n15605: inout std_logic
  );
end IWLS2005__des_perf__part433;

architecture IWLS2005__des_perf__part433_behav of IWLS2005__des_perf__part433 is
begin
    n15605 <= ( lo3025 );
end IWLS2005__des_perf__part433_behav;
