--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part590 is 
  Port (
    lo0659: in std_logic;
    n3594: inout std_logic
  );
end Cookbook__fec_check__part590;

architecture Cookbook__fec_check__part590_behav of Cookbook__fec_check__part590 is
begin
    n3594 <= ( lo0659 );
end Cookbook__fec_check__part590_behav;
