--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part943 is 
  Port (
    lo10524: in std_logic;
    n69161_1: inout std_logic
  );
end Other__ray__part943;

architecture Other__ray__part943_behav of Other__ray__part943 is
begin
    n69161_1 <= ( lo10524 );
end Other__ray__part943_behav;
