--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1220 is 
  Port (
    lo1289: in std_logic;
    n6744: inout std_logic
  );
end Cookbook__fec_check__part1220;

architecture Cookbook__fec_check__part1220_behav of Cookbook__fec_check__part1220 is
begin
    n6744 <= ( lo1289 );
end Cookbook__fec_check__part1220_behav;
