--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part329 is 
  Port (
    lo1196: in std_logic;
    n5795: inout std_logic
  );
end IWLS2005__des_perf__part329;

architecture IWLS2005__des_perf__part329_behav of IWLS2005__des_perf__part329 is
begin
    n5795 <= ( lo1196 );
end IWLS2005__des_perf__part329_behav;
