--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part0 is 
  Port (
    pi00: in std_logic;
    n241_1: inout std_logic
  );
end Cookbook__font_rom__part0;

architecture Cookbook__font_rom__part0_behav of Cookbook__font_rom__part0 is
begin
    n241_1 <= ( pi00 );
end Cookbook__font_rom__part0_behav;
