--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part74 is 
  Port (
    pi1169: in std_logic;
    n71966_1: inout std_logic
  );
end Other__ray__part74;

architecture Other__ray__part74_behav of Other__ray__part74 is
begin
    n71966_1 <= ( pi1169 );
end Other__ray__part74_behav;
