--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1553 is 
  Port (
    lo6141: in std_logic;
    n30845_1: inout std_logic
  );
end IWLS2005__des_perf__part1553;

architecture IWLS2005__des_perf__part1553_behav of IWLS2005__des_perf__part1553 is
begin
    n30845_1 <= ( lo6141 );
end IWLS2005__des_perf__part1553_behav;
