--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part240 is 
  Port (
    lo0309: in std_logic;
    n1844: inout std_logic
  );
end Cookbook__fec_check__part240;

architecture Cookbook__fec_check__part240_behav of Cookbook__fec_check__part240 is
begin
    n1844 <= ( lo0309 );
end Cookbook__fec_check__part240_behav;
