--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1179 is 
  Port (
    lo4548: in std_logic;
    n18229: inout std_logic
  );
end Other__sudoku_check__part1179;

architecture Other__sudoku_check__part1179_behav of Other__sudoku_check__part1179 is
begin
    n18229 <= ( lo4548 );
end Other__sudoku_check__part1179_behav;
