--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1502 is 
  Port (
    lo5617,lo5618,lo5619,lo5620: in std_logic;
    n27129_1,n28664,n28669_1,n28674_1,n28679,n28684_1,n28689,n28694_1,n28699_1: inout std_logic
  );
end Other__sudoku_check__part1502;

architecture Other__sudoku_check__part1502_behav of Other__sudoku_check__part1502 is
begin
    n27129_1 <= ( lo5617 and not lo5618 and not lo5619 and not lo5620 );
    n28664 <= ( lo5617 and not lo5618 and not lo5619 and lo5620 );
    n28669_1 <= ( not lo5617 and not lo5618 and not lo5619 and lo5620 );
    n28674_1 <= ( lo5617 and lo5618 and lo5619 and not lo5620 );
    n28679 <= ( not lo5617 and lo5618 and lo5619 and not lo5620 );
    n28684_1 <= ( lo5617 and not lo5618 and lo5619 and not lo5620 );
    n28689 <= ( not lo5617 and not lo5618 and lo5619 and not lo5620 );
    n28694_1 <= ( lo5617 and lo5618 and not lo5619 and not lo5620 );
    n28699_1 <= ( not lo5617 and lo5618 and not lo5619 and not lo5620 );
end Other__sudoku_check__part1502_behav;
