--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1000 is 
  Port (
    lo10697: in std_logic;
    n71596_1: inout std_logic
  );
end Other__ray__part1000;

architecture Other__ray__part1000_behav of Other__ray__part1000 is
begin
    n71596_1 <= ( lo10697 );
end Other__ray__part1000_behav;
