--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part29 is 
  Port (
    lo0098: in std_logic;
    n789: inout std_logic
  );
end Cookbook__fec_check__part29;

architecture Cookbook__fec_check__part29_behav of Cookbook__fec_check__part29 is
begin
    n789 <= ( lo0098 );
end Cookbook__fec_check__part29_behav;
