--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part991 is 
  Port (
    lo10688: in std_logic;
    n71551_1: inout std_logic
  );
end Other__ray__part991;

architecture Other__ray__part991_behav of Other__ray__part991 is
begin
    n71551_1 <= ( lo10688 );
end Other__ray__part991_behav;
