--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part233 is 
  Port (
    lo0582: in std_logic;
    n7391: inout std_logic
  );
end Other__ucsb_152_tap_fir__part233;

architecture Other__ucsb_152_tap_fir__part233_behav of Other__ucsb_152_tap_fir__part233 is
begin
    n7391 <= ( lo0582 );
end Other__ucsb_152_tap_fir__part233_behav;
