--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part127 is 
  Port (
    lo0247: in std_logic;
    n5696: inout std_logic
  );
end Other__ucsb_152_tap_fir__part127;

architecture Other__ucsb_152_tap_fir__part127_behav of Other__ucsb_152_tap_fir__part127 is
begin
    n5696 <= ( lo0247 );
end Other__ucsb_152_tap_fir__part127_behav;
