--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part699 is 
  Port (
    lo4379: in std_logic;
    n21965: inout std_logic
  );
end IWLS2005__des_perf__part699;

architecture IWLS2005__des_perf__part699_behav of IWLS2005__des_perf__part699 is
begin
    n21965 <= ( lo4379 );
end IWLS2005__des_perf__part699_behav;
