--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1769 is 
  Port (
    lo1838: in std_logic;
    n9489: inout std_logic
  );
end Cookbook__fec_check__part1769;

architecture Cookbook__fec_check__part1769_behav of Cookbook__fec_check__part1769 is
begin
    n9489 <= ( lo1838 );
end Cookbook__fec_check__part1769_behav;
