--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part4 is 
  Port (
    lo009: in std_logic;
    n747: inout std_logic
  );
end Cookbook__gearbox_67_40__part4;

architecture Cookbook__gearbox_67_40__part4_behav of Cookbook__gearbox_67_40__part4 is
begin
    n747 <= ( lo009 );
end Cookbook__gearbox_67_40__part4_behav;
