--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part136 is 
  Port (
    lo230: in std_logic;
    po05: inout std_logic
  );
end Cookbook__gearbox_40_67__part136;

architecture Cookbook__gearbox_40_67__part136_behav of Cookbook__gearbox_40_67__part136 is
begin
    po05 <= ( lo230 );
end Cookbook__gearbox_40_67__part136_behav;
