--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2332 is 
  Port (
    lo5171: in std_logic;
    n30361: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2332;

architecture Other__ucsb_152_tap_fir__part2332_behav of Other__ucsb_152_tap_fir__part2332 is
begin
    n30361 <= ( lo5171 );
end Other__ucsb_152_tap_fir__part2332_behav;
