--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part703 is 
  Port (
    lo0772: in std_logic;
    n4159: inout std_logic
  );
end Cookbook__fec_check__part703;

architecture Cookbook__fec_check__part703_behav of Cookbook__fec_check__part703 is
begin
    n4159 <= ( lo0772 );
end Cookbook__fec_check__part703_behav;
