--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part702 is 
  Port (
    lo4384: in std_logic;
    n22100: inout std_logic
  );
end IWLS2005__des_perf__part702;

architecture IWLS2005__des_perf__part702_behav of IWLS2005__des_perf__part702 is
begin
    n22100 <= ( lo4384 );
end IWLS2005__des_perf__part702_behav;
