--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part247 is 
  Port (
    lo1212: in std_logic;
    n8120_1: inout std_logic
  );
end Other__fp_operators__part247;

architecture Other__fp_operators__part247_behav of Other__fp_operators__part247 is
begin
    n8120_1 <= ( lo1212 );
end Other__fp_operators__part247_behav;
