--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2090 is 
  Port (
    lo2159: in std_logic;
    n11094: inout std_logic
  );
end Cookbook__fec_check__part2090;

architecture Cookbook__fec_check__part2090_behav of Cookbook__fec_check__part2090 is
begin
    n11094 <= ( lo2159 );
end Cookbook__fec_check__part2090_behav;
