--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part296 is 
  Port (
    lo1430: in std_logic;
    n10115_1: inout std_logic
  );
end Other__fp_operators__part296;

architecture Other__fp_operators__part296_behav of Other__fp_operators__part296 is
begin
    n10115_1 <= ( lo1430 );
end Other__fp_operators__part296_behav;
