--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2325 is 
  Port (
    lo5164: in std_logic;
    n30326: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2325;

architecture Other__ucsb_152_tap_fir__part2325_behav of Other__ucsb_152_tap_fir__part2325 is
begin
    n30326 <= ( lo5164 );
end Other__ucsb_152_tap_fir__part2325_behav;
