--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1856 is 
  Port (
    lo9129: in std_logic;
    po493: inout std_logic
  );
end Other__carpat__part1856;

architecture Other__carpat__part1856_behav of Other__carpat__part1856 is
begin
    po493 <= ( lo9129 );
end Other__carpat__part1856_behav;
