--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part933 is 
  Port (
    lo10402: in std_logic;
    po0965: inout std_logic
  );
end Other__ray__part933;

architecture Other__ray__part933_behav of Other__ray__part933 is
begin
    po0965 <= ( lo10402 );
end Other__ray__part933_behav;
