--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part424 is 
  Port (
    lo3073: in std_logic;
    n9159: inout std_logic
  );
end Other__sudoku_check__part424;

architecture Other__sudoku_check__part424_behav of Other__sudoku_check__part424 is
begin
    n9159 <= ( lo3073 );
end Other__sudoku_check__part424_behav;
