--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part98 is 
  Port (
    lo192: in std_logic;
    po43: inout std_logic
  );
end Cookbook__gearbox_40_67__part98;

architecture Cookbook__gearbox_40_67__part98_behav of Cookbook__gearbox_40_67__part98 is
begin
    po43 <= ( lo192 );
end Cookbook__gearbox_40_67__part98_behav;
