--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part567 is 
  Port (
    lo3216: in std_logic;
    n10589: inout std_logic
  );
end Other__sudoku_check__part567;

architecture Other__sudoku_check__part567_behav of Other__sudoku_check__part567 is
begin
    n10589 <= ( lo3216 );
end Other__sudoku_check__part567_behav;
