--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part266 is 
  Port (
    lo1327: in std_logic;
    n9225_1: inout std_logic
  );
end Other__fp_operators__part266;

architecture Other__fp_operators__part266_behav of Other__fp_operators__part266 is
begin
    n9225_1 <= ( lo1327 );
end Other__fp_operators__part266_behav;
