--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part878 is 
  Port (
    lo0947: in std_logic;
    n5034: inout std_logic
  );
end Cookbook__fec_check__part878;

architecture Cookbook__fec_check__part878_behav of Cookbook__fec_check__part878 is
begin
    n5034 <= ( lo0947 );
end Cookbook__fec_check__part878_behav;
