--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part528 is 
  Port (
    lo1965: in std_logic;
    n10934_1: inout std_logic
  );
end Cookbook__ucrypt__part528;

architecture Cookbook__ucrypt__part528_behav of Cookbook__ucrypt__part528 is
begin
    n10934_1 <= ( lo1965 );
end Cookbook__ucrypt__part528_behav;
