--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1060 is 
  Port (
    lo2481: in std_logic;
    n16996: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1060;

architecture Other__ucsb_152_tap_fir__part1060_behav of Other__ucsb_152_tap_fir__part1060 is
begin
    n16996 <= ( lo2481 );
end Other__ucsb_152_tap_fir__part1060_behav;
