--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1401 is 
  Port (
    lo4770: in std_logic;
    n19339_1: inout std_logic
  );
end Other__sudoku_check__part1401;

architecture Other__sudoku_check__part1401_behav of Other__sudoku_check__part1401 is
begin
    n19339_1 <= ( lo4770 );
end Other__sudoku_check__part1401_behav;
