--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part683 is 
  Port (
    lo5206: in std_logic;
    n25039: inout std_logic
  );
end Other__carpat__part683;

architecture Other__carpat__part683_behav of Other__carpat__part683 is
begin
    n25039 <= ( lo5206 );
end Other__carpat__part683_behav;
