--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part635 is 
  Port (
    lo4281: in std_logic;
    n21550: inout std_logic
  );
end IWLS2005__des_perf__part635;

architecture IWLS2005__des_perf__part635_behav of IWLS2005__des_perf__part635 is
begin
    n21550 <= ( lo4281 );
end IWLS2005__des_perf__part635_behav;
