--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part33 is 
  Port (
    lo019: in std_logic;
    po010: inout std_logic
  );
end Cookbook__lc_mult_signed__part33;

architecture Cookbook__lc_mult_signed__part33_behav of Cookbook__lc_mult_signed__part33 is
begin
    po010 <= ( lo019 );
end Cookbook__lc_mult_signed__part33_behav;
