--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_mux__part4 is 
  Port (
    lo05: in std_logic;
    n49_1: inout std_logic
  );
end Cookbook__clock_mux__part4;

architecture Cookbook__clock_mux__part4_behav of Cookbook__clock_mux__part4 is
begin
    n49_1 <= ( lo05 );
end Cookbook__clock_mux__part4_behav;
