--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part225 is 
  Port (
    lo03286: in std_logic;
    n34126: inout std_logic
  );
end Other__ray__part225;

architecture Other__ray__part225_behav of Other__ray__part225 is
begin
    n34126 <= ( lo03286 );
end Other__ray__part225_behav;
