--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part5 is 
  Port (
    lo003: in std_logic;
    n308,n1098: inout std_logic
  );
end ISCAS__s13207__part5;

architecture ISCAS__s13207__part5_behav of ISCAS__s13207__part5 is
begin
    n308 <= ( lo003 );
    n1098 <= ( lo003 );
end ISCAS__s13207__part5_behav;
