--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1868 is 
  Port (
    lo1937: in std_logic;
    n9984: inout std_logic
  );
end Cookbook__fec_check__part1868;

architecture Cookbook__fec_check__part1868_behav of Cookbook__fec_check__part1868 is
begin
    n9984 <= ( lo1937 );
end Cookbook__fec_check__part1868_behav;
