--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1246 is 
  Port (
    lo7685: in std_logic;
    n42414_1: inout std_logic
  );
end Other__carpat__part1246;

architecture Other__carpat__part1246_behav of Other__carpat__part1246 is
begin
    n42414_1 <= ( lo7685 );
end Other__carpat__part1246_behav;
