--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fifo__part17 is 
  Port (
    lo077: in std_logic;
    po22: inout std_logic
  );
end Cookbook__fifo__part17;

architecture Cookbook__fifo__part17_behav of Cookbook__fifo__part17 is
begin
    po22 <= ( lo077 );
end Cookbook__fifo__part17_behav;
