--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part765 is 
  Port (
    lo0834: in std_logic;
    n4469: inout std_logic
  );
end Cookbook__fec_check__part765;

architecture Cookbook__fec_check__part765_behav of Cookbook__fec_check__part765 is
begin
    n4469 <= ( lo0834 );
end Cookbook__fec_check__part765_behav;
