--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part31 is 
  Port (
    pi1123: in std_logic;
    n51326_1: inout std_logic
  );
end Other__ray__part31;

architecture Other__ray__part31_behav of Other__ray__part31 is
begin
    n51326_1 <= ( pi1123 );
end Other__ray__part31_behav;
