--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2234 is 
  Port (
    lo2303: in std_logic;
    n11814: inout std_logic
  );
end Cookbook__fec_check__part2234;

architecture Cookbook__fec_check__part2234_behav of Cookbook__fec_check__part2234 is
begin
    n11814 <= ( lo2303 );
end Cookbook__fec_check__part2234_behav;
