--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part90 is 
  Port (
    lo0305: in std_logic;
    n2784: inout std_logic
  );
end Cookbook__ucrypt__part90;

architecture Cookbook__ucrypt__part90_behav of Cookbook__ucrypt__part90 is
begin
    n2784 <= ( lo0305 );
end Cookbook__ucrypt__part90_behav;
