--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part170 is 
  Port (
    lo1363: in std_logic;
    n7774: inout std_logic
  );
end ISCAS__s38417__part170;

architecture ISCAS__s38417__part170_behav of ISCAS__s38417__part170 is
begin
    n7774 <= ( not lo1363 );
end ISCAS__s38417__part170_behav;
