--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part492 is 
  Port (
    lo4044: in std_logic;
    n20290: inout std_logic
  );
end IWLS2005__des_perf__part492;

architecture IWLS2005__des_perf__part492_behav of IWLS2005__des_perf__part492 is
begin
    n20290 <= ( lo4044 );
end IWLS2005__des_perf__part492_behav;
