--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part138 is 
  Port (
    lo0465: in std_logic;
    n3584: inout std_logic
  );
end Cookbook__ucrypt__part138;

architecture Cookbook__ucrypt__part138_behav of Cookbook__ucrypt__part138 is
begin
    n3584 <= ( lo0465 );
end Cookbook__ucrypt__part138_behav;
