--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1268 is 
  Port (
    lo4637: in std_logic;
    n18674: inout std_logic
  );
end Other__sudoku_check__part1268;

architecture Other__sudoku_check__part1268_behav of Other__sudoku_check__part1268 is
begin
    n18674 <= ( lo4637 );
end Other__sudoku_check__part1268_behav;
