--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2944 is 
  Port (
    lo8257: in std_logic;
    n41545_1: inout std_logic
  );
end IWLS2005__des_perf__part2944;

architecture IWLS2005__des_perf__part2944_behav of IWLS2005__des_perf__part2944 is
begin
    n41545_1 <= ( lo8257 );
end IWLS2005__des_perf__part2944_behav;
