--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part16 is 
  Port (
    lo15: in std_logic;
    po15: inout std_logic
  );
end Other__idxlat10n_m12__part16;

architecture Other__idxlat10n_m12__part16_behav of Other__idxlat10n_m12__part16 is
begin
    po15 <= ( lo15 );
end Other__idxlat10n_m12__part16_behav;
