--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part806 is 
  Port (
    lo6374: in std_logic;
    po534: inout std_logic
  );
end Other__carpat__part806;

architecture Other__carpat__part806_behav of Other__carpat__part806 is
begin
    po534 <= ( lo6374 );
end Other__carpat__part806_behav;
