--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2129 is 
  Port (
    lo2198: in std_logic;
    n11289: inout std_logic
  );
end Cookbook__fec_check__part2129;

architecture Cookbook__fec_check__part2129_behav of Cookbook__fec_check__part2129 is
begin
    n11289 <= ( lo2198 );
end Cookbook__fec_check__part2129_behav;
