--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1025 is 
  Port (
    lo4394: in std_logic;
    n17459: inout std_logic
  );
end Other__sudoku_check__part1025;

architecture Other__sudoku_check__part1025_behav of Other__sudoku_check__part1025 is
begin
    n17459 <= ( lo4394 );
end Other__sudoku_check__part1025_behav;
