--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1772 is 
  Port (
    lo6584: in std_logic;
    n33025_1: inout std_logic
  );
end IWLS2005__des_perf__part1772;

architecture IWLS2005__des_perf__part1772_behav of IWLS2005__des_perf__part1772 is
begin
    n33025_1 <= ( lo6584 );
end IWLS2005__des_perf__part1772_behav;
