--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part13 is 
  Port (
    pi13: in std_logic;
    n166: inout std_logic
  );
end Cookbook__approx_fp_div__part13;

architecture Cookbook__approx_fp_div__part13_behav of Cookbook__approx_fp_div__part13 is
begin
    n166 <= ( pi13 );
end Cookbook__approx_fp_div__part13_behav;
