--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part232 is 
  Port (
    lo336: in std_logic;
    n1192: inout std_logic
  );
end Other__fpu__part232;

architecture Other__fpu__part232_behav of Other__fpu__part232 is
begin
    n1192 <= ( lo336 );
end Other__fpu__part232_behav;
