--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part6 is 
  Port (
    lo05: in std_logic;
    po03: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part6;

architecture Cookbook__x4_decoder_8b10b__part6_behav of Cookbook__x4_decoder_8b10b__part6 is
begin
    po03 <= ( lo05 );
end Cookbook__x4_decoder_8b10b__part6_behav;
