--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part101 is 
  Port (
    lo087: in std_logic;
    po179: inout std_logic
  );
end Cookbook__lc_mult_signed__part101;

architecture Cookbook__lc_mult_signed__part101_behav of Cookbook__lc_mult_signed__part101 is
begin
    po179 <= ( lo087 );
end Cookbook__lc_mult_signed__part101_behav;
