--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s953__part5 is 
  Port (
    lo10: in std_logic;
    po07: inout std_logic
  );
end ISCAS__s953__part5;

architecture ISCAS__s953__part5_behav of ISCAS__s953__part5 is
begin
    po07 <= ( lo10 );
end ISCAS__s953__part5_behav;
