--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1955 is 
  Port (
    lo2024: in std_logic;
    n10419: inout std_logic
  );
end Cookbook__fec_check__part1955;

architecture Cookbook__fec_check__part1955_behav of Cookbook__fec_check__part1955 is
begin
    n10419 <= ( lo2024 );
end Cookbook__fec_check__part1955_behav;
