--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1770 is 
  Port (
    lo4008: in std_logic;
    n24551: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1770;

architecture Other__ucsb_152_tap_fir__part1770_behav of Other__ucsb_152_tap_fir__part1770 is
begin
    n24551 <= ( lo4008 );
end Other__ucsb_152_tap_fir__part1770_behav;
