--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part585 is 
  Port (
    lo3848: in std_logic;
    n17164: inout std_logic
  );
end Other__carpat__part585;

architecture Other__carpat__part585_behav of Other__carpat__part585 is
begin
    n17164 <= ( lo3848 );
end Other__carpat__part585_behav;
