--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1543 is 
  Port (
    lo6131: in std_logic;
    n30780_1: inout std_logic
  );
end IWLS2005__des_perf__part1543;

architecture IWLS2005__des_perf__part1543_behav of IWLS2005__des_perf__part1543 is
begin
    n30780_1 <= ( lo6131 );
end IWLS2005__des_perf__part1543_behav;
