--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part15 is 
  Port (
    pi772,pi773: in std_logic;
    po252: inout std_logic
  );
end Other__fp_operators__part15;

architecture Other__fp_operators__part15_behav of Other__fp_operators__part15 is
begin
    po252 <= ( not pi772 and pi773 )
      or ( pi772 and not pi773 );
end Other__fp_operators__part15_behav;
