--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2327 is 
  Port (
    lo5166: in std_logic;
    n30336: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2327;

architecture Other__ucsb_152_tap_fir__part2327_behav of Other__ucsb_152_tap_fir__part2327 is
begin
    n30336 <= ( lo5166 );
end Other__ucsb_152_tap_fir__part2327_behav;
