--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1534 is 
  Port (
    lo3476: in std_logic;
    n21966: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1534;

architecture Other__ucsb_152_tap_fir__part1534_behav of Other__ucsb_152_tap_fir__part1534 is
begin
    n21966 <= ( lo3476 );
end Other__ucsb_152_tap_fir__part1534_behav;
