--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__eightbyeight_sad__part16 is 
  Port (
    lo323: in std_logic;
    po12: inout std_logic
  );
end Cookbook__eightbyeight_sad__part16;

architecture Cookbook__eightbyeight_sad__part16_behav of Cookbook__eightbyeight_sad__part16 is
begin
    po12 <= ( lo323 );
end Cookbook__eightbyeight_sad__part16_behav;
