--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part494 is 
  Port (
    lo1829: in std_logic;
    n10404_1: inout std_logic
  );
end Cookbook__ucrypt__part494;

architecture Cookbook__ucrypt__part494_behav of Cookbook__ucrypt__part494 is
begin
    n10404_1 <= ( lo1829 );
end Cookbook__ucrypt__part494_behav;
