--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part48 is 
  Port (
    lo017: in std_logic;
    n569: inout std_logic
  );
end Cookbook__gearbox_40_67__part48;

architecture Cookbook__gearbox_40_67__part48_behav of Cookbook__gearbox_40_67__part48 is
begin
    n569 <= ( lo017 );
end Cookbook__gearbox_40_67__part48_behav;
