--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part134 is 
  Port (
    pi0544: in std_logic;
    n43266_1: inout std_logic
  );
end Other__radar__part134;

architecture Other__radar__part134_behav of Other__radar__part134 is
begin
    n43266_1 <= ( pi0544 );
end Other__radar__part134_behav;
