--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1215 is 
  Port (
    lo2807: in std_logic;
    n18561: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1215;

architecture Other__ucsb_152_tap_fir__part1215_behav of Other__ucsb_152_tap_fir__part1215 is
begin
    n18561 <= ( lo2807 );
end Other__ucsb_152_tap_fir__part1215_behav;
