--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_20__part4 is 
  Port (
    lo69: in std_logic;
    po16: inout std_logic
  );
end Cookbook__gearbox_67_20__part4;

architecture Cookbook__gearbox_67_20__part4_behav of Cookbook__gearbox_67_20__part4 is
begin
    po16 <= ( lo69 );
end Cookbook__gearbox_67_20__part4_behav;
