--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part607 is 
  Port (
    lo06088: in std_logic;
    n38386: inout std_logic
  );
end Other__ray__part607;

architecture Other__ray__part607_behav of Other__ray__part607 is
begin
    n38386 <= ( lo06088 );
end Other__ray__part607_behav;
