--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1695 is 
  Port (
    lo1764: in std_logic;
    n9119: inout std_logic
  );
end Cookbook__fec_check__part1695;

architecture Cookbook__fec_check__part1695_behav of Cookbook__fec_check__part1695 is
begin
    n9119 <= ( lo1764 );
end Cookbook__fec_check__part1695_behav;
