--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1238 is 
  Port (
    lo7677: in std_logic;
    n42374_1: inout std_logic
  );
end Other__carpat__part1238;

architecture Other__carpat__part1238_behav of Other__carpat__part1238 is
begin
    n42374_1 <= ( lo7677 );
end Other__carpat__part1238_behav;
