--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part110 is 
  Port (
    lo184868: in std_logic;
    n924346: inout std_logic
  );
end IWLS2005__leon3__part110;

architecture IWLS2005__leon3__part110_behav of IWLS2005__leon3__part110 is
begin
    n924346 <= ( lo184868 );
end IWLS2005__leon3__part110_behav;
