--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s967__part15 is 
  Port (
    lo20: in std_logic;
    po14: inout std_logic
  );
end ISCAS__s967__part15;

architecture ISCAS__s967__part15_behav of ISCAS__s967__part15 is
begin
    po14 <= ( lo20 );
end ISCAS__s967__part15_behav;
