--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2271 is 
  Port (
    lo2371: in std_logic;
    n12154: inout std_logic
  );
end Cookbook__fec_check__part2271;

architecture Cookbook__fec_check__part2271_behav of Cookbook__fec_check__part2271 is
begin
    n12154 <= ( lo2371 );
end Cookbook__fec_check__part2271_behav;
