--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2003 is 
  Port (
    lo2072: in std_logic;
    n10659: inout std_logic
  );
end Cookbook__fec_check__part2003;

architecture Cookbook__fec_check__part2003_behav of Cookbook__fec_check__part2003 is
begin
    n10659 <= ( lo2072 );
end Cookbook__fec_check__part2003_behav;
