--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part116 is 
  Port (
    lo365: in std_logic;
    po027: inout std_logic
  );
end IWLS2005__aes_core__part116;

architecture IWLS2005__aes_core__part116_behav of IWLS2005__aes_core__part116 is
begin
    po027 <= ( lo365 );
end IWLS2005__aes_core__part116_behav;
