--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part492 is 
  Port (
    lo0561: in std_logic;
    n3104: inout std_logic
  );
end Cookbook__fec_check__part492;

architecture Cookbook__fec_check__part492_behav of Cookbook__fec_check__part492 is
begin
    n3104 <= ( lo0561 );
end Cookbook__fec_check__part492_behav;
