--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part470 is 
  Port (
    lo3119: in std_logic;
    n9619: inout std_logic
  );
end Other__sudoku_check__part470;

architecture Other__sudoku_check__part470_behav of Other__sudoku_check__part470 is
begin
    n9619 <= ( lo3119 );
end Other__sudoku_check__part470_behav;
