--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1346 is 
  Port (
    lo5709: in std_logic;
    n28675_1: inout std_logic
  );
end IWLS2005__des_perf__part1346;

architecture IWLS2005__des_perf__part1346_behav of IWLS2005__des_perf__part1346 is
begin
    n28675_1 <= ( lo5709 );
end IWLS2005__des_perf__part1346_behav;
