--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1446 is 
  Port (
    lo1515: in std_logic;
    n7874: inout std_logic
  );
end Cookbook__fec_check__part1446;

architecture Cookbook__fec_check__part1446_behav of Cookbook__fec_check__part1446 is
begin
    n7874 <= ( lo1515 );
end Cookbook__fec_check__part1446_behav;
