--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part34 is 
  Port (
    lo33: in std_logic;
    po33: inout std_logic
  );
end Other__idxlat00n_m12__part34;

architecture Other__idxlat00n_m12__part34_behav of Other__idxlat00n_m12__part34 is
begin
    po33 <= ( lo33 );
end Other__idxlat00n_m12__part34_behav;
