--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1097 is 
  Port (
    lo4466: in std_logic;
    n17819: inout std_logic
  );
end Other__sudoku_check__part1097;

architecture Other__sudoku_check__part1097_behav of Other__sudoku_check__part1097 is
begin
    n17819 <= ( lo4466 );
end Other__sudoku_check__part1097_behav;
