--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part85 is 
  Port (
    lo1759: in std_logic;
    po073: inout std_logic
  );
end Other__mem__part85;

architecture Other__mem__part85_behav of Other__mem__part85 is
begin
    po073 <= ( lo1759 );
end Other__mem__part85_behav;
