--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1507 is 
  Port (
    lo1576: in std_logic;
    n8179: inout std_logic
  );
end Cookbook__fec_check__part1507;

architecture Cookbook__fec_check__part1507_behav of Cookbook__fec_check__part1507 is
begin
    n8179 <= ( lo1576 );
end Cookbook__fec_check__part1507_behav;
