--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part128 is 
  Port (
    lo254: in std_logic;
    po084: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part128;

architecture Cookbook__soft_ecc_ram_64bit__part128_behav of Cookbook__soft_ecc_ram_64bit__part128 is
begin
    po084 <= ( lo254 );
end Cookbook__soft_ecc_ram_64bit__part128_behav;
