--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1213 is 
  Port (
    lo1282: in std_logic;
    n6709: inout std_logic
  );
end Cookbook__fec_check__part1213;

architecture Cookbook__fec_check__part1213_behav of Cookbook__fec_check__part1213 is
begin
    n6709 <= ( lo1282 );
end Cookbook__fec_check__part1213_behav;
