--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1623 is 
  Port (
    lo3670: in std_logic;
    n22841: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1623;

architecture Other__ucsb_152_tap_fir__part1623_behav of Other__ucsb_152_tap_fir__part1623 is
begin
    n22841 <= ( lo3670 );
end Other__ucsb_152_tap_fir__part1623_behav;
