--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part823 is 
  Port (
    lo06582: in std_logic;
    n49246_1: inout std_logic
  );
end Other__ray__part823;

architecture Other__ray__part823_behav of Other__ray__part823 is
begin
    n49246_1 <= ( lo06582 );
end Other__ray__part823_behav;
