--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1390 is 
  Port (
    lo4759: in std_logic;
    n19284_1: inout std_logic
  );
end Other__sudoku_check__part1390;

architecture Other__sudoku_check__part1390_behav of Other__sudoku_check__part1390 is
begin
    n19284_1 <= ( lo4759 );
end Other__sudoku_check__part1390_behav;
