--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part16 is 
  Port (
    lo015: in std_logic;
    n230: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part16;

architecture Cookbook__approx_fp_invsqrt__part16_behav of Cookbook__approx_fp_invsqrt__part16 is
begin
    n230 <= ( lo015 );
end Cookbook__approx_fp_invsqrt__part16_behav;
