--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part89 is 
  Port (
    pi089: in std_logic;
    n2117: inout std_logic
  );
end Other__fpu__part89;

architecture Other__fpu__part89_behav of Other__fpu__part89 is
begin
    n2117 <= ( pi089 );
end Other__fpu__part89_behav;
