--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2136 is 
  Port (
    lo2205: in std_logic;
    n11324: inout std_logic
  );
end Cookbook__fec_check__part2136;

architecture Cookbook__fec_check__part2136_behav of Cookbook__fec_check__part2136 is
begin
    n11324 <= ( lo2205 );
end Cookbook__fec_check__part2136_behav;
