--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part78 is 
  Port (
    lo0659: in std_logic;
    n4264: inout std_logic
  );
end ISCAS__s38417__part78;

architecture ISCAS__s38417__part78_behav of ISCAS__s38417__part78 is
begin
    n4264 <= ( not lo0659 );
end ISCAS__s38417__part78_behav;
