--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part67 is 
  Port (
    lo66: in std_logic;
    po66: inout std_logic
  );
end Other__idxlat03n_m12__part67;

architecture Other__idxlat03n_m12__part67_behav of Other__idxlat03n_m12__part67 is
begin
    po66 <= ( lo66 );
end Other__idxlat03n_m12__part67_behav;
