--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1408 is 
  Port (
    lo5852: in std_logic;
    n29130_1: inout std_logic
  );
end IWLS2005__des_perf__part1408;

architecture IWLS2005__des_perf__part1408_behav of IWLS2005__des_perf__part1408 is
begin
    n29130_1 <= ( lo5852 );
end IWLS2005__des_perf__part1408_behav;
