--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part15 is 
  Port (
    lo203: in std_logic;
    po113: inout std_logic
  );
end IWLS2005__aes_core__part15;

architecture IWLS2005__aes_core__part15_behav of IWLS2005__aes_core__part15 is
begin
    po113 <= ( lo203 );
end IWLS2005__aes_core__part15_behav;
