--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part290 is 
  Port (
    lo1413: in std_logic;
    n10030_1: inout std_logic
  );
end Other__fp_operators__part290;

architecture Other__fp_operators__part290_behav of Other__fp_operators__part290 is
begin
    n10030_1 <= ( lo1413 );
end Other__fp_operators__part290_behav;
