--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part172 is 
  Port (
    pi1116: in std_logic;
    n31859: inout std_logic
  );
end Other__carpat__part172;

architecture Other__carpat__part172_behav of Other__carpat__part172 is
begin
    n31859 <= ( pi1116 );
end Other__carpat__part172_behav;
