--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part105 is 
  Port (
    pi0940: in std_logic;
    n31359_1: inout std_logic
  );
end Other__carpat__part105;

architecture Other__carpat__part105_behav of Other__carpat__part105 is
begin
    n31359_1 <= ( pi0940 );
end Other__carpat__part105_behav;
