--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1338 is 
  Port (
    lo7788: in std_logic;
    n43819_1: inout std_logic
  );
end Other__carpat__part1338;

architecture Other__carpat__part1338_behav of Other__carpat__part1338 is
begin
    n43819_1 <= ( lo7788 );
end Other__carpat__part1338_behav;
