--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part702 is 
  Port (
    lo3351: in std_logic;
    n11939: inout std_logic
  );
end Other__sudoku_check__part702;

architecture Other__sudoku_check__part702_behav of Other__sudoku_check__part702 is
begin
    n11939 <= ( lo3351 );
end Other__sudoku_check__part702_behav;
