--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part122 is 
  Port (
    pi0977: in std_logic;
    n31874: inout std_logic
  );
end Other__carpat__part122;

architecture Other__carpat__part122_behav of Other__carpat__part122 is
begin
    n31874 <= ( pi0977 );
end Other__carpat__part122_behav;
