--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b14_opt__part1 is 
  Port (
    lo243: in std_logic;
    po52: inout std_logic
  );
end ITC99__b14_opt__part1;

architecture ITC99__b14_opt__part1_behav of ITC99__b14_opt__part1 is
begin
    po52 <= ( lo243 );
end ITC99__b14_opt__part1_behav;
