--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part439 is 
  Port (
    lo05911: in std_logic;
    po1377,po1442,po1708,po1777: inout std_logic
  );
end Other__ray__part439;

architecture Other__ray__part439_behav of Other__ray__part439 is
begin
    po1377 <= ( lo05911 );
    po1442 <= ( lo05911 );
    po1708 <= ( lo05911 );
    po1777 <= ( lo05911 );
end Other__ray__part439_behav;
