--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part31 is 
  Port (
    pi31: in std_logic;
    n1574: inout std_logic
  );
end Cookbook__gearbox_40_67__part31;

architecture Cookbook__gearbox_40_67__part31_behav of Cookbook__gearbox_40_67__part31 is
begin
    n1574 <= ( pi31 );
end Cookbook__gearbox_40_67__part31_behav;
