--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part233 is 
  Port (
    lo0784: in std_logic;
    n5179: inout std_logic
  );
end Cookbook__ucrypt__part233;

architecture Cookbook__ucrypt__part233_behav of Cookbook__ucrypt__part233 is
begin
    n5179 <= ( lo0784 );
end Cookbook__ucrypt__part233_behav;
