--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1068 is 
  Port (
    lo10989: in std_logic;
    n73411_1: inout std_logic
  );
end Other__ray__part1068;

architecture Other__ray__part1068_behav of Other__ray__part1068 is
begin
    n73411_1 <= ( lo10989 );
end Other__ray__part1068_behav;
