--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part51 is 
  Port (
    lo2244: in std_logic;
    n5429: inout std_logic
  );
end Other__sudoku_check__part51;

architecture Other__sudoku_check__part51_behav of Other__sudoku_check__part51 is
begin
    n5429 <= ( lo2244 );
end Other__sudoku_check__part51_behav;
