--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part11 is 
  Port (
    lo049: in std_logic;
    po23: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part11;

architecture Cookbook__soft_ecc_ram_32bit__part11_behav of Cookbook__soft_ecc_ram_32bit__part11 is
begin
    po23 <= ( lo049 );
end Cookbook__soft_ecc_ram_32bit__part11_behav;
