--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part407 is 
  Port (
    lo0476: in std_logic;
    n2679: inout std_logic
  );
end Cookbook__fec_check__part407;

architecture Cookbook__fec_check__part407_behav of Cookbook__fec_check__part407 is
begin
    n2679 <= ( lo0476 );
end Cookbook__fec_check__part407_behav;
