--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part227 is 
  Port (
    lo0123: in std_logic;
    n625: inout std_logic
  );
end IWLS2005__des_perf__part227;

architecture IWLS2005__des_perf__part227_behav of IWLS2005__des_perf__part227 is
begin
    n625 <= ( not lo0123 );
end IWLS2005__des_perf__part227_behav;
