--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part458 is 
  Port (
    lo05930: in std_logic;
    po1396,po1430: inout std_logic
  );
end Other__ray__part458;

architecture Other__ray__part458_behav of Other__ray__part458 is
begin
    po1396 <= ( lo05930 );
    po1430 <= ( lo05930 );
end Other__ray__part458_behav;
