--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part36 is 
  Port (
    lo0069: in std_logic;
    po049: inout std_logic
  );
end Other__fp_operators__part36;

architecture Other__fp_operators__part36_behav of Other__fp_operators__part36 is
begin
    po049 <= ( lo0069 );
end Other__fp_operators__part36_behav;
