--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part15 is 
  Port (
    lo00176: in std_logic;
    po006: inout std_logic
  );
end IWLS2005__ethernet__part15;

architecture IWLS2005__ethernet__part15_behav of IWLS2005__ethernet__part15 is
begin
    po006 <= ( lo00176 );
end IWLS2005__ethernet__part15_behav;
