--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part30 is 
  Port (
    lo29: in std_logic;
    po29: inout std_logic
  );
end Other__idxlat10n_m12__part30;

architecture Other__idxlat10n_m12__part30_behav of Other__idxlat10n_m12__part30 is
begin
    po29 <= ( lo29 );
end Other__idxlat10n_m12__part30_behav;
