--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part186 is 
  Port (
    lo0444: in std_logic;
    n6676: inout std_logic
  );
end Other__ucsb_152_tap_fir__part186;

architecture Other__ucsb_152_tap_fir__part186_behav of Other__ucsb_152_tap_fir__part186 is
begin
    n6676 <= ( lo0444 );
end Other__ucsb_152_tap_fir__part186_behav;
