--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part47 is 
  Port (
    lo97736: in std_logic;
    n488475_1: inout std_logic
  );
end IWLS2005__netcard__part47;

architecture IWLS2005__netcard__part47_behav of IWLS2005__netcard__part47 is
begin
    n488475_1 <= ( lo97736 );
end IWLS2005__netcard__part47_behav;
