--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part693 is 
  Port (
    lo5217: in std_logic;
    n25089: inout std_logic
  );
end Other__carpat__part693;

architecture Other__carpat__part693_behav of Other__carpat__part693 is
begin
    n25089 <= ( lo5217 );
end Other__carpat__part693_behav;
