--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part629 is 
  Port (
    lo3278: in std_logic;
    n11209: inout std_logic
  );
end Other__sudoku_check__part629;

architecture Other__sudoku_check__part629_behav of Other__sudoku_check__part629 is
begin
    n11209 <= ( lo3278 );
end Other__sudoku_check__part629_behav;
