--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3119 is 
  Port (
    lo8432: in std_logic;
    n42710_1: inout std_logic
  );
end IWLS2005__des_perf__part3119;

architecture IWLS2005__des_perf__part3119_behav of IWLS2005__des_perf__part3119 is
begin
    n42710_1 <= ( lo8432 );
end IWLS2005__des_perf__part3119_behav;
