--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part12 is 
  Port (
    lo68593: in std_logic;
    n343050_1: inout std_logic
  );
end IWLS2005__netcard__part12;

architecture IWLS2005__netcard__part12_behav of IWLS2005__netcard__part12 is
begin
    n343050_1 <= ( lo68593 );
end IWLS2005__netcard__part12_behav;
