--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1717 is 
  Port (
    lo6500: in std_logic;
    n32500_1: inout std_logic
  );
end IWLS2005__des_perf__part1717;

architecture IWLS2005__des_perf__part1717_behav of IWLS2005__des_perf__part1717 is
begin
    n32500_1 <= ( lo6500 );
end IWLS2005__des_perf__part1717_behav;
