--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part125 is 
  Port (
    lo111: in std_logic;
    po155: inout std_logic
  );
end Cookbook__lc_mult_signed__part125;

architecture Cookbook__lc_mult_signed__part125_behav of Cookbook__lc_mult_signed__part125 is
begin
    po155 <= ( lo111 );
end Cookbook__lc_mult_signed__part125_behav;
