--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part835 is 
  Port (
    lo4639: in std_logic;
    n23155: inout std_logic
  );
end IWLS2005__des_perf__part835;

architecture IWLS2005__des_perf__part835_behav of IWLS2005__des_perf__part835 is
begin
    n23155 <= ( lo4639 );
end IWLS2005__des_perf__part835_behav;
