--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part778 is 
  Port (
    lo0847: in std_logic;
    n4534: inout std_logic
  );
end Cookbook__fec_check__part778;

architecture Cookbook__fec_check__part778_behav of Cookbook__fec_check__part778 is
begin
    n4534 <= ( lo0847 );
end Cookbook__fec_check__part778_behav;
