--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1725 is 
  Port (
    lo1794: in std_logic;
    n9269: inout std_logic
  );
end Cookbook__fec_check__part1725;

architecture Cookbook__fec_check__part1725_behav of Cookbook__fec_check__part1725 is
begin
    n9269 <= ( lo1794 );
end Cookbook__fec_check__part1725_behav;
