--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1530 is 
  Port (
    lo6101: in std_logic;
    n30310_1: inout std_logic
  );
end IWLS2005__des_perf__part1530;

architecture IWLS2005__des_perf__part1530_behav of IWLS2005__des_perf__part1530 is
begin
    n30310_1 <= ( lo6101 );
end IWLS2005__des_perf__part1530_behav;
