--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1548 is 
  Port (
    lo5801,lo5802,lo5803,lo5804: in std_logic;
    n27634_1,n29339_1,n29524,n29704,n29884,n30064,n30244,n30424,n30604: inout std_logic
  );
end Other__sudoku_check__part1548;

architecture Other__sudoku_check__part1548_behav of Other__sudoku_check__part1548 is
begin
    n27634_1 <= ( lo5801 and not lo5802 and not lo5803 and not lo5804 );
    n29339_1 <= ( lo5801 and not lo5802 and not lo5803 and lo5804 );
    n29524 <= ( not lo5801 and not lo5802 and not lo5803 and lo5804 );
    n29704 <= ( lo5801 and lo5802 and lo5803 and not lo5804 );
    n29884 <= ( not lo5801 and lo5802 and lo5803 and not lo5804 );
    n30064 <= ( lo5801 and not lo5802 and lo5803 and not lo5804 );
    n30244 <= ( not lo5801 and not lo5802 and lo5803 and not lo5804 );
    n30424 <= ( lo5801 and lo5802 and not lo5803 and not lo5804 );
    n30604 <= ( not lo5801 and lo5802 and not lo5803 and not lo5804 );
end Other__sudoku_check__part1548_behav;
