--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1422 is 
  Port (
    lo7872: in std_logic;
    n44239_1: inout std_logic
  );
end Other__carpat__part1422;

architecture Other__carpat__part1422_behav of Other__carpat__part1422 is
begin
    n44239_1 <= ( lo7872 );
end Other__carpat__part1422_behav;
