--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part23 is 
  Port (
    lo0643: in std_logic;
    po003: inout std_logic
  );
end IWLS2005__usb_funct__part23;

architecture IWLS2005__usb_funct__part23_behav of IWLS2005__usb_funct__part23 is
begin
    po003 <= ( lo0643 );
end IWLS2005__usb_funct__part23_behav;
