--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part78 is 
  Port (
    lo0147: in std_logic;
    n1034: inout std_logic
  );
end Cookbook__fec_check__part78;

architecture Cookbook__fec_check__part78_behav of Cookbook__fec_check__part78 is
begin
    n1034 <= ( lo0147 );
end Cookbook__fec_check__part78_behav;
