--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part491 is 
  Port (
    lo3140: in std_logic;
    n9829: inout std_logic
  );
end Other__sudoku_check__part491;

architecture Other__sudoku_check__part491_behav of Other__sudoku_check__part491 is
begin
    n9829 <= ( lo3140 );
end Other__sudoku_check__part491_behav;
