--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part497 is 
  Port (
    lo05969: in std_logic;
    po1484,po1549,po1841,po1910: inout std_logic
  );
end Other__ray__part497;

architecture Other__ray__part497_behav of Other__ray__part497 is
begin
    po1484 <= ( lo05969 );
    po1549 <= ( lo05969 );
    po1841 <= ( lo05969 );
    po1910 <= ( lo05969 );
end Other__ray__part497_behav;
