--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part35 is 
  Port (
    lo33: in std_logic;
    po06: inout std_logic
  );
end Cookbook__pipeline_add_msb__part35;

architecture Cookbook__pipeline_add_msb__part35_behav of Cookbook__pipeline_add_msb__part35 is
begin
    po06 <= ( lo33 );
end Cookbook__pipeline_add_msb__part35_behav;
