--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__eightbyeight_sad__part19 is 
  Port (
    lo326: in std_logic;
    po09: inout std_logic
  );
end Cookbook__eightbyeight_sad__part19;

architecture Cookbook__eightbyeight_sad__part19_behav of Cookbook__eightbyeight_sad__part19 is
begin
    po09 <= ( lo326 );
end Cookbook__eightbyeight_sad__part19_behav;
