--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2768 is 
  Port (
    lo8081: in std_logic;
    n40680_1: inout std_logic
  );
end IWLS2005__des_perf__part2768;

architecture IWLS2005__des_perf__part2768_behav of IWLS2005__des_perf__part2768 is
begin
    n40680_1 <= ( lo8081 );
end IWLS2005__des_perf__part2768_behav;
