--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1366 is 
  Port (
    lo4735: in std_logic;
    n19164: inout std_logic
  );
end Other__sudoku_check__part1366;

architecture Other__sudoku_check__part1366_behav of Other__sudoku_check__part1366 is
begin
    n19164 <= ( lo4735 );
end Other__sudoku_check__part1366_behav;
