--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1083 is 
  Port (
    lo7176: in std_logic;
    n38254: inout std_logic
  );
end Other__carpat__part1083;

architecture Other__carpat__part1083_behav of Other__carpat__part1083 is
begin
    n38254 <= ( lo7176 );
end Other__carpat__part1083_behav;
