--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s9234__part12 is 
  Port (
    lo186: in std_logic;
    po03,po07: inout std_logic
  );
end ISCAS__s9234__part12;

architecture ISCAS__s9234__part12_behav of ISCAS__s9234__part12 is
begin
    po03 <= ( lo186 );
    po07 <= ( lo186 );
end ISCAS__s9234__part12_behav;
