--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s6669__part23 is 
  Port (
    lo189: in std_logic;
    n1257_1: inout std_logic
  );
end ISCAS__s6669__part23;

architecture ISCAS__s6669__part23_behav of ISCAS__s6669__part23 is
begin
    n1257_1 <= ( not lo189 );
end ISCAS__s6669__part23_behav;
