--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1792 is 
  Port (
    lo8887: in std_logic;
    po323: inout std_logic
  );
end Other__carpat__part1792;

architecture Other__carpat__part1792_behav of Other__carpat__part1792 is
begin
    po323 <= ( lo8887 );
end Other__carpat__part1792_behav;
