--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part611 is 
  Port (
    lo4979: in std_logic;
    n21974: inout std_logic
  );
end Other__carpat__part611;

architecture Other__carpat__part611_behav of Other__carpat__part611 is
begin
    n21974 <= ( lo4979 );
end Other__carpat__part611_behav;
