--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1302 is 
  Port (
    lo3022: in std_logic;
    n19606: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1302;

architecture Other__ucsb_152_tap_fir__part1302_behav of Other__ucsb_152_tap_fir__part1302 is
begin
    n19606 <= ( lo3022 );
end Other__ucsb_152_tap_fir__part1302_behav;
