--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part37 is 
  Port (
    lo2146: in std_logic;
    n5289: inout std_logic
  );
end Other__sudoku_check__part37;

architecture Other__sudoku_check__part37_behav of Other__sudoku_check__part37 is
begin
    n5289 <= ( lo2146 );
end Other__sudoku_check__part37_behav;
