--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2429 is 
  Port (
    lo7669: in std_logic;
    n38030: inout std_logic
  );
end IWLS2005__des_perf__part2429;

architecture IWLS2005__des_perf__part2429_behav of IWLS2005__des_perf__part2429 is
begin
    n38030 <= ( lo7669 );
end IWLS2005__des_perf__part2429_behav;
