--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part152 is 
  Port (
    pi1060: in std_logic;
    n31849: inout std_logic
  );
end Other__carpat__part152;

architecture Other__carpat__part152_behav of Other__carpat__part152 is
begin
    n31849 <= ( pi1060 );
end Other__carpat__part152_behav;
