--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part546 is 
  Port (
    lo1993: in std_logic;
    n11224_1: inout std_logic
  );
end Cookbook__ucrypt__part546;

architecture Cookbook__ucrypt__part546_behav of Cookbook__ucrypt__part546 is
begin
    n11224_1 <= ( lo1993 );
end Cookbook__ucrypt__part546_behav;
