--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part230 is 
  Port (
    lo2879: in std_logic;
    n7219: inout std_logic
  );
end Other__sudoku_check__part230;

architecture Other__sudoku_check__part230_behav of Other__sudoku_check__part230 is
begin
    n7219 <= ( lo2879 );
end Other__sudoku_check__part230_behav;
