--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1779 is 
  Port (
    lo6591: in std_logic;
    n33125_1: inout std_logic
  );
end IWLS2005__des_perf__part1779;

architecture IWLS2005__des_perf__part1779_behav of IWLS2005__des_perf__part1779 is
begin
    n33125_1 <= ( lo6591 );
end IWLS2005__des_perf__part1779_behav;
