--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part11 is 
  Port (
    pi27: in std_logic;
    n605: inout std_logic
  );
end Cookbook__lc_mult_signed__part11;

architecture Cookbook__lc_mult_signed__part11_behav of Cookbook__lc_mult_signed__part11 is
begin
    n605 <= ( pi27 );
end Cookbook__lc_mult_signed__part11_behav;
