--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part247 is 
  Port (
    lo2896: in std_logic;
    n7389: inout std_logic
  );
end Other__sudoku_check__part247;

architecture Other__sudoku_check__part247_behav of Other__sudoku_check__part247 is
begin
    n7389 <= ( lo2896 );
end Other__sudoku_check__part247_behav;
