--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1743 is 
  Port (
    lo3938: in std_logic;
    n24196: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1743;

architecture Other__ucsb_152_tap_fir__part1743_behav of Other__ucsb_152_tap_fir__part1743 is
begin
    n24196 <= ( lo3938 );
end Other__ucsb_152_tap_fir__part1743_behav;
