--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2097 is 
  Port (
    lo2166: in std_logic;
    n11129: inout std_logic
  );
end Cookbook__fec_check__part2097;

architecture Cookbook__fec_check__part2097_behav of Cookbook__fec_check__part2097 is
begin
    n11129 <= ( lo2166 );
end Cookbook__fec_check__part2097_behav;
