--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2525 is 
  Port (
    lo5569: in std_logic;
    n32431: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2525;

architecture Other__ucsb_152_tap_fir__part2525_behav of Other__ucsb_152_tap_fir__part2525 is
begin
    n32431 <= ( lo5569 );
end Other__ucsb_152_tap_fir__part2525_behav;
