--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1140 is 
  Port (
    lo1209: in std_logic;
    n6344: inout std_logic
  );
end Cookbook__fec_check__part1140;

architecture Cookbook__fec_check__part1140_behav of Cookbook__fec_check__part1140 is
begin
    n6344 <= ( lo1209 );
end Cookbook__fec_check__part1140_behav;
