--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part117 is 
  Port (
    lo0186: in std_logic;
    n1229: inout std_logic
  );
end Cookbook__fec_check__part117;

architecture Cookbook__fec_check__part117_behav of Cookbook__fec_check__part117 is
begin
    n1229 <= ( lo0186 );
end Cookbook__fec_check__part117_behav;
