--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1382 is 
  Port (
    lo7832: in std_logic;
    n44039_1: inout std_logic
  );
end Other__carpat__part1382;

architecture Other__carpat__part1382_behav of Other__carpat__part1382 is
begin
    n44039_1 <= ( lo7832 );
end Other__carpat__part1382_behav;
