--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1490 is 
  Port (
    lo4859: in std_logic;
    n19784_1: inout std_logic
  );
end Other__sudoku_check__part1490;

architecture Other__sudoku_check__part1490_behav of Other__sudoku_check__part1490 is
begin
    n19784_1 <= ( lo4859 );
end Other__sudoku_check__part1490_behav;
