--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2076 is 
  Port (
    lo2145: in std_logic;
    n11024: inout std_logic
  );
end Cookbook__fec_check__part2076;

architecture Cookbook__fec_check__part2076_behav of Cookbook__fec_check__part2076 is
begin
    n11024 <= ( lo2145 );
end Cookbook__fec_check__part2076_behav;
