--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1100 is 
  Port (
    lo5177: in std_logic;
    n25990: inout std_logic
  );
end IWLS2005__des_perf__part1100;

architecture IWLS2005__des_perf__part1100_behav of IWLS2005__des_perf__part1100 is
begin
    n25990 <= ( lo5177 );
end IWLS2005__des_perf__part1100_behav;
