--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s382__part6 is 
  Port (
    lo07: in std_logic;
    po0: inout std_logic
  );
end ISCAS__s382__part6;

architecture ISCAS__s382__part6_behav of ISCAS__s382__part6 is
begin
    po0 <= ( lo07 );
end ISCAS__s382__part6_behav;
