--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part11 is 
  Port (
    pi15: in std_logic;
    n404: inout std_logic
  );
end ISCAS__s38417__part11;

architecture ISCAS__s38417__part11_behav of ISCAS__s38417__part11 is
begin
    n404 <= ( pi15 );
end ISCAS__s38417__part11_behav;
