--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part230 is 
  Port (
    lo03345: in std_logic;
    n34441: inout std_logic
  );
end Other__ray__part230;

architecture Other__ray__part230_behav of Other__ray__part230 is
begin
    n34441 <= ( lo03345 );
end Other__ray__part230_behav;
