--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part65 is 
  Port (
    lo189: in std_logic;
    po26: inout std_logic
  );
end IWLS2005__systemcdes__part65;

architecture IWLS2005__systemcdes__part65_behav of IWLS2005__systemcdes__part65 is
begin
    po26 <= ( lo189 );
end IWLS2005__systemcdes__part65_behav;
