--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part112 is 
  Port (
    lo0901: in std_logic;
    n5354_1: inout std_logic
  );
end LGSynth91__s38417__part112;

architecture LGSynth91__s38417__part112_behav of LGSynth91__s38417__part112 is
begin
    n5354_1 <= ( not lo0901 );
end LGSynth91__s38417__part112_behav;
