--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1402 is 
  Port (
    lo1471: in std_logic;
    n7654: inout std_logic
  );
end Cookbook__fec_check__part1402;

architecture Cookbook__fec_check__part1402_behav of Cookbook__fec_check__part1402 is
begin
    n7654 <= ( lo1471 );
end Cookbook__fec_check__part1402_behav;
