--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part852 is 
  Port (
    lo4683: in std_logic;
    n23555: inout std_logic
  );
end IWLS2005__des_perf__part852;

architecture IWLS2005__des_perf__part852_behav of IWLS2005__des_perf__part852 is
begin
    n23555 <= ( lo4683 );
end IWLS2005__des_perf__part852_behav;
