--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part65 is 
  Port (
    lo00940: in std_logic;
    po066: inout std_logic
  );
end IWLS2005__ethernet__part65;

architecture IWLS2005__ethernet__part65_behav of IWLS2005__ethernet__part65 is
begin
    po066 <= ( lo00940 );
end IWLS2005__ethernet__part65_behav;
