--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1667 is 
  Port (
    lo6372: in std_logic;
    n31920_1: inout std_logic
  );
end IWLS2005__des_perf__part1667;

architecture IWLS2005__des_perf__part1667_behav of IWLS2005__des_perf__part1667 is
begin
    n31920_1 <= ( lo6372 );
end IWLS2005__des_perf__part1667_behav;
