--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part59 is 
  Port (
    lo2324: in std_logic;
    n5509: inout std_logic
  );
end Other__sudoku_check__part59;

architecture Other__sudoku_check__part59_behav of Other__sudoku_check__part59 is
begin
    n5509 <= ( lo2324 );
end Other__sudoku_check__part59_behav;
