--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part150 is 
  Port (
    lo1098: in std_logic;
    n5764_1: inout std_logic
  );
end ISCAS__s38417__part150;

architecture ISCAS__s38417__part150_behav of ISCAS__s38417__part150 is
begin
    n5764_1 <= ( lo1098 );
end ISCAS__s38417__part150_behav;
