--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part192 is 
  Port (
    lo2841: in std_logic;
    n6839: inout std_logic
  );
end Other__sudoku_check__part192;

architecture Other__sudoku_check__part192_behav of Other__sudoku_check__part192 is
begin
    n6839 <= ( lo2841 );
end Other__sudoku_check__part192_behav;
