--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part22 is 
  Port (
    lo0229: in std_logic;
    po012,po014,po015,po017,n1419: inout std_logic
  );
end LGSynth91__s38417__part22;

architecture LGSynth91__s38417__part22_behav of LGSynth91__s38417__part22 is
begin
    po012 <= ( lo0229 );
    po014 <= ( lo0229 );
    po015 <= ( lo0229 );
    po017 <= ( lo0229 );
    n1419 <= ( lo0229 );
end LGSynth91__s38417__part22_behav;
