--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part35 is 
  Port (
    lo137: in std_logic;
    n1345: inout std_logic
  );
end ISCAS__s15850__part35;

architecture ISCAS__s15850__part35_behav of ISCAS__s15850__part35 is
begin
    n1345 <= ( lo137 );
end ISCAS__s15850__part35_behav;
