--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part51 is 
  Port (
    lo49: in std_logic;
    n266: inout std_logic
  );
end Cookbook__pipeline_add__part51;

architecture Cookbook__pipeline_add__part51_behav of Cookbook__pipeline_add__part51 is
begin
    n266 <= ( lo49 );
end Cookbook__pipeline_add__part51_behav;
