--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part547 is 
  Port (
    lo3196: in std_logic;
    n10389: inout std_logic
  );
end Other__sudoku_check__part547;

architecture Other__sudoku_check__part547_behav of Other__sudoku_check__part547 is
begin
    n10389 <= ( lo3196 );
end Other__sudoku_check__part547_behav;
