--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part24 is 
  Port (
    lo079: in std_logic;
    n693: inout std_logic
  );
end ISCAS__s13207__part24;

architecture ISCAS__s13207__part24_behav of ISCAS__s13207__part24 is
begin
    n693 <= ( lo079 );
end ISCAS__s13207__part24_behav;
