--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part754 is 
  Port (
    lo0823: in std_logic;
    n4414: inout std_logic
  );
end Cookbook__fec_check__part754;

architecture Cookbook__fec_check__part754_behav of Cookbook__fec_check__part754 is
begin
    n4414 <= ( lo0823 );
end Cookbook__fec_check__part754_behav;
