--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part88 is 
  Port (
    pi143: in std_logic;
    n43725_1: inout std_logic
  );
end IWLS2005__des_perf__part88;

architecture IWLS2005__des_perf__part88_behav of IWLS2005__des_perf__part88 is
begin
    n43725_1 <= ( pi143 );
end IWLS2005__des_perf__part88_behav;
