--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1178 is 
  Port (
    lo2729: in std_logic;
    n18236: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1178;

architecture Other__ucsb_152_tap_fir__part1178_behav of Other__ucsb_152_tap_fir__part1178 is
begin
    n18236 <= ( lo2729 );
end Other__ucsb_152_tap_fir__part1178_behav;
