--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part2 is 
  Port (
    lo300: in std_logic;
    n1678: inout std_logic
  );
end Cookbook__lane_tx__part2;

architecture Cookbook__lane_tx__part2_behav of Cookbook__lane_tx__part2 is
begin
    n1678 <= ( lo300 );
end Cookbook__lane_tx__part2_behav;
