--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part37 is 
  Port (
    lo023: in std_logic;
    po006: inout std_logic
  );
end Cookbook__lc_mult_signed__part37;

architecture Cookbook__lc_mult_signed__part37_behav of Cookbook__lc_mult_signed__part37 is
begin
    po006 <= ( lo023 );
end Cookbook__lc_mult_signed__part37_behav;
