--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part159 is 
  Port (
    lo1017: in std_logic;
    po093: inout std_logic
  );
end IWLS2005__mem_ctrl__part159;

architecture IWLS2005__mem_ctrl__part159_behav of IWLS2005__mem_ctrl__part159 is
begin
    po093 <= ( lo1017 );
end IWLS2005__mem_ctrl__part159_behav;
