--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1703 is 
  Port (
    lo8707: in std_logic;
    n49039_1: inout std_logic
  );
end Other__carpat__part1703;

architecture Other__carpat__part1703_behav of Other__carpat__part1703 is
begin
    n49039_1 <= ( lo8707 );
end Other__carpat__part1703_behav;
