--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2371 is 
  Port (
    lo5256: in std_logic;
    n30791_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2371;

architecture Other__ucsb_152_tap_fir__part2371_behav of Other__ucsb_152_tap_fir__part2371 is
begin
    n30791_1 <= ( lo5256 );
end Other__ucsb_152_tap_fir__part2371_behav;
