--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part76 is 
  Port (
    pi0805: in std_logic;
    n24814: inout std_logic
  );
end Other__carpat__part76;

architecture Other__carpat__part76_behav of Other__carpat__part76 is
begin
    n24814 <= ( pi0805 );
end Other__carpat__part76_behav;
