--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part894 is 
  Port (
    lo6730: in std_logic;
    n33029_1: inout std_logic
  );
end Other__carpat__part894;

architecture Other__carpat__part894_behav of Other__carpat__part894 is
begin
    n33029_1 <= ( lo6730 );
end Other__carpat__part894_behav;
