--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1314 is 
  Port (
    lo4683: in std_logic;
    n18904: inout std_logic
  );
end Other__sudoku_check__part1314;

architecture Other__sudoku_check__part1314_behav of Other__sudoku_check__part1314 is
begin
    n18904 <= ( lo4683 );
end Other__sudoku_check__part1314_behav;
