--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part740 is 
  Port (
    lo0809: in std_logic;
    n4344: inout std_logic
  );
end Cookbook__fec_check__part740;

architecture Cookbook__fec_check__part740_behav of Cookbook__fec_check__part740 is
begin
    n4344 <= ( lo0809 );
end Cookbook__fec_check__part740_behav;
