--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1054 is 
  Port (
    lo4423: in std_logic;
    n17604: inout std_logic
  );
end Other__sudoku_check__part1054;

architecture Other__sudoku_check__part1054_behav of Other__sudoku_check__part1054 is
begin
    n17604 <= ( lo4423 );
end Other__sudoku_check__part1054_behav;
