--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part112 is 
  Port (
    lo01339: in std_logic;
    po2781,po2877,po2973,po3606,po3654,po3702,n20951: inout std_logic
  );
end Other__ray__part112;

architecture Other__ray__part112_behav of Other__ray__part112 is
begin
    po2781 <= ( lo01339 );
    po2877 <= ( lo01339 );
    po2973 <= ( lo01339 );
    po3606 <= ( lo01339 );
    po3654 <= ( lo01339 );
    po3702 <= ( lo01339 );
    n20951 <= ( lo01339 );
end Other__ray__part112_behav;
