--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part483 is 
  Port (
    lo0552: in std_logic;
    n3059: inout std_logic
  );
end Cookbook__fec_check__part483;

architecture Cookbook__fec_check__part483_behav of Cookbook__fec_check__part483 is
begin
    n3059 <= ( lo0552 );
end Cookbook__fec_check__part483_behav;
