--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1428 is 
  Port (
    lo7878: in std_logic;
    n44269_1: inout std_logic
  );
end Other__carpat__part1428;

architecture Other__carpat__part1428_behav of Other__carpat__part1428 is
begin
    n44269_1 <= ( lo7878 );
end Other__carpat__part1428_behav;
