--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1185 is 
  Port (
    lo1254: in std_logic;
    n6569: inout std_logic
  );
end Cookbook__fec_check__part1185;

architecture Cookbook__fec_check__part1185_behav of Cookbook__fec_check__part1185 is
begin
    n6569 <= ( lo1254 );
end Cookbook__fec_check__part1185_behav;
