--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part18 is 
  Port (
    pi25: in std_logic;
    n414: inout std_logic
  );
end ISCAS__s38417__part18;

architecture ISCAS__s38417__part18_behav of ISCAS__s38417__part18 is
begin
    n414 <= ( pi25 );
end ISCAS__s38417__part18_behav;
