--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part61 is 
  Port (
    lo137: in std_logic;
    po41: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part61;

architecture Cookbook__soft_ecc_ram_32bit__part61_behav of Cookbook__soft_ecc_ram_32bit__part61 is
begin
    po41 <= ( lo137 );
end Cookbook__soft_ecc_ram_32bit__part61_behav;
