--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part72 is 
  Port (
    pi127: in std_logic;
    n44080_1: inout std_logic
  );
end IWLS2005__des_perf__part72;

architecture IWLS2005__des_perf__part72_behav of IWLS2005__des_perf__part72 is
begin
    n44080_1 <= ( pi127 );
end IWLS2005__des_perf__part72_behav;
