--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1835 is 
  Port (
    lo6743: in std_logic;
    n33510: inout std_logic
  );
end IWLS2005__des_perf__part1835;

architecture IWLS2005__des_perf__part1835_behav of IWLS2005__des_perf__part1835 is
begin
    n33510 <= ( lo6743 );
end IWLS2005__des_perf__part1835_behav;
