--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part873 is 
  Port (
    lo4242: in std_logic;
    n16699: inout std_logic
  );
end Other__sudoku_check__part873;

architecture Other__sudoku_check__part873_behav of Other__sudoku_check__part873 is
begin
    n16699 <= ( lo4242 );
end Other__sudoku_check__part873_behav;
