--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part87 is 
  Port (
    pi0497: in std_logic;
    n43031_1: inout std_logic
  );
end Other__radar__part87;

architecture Other__radar__part87_behav of Other__radar__part87 is
begin
    n43031_1 <= ( pi0497 );
end Other__radar__part87_behav;
