--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part130 is 
  Port (
    pi0540: in std_logic;
    n43246_1: inout std_logic
  );
end Other__radar__part130;

architecture Other__radar__part130_behav of Other__radar__part130 is
begin
    n43246_1 <= ( pi0540 );
end Other__radar__part130_behav;
