--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part25 is 
  Port (
    lo11,lo12,lo14,lo15,lo13: in std_logic;
    n264_1: inout std_logic
  );
end Cookbook__pipe_equal__part25;

architecture Cookbook__pipe_equal__part25_behav of Cookbook__pipe_equal__part25 is
signal n323,n324,n325: std_logic;
begin
    n323 <= ( lo11 and lo12 );
    n324 <= ( lo14 and lo15 );
    n325 <= ( lo13 and n324 );
    n264_1 <= ( n323 and n325 );
end Cookbook__pipe_equal__part25_behav;
