--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1033 is 
  Port (
    lo5065: in std_logic;
    n25295: inout std_logic
  );
end IWLS2005__des_perf__part1033;

architecture IWLS2005__des_perf__part1033_behav of IWLS2005__des_perf__part1033 is
begin
    n25295 <= ( lo5065 );
end IWLS2005__des_perf__part1033_behav;
