--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1852 is 
  Port (
    lo9125: in std_logic;
    po489: inout std_logic
  );
end Other__carpat__part1852;

architecture Other__carpat__part1852_behav of Other__carpat__part1852 is
begin
    po489 <= ( lo9125 );
end Other__carpat__part1852_behav;
