--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part72 is 
  Port (
    pi0482: in std_logic;
    n42956_1: inout std_logic
  );
end Other__radar__part72;

architecture Other__radar__part72_behav of Other__radar__part72 is
begin
    n42956_1 <= ( pi0482 );
end Other__radar__part72_behav;
