--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part61 is 
  Port (
    lo0129: in std_logic;
    po138: inout std_logic
  );
end Other__mem__part61;

architecture Other__mem__part61_behav of Other__mem__part61 is
begin
    po138 <= ( lo0129 );
end Other__mem__part61_behav;
