--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part216 is 
  Port (
    lo0612: in std_logic;
    n2534: inout std_logic
  );
end Other__desperf__part216;

architecture Other__desperf__part216_behav of Other__desperf__part216 is
begin
    n2534 <= ( lo0612 );
end Other__desperf__part216_behav;
