--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part175 is 
  Port (
    lo161: in std_logic;
    po105: inout std_logic
  );
end Cookbook__lc_mult_signed__part175;

architecture Cookbook__lc_mult_signed__part175_behav of Cookbook__lc_mult_signed__part175 is
begin
    po105 <= ( lo161 );
end Cookbook__lc_mult_signed__part175_behav;
