--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2339 is 
  Port (
    lo5178: in std_logic;
    n30396: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2339;

architecture Other__ucsb_152_tap_fir__part2339_behav of Other__ucsb_152_tap_fir__part2339 is
begin
    n30396 <= ( lo5178 );
end Other__ucsb_152_tap_fir__part2339_behav;
