--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part107 is 
  Port (
    lo184857: in std_logic;
    n924231: inout std_logic
  );
end IWLS2005__leon3__part107;

architecture IWLS2005__leon3__part107_behav of IWLS2005__leon3__part107 is
begin
    n924231 <= ( lo184857 );
end IWLS2005__leon3__part107_behav;
