--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1085 is 
  Port (
    lo1154: in std_logic;
    n6069: inout std_logic
  );
end Cookbook__fec_check__part1085;

architecture Cookbook__fec_check__part1085_behav of Cookbook__fec_check__part1085 is
begin
    n6069 <= ( lo1154 );
end Cookbook__fec_check__part1085_behav;
