--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part607 is 
  Port (
    lo4217: in std_logic;
    n21340: inout std_logic
  );
end IWLS2005__des_perf__part607;

architecture IWLS2005__des_perf__part607_behav of IWLS2005__des_perf__part607 is
begin
    n21340 <= ( lo4217 );
end IWLS2005__des_perf__part607_behav;
