--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1679 is 
  Port (
    lo8624: in std_logic;
    n48619_1: inout std_logic
  );
end Other__carpat__part1679;

architecture Other__carpat__part1679_behav of Other__carpat__part1679 is
begin
    n48619_1 <= ( lo8624 );
end Other__carpat__part1679_behav;
