--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part349 is 
  Port (
    lo0418: in std_logic;
    n2389: inout std_logic
  );
end Cookbook__fec_check__part349;

architecture Cookbook__fec_check__part349_behav of Cookbook__fec_check__part349 is
begin
    n2389 <= ( lo0418 );
end Cookbook__fec_check__part349_behav;
