--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part15 is 
  Port (
    lo14: in std_logic;
    po14: inout std_logic
  );
end Other__idxlat01n_m12__part15;

architecture Other__idxlat01n_m12__part15_behav of Other__idxlat01n_m12__part15 is
begin
    po14 <= ( lo14 );
end Other__idxlat01n_m12__part15_behav;
