--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part169 is 
  Port (
    lo0661: in std_logic;
    n5690: inout std_logic
  );
end Other__fp_operators__part169;

architecture Other__fp_operators__part169_behav of Other__fp_operators__part169 is
begin
    n5690 <= ( lo0661 );
end Other__fp_operators__part169_behav;
