--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1038 is 
  Port (
    lo7131: in std_logic;
    n37839_1: inout std_logic
  );
end Other__carpat__part1038;

architecture Other__carpat__part1038_behav of Other__carpat__part1038 is
begin
    n37839_1 <= ( lo7131 );
end Other__carpat__part1038_behav;
