--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2151 is 
  Port (
    lo2220: in std_logic;
    n11399: inout std_logic
  );
end Cookbook__fec_check__part2151;

architecture Cookbook__fec_check__part2151_behav of Cookbook__fec_check__part2151 is
begin
    n11399 <= ( lo2220 );
end Cookbook__fec_check__part2151_behav;
