--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1773 is 
  Port (
    lo8868: in std_logic;
    po303: inout std_logic
  );
end Other__carpat__part1773;

architecture Other__carpat__part1773_behav of Other__carpat__part1773 is
begin
    po303 <= ( lo8868 );
end Other__carpat__part1773_behav;
