--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1711 is 
  Port (
    lo1780: in std_logic;
    n9199: inout std_logic
  );
end Cookbook__fec_check__part1711;

architecture Cookbook__fec_check__part1711_behav of Cookbook__fec_check__part1711 is
begin
    n9199 <= ( lo1780 );
end Cookbook__fec_check__part1711_behav;
