--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part715 is 
  Port (
    lo5246: in std_logic;
    n25199: inout std_logic
  );
end Other__carpat__part715;

architecture Other__carpat__part715_behav of Other__carpat__part715 is
begin
    n25199 <= ( lo5246 );
end Other__carpat__part715_behav;
