--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1998 is 
  Port (
    lo7033: in std_logic;
    n35440_1: inout std_logic
  );
end IWLS2005__des_perf__part1998;

architecture IWLS2005__des_perf__part1998_behav of IWLS2005__des_perf__part1998 is
begin
    n35440_1 <= ( lo7033 );
end IWLS2005__des_perf__part1998_behav;
