--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part285 is 
  Port (
    lo1132: in std_logic;
    n6135: inout std_logic
  );
end IWLS2005__des_perf__part285;

architecture IWLS2005__des_perf__part285_behav of IWLS2005__des_perf__part285 is
begin
    n6135 <= ( lo1132 );
end IWLS2005__des_perf__part285_behav;
