--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part71 is 
  Port (
    lo085: in std_logic;
    po08: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part71;

architecture Cookbook__approx_fp_invsqrt__part71_behav of Cookbook__approx_fp_invsqrt__part71 is
begin
    po08 <= ( lo085 );
end Cookbook__approx_fp_invsqrt__part71_behav;
