--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__simple_spi__part6 is 
  Port (
    lo071: in std_logic;
    po00: inout std_logic
  );
end IWLS2005__simple_spi__part6;

architecture IWLS2005__simple_spi__part6_behav of IWLS2005__simple_spi__part6 is
begin
    po00 <= ( lo071 );
end IWLS2005__simple_spi__part6_behav;
