--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b06__part4 is 
  Port (
    lo6: in std_logic;
    po2: inout std_logic
  );
end ITC99__b06__part4;

architecture ITC99__b06__part4_behav of ITC99__b06__part4 is
begin
    po2 <= ( lo6 );
end ITC99__b06__part4_behav;
