--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part14 is 
  Port (
    lo114: in std_logic;
    n750: inout std_logic
  );
end ISCAS__s15850__part14;

architecture ISCAS__s15850__part14_behav of ISCAS__s15850__part14 is
begin
    n750 <= ( lo114 );
end ISCAS__s15850__part14_behav;
