--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1500 is 
  Port (
    lo1569: in std_logic;
    n8144: inout std_logic
  );
end Cookbook__fec_check__part1500;

architecture Cookbook__fec_check__part1500_behav of Cookbook__fec_check__part1500 is
begin
    n8144 <= ( lo1569 );
end Cookbook__fec_check__part1500_behav;
