--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1010 is 
  Port (
    lo4379: in std_logic;
    n17384: inout std_logic
  );
end Other__sudoku_check__part1010;

architecture Other__sudoku_check__part1010_behav of Other__sudoku_check__part1010 is
begin
    n17384 <= ( lo4379 );
end Other__sudoku_check__part1010_behav;
