--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1910 is 
  Port (
    lo4293: in std_logic;
    n26051: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1910;

architecture Other__ucsb_152_tap_fir__part1910_behav of Other__ucsb_152_tap_fir__part1910 is
begin
    n26051 <= ( lo4293 );
end Other__ucsb_152_tap_fir__part1910_behav;
