--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1808 is 
  Port (
    lo8903: in std_logic;
    po339: inout std_logic
  );
end Other__carpat__part1808;

architecture Other__carpat__part1808_behav of Other__carpat__part1808 is
begin
    po339 <= ( lo8903 );
end Other__carpat__part1808_behav;
