--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part353 is 
  Port (
    pi1702: in std_logic;
    n48289_1: inout std_logic
  );
end Other__carpat__part353;

architecture Other__carpat__part353_behav of Other__carpat__part353 is
begin
    n48289_1 <= ( pi1702 );
end Other__carpat__part353_behav;
