--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part165 is 
  Port (
    lo0365: in std_logic;
    n6276: inout std_logic
  );
end Other__ucsb_152_tap_fir__part165;

architecture Other__ucsb_152_tap_fir__part165_behav of Other__ucsb_152_tap_fir__part165 is
begin
    n6276 <= ( lo0365 );
end Other__ucsb_152_tap_fir__part165_behav;
