--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1059 is 
  Port (
    lo4428: in std_logic;
    n17629: inout std_logic
  );
end Other__sudoku_check__part1059;

architecture Other__sudoku_check__part1059_behav of Other__sudoku_check__part1059 is
begin
    n17629 <= ( lo4428 );
end Other__sudoku_check__part1059_behav;
