--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part12 is 
  Port (
    pi12: in std_logic;
    n544253: inout std_logic
  );
end IWLS2005__leon3mp__part12;

architecture IWLS2005__leon3mp__part12_behav of IWLS2005__leon3mp__part12 is
begin
    n544253 <= ( pi12 );
end IWLS2005__leon3mp__part12_behav;
