--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1820 is 
  Port (
    lo9066: in std_logic;
    po451: inout std_logic
  );
end Other__carpat__part1820;

architecture Other__carpat__part1820_behav of Other__carpat__part1820 is
begin
    po451 <= ( lo9066 );
end Other__carpat__part1820_behav;
