--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part526 is 
  Port (
    lo3175: in std_logic;
    n10179: inout std_logic
  );
end Other__sudoku_check__part526;

architecture Other__sudoku_check__part526_behav of Other__sudoku_check__part526 is
begin
    n10179 <= ( lo3175 );
end Other__sudoku_check__part526_behav;
