--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1168 is 
  Port (
    lo7415: in std_logic;
    n41154_1: inout std_logic
  );
end Other__carpat__part1168;

architecture Other__carpat__part1168_behav of Other__carpat__part1168 is
begin
    n41154_1 <= ( lo7415 );
end Other__carpat__part1168_behav;
