--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part686 is 
  Port (
    lo3335: in std_logic;
    n11779: inout std_logic
  );
end Other__sudoku_check__part686;

architecture Other__sudoku_check__part686_behav of Other__sudoku_check__part686 is
begin
    n11779 <= ( lo3335 );
end Other__sudoku_check__part686_behav;
