--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part572 is 
  Port (
    lo06053: in std_logic;
    po1574,po1669: inout std_logic
  );
end Other__ray__part572;

architecture Other__ray__part572_behav of Other__ray__part572 is
begin
    po1574 <= ( lo06053 );
    po1669 <= ( lo06053 );
end Other__ray__part572_behav;
