--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_40__part2 is 
  Port (
    lo007: in std_logic;
    po41: inout std_logic
  );
end Cookbook__gearbox_66_40__part2;

architecture Cookbook__gearbox_66_40__part2_behav of Cookbook__gearbox_66_40__part2 is
begin
    po41 <= ( lo007 );
end Cookbook__gearbox_66_40__part2_behav;
