--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1176 is 
  Port (
    lo2727: in std_logic;
    n18226: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1176;

architecture Other__ucsb_152_tap_fir__part1176_behav of Other__ucsb_152_tap_fir__part1176 is
begin
    n18226 <= ( lo2727 );
end Other__ucsb_152_tap_fir__part1176_behav;
