--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part8 is 
  Port (
    pi61: in std_logic;
    n974: inout std_logic
  );
end Cookbook__ucrypt__part8;

architecture Cookbook__ucrypt__part8_behav of Cookbook__ucrypt__part8 is
begin
    n974 <= ( pi61 );
end Cookbook__ucrypt__part8_behav;
