--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2463 is 
  Port (
    lo5439: in std_logic;
    n31751: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2463;

architecture Other__ucsb_152_tap_fir__part2463_behav of Other__ucsb_152_tap_fir__part2463 is
begin
    n31751 <= ( lo5439 );
end Other__ucsb_152_tap_fir__part2463_behav;
