--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part79 is 
  Port (
    pi079: in std_logic;
    n10044_1: inout std_logic
  );
end Other__desperf__part79;

architecture Other__desperf__part79_behav of Other__desperf__part79 is
begin
    n10044_1 <= ( pi079 );
end Other__desperf__part79_behav;
