--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part20 is 
  Port (
    pi0331: in std_logic;
    n19539: inout std_logic
  );
end Other__carpat__part20;

architecture Other__carpat__part20_behav of Other__carpat__part20 is
begin
    n19539 <= ( pi0331 );
end Other__carpat__part20_behav;
