--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part195 is 
  Port (
    pi0645: in std_logic;
    n44936_1: inout std_logic
  );
end Other__radar__part195;

architecture Other__radar__part195_behav of Other__radar__part195 is
begin
    n44936_1 <= ( pi0645 );
end Other__radar__part195_behav;
