--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part821 is 
  Port (
    lo4616: in std_logic;
    n23100: inout std_logic
  );
end IWLS2005__des_perf__part821;

architecture IWLS2005__des_perf__part821_behav of IWLS2005__des_perf__part821 is
begin
    n23100 <= ( lo4616 );
end IWLS2005__des_perf__part821_behav;
