--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part102 is 
  Port (
    lo088: in std_logic;
    po178: inout std_logic
  );
end Cookbook__lc_mult_signed__part102;

architecture Cookbook__lc_mult_signed__part102_behav of Cookbook__lc_mult_signed__part102 is
begin
    po178 <= ( lo088 );
end Cookbook__lc_mult_signed__part102_behav;
