--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part836 is 
  Port (
    lo4205: in std_logic;
    n16184: inout std_logic
  );
end Other__sudoku_check__part836;

architecture Other__sudoku_check__part836_behav of Other__sudoku_check__part836 is
begin
    n16184 <= ( lo4205 );
end Other__sudoku_check__part836_behav;
