--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part971 is 
  Port (
    lo4934: in std_logic;
    n24955: inout std_logic
  );
end IWLS2005__des_perf__part971;

architecture IWLS2005__des_perf__part971_behav of IWLS2005__des_perf__part971 is
begin
    n24955 <= ( lo4934 );
end IWLS2005__des_perf__part971_behav;
