--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1410 is 
  Port (
    lo3238: in std_logic;
    n20766: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1410;

architecture Other__ucsb_152_tap_fir__part1410_behav of Other__ucsb_152_tap_fir__part1410 is
begin
    n20766 <= ( lo3238 );
end Other__ucsb_152_tap_fir__part1410_behav;
