--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part87 is 
  Port (
    lo073: in std_logic;
    po193: inout std_logic
  );
end Cookbook__lc_mult_signed__part87;

architecture Cookbook__lc_mult_signed__part87_behav of Cookbook__lc_mult_signed__part87 is
begin
    po193 <= ( lo073 );
end Cookbook__lc_mult_signed__part87_behav;
