--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1891 is 
  Port (
    lo6829: in std_logic;
    n34460_1: inout std_logic
  );
end IWLS2005__des_perf__part1891;

architecture IWLS2005__des_perf__part1891_behav of IWLS2005__des_perf__part1891 is
begin
    n34460_1 <= ( lo6829 );
end IWLS2005__des_perf__part1891_behav;
