--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part121 is 
  Port (
    lo0235: in std_logic;
    n5641: inout std_logic
  );
end Other__ucsb_152_tap_fir__part121;

architecture Other__ucsb_152_tap_fir__part121_behav of Other__ucsb_152_tap_fir__part121 is
begin
    n5641 <= ( lo0235 );
end Other__ucsb_152_tap_fir__part121_behav;
