--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part798 is 
  Port (
    lo4167: in std_logic;
    n14464: inout std_logic
  );
end Other__sudoku_check__part798;

architecture Other__sudoku_check__part798_behav of Other__sudoku_check__part798 is
begin
    n14464 <= ( lo4167 );
end Other__sudoku_check__part798_behav;
