--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part172 is 
  Port (
    pi0602: in std_logic;
    n44056_1: inout std_logic
  );
end Other__radar__part172;

architecture Other__radar__part172_behav of Other__radar__part172 is
begin
    n44056_1 <= ( pi0602 );
end Other__radar__part172_behav;
