--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part370 is 
  Port (
    lo1369: in std_logic;
    n8104: inout std_logic
  );
end Cookbook__ucrypt__part370;

architecture Cookbook__ucrypt__part370_behav of Cookbook__ucrypt__part370 is
begin
    n8104 <= ( lo1369 );
end Cookbook__ucrypt__part370_behav;
