--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part35 is 
  Port (
    pi035: in std_logic;
    n9824_1: inout std_logic
  );
end Other__desperf__part35;

architecture Other__desperf__part35_behav of Other__desperf__part35 is
begin
    n9824_1 <= ( pi035 );
end Other__desperf__part35_behav;
