--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part565 is 
  Port (
    lo3214: in std_logic;
    n10569: inout std_logic
  );
end Other__sudoku_check__part565;

architecture Other__sudoku_check__part565_behav of Other__sudoku_check__part565 is
begin
    n10569 <= ( lo3214 );
end Other__sudoku_check__part565_behav;
