--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1496 is 
  Port (
    lo5593,lo5594,lo5595,lo5596: in std_logic;
    n27099_1,n29264,n29269,n29274,n29279,n29284_1,n29289,n29294,n29479_1: inout std_logic
  );
end Other__sudoku_check__part1496;

architecture Other__sudoku_check__part1496_behav of Other__sudoku_check__part1496 is
begin
    n27099_1 <= ( lo5593 and not lo5594 and not lo5595 and not lo5596 );
    n29264 <= ( not lo5593 and not lo5594 and not lo5595 and lo5596 );
    n29269 <= ( lo5593 and lo5594 and lo5595 and not lo5596 );
    n29274 <= ( not lo5593 and lo5594 and lo5595 and not lo5596 );
    n29279 <= ( lo5593 and not lo5594 and lo5595 and not lo5596 );
    n29284_1 <= ( not lo5593 and not lo5594 and lo5595 and not lo5596 );
    n29289 <= ( lo5593 and lo5594 and not lo5595 and not lo5596 );
    n29294 <= ( not lo5593 and lo5594 and not lo5595 and not lo5596 );
    n29479_1 <= ( lo5593 and not lo5594 and not lo5595 and lo5596 );
end Other__sudoku_check__part1496_behav;
