--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part70 is 
  Port (
    lo056: in std_logic;
    po210: inout std_logic
  );
end Cookbook__lc_mult_signed__part70;

architecture Cookbook__lc_mult_signed__part70_behav of Cookbook__lc_mult_signed__part70 is
begin
    po210 <= ( lo056 );
end Cookbook__lc_mult_signed__part70_behav;
