--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1071 is 
  Port (
    lo5112: in std_logic;
    n25485: inout std_logic
  );
end IWLS2005__des_perf__part1071;

architecture IWLS2005__des_perf__part1071_behav of IWLS2005__des_perf__part1071 is
begin
    n25485 <= ( lo5112 );
end IWLS2005__des_perf__part1071_behav;
