--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2237 is 
  Port (
    lo4958: in std_logic;
    n29376: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2237;

architecture Other__ucsb_152_tap_fir__part2237_behav of Other__ucsb_152_tap_fir__part2237 is
begin
    n29376 <= ( lo4958 );
end Other__ucsb_152_tap_fir__part2237_behav;
