--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part210 is 
  Port (
    lo0532: in std_logic;
    n2269: inout std_logic
  );
end Other__desperf__part210;

architecture Other__desperf__part210_behav of Other__desperf__part210 is
begin
    n2269 <= ( lo0532 );
end Other__desperf__part210_behav;
