--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1765 is 
  Port (
    lo8836: in std_logic;
    po291: inout std_logic
  );
end Other__carpat__part1765;

architecture Other__carpat__part1765_behav of Other__carpat__part1765 is
begin
    po291 <= ( lo8836 );
end Other__carpat__part1765_behav;
