--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part158 is 
  Port (
    lo1068: in std_logic;
    n6074: inout std_logic
  );
end IWLS93__s38417__part158;

architecture IWLS93__s38417__part158_behav of IWLS93__s38417__part158 is
begin
    n6074 <= ( lo1068 );
end IWLS93__s38417__part158_behav;
