--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1713 is 
  Port (
    lo3863: in std_logic;
    n23896: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1713;

architecture Other__ucsb_152_tap_fir__part1713_behav of Other__ucsb_152_tap_fir__part1713 is
begin
    n23896 <= ( lo3863 );
end Other__ucsb_152_tap_fir__part1713_behav;
