--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part70 is 
  Port (
    lo133: in std_logic;
    po003: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part70;

architecture Cookbook__soft_ecc_ram_64bit__part70_behav of Cookbook__soft_ecc_ram_64bit__part70 is
begin
    po003 <= ( lo133 );
end Cookbook__soft_ecc_ram_64bit__part70_behav;
