--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part91 is 
  Port (
    lo077: in std_logic;
    po189: inout std_logic
  );
end Cookbook__lc_mult_signed__part91;

architecture Cookbook__lc_mult_signed__part91_behav of Cookbook__lc_mult_signed__part91 is
begin
    po189 <= ( lo077 );
end Cookbook__lc_mult_signed__part91_behav;
