--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2214 is 
  Port (
    lo2283: in std_logic;
    n11714: inout std_logic
  );
end Cookbook__fec_check__part2214;

architecture Cookbook__fec_check__part2214_behav of Cookbook__fec_check__part2214 is
begin
    n11714 <= ( lo2283 );
end Cookbook__fec_check__part2214_behav;
