--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part886 is 
  Port (
    lo6722: in std_logic;
    n32824: inout std_logic
  );
end Other__carpat__part886;

architecture Other__carpat__part886_behav of Other__carpat__part886 is
begin
    n32824 <= ( lo6722 );
end Other__carpat__part886_behav;
