--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1359 is 
  Port (
    lo7809: in std_logic;
    n43924_1: inout std_logic
  );
end Other__carpat__part1359;

architecture Other__carpat__part1359_behav of Other__carpat__part1359 is
begin
    n43924_1 <= ( lo7809 );
end Other__carpat__part1359_behav;
