--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part16 is 
  Port (
    pi1108: in std_logic;
    n51251_1: inout std_logic
  );
end Other__ray__part16;

architecture Other__ray__part16_behav of Other__ray__part16 is
begin
    n51251_1 <= ( pi1108 );
end Other__ray__part16_behav;
