--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part387 is 
  Port (
    lo0001: in std_logic;
    po001: inout std_logic
  );
end Other__carpat__part387;

architecture Other__carpat__part387_behav of Other__carpat__part387 is
begin
    po001 <= ( lo0001 );
end Other__carpat__part387_behav;
