--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1824 is 
  Port (
    lo9070: in std_logic;
    po455: inout std_logic
  );
end Other__carpat__part1824;

architecture Other__carpat__part1824_behav of Other__carpat__part1824 is
begin
    po455 <= ( lo9070 );
end Other__carpat__part1824_behav;
