--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1505 is 
  Port (
    lo3421: in std_logic;
    n21606: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1505;

architecture Other__ucsb_152_tap_fir__part1505_behav of Other__ucsb_152_tap_fir__part1505 is
begin
    n21606 <= ( lo3421 );
end Other__ucsb_152_tap_fir__part1505_behav;
