--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part695 is 
  Port (
    lo4374: in std_logic;
    n22040: inout std_logic
  );
end IWLS2005__des_perf__part695;

architecture IWLS2005__des_perf__part695_behav of IWLS2005__des_perf__part695 is
begin
    n22040 <= ( lo4374 );
end IWLS2005__des_perf__part695_behav;
