--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part514 is 
  Port (
    lo4096: in std_logic;
    n20725: inout std_logic
  );
end IWLS2005__des_perf__part514;

architecture IWLS2005__des_perf__part514_behav of IWLS2005__des_perf__part514 is
begin
    n20725 <= ( lo4096 );
end IWLS2005__des_perf__part514_behav;
