--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1581 is 
  Port (
    lo1650: in std_logic;
    n8549: inout std_logic
  );
end Cookbook__fec_check__part1581;

architecture Cookbook__fec_check__part1581_behav of Cookbook__fec_check__part1581 is
begin
    n8549 <= ( lo1650 );
end Cookbook__fec_check__part1581_behav;
