--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part208 is 
  Port (
    lo0911,lo0912: in std_logic;
    n6400,n6420,n6430,n6440,n6470,n6565,n6575,n6405,n9430_1: inout std_logic
  );
end Other__fp_operators__part208;

architecture Other__fp_operators__part208_behav of Other__fp_operators__part208 is
signal n6520,n24870,n24895: std_logic;
begin
    n6400 <= ( not lo0911 and lo0912 )
      or ( lo0911 and not lo0912 );
    n6520 <= ( lo0911 and lo0912 );
    n6420 <= ( not lo0911 and not lo0912 and n6520 )
      or ( not lo0911 and lo0912 and not n6520 )
      or ( lo0911 and not lo0912 and not n6520 )
      or ( lo0911 and lo0912 and n6520 );
    n6430 <= ( lo0912 and not n6520 );
    n24870 <= ( lo0912 and n6520 );
    n6440 <= ( lo0911 and not n24870 );
    n24895 <= ( lo0911 and n24870 );
    n6470 <= ( lo0912 and not n24895 );
    n6565 <= ( lo0911 and not n6520 );
    n6575 <= ( not lo0911 and lo0912 );
    n6405 <= ( lo0911 );
    n9430_1 <= ( lo0912 );
end Other__fp_operators__part208_behav;
