--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1991 is 
  Port (
    lo7026: in std_logic;
    n35670_1: inout std_logic
  );
end IWLS2005__des_perf__part1991;

architecture IWLS2005__des_perf__part1991_behav of IWLS2005__des_perf__part1991 is
begin
    n35670_1 <= ( lo7026 );
end IWLS2005__des_perf__part1991_behav;
