--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1562 is 
  Port (
    lo5857,lo5858,lo5859,lo5860: in std_logic;
    n27864_1,n29394,n29579,n29759,n29939_1,n30119,n30299,n30479,n30659: inout std_logic
  );
end Other__sudoku_check__part1562;

architecture Other__sudoku_check__part1562_behav of Other__sudoku_check__part1562 is
begin
    n27864_1 <= ( lo5857 and not lo5858 and not lo5859 and not lo5860 );
    n29394 <= ( lo5857 and not lo5858 and not lo5859 and lo5860 );
    n29579 <= ( not lo5857 and not lo5858 and not lo5859 and lo5860 );
    n29759 <= ( lo5857 and lo5858 and lo5859 and not lo5860 );
    n29939_1 <= ( not lo5857 and lo5858 and lo5859 and not lo5860 );
    n30119 <= ( lo5857 and not lo5858 and lo5859 and not lo5860 );
    n30299 <= ( not lo5857 and not lo5858 and lo5859 and not lo5860 );
    n30479 <= ( lo5857 and lo5858 and not lo5859 and not lo5860 );
    n30659 <= ( not lo5857 and lo5858 and not lo5859 and not lo5860 );
end Other__sudoku_check__part1562_behav;
