--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part220 is 
  Port (
    lo03270: in std_logic;
    po1247: inout std_logic
  );
end Other__ray__part220;

architecture Other__ray__part220_behav of Other__ray__part220 is
begin
    po1247 <= ( lo03270 );
end Other__ray__part220_behav;
