--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part61 is 
  Port (
    lo60: in std_logic;
    po60: inout std_logic
  );
end Other__idxlat02n_m12__part61;

architecture Other__idxlat02n_m12__part61_behav of Other__idxlat02n_m12__part61 is
begin
    po60 <= ( lo60 );
end Other__idxlat02n_m12__part61_behav;
