--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part9 is 
  Port (
    pi027,pi091,pi026,pi090,pi025,pi089: in std_logic;
    n349: inout std_logic
  );
end Cookbook__pipe_equal__part9;

architecture Cookbook__pipe_equal__part9_behav of Cookbook__pipe_equal__part9 is
signal n273,n274,n275,n276: std_logic;
begin
    n273 <= ( not pi027 and pi091 )
      or ( pi027 and not pi091 );
    n274 <= ( not pi026 and pi090 )
      or ( pi026 and not pi090 );
    n275 <= ( not pi025 and pi089 )
      or ( pi025 and not pi089 );
    n276 <= not (( not n274 and not n275 ));
    n349 <= ( not n273 and not n276 );
end Cookbook__pipe_equal__part9_behav;
