--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1195 is 
  Port (
    lo7442: in std_logic;
    n41389_1: inout std_logic
  );
end Other__carpat__part1195;

architecture Other__carpat__part1195_behav of Other__carpat__part1195 is
begin
    n41389_1 <= ( lo7442 );
end Other__carpat__part1195_behav;
