--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2910 is 
  Port (
    lo8223: in std_logic;
    n41410: inout std_logic
  );
end IWLS2005__des_perf__part2910;

architecture IWLS2005__des_perf__part2910_behav of IWLS2005__des_perf__part2910 is
begin
    n41410 <= ( lo8223 );
end IWLS2005__des_perf__part2910_behav;
