--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1649 is 
  Port (
    lo8441: in std_logic;
    n47504_1: inout std_logic
  );
end Other__carpat__part1649;

architecture Other__carpat__part1649_behav of Other__carpat__part1649 is
begin
    n47504_1 <= ( lo8441 );
end Other__carpat__part1649_behav;
