--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part234 is 
  Port (
    lo0785: in std_logic;
    n5184: inout std_logic
  );
end Cookbook__ucrypt__part234;

architecture Cookbook__ucrypt__part234_behav of Cookbook__ucrypt__part234 is
begin
    n5184 <= ( lo0785 );
end Cookbook__ucrypt__part234_behav;
