--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part118 is 
  Port (
    pi0528: in std_logic;
    n43186_1: inout std_logic
  );
end Other__radar__part118;

architecture Other__radar__part118_behav of Other__radar__part118 is
begin
    n43186_1 <= ( pi0528 );
end Other__radar__part118_behav;
