--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part569 is 
  Port (
    lo06050: in std_logic;
    n38341: inout std_logic
  );
end Other__ray__part569;

architecture Other__ray__part569_behav of Other__ray__part569 is
begin
    n38341 <= ( lo06050 );
end Other__ray__part569_behav;
