--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part62 is 
  Port (
    lo229: in std_logic;
    po21: inout std_logic
  );
end Cookbook__gearbox_67_40__part62;

architecture Cookbook__gearbox_67_40__part62_behav of Cookbook__gearbox_67_40__part62 is
begin
    po21 <= ( lo229 );
end Cookbook__gearbox_67_40__part62_behav;
