--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s9234__part3 is 
  Port (
    lo003: in std_logic;
    n88,n788,n803: inout std_logic
  );
end ISCAS__s9234__part3;

architecture ISCAS__s9234__part3_behav of ISCAS__s9234__part3 is
begin
    n88 <= ( lo003 );
    n788 <= ( lo003 );
    n803 <= ( lo003 );
end ISCAS__s9234__part3_behav;
