--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1056 is 
  Port (
    lo5096: in std_logic;
    n25380: inout std_logic
  );
end IWLS2005__des_perf__part1056;

architecture IWLS2005__des_perf__part1056_behav of IWLS2005__des_perf__part1056 is
begin
    n25380 <= ( lo5096 );
end IWLS2005__des_perf__part1056_behav;
