--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part124 is 
  Port (
    lo0004: in std_logic;
    po04: inout std_logic
  );
end Other__desperf__part124;

architecture Other__desperf__part124_behav of Other__desperf__part124 is
begin
    po04 <= ( lo0004 );
end Other__desperf__part124_behav;
