--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part372 is 
  Port (
    lo0441: in std_logic;
    n2504: inout std_logic
  );
end Cookbook__fec_check__part372;

architecture Cookbook__fec_check__part372_behav of Cookbook__fec_check__part372 is
begin
    n2504 <= ( lo0441 );
end Cookbook__fec_check__part372_behav;
