--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part868 is 
  Port (
    lo0937: in std_logic;
    n4984: inout std_logic
  );
end Cookbook__fec_check__part868;

architecture Cookbook__fec_check__part868_behav of Cookbook__fec_check__part868 is
begin
    n4984 <= ( lo0937 );
end Cookbook__fec_check__part868_behav;
