--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1863 is 
  Port (
    lo9136: in std_logic;
    po500: inout std_logic
  );
end Other__carpat__part1863;

architecture Other__carpat__part1863_behav of Other__carpat__part1863 is
begin
    po500 <= ( lo9136 );
end Other__carpat__part1863_behav;
