--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part438 is 
  Port (
    lo3087: in std_logic;
    n9299: inout std_logic
  );
end Other__sudoku_check__part438;

architecture Other__sudoku_check__part438_behav of Other__sudoku_check__part438 is
begin
    n9299 <= ( lo3087 );
end Other__sudoku_check__part438_behav;
