--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1352 is 
  Port (
    lo1421: in std_logic;
    n7404: inout std_logic
  );
end Cookbook__fec_check__part1352;

architecture Cookbook__fec_check__part1352_behav of Cookbook__fec_check__part1352 is
begin
    n7404 <= ( lo1421 );
end Cookbook__fec_check__part1352_behav;
