--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part132 is 
  Port (
    lo0459: in std_logic;
    n3554: inout std_logic
  );
end Cookbook__ucrypt__part132;

architecture Cookbook__ucrypt__part132_behav of Cookbook__ucrypt__part132 is
begin
    n3554 <= ( lo0459 );
end Cookbook__ucrypt__part132_behav;
