--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part525 is 
  Port (
    lo3264: in std_logic;
    n15439: inout std_logic
  );
end Other__carpat__part525;

architecture Other__carpat__part525_behav of Other__carpat__part525 is
begin
    n15439 <= ( lo3264 );
end Other__carpat__part525_behav;
