--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1413 is 
  Port (
    lo3241: in std_logic;
    n20781: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1413;

architecture Other__ucsb_152_tap_fir__part1413_behav of Other__ucsb_152_tap_fir__part1413 is
begin
    n20781 <= ( lo3241 );
end Other__ucsb_152_tap_fir__part1413_behav;
