--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part450 is 
  Port (
    lo3099: in std_logic;
    n9419: inout std_logic
  );
end Other__sudoku_check__part450;

architecture Other__sudoku_check__part450_behav of Other__sudoku_check__part450 is
begin
    n9419 <= ( lo3099 );
end Other__sudoku_check__part450_behav;
