--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part948 is 
  Port (
    lo10529: in std_logic;
    n69186_1: inout std_logic
  );
end Other__ray__part948;

architecture Other__ray__part948_behav of Other__ray__part948 is
begin
    n69186_1 <= ( lo10529 );
end Other__ray__part948_behav;
