--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1029 is 
  Port (
    lo2422: in std_logic;
    n16691: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1029;

architecture Other__ucsb_152_tap_fir__part1029_behav of Other__ucsb_152_tap_fir__part1029 is
begin
    n16691 <= ( lo2422 );
end Other__ucsb_152_tap_fir__part1029_behav;
