--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part263 is 
  Port (
    lo447: in std_logic;
    n1542: inout std_logic
  );
end Other__fpu__part263;

architecture Other__fpu__part263_behav of Other__fpu__part263 is
begin
    n1542 <= ( lo447 );
end Other__fpu__part263_behav;
