--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part789 is 
  Port (
    lo06516: in std_logic;
    n48906_1: inout std_logic
  );
end Other__ray__part789;

architecture Other__ray__part789_behav of Other__ray__part789 is
begin
    n48906_1 <= ( lo06516 );
end Other__ray__part789_behav;
