--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part63 is 
  Port (
    lo032: in std_logic;
    n644: inout std_logic
  );
end Cookbook__gearbox_40_67__part63;

architecture Cookbook__gearbox_40_67__part63_behav of Cookbook__gearbox_40_67__part63 is
begin
    n644 <= ( lo032 );
end Cookbook__gearbox_40_67__part63_behav;
