--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_20__part33 is 
  Port (
    lo107: in std_logic;
    po08: inout std_logic
  );
end Cookbook__gearbox_66_20__part33;

architecture Cookbook__gearbox_66_20__part33_behav of Cookbook__gearbox_66_20__part33 is
begin
    po08 <= ( lo107 );
end Cookbook__gearbox_66_20__part33_behav;
