--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part3 is 
  Port (
    pi03: in std_logic;
    n153: inout std_logic
  );
end Cookbook__pipeline_add_msb__part3;

architecture Cookbook__pipeline_add_msb__part3_behav of Cookbook__pipeline_add_msb__part3 is
begin
    n153 <= ( pi03 );
end Cookbook__pipeline_add_msb__part3_behav;
