--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1509 is 
  Port (
    lo8140: in std_logic;
    n44749_1: inout std_logic
  );
end Other__carpat__part1509;

architecture Other__carpat__part1509_behav of Other__carpat__part1509 is
begin
    n44749_1 <= ( lo8140 );
end Other__carpat__part1509_behav;
