--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1582 is 
  Port (
    lo3581: in std_logic;
    n22491: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1582;

architecture Other__ucsb_152_tap_fir__part1582_behav of Other__ucsb_152_tap_fir__part1582 is
begin
    n22491 <= ( lo3581 );
end Other__ucsb_152_tap_fir__part1582_behav;
