--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part933 is 
  Port (
    lo4852: in std_logic;
    n24135: inout std_logic
  );
end IWLS2005__des_perf__part933;

architecture IWLS2005__des_perf__part933_behav of IWLS2005__des_perf__part933 is
begin
    n24135 <= ( lo4852 );
end IWLS2005__des_perf__part933_behav;
