--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part907 is 
  Port (
    lo09812: in std_logic;
    n64971_1: inout std_logic
  );
end Other__ray__part907;

architecture Other__ray__part907_behav of Other__ray__part907 is
begin
    n64971_1 <= ( lo09812 );
end Other__ray__part907_behav;
