--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1286 is 
  Port (
    lo7725: in std_logic;
    n42614_1: inout std_logic
  );
end Other__carpat__part1286;

architecture Other__carpat__part1286_behav of Other__carpat__part1286 is
begin
    n42614_1 <= ( lo7725 );
end Other__carpat__part1286_behav;
