--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1186 is 
  Port (
    lo5361: in std_logic;
    n26285: inout std_logic
  );
end IWLS2005__des_perf__part1186;

architecture IWLS2005__des_perf__part1186_behav of IWLS2005__des_perf__part1186 is
begin
    n26285 <= ( lo5361 );
end IWLS2005__des_perf__part1186_behav;
