--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part3 is 
  Port (
    lo02: in std_logic;
    po06: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part3;

architecture Cookbook__x4_decoder_8b10b__part3_behav of Cookbook__x4_decoder_8b10b__part3 is
begin
    po06 <= ( lo02 );
end Cookbook__x4_decoder_8b10b__part3_behav;
