--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part68 is 
  Port (
    lo0137: in std_logic;
    n984: inout std_logic
  );
end Cookbook__fec_check__part68;

architecture Cookbook__fec_check__part68_behav of Cookbook__fec_check__part68 is
begin
    n984 <= ( lo0137 );
end Cookbook__fec_check__part68_behav;
