--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part806 is 
  Port (
    lo4579: in std_logic;
    n23145: inout std_logic
  );
end IWLS2005__des_perf__part806;

architecture IWLS2005__des_perf__part806_behav of IWLS2005__des_perf__part806 is
begin
    n23145 <= ( lo4579 );
end IWLS2005__des_perf__part806_behav;
