--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3321 is 
  Port (
    lo8708: in std_logic;
    n43650_1: inout std_logic
  );
end IWLS2005__des_perf__part3321;

architecture IWLS2005__des_perf__part3321_behav of IWLS2005__des_perf__part3321 is
begin
    n43650_1 <= ( lo8708 );
end IWLS2005__des_perf__part3321_behav;
