--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2333 is 
  Port (
    lo5172: in std_logic;
    n30366: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2333;

architecture Other__ucsb_152_tap_fir__part2333_behav of Other__ucsb_152_tap_fir__part2333 is
begin
    n30366 <= ( lo5172 );
end Other__ucsb_152_tap_fir__part2333_behav;
