--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part530 is 
  Port (
    lo4113: in std_logic;
    n20635: inout std_logic
  );
end IWLS2005__des_perf__part530;

architecture IWLS2005__des_perf__part530_behav of IWLS2005__des_perf__part530 is
begin
    n20635 <= ( lo4113 );
end IWLS2005__des_perf__part530_behav;
