--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part965 is 
  Port (
    lo4924: in std_logic;
    n24755: inout std_logic
  );
end IWLS2005__des_perf__part965;

architecture IWLS2005__des_perf__part965_behav of IWLS2005__des_perf__part965 is
begin
    n24755 <= ( lo4924 );
end IWLS2005__des_perf__part965_behav;
