--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part1 is 
  Port (
    pi04: in std_logic;
    n937: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part1;

architecture Cookbook__ycbcr_to_rgb__part1_behav of Cookbook__ycbcr_to_rgb__part1 is
begin
    n937 <= ( pi04 );
end Cookbook__ycbcr_to_rgb__part1_behav;
