--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part402 is 
  Port (
    lo3051: in std_logic;
    n8939: inout std_logic
  );
end Other__sudoku_check__part402;

architecture Other__sudoku_check__part402_behav of Other__sudoku_check__part402 is
begin
    n8939 <= ( lo3051 );
end Other__sudoku_check__part402_behav;
