--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1,po2: inout std_logic
  );
end top;

architecture top_behav of top is
signal n9: std_logic;
begin
    po2 <= ( not pi4 and not pi2 and pi3 )
      or ( not pi4 and pi2 and not pi3 )
      or ( pi4 and not pi2 and not pi3 )
      or ( pi4 and pi2 and pi3 );
    n9 <= ( pi4 and pi2 )
      or ( pi4 and pi3 )
      or ( pi2 and pi3 );
    po1 <= ( not n9 and not pi0 and pi1 )
      or ( not n9 and pi0 and not pi1 )
      or ( n9 and not pi0 and not pi1 )
      or ( n9 and pi0 and pi1 );
    po0 <= ( n9 and pi0 )
      or ( n9 and pi1 )
      or ( pi0 and pi1 );
end top_behav;
