--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part79 is 
  Port (
    lo313: in std_logic;
    po072: inout std_logic
  );
end IWLS2005__aes_core__part79;

architecture IWLS2005__aes_core__part79_behav of IWLS2005__aes_core__part79 is
begin
    po072 <= ( lo313 );
end IWLS2005__aes_core__part79_behav;
