--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part539 is 
  Port (
    lo0608: in std_logic;
    n3339: inout std_logic
  );
end Cookbook__fec_check__part539;

architecture Cookbook__fec_check__part539_behav of Cookbook__fec_check__part539 is
begin
    n3339 <= ( lo0608 );
end Cookbook__fec_check__part539_behav;
