--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1225 is 
  Port (
    lo1294: in std_logic;
    n6769: inout std_logic
  );
end Cookbook__fec_check__part1225;

architecture Cookbook__fec_check__part1225_behav of Cookbook__fec_check__part1225 is
begin
    n6769 <= ( lo1294 );
end Cookbook__fec_check__part1225_behav;
