--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part223 is 
  Port (
    lo1517: in std_logic;
    n41056_1: inout std_logic
  );
end Other__radar__part223;

architecture Other__radar__part223_behav of Other__radar__part223 is
begin
    n41056_1 <= ( lo1517 );
end Other__radar__part223_behav;
