--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1372 is 
  Port (
    lo5798: in std_logic;
    n29055_1: inout std_logic
  );
end IWLS2005__des_perf__part1372;

architecture IWLS2005__des_perf__part1372_behav of IWLS2005__des_perf__part1372 is
begin
    n29055_1 <= ( lo5798 );
end IWLS2005__des_perf__part1372_behav;
