--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2258 is 
  Port (
    lo2358: in std_logic;
    n12089: inout std_logic
  );
end Cookbook__fec_check__part2258;

architecture Cookbook__fec_check__part2258_behav of Cookbook__fec_check__part2258 is
begin
    n12089 <= ( lo2358 );
end Cookbook__fec_check__part2258_behav;
