--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part50 is 
  Port (
    pi56: in std_logic;
    n869226: inout std_logic
  );
end IWLS2005__leon3__part50;

architecture IWLS2005__leon3__part50_behav of IWLS2005__leon3__part50 is
begin
    n869226 <= ( pi56 );
end IWLS2005__leon3__part50_behav;
