--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part258 is 
  Port (
    lo03622: in std_logic;
    n36121: inout std_logic
  );
end Other__ray__part258;

architecture Other__ray__part258_behav of Other__ray__part258 is
begin
    n36121 <= ( lo03622 );
end Other__ray__part258_behav;
