--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part235 is 
  Port (
    lo0304: in std_logic;
    n1819: inout std_logic
  );
end Cookbook__fec_check__part235;

architecture Cookbook__fec_check__part235_behav of Cookbook__fec_check__part235 is
begin
    n1819 <= ( lo0304 );
end Cookbook__fec_check__part235_behav;
