--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part582 is 
  Port (
    lo4187: in std_logic;
    n21305: inout std_logic
  );
end IWLS2005__des_perf__part582;

architecture IWLS2005__des_perf__part582_behav of IWLS2005__des_perf__part582 is
begin
    n21305 <= ( lo4187 );
end IWLS2005__des_perf__part582_behav;
