--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part404 is 
  Port (
    lo0473: in std_logic;
    n2664: inout std_logic
  );
end Cookbook__fec_check__part404;

architecture Cookbook__fec_check__part404_behav of Cookbook__fec_check__part404 is
begin
    n2664 <= ( lo0473 );
end Cookbook__fec_check__part404_behav;
