--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part82 is 
  Port (
    lo158070: in std_logic;
    po21: inout std_logic
  );
end IWLS2005__leon3__part82;

architecture IWLS2005__leon3__part82_behav of IWLS2005__leon3__part82 is
begin
    po21 <= ( lo158070 );
end IWLS2005__leon3__part82_behav;
