--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1385 is 
  Port (
    lo4754: in std_logic;
    n19259_1: inout std_logic
  );
end Other__sudoku_check__part1385;

architecture Other__sudoku_check__part1385_behav of Other__sudoku_check__part1385 is
begin
    n19259_1 <= ( lo4754 );
end Other__sudoku_check__part1385_behav;
