--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2939 is 
  Port (
    lo8252: in std_logic;
    n41415: inout std_logic
  );
end IWLS2005__des_perf__part2939;

architecture IWLS2005__des_perf__part2939_behav of IWLS2005__des_perf__part2939 is
begin
    n41415 <= ( lo8252 );
end IWLS2005__des_perf__part2939_behav;
