--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part19 is 
  Port (
    lo0119: in std_logic;
    po085: inout std_logic
  );
end Other__cfft__part19;

architecture Other__cfft__part19_behav of Other__cfft__part19 is
begin
    po085 <= ( lo0119 );
end Other__cfft__part19_behav;
