--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part240 is 
  Port (
    lo0948: in std_logic;
    n4289: inout std_logic
  );
end Other__desperf__part240;

architecture Other__desperf__part240_behav of Other__desperf__part240 is
begin
    n4289 <= ( lo0948 );
end Other__desperf__part240_behav;
