--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1312 is 
  Port (
    lo3032: in std_logic;
    n19656: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1312;

architecture Other__ucsb_152_tap_fir__part1312_behav of Other__ucsb_152_tap_fir__part1312 is
begin
    n19656 <= ( lo3032 );
end Other__ucsb_152_tap_fir__part1312_behav;
