--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1081 is 
  Port (
    lo5157: in std_logic;
    n26115: inout std_logic
  );
end IWLS2005__des_perf__part1081;

architecture IWLS2005__des_perf__part1081_behav of IWLS2005__des_perf__part1081 is
begin
    n26115 <= ( lo5157 );
end IWLS2005__des_perf__part1081_behav;
