--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3223 is 
  Port (
    lo8564: in std_logic;
    n42850_1: inout std_logic
  );
end IWLS2005__des_perf__part3223;

architecture IWLS2005__des_perf__part3223_behav of IWLS2005__des_perf__part3223 is
begin
    n42850_1 <= ( lo8564 );
end IWLS2005__des_perf__part3223_behav;
