--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1760 is 
  Port (
    lo3998: in std_logic;
    n24501: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1760;

architecture Other__ucsb_152_tap_fir__part1760_behav of Other__ucsb_152_tap_fir__part1760 is
begin
    n24501 <= ( lo3998 );
end Other__ucsb_152_tap_fir__part1760_behav;
