--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1036 is 
  Port (
    lo10771: in std_logic;
    n72196_1: inout std_logic
  );
end Other__ray__part1036;

architecture Other__ray__part1036_behav of Other__ray__part1036 is
begin
    n72196_1 <= ( lo10771 );
end Other__ray__part1036_behav;
