--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part286 is 
  Port (
    lo03676: in std_logic;
    po6176,po6227,po6482,po6533: inout std_logic
  );
end Other__ray__part286;

architecture Other__ray__part286_behav of Other__ray__part286 is
begin
    po6176 <= ( lo03676 );
    po6227 <= ( lo03676 );
    po6482 <= ( lo03676 );
    po6533 <= ( lo03676 );
end Other__ray__part286_behav;
