--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1536 is 
  Port (
    lo6123: in std_logic;
    n30935_1: inout std_logic
  );
end IWLS2005__des_perf__part1536;

architecture IWLS2005__des_perf__part1536_behav of IWLS2005__des_perf__part1536 is
begin
    n30935_1 <= ( lo6123 );
end IWLS2005__des_perf__part1536_behav;
