--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part700 is 
  Port (
    lo06197: in std_logic;
    n46906: inout std_logic
  );
end Other__ray__part700;

architecture Other__ray__part700_behav of Other__ray__part700 is
begin
    n46906 <= ( lo06197 );
end Other__ray__part700_behav;
