--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part220 is 
  Port (
    lo1062: in std_logic;
    n6785_1: inout std_logic
  );
end Other__fp_operators__part220;

architecture Other__fp_operators__part220_behav of Other__fp_operators__part220 is
begin
    n6785_1 <= ( lo1062 );
end Other__fp_operators__part220_behav;
