--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part923 is 
  Port (
    lo4839: in std_logic;
    n24015: inout std_logic
  );
end IWLS2005__des_perf__part923;

architecture IWLS2005__des_perf__part923_behav of IWLS2005__des_perf__part923 is
begin
    n24015 <= ( lo4839 );
end IWLS2005__des_perf__part923_behav;
