--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part418 is 
  Port (
    lo1529: in std_logic;
    n8904_1: inout std_logic
  );
end Cookbook__ucrypt__part418;

architecture Cookbook__ucrypt__part418_behav of Cookbook__ucrypt__part418 is
begin
    n8904_1 <= ( lo1529 );
end Cookbook__ucrypt__part418_behav;
