--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part8 is 
  Port (
    lo2117: in std_logic;
    n5357: inout std_logic
  );
end Other__top_rs_decode__part8;

architecture Other__top_rs_decode__part8_behav of Other__top_rs_decode__part8 is
begin
    n5357 <= ( lo2117 );
end Other__top_rs_decode__part8_behav;
