--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1564 is 
  Port (
    lo1633: in std_logic;
    n8464: inout std_logic
  );
end Cookbook__fec_check__part1564;

architecture Cookbook__fec_check__part1564_behav of Cookbook__fec_check__part1564 is
begin
    n8464 <= ( lo1633 );
end Cookbook__fec_check__part1564_behav;
