--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part519 is 
  Port (
    lo4101: in std_logic;
    n20595: inout std_logic
  );
end IWLS2005__des_perf__part519;

architecture IWLS2005__des_perf__part519_behav of IWLS2005__des_perf__part519 is
begin
    n20595 <= ( lo4101 );
end IWLS2005__des_perf__part519_behav;
