--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1733 is 
  Port (
    lo3924: in std_logic;
    n24146: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1733;

architecture Other__ucsb_152_tap_fir__part1733_behav of Other__ucsb_152_tap_fir__part1733 is
begin
    n24146 <= ( lo3924 );
end Other__ucsb_152_tap_fir__part1733_behav;
