--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1227 is 
  Port (
    lo5439: in std_logic;
    n27110_1: inout std_logic
  );
end IWLS2005__des_perf__part1227;

architecture IWLS2005__des_perf__part1227_behav of IWLS2005__des_perf__part1227 is
begin
    n27110_1 <= ( lo5439 );
end IWLS2005__des_perf__part1227_behav;
