--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part104 is 
  Port (
    pi104: in std_logic;
    n2042: inout std_logic
  );
end Other__fpu__part104;

architecture Other__fpu__part104_behav of Other__fpu__part104 is
begin
    n2042 <= ( pi104 );
end Other__fpu__part104_behav;
