--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1065 is 
  Port (
    lo5106: in std_logic;
    n25365: inout std_logic
  );
end IWLS2005__des_perf__part1065;

architecture IWLS2005__des_perf__part1065_behav of IWLS2005__des_perf__part1065 is
begin
    n25365 <= ( lo5106 );
end IWLS2005__des_perf__part1065_behav;
