--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part67 is 
  Port (
    lo298: in std_logic;
    po058: inout std_logic
  );
end IWLS2005__aes_core__part67;

architecture IWLS2005__aes_core__part67_behav of IWLS2005__aes_core__part67 is
begin
    po058 <= ( lo298 );
end IWLS2005__aes_core__part67_behav;
