--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part453 is 
  Port (
    lo4002: in std_logic;
    n20415: inout std_logic
  );
end IWLS2005__des_perf__part453;

architecture IWLS2005__des_perf__part453_behav of IWLS2005__des_perf__part453 is
begin
    n20415 <= ( lo4002 );
end IWLS2005__des_perf__part453_behav;
