--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s1238__part2 is 
  Port (
    lo16: in std_logic;
    po12: inout std_logic
  );
end ISCAS__s1238__part2;

architecture ISCAS__s1238__part2_behav of ISCAS__s1238__part2 is
begin
    po12 <= ( lo16 );
end ISCAS__s1238__part2_behav;
