--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part948 is 
  Port (
    lo4868: in std_logic;
    n24225: inout std_logic
  );
end IWLS2005__des_perf__part948;

architecture IWLS2005__des_perf__part948_behav of IWLS2005__des_perf__part948 is
begin
    n24225 <= ( lo4868 );
end IWLS2005__des_perf__part948_behav;
