--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part478 is 
  Port (
    lo05950: in std_logic;
    po1416,po1465,po1749,po1811: inout std_logic
  );
end Other__ray__part478;

architecture Other__ray__part478_behav of Other__ray__part478 is
begin
    po1416 <= ( lo05950 );
    po1465 <= ( lo05950 );
    po1749 <= ( lo05950 );
    po1811 <= ( lo05950 );
end Other__ray__part478_behav;
