--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part181 is 
  Port (
    lo0429: in std_logic;
    n6626: inout std_logic
  );
end Other__ucsb_152_tap_fir__part181;

architecture Other__ucsb_152_tap_fir__part181_behav of Other__ucsb_152_tap_fir__part181 is
begin
    n6626 <= ( lo0429 );
end Other__ucsb_152_tap_fir__part181_behav;
