--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part459 is 
  Port (
    lo05931: in std_logic;
    po1397,po1431: inout std_logic
  );
end Other__ray__part459;

architecture Other__ray__part459_behav of Other__ray__part459 is
begin
    po1397 <= ( lo05931 );
    po1431 <= ( lo05931 );
end Other__ray__part459_behav;
