--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1761 is 
  Port (
    lo8832: in std_logic;
    po287: inout std_logic
  );
end Other__carpat__part1761;

architecture Other__carpat__part1761_behav of Other__carpat__part1761 is
begin
    po287 <= ( lo8832 );
end Other__carpat__part1761_behav;
