--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__adder_tree_node__part4 is 
  Port (
    lo02: in std_logic;
    po14: inout std_logic
  );
end Cookbook__adder_tree_node__part4;

architecture Cookbook__adder_tree_node__part4_behav of Cookbook__adder_tree_node__part4 is
begin
    po14 <= ( lo02 );
end Cookbook__adder_tree_node__part4_behav;
