--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part257 is 
  Port (
    pi1514: in std_logic;
    n44369_1: inout std_logic
  );
end Other__carpat__part257;

architecture Other__carpat__part257_behav of Other__carpat__part257 is
begin
    n44369_1 <= ( pi1514 );
end Other__carpat__part257_behav;
