--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part152 is 
  Port (
    lo0542: in std_logic;
    n5220: inout std_logic
  );
end Other__fp_operators__part152;

architecture Other__fp_operators__part152_behav of Other__fp_operators__part152 is
begin
    n5220 <= ( lo0542 );
end Other__fp_operators__part152_behav;
