--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fifo__part8 is 
  Port (
    lo068: in std_logic;
    po12: inout std_logic
  );
end Cookbook__fifo__part8;

architecture Cookbook__fifo__part8_behav of Cookbook__fifo__part8 is
begin
    po12 <= ( lo068 );
end Cookbook__fifo__part8_behav;
