--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part264 is 
  Port (
    lo03639: in std_logic;
    po6139,po6206,po6445,po6512: inout std_logic
  );
end Other__ray__part264;

architecture Other__ray__part264_behav of Other__ray__part264 is
begin
    po6139 <= ( lo03639 );
    po6206 <= ( lo03639 );
    po6445 <= ( lo03639 );
    po6512 <= ( lo03639 );
end Other__ray__part264_behav;
