--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1561 is 
  Port (
    lo8192: in std_logic;
    n46029_1: inout std_logic
  );
end Other__carpat__part1561;

architecture Other__carpat__part1561_behav of Other__carpat__part1561 is
begin
    n46029_1 <= ( lo8192 );
end Other__carpat__part1561_behav;
