--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part52 is 
  Port (
    lo0093: in std_logic;
    po073: inout std_logic
  );
end Other__fp_operators__part52;

architecture Other__fp_operators__part52_behav of Other__fp_operators__part52 is
begin
    po073 <= ( lo0093 );
end Other__fp_operators__part52_behav;
