--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1887 is 
  Port (
    lo1956: in std_logic;
    n10079: inout std_logic
  );
end Cookbook__fec_check__part1887;

architecture Cookbook__fec_check__part1887_behav of Cookbook__fec_check__part1887 is
begin
    n10079 <= ( lo1956 );
end Cookbook__fec_check__part1887_behav;
