--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1183 is 
  Port (
    lo5355: in std_logic;
    n26495: inout std_logic
  );
end IWLS2005__des_perf__part1183;

architecture IWLS2005__des_perf__part1183_behav of IWLS2005__des_perf__part1183 is
begin
    n26495 <= ( lo5355 );
end IWLS2005__des_perf__part1183_behav;
