--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part888 is 
  Port (
    lo6724: in std_logic;
    n32864_1: inout std_logic
  );
end Other__carpat__part888;

architecture Other__carpat__part888_behav of Other__carpat__part888 is
begin
    n32864_1 <= ( lo6724 );
end Other__carpat__part888_behav;
