--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part106 is 
  Port (
    lo092: in std_logic;
    po174: inout std_logic
  );
end Cookbook__lc_mult_signed__part106;

architecture Cookbook__lc_mult_signed__part106_behav of Cookbook__lc_mult_signed__part106 is
begin
    po174 <= ( lo092 );
end Cookbook__lc_mult_signed__part106_behav;
