--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1488 is 
  Port (
    lo1557: in std_logic;
    n8084: inout std_logic
  );
end Cookbook__fec_check__part1488;

architecture Cookbook__fec_check__part1488_behav of Cookbook__fec_check__part1488 is
begin
    n8084 <= ( lo1557 );
end Cookbook__fec_check__part1488_behav;
