--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1874 is 
  Port (
    lo4226: in std_logic;
    n25716: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1874;

architecture Other__ucsb_152_tap_fir__part1874_behav of Other__ucsb_152_tap_fir__part1874 is
begin
    n25716 <= ( lo4226 );
end Other__ucsb_152_tap_fir__part1874_behav;
