--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part319 is 
  Port (
    lo0388: in std_logic;
    n2239: inout std_logic
  );
end Cookbook__fec_check__part319;

architecture Cookbook__fec_check__part319_behav of Cookbook__fec_check__part319 is
begin
    n2239 <= ( lo0388 );
end Cookbook__fec_check__part319_behav;
