--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2447 is 
  Port (
    lo5387: in std_logic;
    n31531_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2447;

architecture Other__ucsb_152_tap_fir__part2447_behav of Other__ucsb_152_tap_fir__part2447 is
begin
    n31531_1 <= ( lo5387 );
end Other__ucsb_152_tap_fir__part2447_behav;
