--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part337 is 
  Port (
    lo1596,lo1597,lo1598: in std_logic;
    n11355_1,n11360_1,n11365_1,po265,po266,po267: inout std_logic
  );
end Other__fp_operators__part337;

architecture Other__fp_operators__part337_behav of Other__fp_operators__part337 is
signal n22594,n22595,n37122,n37123,n37124,n37125: std_logic;
begin
    n22594 <= ( not lo1596 and lo1597 and lo1598 );
    n22595 <= not (( not n37125 and not n22594 ));
    n11355_1 <= ( not lo1596 and not n22595 );
    n11360_1 <= ( not n22595 and n37122 );
    n11365_1 <= ( not n22595 and n37124 );
    n37122 <= ( not lo1597 and lo1596 )
      or ( lo1597 and not lo1596 );
    n37123 <= ( lo1597 and lo1596 );
    n37124 <= ( not lo1598 and n37123 )
      or ( lo1598 and not n37123 );
    n37125 <= ( lo1598 and n37123 );
    po265 <= ( lo1596 );
    po266 <= ( lo1597 );
    po267 <= ( lo1598 );
end Other__fp_operators__part337_behav;
