--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part267 is 
  Port (
    lo452: in std_logic;
    n1562: inout std_logic
  );
end Other__fpu__part267;

architecture Other__fpu__part267_behav of Other__fpu__part267 is
begin
    n1562 <= ( lo452 );
end Other__fpu__part267_behav;
