--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1055 is 
  Port (
    lo4424: in std_logic;
    n17609: inout std_logic
  );
end Other__sudoku_check__part1055;

architecture Other__sudoku_check__part1055_behav of Other__sudoku_check__part1055 is
begin
    n17609 <= ( lo4424 );
end Other__sudoku_check__part1055_behav;
