--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1690 is 
  Port (
    lo3811: in std_logic;
    n23631: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1690;

architecture Other__ucsb_152_tap_fir__part1690_behav of Other__ucsb_152_tap_fir__part1690 is
begin
    n23631 <= ( lo3811 );
end Other__ucsb_152_tap_fir__part1690_behav;
