--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_mux__part5 is 
  Port (
    lo06: in std_logic;
    n54: inout std_logic
  );
end Cookbook__clock_mux__part5;

architecture Cookbook__clock_mux__part5_behav of Cookbook__clock_mux__part5 is
begin
    n54 <= ( lo06 );
end Cookbook__clock_mux__part5_behav;
