--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2410 is 
  Port (
    lo5323: in std_logic;
    n31206_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2410;

architecture Other__ucsb_152_tap_fir__part2410_behav of Other__ucsb_152_tap_fir__part2410 is
begin
    n31206_1 <= ( lo5323 );
end Other__ucsb_152_tap_fir__part2410_behav;
