--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part763 is 
  Port (
    lo06443: in std_logic;
    n48476: inout std_logic
  );
end Other__ray__part763;

architecture Other__ray__part763_behav of Other__ray__part763 is
begin
    n48476 <= ( lo06443 );
end Other__ray__part763_behav;
