--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part196 is 
  Port (
    lo0083: in std_logic;
    n805: inout std_logic
  );
end IWLS2005__des_perf__part196;

architecture IWLS2005__des_perf__part196_behav of IWLS2005__des_perf__part196 is
begin
    n805 <= ( lo0083 );
end IWLS2005__des_perf__part196_behav;
