--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part733 is 
  Port (
    lo0802: in std_logic;
    n4309: inout std_logic
  );
end Cookbook__fec_check__part733;

architecture Cookbook__fec_check__part733_behav of Cookbook__fec_check__part733 is
begin
    n4309 <= ( lo0802 );
end Cookbook__fec_check__part733_behav;
