--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part201 is 
  Port (
    lo2850: in std_logic;
    n6929: inout std_logic
  );
end Other__sudoku_check__part201;

architecture Other__sudoku_check__part201_behav of Other__sudoku_check__part201 is
begin
    n6929 <= ( lo2850 );
end Other__sudoku_check__part201_behav;
