--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part85 is 
  Port (
    lo539: in std_logic;
    n2873_1: inout std_logic
  );
end Cookbook__lane_tx__part85;

architecture Cookbook__lane_tx__part85_behav of Cookbook__lane_tx__part85 is
begin
    n2873_1 <= ( lo539 );
end Cookbook__lane_tx__part85_behav;
