--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part254 is 
  Port (
    lo03607: in std_logic;
    n36081: inout std_logic
  );
end Other__ray__part254;

architecture Other__ray__part254_behav of Other__ray__part254 is
begin
    n36081 <= ( lo03607 );
end Other__ray__part254_behav;
