--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1337 is 
  Port (
    lo4706: in std_logic;
    n19019: inout std_logic
  );
end Other__sudoku_check__part1337;

architecture Other__sudoku_check__part1337_behav of Other__sudoku_check__part1337 is
begin
    n19019 <= ( lo4706 );
end Other__sudoku_check__part1337_behav;
