--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1246 is 
  Port (
    lo4615: in std_logic;
    n18564: inout std_logic
  );
end Other__sudoku_check__part1246;

architecture Other__sudoku_check__part1246_behav of Other__sudoku_check__part1246 is
begin
    n18564 <= ( lo4615 );
end Other__sudoku_check__part1246_behav;
