--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_phy__part5 is 
  Port (
    lo40: in std_logic;
    po04: inout std_logic
  );
end IWLS2005__usb_phy__part5;

architecture IWLS2005__usb_phy__part5_behav of IWLS2005__usb_phy__part5 is
begin
    po04 <= ( lo40 );
end IWLS2005__usb_phy__part5_behav;
