--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1316 is 
  Port (
    lo1385: in std_logic;
    n7224: inout std_logic
  );
end Cookbook__fec_check__part1316;

architecture Cookbook__fec_check__part1316_behav of Cookbook__fec_check__part1316 is
begin
    n7224 <= ( lo1385 );
end Cookbook__fec_check__part1316_behav;
