--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part239 is 
  Port (
    lo343: in std_logic;
    n1227: inout std_logic
  );
end Other__fpu__part239;

architecture Other__fpu__part239_behav of Other__fpu__part239 is
begin
    n1227 <= ( lo343 );
end Other__fpu__part239_behav;
