--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1397 is 
  Port (
    lo1466: in std_logic;
    n7629: inout std_logic
  );
end Cookbook__fec_check__part1397;

architecture Cookbook__fec_check__part1397_behav of Cookbook__fec_check__part1397 is
begin
    n7629 <= ( lo1466 );
end Cookbook__fec_check__part1397_behav;
