--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part934 is 
  Port (
    lo10492: in std_logic;
    n68821_1: inout std_logic
  );
end Other__ray__part934;

architecture Other__ray__part934_behav of Other__ray__part934 is
begin
    n68821_1 <= ( lo10492 );
end Other__ray__part934_behav;
