--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part519 is 
  Port (
    lo3258: in std_logic;
    n15354: inout std_logic
  );
end Other__carpat__part519;

architecture Other__carpat__part519_behav of Other__carpat__part519 is
begin
    n15354 <= ( lo3258 );
end Other__carpat__part519_behav;
