--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part172 is 
  Port (
    lo0052: in std_logic;
    po52: inout std_logic
  );
end Other__desperf__part172;

architecture Other__desperf__part172_behav of Other__desperf__part172 is
begin
    po52 <= ( lo0052 );
end Other__desperf__part172_behav;
