--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1830 is 
  Port (
    lo1899: in std_logic;
    n9794: inout std_logic
  );
end Cookbook__fec_check__part1830;

architecture Cookbook__fec_check__part1830_behav of Cookbook__fec_check__part1830 is
begin
    n9794 <= ( lo1899 );
end Cookbook__fec_check__part1830_behav;
