--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part556 is 
  Port (
    lo0625: in std_logic;
    n3424: inout std_logic
  );
end Cookbook__fec_check__part556;

architecture Cookbook__fec_check__part556_behav of Cookbook__fec_check__part556 is
begin
    n3424 <= ( lo0625 );
end Cookbook__fec_check__part556_behav;
