--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part246 is 
  Port (
    lo2895: in std_logic;
    n7379: inout std_logic
  );
end Other__sudoku_check__part246;

architecture Other__sudoku_check__part246_behav of Other__sudoku_check__part246 is
begin
    n7379 <= ( lo2895 );
end Other__sudoku_check__part246_behav;
