--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part994 is 
  Port (
    lo4363: in std_logic;
    n17304: inout std_logic
  );
end Other__sudoku_check__part994;

architecture Other__sudoku_check__part994_behav of Other__sudoku_check__part994 is
begin
    n17304 <= ( lo4363 );
end Other__sudoku_check__part994_behav;
