--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part20 is 
  Port (
    pi29: in std_logic;
    n173: inout std_logic
  );
end Cookbook__pipeline_add_msb__part20;

architecture Cookbook__pipeline_add_msb__part20_behav of Cookbook__pipeline_add_msb__part20 is
begin
    n173 <= ( pi29 );
end Cookbook__pipeline_add_msb__part20_behav;
