--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__tx_buffer_fifo_8word__part2 is 
  Port (
    lo4005: in std_logic;
    po402: inout std_logic
  );
end Cookbook__tx_buffer_fifo_8word__part2;

architecture Cookbook__tx_buffer_fifo_8word__part2_behav of Cookbook__tx_buffer_fifo_8word__part2 is
begin
    po402 <= ( lo4005 );
end Cookbook__tx_buffer_fifo_8word__part2_behav;
