--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part149 is 
  Port (
    lo01380: in std_logic;
    po5350,po5398,po5446,n21216: inout std_logic
  );
end Other__ray__part149;

architecture Other__ray__part149_behav of Other__ray__part149 is
begin
    po5350 <= ( lo01380 );
    po5398 <= ( lo01380 );
    po5446 <= ( lo01380 );
    n21216 <= ( lo01380 );
end Other__ray__part149_behav;
