--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part67 is 
  Port (
    pi73: in std_logic;
    n869456: inout std_logic
  );
end IWLS2005__leon3__part67;

architecture IWLS2005__leon3__part67_behav of IWLS2005__leon3__part67 is
begin
    n869456 <= ( pi73 );
end IWLS2005__leon3__part67_behav;
