--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1871 is 
  Port (
    lo4199: in std_logic;
    n25581: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1871;

architecture Other__ucsb_152_tap_fir__part1871_behav of Other__ucsb_152_tap_fir__part1871 is
begin
    n25581 <= ( lo4199 );
end Other__ucsb_152_tap_fir__part1871_behav;
