--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part63 is 
  Port (
    pi063: in std_logic;
    n9964_1: inout std_logic
  );
end Other__desperf__part63;

architecture Other__desperf__part63_behav of Other__desperf__part63 is
begin
    n9964_1 <= ( pi063 );
end Other__desperf__part63_behav;
