--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s5378__part4 is 
  Port (
    lo105: in std_logic;
    n699: inout std_logic
  );
end LGSynth91__s5378__part4;

architecture LGSynth91__s5378__part4_behav of LGSynth91__s5378__part4 is
begin
    n699 <= ( not lo105 );
end LGSynth91__s5378__part4_behav;
