--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part28 is 
  Port (
    lo0026: in std_logic;
    po0030: inout std_logic
  );
end Other__ether__part28;

architecture Other__ether__part28_behav of Other__ether__part28 is
begin
    po0030 <= ( lo0026 );
end Other__ether__part28_behav;
