--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part123 is 
  Port (
    lo2772: in std_logic;
    n6149: inout std_logic
  );
end Other__sudoku_check__part123;

architecture Other__sudoku_check__part123_behav of Other__sudoku_check__part123 is
begin
    n6149 <= ( lo2772 );
end Other__sudoku_check__part123_behav;
