--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part66 is 
  Port (
    lo035: in std_logic;
    n659: inout std_logic
  );
end Cookbook__gearbox_40_67__part66;

architecture Cookbook__gearbox_40_67__part66_behav of Cookbook__gearbox_40_67__part66 is
begin
    n659 <= ( lo035 );
end Cookbook__gearbox_40_67__part66_behav;
