--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part204 is 
  Port (
    lo0723: in std_logic;
    n4724: inout std_logic
  );
end Cookbook__ucrypt__part204;

architecture Cookbook__ucrypt__part204_behav of Cookbook__ucrypt__part204 is
begin
    n4724 <= ( lo0723 );
end Cookbook__ucrypt__part204_behav;
