--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2277 is 
  Port (
    lo2377: in std_logic;
    n12184: inout std_logic
  );
end Cookbook__fec_check__part2277;

architecture Cookbook__fec_check__part2277_behav of Cookbook__fec_check__part2277 is
begin
    n12184 <= ( lo2377 );
end Cookbook__fec_check__part2277_behav;
