--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part327 is 
  Port (
    lo03732: in std_logic;
    po6283,po6334,po6589,po6640: inout std_logic
  );
end Other__ray__part327;

architecture Other__ray__part327_behav of Other__ray__part327 is
begin
    po6283 <= ( lo03732 );
    po6334 <= ( lo03732 );
    po6589 <= ( lo03732 );
    po6640 <= ( lo03732 );
end Other__ray__part327_behav;
