--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part62 is 
  Port (
    lo2363: in std_logic;
    n5539: inout std_logic
  );
end Other__sudoku_check__part62;

architecture Other__sudoku_check__part62_behav of Other__sudoku_check__part62 is
begin
    n5539 <= ( lo2363 );
end Other__sudoku_check__part62_behav;
