--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1143 is 
  Port (
    lo4512: in std_logic;
    n18049: inout std_logic
  );
end Other__sudoku_check__part1143;

architecture Other__sudoku_check__part1143_behav of Other__sudoku_check__part1143 is
begin
    n18049 <= ( lo4512 );
end Other__sudoku_check__part1143_behav;
