--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1454 is 
  Port (
    lo1523: in std_logic;
    n7914: inout std_logic
  );
end Cookbook__fec_check__part1454;

architecture Cookbook__fec_check__part1454_behav of Cookbook__fec_check__part1454 is
begin
    n7914 <= ( lo1523 );
end Cookbook__fec_check__part1454_behav;
