--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part398 is 
  Port (
    lo0012: in std_logic;
    po012,po013: inout std_logic
  );
end Other__carpat__part398;

architecture Other__carpat__part398_behav of Other__carpat__part398 is
begin
    po012 <= ( lo0012 );
    po013 <= ( lo0012 );
end Other__carpat__part398_behav;
