--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part39 is 
  Port (
    lo0314: in std_logic;
    n1844: inout std_logic
  );
end ISCAS__s38417__part39;

architecture ISCAS__s38417__part39_behav of ISCAS__s38417__part39 is
begin
    n1844 <= ( lo0314 );
end ISCAS__s38417__part39_behav;
