--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1357 is 
  Port (
    lo1426: in std_logic;
    n7429: inout std_logic
  );
end Cookbook__fec_check__part1357;

architecture Cookbook__fec_check__part1357_behav of Cookbook__fec_check__part1357 is
begin
    n7429 <= ( lo1426 );
end Cookbook__fec_check__part1357_behav;
