--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part54 is 
  Port (
    lo0327: in std_logic;
    n1909: inout std_logic
  );
end LGSynth91__s38417__part54;

architecture LGSynth91__s38417__part54_behav of LGSynth91__s38417__part54 is
begin
    n1909 <= ( lo0327 );
end LGSynth91__s38417__part54_behav;
