--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1768 is 
  Port (
    lo1837: in std_logic;
    n9484: inout std_logic
  );
end Cookbook__fec_check__part1768;

architecture Cookbook__fec_check__part1768_behav of Cookbook__fec_check__part1768 is
begin
    n9484 <= ( lo1837 );
end Cookbook__fec_check__part1768_behav;
