--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part116 is 
  Port (
    lo0225: in std_logic;
    n5576: inout std_logic
  );
end Other__ucsb_152_tap_fir__part116;

architecture Other__ucsb_152_tap_fir__part116_behav of Other__ucsb_152_tap_fir__part116 is
begin
    n5576 <= ( lo0225 );
end Other__ucsb_152_tap_fir__part116_behav;
