--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1099 is 
  Port (
    lo1168: in std_logic;
    n6139: inout std_logic
  );
end Cookbook__fec_check__part1099;

architecture Cookbook__fec_check__part1099_behav of Cookbook__fec_check__part1099 is
begin
    n6139 <= ( lo1168 );
end Cookbook__fec_check__part1099_behav;
