--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part436 is 
  Port (
    lo3085: in std_logic;
    n9279: inout std_logic
  );
end Other__sudoku_check__part436;

architecture Other__sudoku_check__part436_behav of Other__sudoku_check__part436 is
begin
    n9279 <= ( lo3085 );
end Other__sudoku_check__part436_behav;
