--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2094 is 
  Port (
    lo4654: in std_logic;
    n27856: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2094;

architecture Other__ucsb_152_tap_fir__part2094_behav of Other__ucsb_152_tap_fir__part2094 is
begin
    n27856 <= ( lo4654 );
end Other__ucsb_152_tap_fir__part2094_behav;
