--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2390 is 
  Port (
    lo5275: in std_logic;
    n30961_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2390;

architecture Other__ucsb_152_tap_fir__part2390_behav of Other__ucsb_152_tap_fir__part2390 is
begin
    n30961_1 <= ( lo5275 );
end Other__ucsb_152_tap_fir__part2390_behav;
