--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part640 is 
  Port (
    lo0709: in std_logic;
    n3844: inout std_logic
  );
end Cookbook__fec_check__part640;

architecture Cookbook__fec_check__part640_behav of Cookbook__fec_check__part640 is
begin
    n3844 <= ( lo0709 );
end Cookbook__fec_check__part640_behav;
