--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part19 is 
  Port (
    lo005: in std_logic;
    po024: inout std_logic
  );
end Cookbook__lc_mult_signed__part19;

architecture Cookbook__lc_mult_signed__part19_behav of Cookbook__lc_mult_signed__part19 is
begin
    po024 <= ( lo005 );
end Cookbook__lc_mult_signed__part19_behav;
