--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part78 is 
  Port (
    lo77: in std_logic;
    po77: inout std_logic
  );
end Other__idxlat00n_m12__part78;

architecture Other__idxlat00n_m12__part78_behav of Other__idxlat00n_m12__part78 is
begin
    po77 <= ( lo77 );
end Other__idxlat00n_m12__part78_behav;
