--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part693 is 
  Port (
    lo06190: in std_logic;
    n46871: inout std_logic
  );
end Other__ray__part693;

architecture Other__ray__part693_behav of Other__ray__part693 is
begin
    n46871 <= ( lo06190 );
end Other__ray__part693_behav;
