--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1188 is 
  Port (
    lo7435: in std_logic;
    n41254_1: inout std_logic
  );
end Other__carpat__part1188;

architecture Other__carpat__part1188_behav of Other__carpat__part1188 is
begin
    n41254_1 <= ( lo7435 );
end Other__carpat__part1188_behav;
