--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part269 is 
  Port (
    lo1088: in std_logic;
    n5950: inout std_logic
  );
end IWLS2005__des_perf__part269;

architecture IWLS2005__des_perf__part269_behav of IWLS2005__des_perf__part269 is
begin
    n5950 <= ( lo1088 );
end IWLS2005__des_perf__part269_behav;
