--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__i1__part0 is 
  Port (
    pi00,pi24: in std_logic;
    po00: inout std_logic
  );
end IWLS93__i1__part0;

architecture IWLS93__i1__part0_behav of IWLS93__i1__part0 is
signal n64: std_logic;
begin
    po00 <= ( not n64 );
    n64 <= ( not pi00 and not pi24 );
end IWLS93__i1__part0_behav;
