--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part34 is 
  Port (
    lo020: in std_logic;
    po009: inout std_logic
  );
end Cookbook__lc_mult_signed__part34;

architecture Cookbook__lc_mult_signed__part34_behav of Cookbook__lc_mult_signed__part34 is
begin
    po009 <= ( lo020 );
end Cookbook__lc_mult_signed__part34_behav;
