--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1472 is 
  Port (
    lo4841: in std_logic;
    n19694_1: inout std_logic
  );
end Other__sudoku_check__part1472;

architecture Other__sudoku_check__part1472_behav of Other__sudoku_check__part1472 is
begin
    n19694_1 <= ( lo4841 );
end Other__sudoku_check__part1472_behav;
