--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1340 is 
  Port (
    lo1409: in std_logic;
    n7344: inout std_logic
  );
end Cookbook__fec_check__part1340;

architecture Cookbook__fec_check__part1340_behav of Cookbook__fec_check__part1340 is
begin
    n7344 <= ( lo1409 );
end Cookbook__fec_check__part1340_behav;
