--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part63 is 
  Port (
    lo077: in std_logic;
    po16: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part63;

architecture Cookbook__approx_fp_invsqrt__part63_behav of Cookbook__approx_fp_invsqrt__part63 is
begin
    po16 <= ( lo077 );
end Cookbook__approx_fp_invsqrt__part63_behav;
