--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part12 is 
  Port (
    lo0081: in std_logic;
    n704: inout std_logic
  );
end Cookbook__fec_check__part12;

architecture Cookbook__fec_check__part12_behav of Cookbook__fec_check__part12 is
begin
    n704 <= ( lo0081 );
end Cookbook__fec_check__part12_behav;
