--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part855 is 
  Port (
    lo6484: in std_logic;
    n30799_1: inout std_logic
  );
end Other__carpat__part855;

architecture Other__carpat__part855_behav of Other__carpat__part855 is
begin
    n30799_1 <= ( lo6484 );
end Other__carpat__part855_behav;
