--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1095 is 
  Port (
    lo11164: in std_logic;
    n74346_1: inout std_logic
  );
end Other__ray__part1095;

architecture Other__ray__part1095_behav of Other__ray__part1095 is
begin
    n74346_1 <= ( lo11164 );
end Other__ray__part1095_behav;
