--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1502 is 
  Port (
    lo6054: in std_logic;
    n30095: inout std_logic
  );
end IWLS2005__des_perf__part1502;

architecture IWLS2005__des_perf__part1502_behav of IWLS2005__des_perf__part1502 is
begin
    n30095 <= ( lo6054 );
end IWLS2005__des_perf__part1502_behav;
