--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1237 is 
  Port (
    lo1306: in std_logic;
    n6829: inout std_logic
  );
end Cookbook__fec_check__part1237;

architecture Cookbook__fec_check__part1237_behav of Cookbook__fec_check__part1237 is
begin
    n6829 <= ( lo1306 );
end Cookbook__fec_check__part1237_behav;
