--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part73 is 
  Port (
    lo042: in std_logic;
    n694: inout std_logic
  );
end Cookbook__gearbox_40_67__part73;

architecture Cookbook__gearbox_40_67__part73_behav of Cookbook__gearbox_40_67__part73 is
begin
    n694 <= ( lo042 );
end Cookbook__gearbox_40_67__part73_behav;
