--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part35 is 
  Port (
    pi0363: in std_logic;
    n19599: inout std_logic
  );
end Other__carpat__part35;

architecture Other__carpat__part35_behav of Other__carpat__part35 is
begin
    n19599 <= ( pi0363 );
end Other__carpat__part35_behav;
