--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1575 is 
  Port (
    lo6167: in std_logic;
    n30815_1: inout std_logic
  );
end IWLS2005__des_perf__part1575;

architecture IWLS2005__des_perf__part1575_behav of IWLS2005__des_perf__part1575 is
begin
    n30815_1 <= ( lo6167 );
end IWLS2005__des_perf__part1575_behav;
