--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part80 is 
  Port (
    lo2501: in std_logic;
    n5719: inout std_logic
  );
end Other__sudoku_check__part80;

architecture Other__sudoku_check__part80_behav of Other__sudoku_check__part80 is
begin
    n5719 <= ( lo2501 );
end Other__sudoku_check__part80_behav;
