--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1044 is 
  Port (
    lo2437: in std_logic;
    n16766: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1044;

architecture Other__ucsb_152_tap_fir__part1044_behav of Other__ucsb_152_tap_fir__part1044 is
begin
    n16766 <= ( lo2437 );
end Other__ucsb_152_tap_fir__part1044_behav;
