--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part195 is 
  Port (
    lo0792: in std_logic;
    n6100: inout std_logic
  );
end Other__fp_operators__part195;

architecture Other__fp_operators__part195_behav of Other__fp_operators__part195 is
begin
    n6100 <= ( lo0792 );
end Other__fp_operators__part195_behav;
