--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part259 is 
  Port (
    lo1043: in std_logic;
    n5675: inout std_logic
  );
end IWLS2005__des_perf__part259;

architecture IWLS2005__des_perf__part259_behav of IWLS2005__des_perf__part259 is
begin
    n5675 <= ( lo1043 );
end IWLS2005__des_perf__part259_behav;
