--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part24 is 
  Port (
    pi0335: in std_logic;
    n19594: inout std_logic
  );
end Other__carpat__part24;

architecture Other__carpat__part24_behav of Other__carpat__part24 is
begin
    n19594 <= ( pi0335 );
end Other__carpat__part24_behav;
