--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part835 is 
  Port (
    lo4204: in std_logic;
    n16149: inout std_logic
  );
end Other__sudoku_check__part835;

architecture Other__sudoku_check__part835_behav of Other__sudoku_check__part835 is
begin
    n16149 <= ( lo4204 );
end Other__sudoku_check__part835_behav;
