--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part117 is 
  Port (
    pi0962: in std_logic;
    n31274_1: inout std_logic
  );
end Other__carpat__part117;

architecture Other__carpat__part117_behav of Other__carpat__part117 is
begin
    n31274_1 <= ( pi0962 );
end Other__carpat__part117_behav;
