--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part0 is 
  Port (
    pi00: in std_logic;
    n166: inout std_logic
  );
end Cookbook__pipeline_add__part0;

architecture Cookbook__pipeline_add__part0_behav of Cookbook__pipeline_add__part0 is
begin
    n166 <= ( pi00 );
end Cookbook__pipeline_add__part0_behav;
