--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part739 is 
  Port (
    lo4463: in std_logic;
    n22660: inout std_logic
  );
end IWLS2005__des_perf__part739;

architecture IWLS2005__des_perf__part739_behav of IWLS2005__des_perf__part739 is
begin
    n22660 <= ( lo4463 );
end IWLS2005__des_perf__part739_behav;
