--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part633 is 
  Port (
    lo4279: in std_logic;
    n21485: inout std_logic
  );
end IWLS2005__des_perf__part633;

architecture IWLS2005__des_perf__part633_behav of IWLS2005__des_perf__part633 is
begin
    n21485 <= ( lo4279 );
end IWLS2005__des_perf__part633_behav;
