--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1019 is 
  Port (
    lo7112: in std_logic;
    n37744_1: inout std_logic
  );
end Other__carpat__part1019;

architecture Other__carpat__part1019_behav of Other__carpat__part1019 is
begin
    n37744_1 <= ( lo7112 );
end Other__carpat__part1019_behav;
