--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part144 is 
  Port (
    lo2793: in std_logic;
    n6359: inout std_logic
  );
end Other__sudoku_check__part144;

architecture Other__sudoku_check__part144_behav of Other__sudoku_check__part144 is
begin
    n6359 <= ( lo2793 );
end Other__sudoku_check__part144_behav;
