--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1204 is 
  Port (
    lo4573: in std_logic;
    n18354: inout std_logic
  );
end Other__sudoku_check__part1204;

architecture Other__sudoku_check__part1204_behav of Other__sudoku_check__part1204 is
begin
    n18354 <= ( lo4573 );
end Other__sudoku_check__part1204_behav;
