--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1918 is 
  Port (
    lo1987: in std_logic;
    n10234: inout std_logic
  );
end Cookbook__fec_check__part1918;

architecture Cookbook__fec_check__part1918_behav of Cookbook__fec_check__part1918 is
begin
    n10234 <= ( lo1987 );
end Cookbook__fec_check__part1918_behav;
