--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part63 is 
  Port (
    lo0021: in std_logic;
    po146: inout std_logic
  );
end IWLS2005__mem_ctrl__part63;

architecture IWLS2005__mem_ctrl__part63_behav of IWLS2005__mem_ctrl__part63 is
begin
    po146 <= ( lo0021 );
end IWLS2005__mem_ctrl__part63_behav;
