--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part544 is 
  Port (
    lo3193: in std_logic;
    n10359: inout std_logic
  );
end Other__sudoku_check__part544;

architecture Other__sudoku_check__part544_behav of Other__sudoku_check__part544 is
begin
    n10359 <= ( lo3193 );
end Other__sudoku_check__part544_behav;
