--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part91 is 
  Port (
    pi1186: in std_logic;
    n71981_1: inout std_logic
  );
end Other__ray__part91;

architecture Other__ray__part91_behav of Other__ray__part91 is
begin
    n71981_1 <= ( pi1186 );
end Other__ray__part91_behav;
