--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part207 is 
  Port (
    lo311: in std_logic;
    n1067: inout std_logic
  );
end Other__fpu__part207;

architecture Other__fpu__part207_behav of Other__fpu__part207 is
begin
    n1067 <= ( lo311 );
end Other__fpu__part207_behav;
