--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part127 is 
  Port (
    lo0196: in std_logic;
    n1279: inout std_logic
  );
end Cookbook__fec_check__part127;

architecture Cookbook__fec_check__part127_behav of Cookbook__fec_check__part127 is
begin
    n1279 <= ( lo0196 );
end Cookbook__fec_check__part127_behav;
