--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1429 is 
  Port (
    lo1498: in std_logic;
    n7789: inout std_logic
  );
end Cookbook__fec_check__part1429;

architecture Cookbook__fec_check__part1429_behav of Cookbook__fec_check__part1429 is
begin
    n7789 <= ( lo1498 );
end Cookbook__fec_check__part1429_behav;
