--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2058 is 
  Port (
    lo2127: in std_logic;
    n10934: inout std_logic
  );
end Cookbook__fec_check__part2058;

architecture Cookbook__fec_check__part2058_behav of Cookbook__fec_check__part2058 is
begin
    n10934 <= ( lo2127 );
end Cookbook__fec_check__part2058_behav;
