--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1560 is 
  Port (
    lo8191: in std_logic;
    n46024_1: inout std_logic
  );
end Other__carpat__part1560;

architecture Other__carpat__part1560_behav of Other__carpat__part1560 is
begin
    n46024_1 <= ( lo8191 );
end Other__carpat__part1560_behav;
