--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part93 is 
  Port (
    lo330: in std_logic;
    po104: inout std_logic
  );
end IWLS2005__aes_core__part93;

architecture IWLS2005__aes_core__part93_behav of IWLS2005__aes_core__part93 is
begin
    po104 <= ( lo330 );
end IWLS2005__aes_core__part93_behav;
