--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2057 is 
  Port (
    lo4588: in std_logic;
    n27521: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2057;

architecture Other__ucsb_152_tap_fir__part2057_behav of Other__ucsb_152_tap_fir__part2057 is
begin
    n27521 <= ( lo4588 );
end Other__ucsb_152_tap_fir__part2057_behav;
