--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part39 is 
  Port (
    lo38: in std_logic;
    po30: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part39;

architecture Cookbook__x4_decoder_8b10b__part39_behav of Cookbook__x4_decoder_8b10b__part39 is
begin
    po30 <= ( lo38 );
end Cookbook__x4_decoder_8b10b__part39_behav;
