--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1347 is 
  Port (
    lo3115: in std_logic;
    n20086: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1347;

architecture Other__ucsb_152_tap_fir__part1347_behav of Other__ucsb_152_tap_fir__part1347 is
begin
    n20086 <= ( lo3115 );
end Other__ucsb_152_tap_fir__part1347_behav;
