--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part78 is 
  Port (
    lo092: in std_logic;
    po01: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part78;

architecture Cookbook__approx_fp_invsqrt__part78_behav of Cookbook__approx_fp_invsqrt__part78 is
begin
    po01 <= ( lo092 );
end Cookbook__approx_fp_invsqrt__part78_behav;
