--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part79 is 
  Port (
    lo0182: in std_logic;
    n2169: inout std_logic
  );
end Cookbook__ucrypt__part79;

architecture Cookbook__ucrypt__part79_behav of Cookbook__ucrypt__part79 is
begin
    n2169 <= ( lo0182 );
end Cookbook__ucrypt__part79_behav;
