--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part788 is 
  Port (
    lo06515: in std_logic;
    n48901: inout std_logic
  );
end Other__ray__part788;

architecture Other__ray__part788_behav of Other__ray__part788 is
begin
    n48901 <= ( lo06515 );
end Other__ray__part788_behav;
