--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part230 is 
  Port (
    lo1166: in std_logic;
    n7285_1: inout std_logic
  );
end Other__fp_operators__part230;

architecture Other__fp_operators__part230_behav of Other__fp_operators__part230 is
begin
    n7285_1 <= ( lo1166 );
end Other__fp_operators__part230_behav;
