--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part217 is 
  Port (
    lo0732: in std_logic;
    n37221_1: inout std_logic
  );
end Other__radar__part217;

architecture Other__radar__part217_behav of Other__radar__part217 is
begin
    n37221_1 <= ( lo0732 );
end Other__radar__part217_behav;
