--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1850 is 
  Port (
    lo1919: in std_logic;
    n9894: inout std_logic
  );
end Cookbook__fec_check__part1850;

architecture Cookbook__fec_check__part1850_behav of Cookbook__fec_check__part1850 is
begin
    n9894 <= ( lo1919 );
end Cookbook__fec_check__part1850_behav;
