--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part262 is 
  Port (
    lo03634: in std_logic;
    n36161: inout std_logic
  );
end Other__ray__part262;

architecture Other__ray__part262_behav of Other__ray__part262 is
begin
    n36161 <= ( lo03634 );
end Other__ray__part262_behav;
