--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2367 is 
  Port (
    lo5207: in std_logic;
    n30536: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2367;

architecture Other__ucsb_152_tap_fir__part2367_behav of Other__ucsb_152_tap_fir__part2367 is
begin
    n30536 <= ( lo5207 );
end Other__ucsb_152_tap_fir__part2367_behav;
