--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part973 is 
  Port (
    lo6928: in std_logic;
    n36204_1: inout std_logic
  );
end Other__carpat__part973;

architecture Other__carpat__part973_behav of Other__carpat__part973 is
begin
    n36204_1 <= ( lo6928 );
end Other__carpat__part973_behav;
