--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2232 is 
  Port (
    lo4924: in std_logic;
    n29206: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2232;

architecture Other__ucsb_152_tap_fir__part2232_behav of Other__ucsb_152_tap_fir__part2232 is
begin
    n29206 <= ( lo4924 );
end Other__ucsb_152_tap_fir__part2232_behav;
