--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part780 is 
  Port (
    lo4517: in std_logic;
    n22365: inout std_logic
  );
end IWLS2005__des_perf__part780;

architecture IWLS2005__des_perf__part780_behav of IWLS2005__des_perf__part780 is
begin
    n22365 <= ( lo4517 );
end IWLS2005__des_perf__part780_behav;
