--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part110 is 
  Port (
    lo0899: in std_logic;
    n5349_1: inout std_logic
  );
end LGSynth91__s38417__part110;

architecture LGSynth91__s38417__part110_behav of LGSynth91__s38417__part110 is
begin
    n5349_1 <= ( not lo0899 );
end LGSynth91__s38417__part110_behav;
