--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part634 is 
  Port (
    lo06131: in std_logic;
    po1697,po1792: inout std_logic
  );
end Other__ray__part634;

architecture Other__ray__part634_behav of Other__ray__part634 is
begin
    po1697 <= ( lo06131 );
    po1792 <= ( lo06131 );
end Other__ray__part634_behav;
