--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part233 is 
  Port (
    lo337: in std_logic;
    n1197: inout std_logic
  );
end Other__fpu__part233;

architecture Other__fpu__part233_behav of Other__fpu__part233 is
begin
    n1197 <= ( lo337 );
end Other__fpu__part233_behav;
