--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part237 is 
  Port (
    lo0891: in std_logic;
    n4059: inout std_logic
  );
end Other__desperf__part237;

architecture Other__desperf__part237_behav of Other__desperf__part237 is
begin
    n4059 <= ( lo0891 );
end Other__desperf__part237_behav;
