--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part139 is 
  Port (
    lo0997: in std_logic;
    po094: inout std_logic
  );
end IWLS2005__mem_ctrl__part139;

architecture IWLS2005__mem_ctrl__part139_behav of IWLS2005__mem_ctrl__part139 is
begin
    po094 <= ( lo0997 );
end IWLS2005__mem_ctrl__part139_behav;
