--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part516 is 
  Port (
    lo3165: in std_logic;
    n10079: inout std_logic
  );
end Other__sudoku_check__part516;

architecture Other__sudoku_check__part516_behav of Other__sudoku_check__part516 is
begin
    n10079 <= ( lo3165 );
end Other__sudoku_check__part516_behav;
