--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1377 is 
  Port (
    lo1446: in std_logic;
    n7529: inout std_logic
  );
end Cookbook__fec_check__part1377;

architecture Cookbook__fec_check__part1377_behav of Cookbook__fec_check__part1377 is
begin
    n7529 <= ( lo1446 );
end Cookbook__fec_check__part1377_behav;
