--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1013 is 
  Port (
    lo1082: in std_logic;
    n5709: inout std_logic
  );
end Cookbook__fec_check__part1013;

architecture Cookbook__fec_check__part1013_behav of Cookbook__fec_check__part1013 is
begin
    n5709 <= ( lo1082 );
end Cookbook__fec_check__part1013_behav;
