--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part777 is 
  Port (
    lo0846: in std_logic;
    n4529: inout std_logic
  );
end Cookbook__fec_check__part777;

architecture Cookbook__fec_check__part777_behav of Cookbook__fec_check__part777 is
begin
    n4529 <= ( lo0846 );
end Cookbook__fec_check__part777_behav;
