--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part305 is 
  Port (
    lo03695: in std_logic;
    po6246,po6313,po6552,po6619: inout std_logic
  );
end Other__ray__part305;

architecture Other__ray__part305_behav of Other__ray__part305 is
begin
    po6246 <= ( lo03695 );
    po6313 <= ( lo03695 );
    po6552 <= ( lo03695 );
    po6619 <= ( lo03695 );
end Other__ray__part305_behav;
