--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part992 is 
  Port (
    lo4955: in std_logic;
    n24670: inout std_logic
  );
end IWLS2005__des_perf__part992;

architecture IWLS2005__des_perf__part992_behav of IWLS2005__des_perf__part992 is
begin
    n24670 <= ( lo4955 );
end IWLS2005__des_perf__part992_behav;
