--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part309 is 
  Port (
    lo1483: in std_logic;
    n10420_1: inout std_logic
  );
end Other__fp_operators__part309;

architecture Other__fp_operators__part309_behav of Other__fp_operators__part309 is
begin
    n10420_1 <= ( lo1483 );
end Other__fp_operators__part309_behav;
