--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part16 is 
  Port (
    lo118: in std_logic;
    po10: inout std_logic
  );
end ISCAS__s15850__part16;

architecture ISCAS__s15850__part16_behav of ISCAS__s15850__part16 is
begin
    po10 <= ( lo118 );
end ISCAS__s15850__part16_behav;
