--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part186 is 
  Port (
    lo285: in std_logic;
    n937: inout std_logic
  );
end Other__fpu__part186;

architecture Other__fpu__part186_behav of Other__fpu__part186 is
begin
    n937 <= ( lo285 );
end Other__fpu__part186_behav;
