--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part840 is 
  Port (
    lo6469: in std_logic;
    n30599: inout std_logic
  );
end Other__carpat__part840;

architecture Other__carpat__part840_behav of Other__carpat__part840 is
begin
    n30599 <= ( lo6469 );
end Other__carpat__part840_behav;
