--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part140 is 
  Port (
    lo01369: in std_logic;
    po4918,po4966,po5014,n21151: inout std_logic
  );
end Other__ray__part140;

architecture Other__ray__part140_behav of Other__ray__part140 is
begin
    po4918 <= ( lo01369 );
    po4966 <= ( lo01369 );
    po5014 <= ( lo01369 );
    n21151 <= ( lo01369 );
end Other__ray__part140_behav;
