--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2196 is 
  Port (
    lo2265: in std_logic;
    n11624: inout std_logic
  );
end Cookbook__fec_check__part2196;

architecture Cookbook__fec_check__part2196_behav of Cookbook__fec_check__part2196 is
begin
    n11624 <= ( lo2265 );
end Cookbook__fec_check__part2196_behav;
