--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part454 is 
  Port (
    lo1677: in std_logic;
    n9644: inout std_logic
  );
end Cookbook__ucrypt__part454;

architecture Cookbook__ucrypt__part454_behav of Cookbook__ucrypt__part454 is
begin
    n9644 <= ( lo1677 );
end Cookbook__ucrypt__part454_behav;
