--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part932 is 
  Port (
    lo4851: in std_logic;
    n24120: inout std_logic
  );
end IWLS2005__des_perf__part932;

architecture IWLS2005__des_perf__part932_behav of IWLS2005__des_perf__part932 is
begin
    n24120 <= ( lo4851 );
end IWLS2005__des_perf__part932_behav;
