--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part404 is 
  Port (
    lo3053: in std_logic;
    n8959: inout std_logic
  );
end Other__sudoku_check__part404;

architecture Other__sudoku_check__part404_behav of Other__sudoku_check__part404 is
begin
    n8959 <= ( lo3053 );
end Other__sudoku_check__part404_behav;
