--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1094 is 
  Port (
    lo7300: in std_logic;
    n40109_1: inout std_logic
  );
end Other__carpat__part1094;

architecture Other__carpat__part1094_behav of Other__carpat__part1094 is
begin
    n40109_1 <= ( lo7300 );
end Other__carpat__part1094_behav;
