--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part958 is 
  Port (
    lo1027: in std_logic;
    n5434: inout std_logic
  );
end Cookbook__fec_check__part958;

architecture Cookbook__fec_check__part958_behav of Cookbook__fec_check__part958 is
begin
    n5434 <= ( lo1027 );
end Cookbook__fec_check__part958_behav;
