--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1014 is 
  Port (
    lo4981: in std_logic;
    n24700: inout std_logic
  );
end IWLS2005__des_perf__part1014;

architecture IWLS2005__des_perf__part1014_behav of IWLS2005__des_perf__part1014 is
begin
    n24700 <= ( lo4981 );
end IWLS2005__des_perf__part1014_behav;
