--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part667 is 
  Port (
    lo5188: in std_logic;
    n24959: inout std_logic
  );
end Other__carpat__part667;

architecture Other__carpat__part667_behav of Other__carpat__part667 is
begin
    n24959 <= ( lo5188 );
end Other__carpat__part667_behav;
