--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1553 is 
  Port (
    lo1622: in std_logic;
    n8409: inout std_logic
  );
end Cookbook__fec_check__part1553;

architecture Cookbook__fec_check__part1553_behav of Cookbook__fec_check__part1553 is
begin
    n8409 <= ( lo1622 );
end Cookbook__fec_check__part1553_behav;
