--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part58 is 
  Port (
    pi058: in std_logic;
    n2517_1: inout std_logic
  );
end Other__fpu__part58;

architecture Other__fpu__part58_behav of Other__fpu__part58 is
begin
    n2517_1 <= ( pi058 );
end Other__fpu__part58_behav;
