--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part642 is 
  Port (
    lo3291: in std_logic;
    n11339: inout std_logic
  );
end Other__sudoku_check__part642;

architecture Other__sudoku_check__part642_behav of Other__sudoku_check__part642 is
begin
    n11339 <= ( lo3291 );
end Other__sudoku_check__part642_behav;
