--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1146 is 
  Port (
    lo1215: in std_logic;
    n6374: inout std_logic
  );
end Cookbook__fec_check__part1146;

architecture Cookbook__fec_check__part1146_behav of Cookbook__fec_check__part1146 is
begin
    n6374 <= ( lo1215 );
end Cookbook__fec_check__part1146_behav;
