--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part427 is 
  Port (
    lo1538: in std_logic;
    n8949_1: inout std_logic
  );
end Cookbook__ucrypt__part427;

architecture Cookbook__ucrypt__part427_behav of Cookbook__ucrypt__part427 is
begin
    n8949_1 <= ( lo1538 );
end Cookbook__ucrypt__part427_behav;
