--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3296 is 
  Port (
    lo8661: in std_logic;
    n43665_1: inout std_logic
  );
end IWLS2005__des_perf__part3296;

architecture IWLS2005__des_perf__part3296_behav of IWLS2005__des_perf__part3296 is
begin
    n43665_1 <= ( lo8661 );
end IWLS2005__des_perf__part3296_behav;
