--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part115 is 
  Port (
    lo0330: in std_logic;
    n2909: inout std_logic
  );
end Cookbook__ucrypt__part115;

architecture Cookbook__ucrypt__part115_behav of Cookbook__ucrypt__part115 is
begin
    n2909 <= ( lo0330 );
end Cookbook__ucrypt__part115_behav;
