--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_40__part17 is 
  Port (
    lo022: in std_logic;
    po26: inout std_logic
  );
end Cookbook__gearbox_66_40__part17;

architecture Cookbook__gearbox_66_40__part17_behav of Cookbook__gearbox_66_40__part17 is
begin
    po26 <= ( lo022 );
end Cookbook__gearbox_66_40__part17_behav;
