--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3mp__part13 is 
  Port (
    pi13: in std_logic;
    n544258: inout std_logic
  );
end IWLS2005__leon3mp__part13;

architecture IWLS2005__leon3mp__part13_behav of IWLS2005__leon3mp__part13 is
begin
    n544258 <= ( pi13 );
end IWLS2005__leon3mp__part13_behav;
