--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part805 is 
  Port (
    lo06564: in std_logic;
    n49156_1: inout std_logic
  );
end Other__ray__part805;

architecture Other__ray__part805_behav of Other__ray__part805 is
begin
    n49156_1 <= ( lo06564 );
end Other__ray__part805_behav;
