--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part207 is 
  Port (
    lo0506: in std_logic;
    n7106: inout std_logic
  );
end Other__ucsb_152_tap_fir__part207;

architecture Other__ucsb_152_tap_fir__part207_behav of Other__ucsb_152_tap_fir__part207 is
begin
    n7106 <= ( lo0506 );
end Other__ucsb_152_tap_fir__part207_behav;
