--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part324 is 
  Port (
    lo1180: in std_logic;
    n7004: inout std_logic
  );
end Cookbook__ucrypt__part324;

architecture Cookbook__ucrypt__part324_behav of Cookbook__ucrypt__part324 is
begin
    n7004 <= ( lo1180 );
end Cookbook__ucrypt__part324_behav;
