--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2517 is 
  Port (
    lo5561: in std_logic;
    n32381_1: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2517;

architecture Other__ucsb_152_tap_fir__part2517_behav of Other__ucsb_152_tap_fir__part2517 is
begin
    n32381_1 <= ( lo5561 );
end Other__ucsb_152_tap_fir__part2517_behav;
