--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1441 is 
  Port (
    lo1510: in std_logic;
    n7849: inout std_logic
  );
end Cookbook__fec_check__part1441;

architecture Cookbook__fec_check__part1441_behav of Cookbook__fec_check__part1441 is
begin
    n7849 <= ( lo1510 );
end Cookbook__fec_check__part1441_behav;
