--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part143 is 
  Port (
    lo0533: in std_logic;
    n5175: inout std_logic
  );
end Other__fp_operators__part143;

architecture Other__fp_operators__part143_behav of Other__fp_operators__part143 is
begin
    n5175 <= ( lo0533 );
end Other__fp_operators__part143_behav;
