--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2213 is 
  Port (
    lo4905: in std_logic;
    n29111: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2213;

architecture Other__ucsb_152_tap_fir__part2213_behav of Other__ucsb_152_tap_fir__part2213 is
begin
    n29111 <= ( lo4905 );
end Other__ucsb_152_tap_fir__part2213_behav;
