--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part81 is 
  Port (
    lo2508: in std_logic;
    n5729: inout std_logic
  );
end Other__sudoku_check__part81;

architecture Other__sudoku_check__part81_behav of Other__sudoku_check__part81 is
begin
    n5729 <= ( lo2508 );
end Other__sudoku_check__part81_behav;
