--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1126 is 
  Port (
    lo12973: in std_logic;
    po1951,po2014,po2131,po2194,n51596_1: inout std_logic
  );
end Other__ray__part1126;

architecture Other__ray__part1126_behav of Other__ray__part1126 is
begin
    po1951 <= ( lo12973 );
    po2014 <= ( lo12973 );
    po2131 <= ( lo12973 );
    po2194 <= ( lo12973 );
    n51596_1 <= ( lo12973 );
end Other__ray__part1126_behav;
