--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part343 is 
  Port (
    lo0412: in std_logic;
    n2359: inout std_logic
  );
end Cookbook__fec_check__part343;

architecture Cookbook__fec_check__part343_behav of Cookbook__fec_check__part343 is
begin
    n2359 <= ( lo0412 );
end Cookbook__fec_check__part343_behav;
