--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2863 is 
  Port (
    lo8176: in std_logic;
    n41320_1: inout std_logic
  );
end IWLS2005__des_perf__part2863;

architecture IWLS2005__des_perf__part2863_behav of IWLS2005__des_perf__part2863 is
begin
    n41320_1 <= ( lo8176 );
end IWLS2005__des_perf__part2863_behav;
