--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1546 is 
  Port (
    lo8177: in std_logic;
    n45954_1: inout std_logic
  );
end Other__carpat__part1546;

architecture Other__carpat__part1546_behav of Other__carpat__part1546 is
begin
    n45954_1 <= ( lo8177 );
end Other__carpat__part1546_behav;
