--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part318 is 
  Port (
    lo2967: in std_logic;
    n8099: inout std_logic
  );
end Other__sudoku_check__part318;

architecture Other__sudoku_check__part318_behav of Other__sudoku_check__part318 is
begin
    n8099 <= ( lo2967 );
end Other__sudoku_check__part318_behav;
