--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part70 is 
  Port (
    lo69: in std_logic;
    po69: inout std_logic
  );
end Other__idxlat02n_m12__part70;

architecture Other__idxlat02n_m12__part70_behav of Other__idxlat02n_m12__part70 is
begin
    po69 <= ( lo69 );
end Other__idxlat02n_m12__part70_behav;
