--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part895 is 
  Port (
    lo4264: in std_logic;
    n16809: inout std_logic
  );
end Other__sudoku_check__part895;

architecture Other__sudoku_check__part895_behav of Other__sudoku_check__part895 is
begin
    n16809 <= ( lo4264 );
end Other__sudoku_check__part895_behav;
