--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part92 is 
  Port (
    lo1766: in std_logic;
    po085: inout std_logic
  );
end Other__mem__part92;

architecture Other__mem__part92_behav of Other__mem__part92 is
begin
    po085 <= ( lo1766 );
end Other__mem__part92_behav;
