--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part203 is 
  Port (
    lo0501: in std_logic;
    n7081: inout std_logic
  );
end Other__ucsb_152_tap_fir__part203;

architecture Other__ucsb_152_tap_fir__part203_behav of Other__ucsb_152_tap_fir__part203 is
begin
    n7081 <= ( lo0501 );
end Other__ucsb_152_tap_fir__part203_behav;
