--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part272 is 
  Port (
    lo457: in std_logic;
    n1587: inout std_logic
  );
end Other__fpu__part272;

architecture Other__fpu__part272_behav of Other__fpu__part272 is
begin
    n1587 <= ( lo457 );
end Other__fpu__part272_behav;
