--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part45 is 
  Port (
    lo0126: in std_logic;
    n1734: inout std_logic
  );
end Cookbook__ucrypt__part45;

architecture Cookbook__ucrypt__part45_behav of Cookbook__ucrypt__part45 is
begin
    n1734 <= ( lo0126 );
end Cookbook__ucrypt__part45_behav;
