--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part196 is 
  Port (
    lo1453: in std_logic;
    n7539: inout std_logic
  );
end ISCAS__s38417__part196;

architecture ISCAS__s38417__part196_behav of ISCAS__s38417__part196 is
begin
    n7539 <= ( lo1453 );
end ISCAS__s38417__part196_behav;
