--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1581 is 
  Port (
    lo8294: in std_logic;
    n46359_1: inout std_logic
  );
end Other__carpat__part1581;

architecture Other__carpat__part1581_behav of Other__carpat__part1581 is
begin
    n46359_1 <= ( lo8294 );
end Other__carpat__part1581_behav;
