--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2432 is 
  Port (
    lo7673: in std_logic;
    n38165_1: inout std_logic
  );
end IWLS2005__des_perf__part2432;

architecture IWLS2005__des_perf__part2432_behav of IWLS2005__des_perf__part2432 is
begin
    n38165_1 <= ( lo7673 );
end IWLS2005__des_perf__part2432_behav;
