--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part401 is 
  Port (
    lo05873: in std_logic;
    po1290,po1355,po1595,po1664: inout std_logic
  );
end Other__ray__part401;

architecture Other__ray__part401_behav of Other__ray__part401 is
begin
    po1290 <= ( lo05873 );
    po1355 <= ( lo05873 );
    po1595 <= ( lo05873 );
    po1664 <= ( lo05873 );
end Other__ray__part401_behav;
