--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1125 is 
  Port (
    lo7371: in std_logic;
    n40929_1: inout std_logic
  );
end Other__carpat__part1125;

architecture Other__carpat__part1125_behav of Other__carpat__part1125 is
begin
    n40929_1 <= ( lo7371 );
end Other__carpat__part1125_behav;
