--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part2 is 
  Port (
    pi02: in std_logic;
    n439: inout std_logic
  );
end ISCAS__s3384__part2;

architecture ISCAS__s3384__part2_behav of ISCAS__s3384__part2 is
begin
    n439 <= ( pi02 );
end ISCAS__s3384__part2_behav;
