--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1023 is 
  Port (
    lo7116: in std_logic;
    n37764_1: inout std_logic
  );
end Other__carpat__part1023;

architecture Other__carpat__part1023_behav of Other__carpat__part1023 is
begin
    n37764_1 <= ( lo7116 );
end Other__carpat__part1023_behav;
