--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s5378__part5 is 
  Port (
    lo127: in std_logic;
    n803_1: inout std_logic
  );
end ISCAS__s5378__part5;

architecture ISCAS__s5378__part5_behav of ISCAS__s5378__part5 is
begin
    n803_1 <= ( not lo127 );
end ISCAS__s5378__part5_behav;
