--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part95 is 
  Port (
    lo1769: in std_logic;
    po088: inout std_logic
  );
end Other__mem__part95;

architecture Other__mem__part95_behav of Other__mem__part95 is
begin
    po088 <= ( lo1769 );
end Other__mem__part95_behav;
