--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2708 is 
  Port (
    lo8021: in std_logic;
    n39835_1: inout std_logic
  );
end IWLS2005__des_perf__part2708;

architecture IWLS2005__des_perf__part2708_behav of IWLS2005__des_perf__part2708 is
begin
    n39835_1 <= ( lo8021 );
end IWLS2005__des_perf__part2708_behav;
