--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part20 is 
  Port (
    lo09: in std_logic;
    po14: inout std_logic
  );
end Cookbook__font_rom__part20;

architecture Cookbook__font_rom__part20_behav of Cookbook__font_rom__part20 is
begin
    po14 <= ( lo09 );
end Cookbook__font_rom__part20_behav;
