--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part517 is 
  Port (
    lo0586: in std_logic;
    n3229: inout std_logic
  );
end Cookbook__fec_check__part517;

architecture Cookbook__fec_check__part517_behav of Cookbook__fec_check__part517 is
begin
    n3229 <= ( lo0586 );
end Cookbook__fec_check__part517_behav;
