--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__soar__part4 is 
  Port (
    pi67,pi68,pi69,pi70,pi71,pi72,pi73,pi74: in std_logic;
    po72: inout std_logic
  );
end Espresso__soar__part4;

architecture Espresso__soar__part4_behav of Espresso__soar__part4 is
begin
    po72 <= ( pi67 )
      or ( not pi68 )
      or ( pi69 )
      or ( pi70 and not pi71 and not pi72 )
      or ( pi70 and not pi71 and not pi73 )
      or ( pi70 and not pi72 and not pi73 )
      or ( pi70 and not pi71 and not pi74 )
      or ( pi70 and not pi72 and not pi74 );
end Espresso__soar__part4_behav;
