--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part139 is 
  Port (
    lo0208: in std_logic;
    n1339: inout std_logic
  );
end Cookbook__fec_check__part139;

architecture Cookbook__fec_check__part139_behav of Cookbook__fec_check__part139 is
begin
    n1339 <= ( lo0208 );
end Cookbook__fec_check__part139_behav;
