--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1941 is 
  Port (
    lo2010: in std_logic;
    n10349: inout std_logic
  );
end Cookbook__fec_check__part1941;

architecture Cookbook__fec_check__part1941_behav of Cookbook__fec_check__part1941 is
begin
    n10349 <= ( lo2010 );
end Cookbook__fec_check__part1941_behav;
