--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1848 is 
  Port (
    lo1917: in std_logic;
    n9884: inout std_logic
  );
end Cookbook__fec_check__part1848;

architecture Cookbook__fec_check__part1848_behav of Cookbook__fec_check__part1848 is
begin
    n9884 <= ( lo1917 );
end Cookbook__fec_check__part1848_behav;
