--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1251 is 
  Port (
    lo1320: in std_logic;
    n6899: inout std_logic
  );
end Cookbook__fec_check__part1251;

architecture Cookbook__fec_check__part1251_behav of Cookbook__fec_check__part1251 is
begin
    n6899 <= ( lo1320 );
end Cookbook__fec_check__part1251_behav;
