--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part265 is 
  Port (
    lo0334: in std_logic;
    n1969: inout std_logic
  );
end Cookbook__fec_check__part265;

architecture Cookbook__fec_check__part265_behav of Cookbook__fec_check__part265 is
begin
    n1969 <= ( lo0334 );
end Cookbook__fec_check__part265_behav;
