--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1009 is 
  Port (
    lo1078: in std_logic;
    n5689: inout std_logic
  );
end Cookbook__fec_check__part1009;

architecture Cookbook__fec_check__part1009_behav of Cookbook__fec_check__part1009 is
begin
    n5689 <= ( lo1078 );
end Cookbook__fec_check__part1009_behav;
