--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part15 is 
  Port (
    lo2876: in std_logic;
    n13647: inout std_logic
  );
end Other__top_rs_decode__part15;

architecture Other__top_rs_decode__part15_behav of Other__top_rs_decode__part15 is
begin
    n13647 <= ( lo2876 );
end Other__top_rs_decode__part15_behav;
