--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part26 is 
  Port (
    lo25: in std_logic;
    po25: inout std_logic
  );
end Other__idxlat00n_m12__part26;

architecture Other__idxlat00n_m12__part26_behav of Other__idxlat00n_m12__part26 is
begin
    po25 <= ( lo25 );
end Other__idxlat00n_m12__part26_behav;
