--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part640 is 
  Port (
    lo4286: in std_logic;
    n21740: inout std_logic
  );
end IWLS2005__des_perf__part640;

architecture IWLS2005__des_perf__part640_behav of IWLS2005__des_perf__part640 is
begin
    n21740 <= ( lo4286 );
end IWLS2005__des_perf__part640_behav;
