--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2313 is 
  Port (
    lo3489,lo3477,lo3465,lo3453,lo3441,lo3429,lo3417,lo3405,lo3793: in std_logic;
    n18944: inout std_logic
  );
end Cookbook__fec_check__part2313;

architecture Cookbook__fec_check__part2313_behav of Cookbook__fec_check__part2313 is
signal n13689,n13690,n13691,n13692,n13693,n13694,n13695: std_logic;
begin
    n13689 <= not (( not lo3489 and not lo3477 ));
    n13690 <= not (( not lo3465 and not lo3453 ));
    n13691 <= not (( not n13689 and not n13690 ));
    n13692 <= not (( not lo3441 and not lo3429 ));
    n13693 <= not (( not lo3417 and not lo3405 ));
    n13694 <= not (( not n13692 and not n13693 ));
    n13695 <= not (( not n13691 and not n13694 ));
    n18944 <= not (( not n13695 and not lo3793 ));
end Cookbook__fec_check__part2313_behav;
