--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part369 is 
  Port (
    lo2136: in std_logic;
    n11210: inout std_logic
  );
end IWLS2005__des_perf__part369;

architecture IWLS2005__des_perf__part369_behav of IWLS2005__des_perf__part369 is
begin
    n11210 <= ( lo2136 );
end IWLS2005__des_perf__part369_behav;
