--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part283 is 
  Port (
    lo1124: in std_logic;
    n6110: inout std_logic
  );
end IWLS2005__des_perf__part283;

architecture IWLS2005__des_perf__part283_behav of IWLS2005__des_perf__part283 is
begin
    n6110 <= ( lo1124 );
end IWLS2005__des_perf__part283_behav;
