--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1984 is 
  Port (
    lo2053: in std_logic;
    n10564: inout std_logic
  );
end Cookbook__fec_check__part1984;

architecture Cookbook__fec_check__part1984_behav of Cookbook__fec_check__part1984 is
begin
    n10564 <= ( lo2053 );
end Cookbook__fec_check__part1984_behav;
