--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part37 is 
  Port (
    lo036: in std_logic;
    n490: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part37;

architecture Cookbook__approx_fp_invsqrt__part37_behav of Cookbook__approx_fp_invsqrt__part37 is
begin
    n490 <= ( lo036 );
end Cookbook__approx_fp_invsqrt__part37_behav;
