--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part735 is 
  Port (
    lo3384: in std_logic;
    n12269: inout std_logic
  );
end Other__sudoku_check__part735;

architecture Other__sudoku_check__part735_behav of Other__sudoku_check__part735 is
begin
    n12269 <= ( lo3384 );
end Other__sudoku_check__part735_behav;
