--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1334 is 
  Port (
    lo7784: in std_logic;
    n43799_1: inout std_logic
  );
end Other__carpat__part1334;

architecture Other__carpat__part1334_behav of Other__carpat__part1334 is
begin
    n43799_1 <= ( lo7784 );
end Other__carpat__part1334_behav;
