--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part425 is 
  Port (
    lo3074: in std_logic;
    n9169: inout std_logic
  );
end Other__sudoku_check__part425;

architecture Other__sudoku_check__part425_behav of Other__sudoku_check__part425 is
begin
    n9169 <= ( lo3074 );
end Other__sudoku_check__part425_behav;
