--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part13 is 
  Port (
    lo44: in std_logic;
    po13: inout std_logic
  );
end Cookbook__temp_sense_s5__part13;

architecture Cookbook__temp_sense_s5__part13_behav of Cookbook__temp_sense_s5__part13 is
begin
    po13 <= ( lo44 );
end Cookbook__temp_sense_s5__part13_behav;
