--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part289 is 
  Port (
    lo1412: in std_logic;
    n10025_1: inout std_logic
  );
end Other__fp_operators__part289;

architecture Other__fp_operators__part289_behav of Other__fp_operators__part289 is
begin
    n10025_1 <= ( lo1412 );
end Other__fp_operators__part289_behav;
