--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1057 is 
  Port (
    lo7150: in std_logic;
    n37934_1: inout std_logic
  );
end Other__carpat__part1057;

architecture Other__carpat__part1057_behav of Other__carpat__part1057 is
begin
    n37934_1 <= ( lo7150 );
end Other__carpat__part1057_behav;
