--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part127 is 
  Port (
    pi0982: in std_logic;
    n32024_1: inout std_logic
  );
end Other__carpat__part127;

architecture Other__carpat__part127_behav of Other__carpat__part127 is
begin
    n32024_1 <= ( pi0982 );
end Other__carpat__part127_behav;
