--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part507 is 
  Port (
    lo2503: in std_logic;
    n14734: inout std_logic
  );
end Other__carpat__part507;

architecture Other__carpat__part507_behav of Other__carpat__part507 is
begin
    n14734 <= ( lo2503 );
end Other__carpat__part507_behav;
