--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part105 is 
  Port (
    lo2730: in std_logic;
    n5969: inout std_logic
  );
end Other__sudoku_check__part105;

architecture Other__sudoku_check__part105_behav of Other__sudoku_check__part105 is
begin
    n5969 <= ( lo2730 );
end Other__sudoku_check__part105_behav;
