--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part36 is 
  Port (
    lo33: in std_logic;
    po37: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part36;

architecture Cookbook__x4_encoder_8b10b__part36_behav of Cookbook__x4_encoder_8b10b__part36 is
begin
    po37 <= ( lo33 );
end Cookbook__x4_encoder_8b10b__part36_behav;
