--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lfsr__part10 is 
  Port (
    lo16: in std_logic;
    n150,po15: inout std_logic
  );
end Cookbook__lfsr__part10;

architecture Cookbook__lfsr__part10_behav of Cookbook__lfsr__part10 is
begin
    n150 <= ( lo16 );
    po15 <= ( lo16 );
end Cookbook__lfsr__part10_behav;
