--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2152 is 
  Port (
    lo4785: in std_logic;
    n28511: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2152;

architecture Other__ucsb_152_tap_fir__part2152_behav of Other__ucsb_152_tap_fir__part2152 is
begin
    n28511 <= ( lo4785 );
end Other__ucsb_152_tap_fir__part2152_behav;
