--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part208 is 
  Port (
    lo03254: in std_logic;
    po0917: inout std_logic
  );
end Other__ray__part208;

architecture Other__ray__part208_behav of Other__ray__part208 is
begin
    po0917 <= ( lo03254 );
end Other__ray__part208_behav;
