--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part249 is 
  Port (
    lo2898: in std_logic;
    n7409: inout std_logic
  );
end Other__sudoku_check__part249;

architecture Other__sudoku_check__part249_behav of Other__sudoku_check__part249 is
begin
    n7409 <= ( lo2898 );
end Other__sudoku_check__part249_behav;
