--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part172 is 
  Port (
    lo0052: in std_logic;
    po59: inout std_logic
  );
end IWLS2005__des_perf__part172;

architecture IWLS2005__des_perf__part172_behav of IWLS2005__des_perf__part172 is
begin
    po59 <= ( lo0052 );
end IWLS2005__des_perf__part172_behav;
