--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1356 is 
  Port (
    lo1425: in std_logic;
    n7424: inout std_logic
  );
end Cookbook__fec_check__part1356;

architecture Cookbook__fec_check__part1356_behav of Cookbook__fec_check__part1356 is
begin
    n7424 <= ( lo1425 );
end Cookbook__fec_check__part1356_behav;
