--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2160 is 
  Port (
    lo2229: in std_logic;
    n11444: inout std_logic
  );
end Cookbook__fec_check__part2160;

architecture Cookbook__fec_check__part2160_behav of Cookbook__fec_check__part2160 is
begin
    n11444 <= ( lo2229 );
end Cookbook__fec_check__part2160_behav;
