--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1045 is 
  Port (
    lo7138: in std_logic;
    n37874_1: inout std_logic
  );
end Other__carpat__part1045;

architecture Other__carpat__part1045_behav of Other__carpat__part1045 is
begin
    n37874_1 <= ( lo7138 );
end Other__carpat__part1045_behav;
