--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part921 is 
  Port (
    lo4290: in std_logic;
    n16939: inout std_logic
  );
end Other__sudoku_check__part921;

architecture Other__sudoku_check__part921_behav of Other__sudoku_check__part921 is
begin
    n16939 <= ( lo4290 );
end Other__sudoku_check__part921_behav;
