--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1746 is 
  Port (
    lo1815: in std_logic;
    n9374: inout std_logic
  );
end Cookbook__fec_check__part1746;

architecture Cookbook__fec_check__part1746_behav of Cookbook__fec_check__part1746 is
begin
    n9374 <= ( lo1815 );
end Cookbook__fec_check__part1746_behav;
