--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part785 is 
  Port (
    lo0854: in std_logic;
    n4569: inout std_logic
  );
end Cookbook__fec_check__part785;

architecture Cookbook__fec_check__part785_behav of Cookbook__fec_check__part785 is
begin
    n4569 <= ( lo0854 );
end Cookbook__fec_check__part785_behav;
