--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part580 is 
  Port (
    lo4185: in std_logic;
    n21245: inout std_logic
  );
end IWLS2005__des_perf__part580;

architecture IWLS2005__des_perf__part580_behav of IWLS2005__des_perf__part580 is
begin
    n21245 <= ( lo4185 );
end IWLS2005__des_perf__part580_behav;
