--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part123 is 
  Port (
    lo0807: in std_logic;
    n469: inout std_logic
  );
end IWLS93__s38417__part123;

architecture IWLS93__s38417__part123_behav of IWLS93__s38417__part123 is
begin
    n469 <= ( lo0807 );
end IWLS93__s38417__part123_behav;
