--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1818 is 
  Port (
    lo6722: in std_logic;
    n33530: inout std_logic
  );
end IWLS2005__des_perf__part1818;

architecture IWLS2005__des_perf__part1818_behav of IWLS2005__des_perf__part1818 is
begin
    n33530 <= ( lo6722 );
end IWLS2005__des_perf__part1818_behav;
