--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1063 is 
  Port (
    lo5104: in std_logic;
    n25375: inout std_logic
  );
end IWLS2005__des_perf__part1063;

architecture IWLS2005__des_perf__part1063_behav of IWLS2005__des_perf__part1063 is
begin
    n25375 <= ( lo5104 );
end IWLS2005__des_perf__part1063_behav;
