--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1148 is 
  Port (
    lo5306: in std_logic;
    n26600_1: inout std_logic
  );
end IWLS2005__des_perf__part1148;

architecture IWLS2005__des_perf__part1148_behav of IWLS2005__des_perf__part1148 is
begin
    n26600_1 <= ( lo5306 );
end IWLS2005__des_perf__part1148_behav;
