--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1564 is 
  Port (
    lo3535: in std_logic;
    n22256: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1564;

architecture Other__ucsb_152_tap_fir__part1564_behav of Other__ucsb_152_tap_fir__part1564 is
begin
    n22256 <= ( lo3535 );
end Other__ucsb_152_tap_fir__part1564_behav;
