--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part720 is 
  Port (
    lo0789: in std_logic;
    n4244: inout std_logic
  );
end Cookbook__fec_check__part720;

architecture Cookbook__fec_check__part720_behav of Cookbook__fec_check__part720 is
begin
    n4244 <= ( lo0789 );
end Cookbook__fec_check__part720_behav;
