--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part682 is 
  Port (
    lo06179: in std_logic;
    po1855,po1891: inout std_logic
  );
end Other__ray__part682;

architecture Other__ray__part682_behav of Other__ray__part682 is
begin
    po1855 <= ( lo06179 );
    po1891 <= ( lo06179 );
end Other__ray__part682_behav;
