--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part739 is 
  Port (
    lo0808: in std_logic;
    n4339: inout std_logic
  );
end Cookbook__fec_check__part739;

architecture Cookbook__fec_check__part739_behav of Cookbook__fec_check__part739 is
begin
    n4339 <= ( lo0808 );
end Cookbook__fec_check__part739_behav;
