--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3011 is 
  Port (
    lo8324: in std_logic;
    n42085_1: inout std_logic
  );
end IWLS2005__des_perf__part3011;

architecture IWLS2005__des_perf__part3011_behav of IWLS2005__des_perf__part3011 is
begin
    n42085_1 <= ( lo8324 );
end IWLS2005__des_perf__part3011_behav;
