--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s444__part2 is 
  Port (
    lo15: in std_logic;
    po5: inout std_logic
  );
end ISCAS__s444__part2;

architecture ISCAS__s444__part2_behav of ISCAS__s444__part2 is
begin
    po5 <= ( lo15 );
end ISCAS__s444__part2_behav;
