--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part17 is 
  Port (
    lo0086: in std_logic;
    n729: inout std_logic
  );
end Cookbook__fec_check__part17;

architecture Cookbook__fec_check__part17_behav of Cookbook__fec_check__part17 is
begin
    n729 <= ( lo0086 );
end Cookbook__fec_check__part17_behav;
