--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part557 is 
  Port (
    lo4144: in std_logic;
    n20645: inout std_logic
  );
end IWLS2005__des_perf__part557;

architecture IWLS2005__des_perf__part557_behav of IWLS2005__des_perf__part557 is
begin
    n20645 <= ( lo4144 );
end IWLS2005__des_perf__part557_behav;
