--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part628 is 
  Port (
    lo5016: in std_logic;
    n22224: inout std_logic
  );
end Other__carpat__part628;

architecture Other__carpat__part628_behav of Other__carpat__part628 is
begin
    n22224 <= ( lo5016 );
end Other__carpat__part628_behav;
