--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1766 is 
  Port (
    lo8837: in std_logic;
    po292: inout std_logic
  );
end Other__carpat__part1766;

architecture Other__carpat__part1766_behav of Other__carpat__part1766 is
begin
    po292 <= ( lo8837 );
end Other__carpat__part1766_behav;
