--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1067 is 
  Port (
    lo1136: in std_logic;
    n5979: inout std_logic
  );
end Cookbook__fec_check__part1067;

architecture Cookbook__fec_check__part1067_behav of Cookbook__fec_check__part1067 is
begin
    n5979 <= ( lo1136 );
end Cookbook__fec_check__part1067_behav;
