--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part164 is 
  Port (
    lo0363: in std_logic;
    n6266: inout std_logic
  );
end Other__ucsb_152_tap_fir__part164;

architecture Other__ucsb_152_tap_fir__part164_behav of Other__ucsb_152_tap_fir__part164 is
begin
    n6266 <= ( lo0363 );
end Other__ucsb_152_tap_fir__part164_behav;
