--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1628 is 
  Port (
    lo6297: in std_logic;
    n31220: inout std_logic
  );
end IWLS2005__des_perf__part1628;

architecture IWLS2005__des_perf__part1628_behav of IWLS2005__des_perf__part1628 is
begin
    n31220 <= ( lo6297 );
end IWLS2005__des_perf__part1628_behav;
