--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part686 is 
  Port (
    lo5209: in std_logic;
    n25054: inout std_logic
  );
end Other__carpat__part686;

architecture Other__carpat__part686_behav of Other__carpat__part686 is
begin
    n25054 <= ( lo5209 );
end Other__carpat__part686_behav;
