--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1423 is 
  Port (
    lo7873: in std_logic;
    n44244_1: inout std_logic
  );
end Other__carpat__part1423;

architecture Other__carpat__part1423_behav of Other__carpat__part1423 is
begin
    n44244_1 <= ( lo7873 );
end Other__carpat__part1423_behav;
