--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2276 is 
  Port (
    lo5027: in std_logic;
    n29716: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2276;

architecture Other__ucsb_152_tap_fir__part2276_behav of Other__ucsb_152_tap_fir__part2276 is
begin
    n29716 <= ( lo5027 );
end Other__ucsb_152_tap_fir__part2276_behav;
