--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part851 is 
  Port (
    lo0920: in std_logic;
    n4899: inout std_logic
  );
end Cookbook__fec_check__part851;

architecture Cookbook__fec_check__part851_behav of Cookbook__fec_check__part851 is
begin
    n4899 <= ( lo0920 );
end Cookbook__fec_check__part851_behav;
