--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part312 is 
  Port (
    lo1177: in std_logic;
    n6395: inout std_logic
  );
end IWLS2005__des_perf__part312;

architecture IWLS2005__des_perf__part312_behav of IWLS2005__des_perf__part312 is
begin
    n6395 <= ( lo1177 );
end IWLS2005__des_perf__part312_behav;
