--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2298 is 
  Port (
    lo5080: in std_logic;
    n29976: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2298;

architecture Other__ucsb_152_tap_fir__part2298_behav of Other__ucsb_152_tap_fir__part2298 is
begin
    n29976 <= ( lo5080 );
end Other__ucsb_152_tap_fir__part2298_behav;
