--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2095 is 
  Port (
    lo2164: in std_logic;
    n11119: inout std_logic
  );
end Cookbook__fec_check__part2095;

architecture Cookbook__fec_check__part2095_behav of Cookbook__fec_check__part2095 is
begin
    n11119 <= ( lo2164 );
end Cookbook__fec_check__part2095_behav;
