--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part60 is 
  Port (
    lo57: in std_logic;
    po27: inout std_logic
  );
end Cookbook__approx_fp_div__part60;

architecture Cookbook__approx_fp_div__part60_behav of Cookbook__approx_fp_div__part60 is
begin
    po27 <= ( lo57 );
end Cookbook__approx_fp_div__part60_behav;
