--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part944 is 
  Port (
    lo4864: in std_logic;
    n24355: inout std_logic
  );
end IWLS2005__des_perf__part944;

architecture IWLS2005__des_perf__part944_behav of IWLS2005__des_perf__part944 is
begin
    n24355 <= ( lo4864 );
end IWLS2005__des_perf__part944_behav;
