--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part134 is 
  Port (
    lo0878: in std_logic;
    n4314: inout std_logic
  );
end IWLS93__s38417__part134;

architecture IWLS93__s38417__part134_behav of IWLS93__s38417__part134 is
begin
    n4314 <= ( lo0878 );
end IWLS93__s38417__part134_behav;
