--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part94 is 
  Port (
    lo331: in std_logic;
    po016: inout std_logic
  );
end IWLS2005__aes_core__part94;

architecture IWLS2005__aes_core__part94_behav of IWLS2005__aes_core__part94 is
begin
    po016 <= ( lo331 );
end IWLS2005__aes_core__part94_behav;
