--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part293 is 
  Port (
    lo0362: in std_logic;
    n2109: inout std_logic
  );
end Cookbook__fec_check__part293;

architecture Cookbook__fec_check__part293_behav of Cookbook__fec_check__part293 is
begin
    n2109 <= ( lo0362 );
end Cookbook__fec_check__part293_behav;
