--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1839 is 
  Port (
    lo9112: in std_logic;
    po476: inout std_logic
  );
end Other__carpat__part1839;

architecture Other__carpat__part1839_behav of Other__carpat__part1839 is
begin
    po476 <= ( lo9112 );
end Other__carpat__part1839_behav;
