--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part32 is 
  Port (
    lo095: in std_logic;
    po041: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part32;

architecture Cookbook__soft_ecc_ram_64bit__part32_behav of Cookbook__soft_ecc_ram_64bit__part32 is
begin
    po041 <= ( lo095 );
end Cookbook__soft_ecc_ram_64bit__part32_behav;
