--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part688 is 
  Port (
    lo4366: in std_logic;
    n22170: inout std_logic
  );
end IWLS2005__des_perf__part688;

architecture IWLS2005__des_perf__part688_behav of IWLS2005__des_perf__part688 is
begin
    n22170 <= ( lo4366 );
end IWLS2005__des_perf__part688_behav;
