--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part130 is 
  Port (
    lo0009: in std_logic;
    po44: inout std_logic
  );
end IWLS2005__des_perf__part130;

architecture IWLS2005__des_perf__part130_behav of IWLS2005__des_perf__part130 is
begin
    po44 <= ( lo0009 );
end IWLS2005__des_perf__part130_behav;
