--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part160 is 
  Port (
    lo1353: in std_logic;
    n7749: inout std_logic
  );
end ISCAS__s38417__part160;

architecture ISCAS__s38417__part160_behav of ISCAS__s38417__part160 is
begin
    n7749 <= ( not lo1353 );
end ISCAS__s38417__part160_behav;
