--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part949 is 
  Port (
    lo1018: in std_logic;
    n5389: inout std_logic
  );
end Cookbook__fec_check__part949;

architecture Cookbook__fec_check__part949_behav of Cookbook__fec_check__part949 is
begin
    n5389 <= ( lo1018 );
end Cookbook__fec_check__part949_behav;
