--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part52 is 
  Port (
    lo0121: in std_logic;
    n904: inout std_logic
  );
end Cookbook__fec_check__part52;

architecture Cookbook__fec_check__part52_behav of Cookbook__fec_check__part52 is
begin
    n904 <= ( lo0121 );
end Cookbook__fec_check__part52_behav;
