--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part44 is 
  Port (
    lo0116: in std_logic;
    n1684: inout std_logic
  );
end Cookbook__ucrypt__part44;

architecture Cookbook__ucrypt__part44_behav of Cookbook__ucrypt__part44 is
begin
    n1684 <= ( lo0116 );
end Cookbook__ucrypt__part44_behav;
