--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part646 is 
  Port (
    lo3295: in std_logic;
    n11379: inout std_logic
  );
end Other__sudoku_check__part646;

architecture Other__sudoku_check__part646_behav of Other__sudoku_check__part646 is
begin
    n11379 <= ( lo3295 );
end Other__sudoku_check__part646_behav;
