--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part559 is 
  Port (
    lo4146: in std_logic;
    n20685: inout std_logic
  );
end IWLS2005__des_perf__part559;

architecture IWLS2005__des_perf__part559_behav of IWLS2005__des_perf__part559 is
begin
    n20685 <= ( lo4146 );
end IWLS2005__des_perf__part559_behav;
