--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part627 is 
  Port (
    lo06108: in std_logic;
    n38486: inout std_logic
  );
end Other__ray__part627;

architecture Other__ray__part627_behav of Other__ray__part627 is
begin
    n38486 <= ( lo06108 );
end Other__ray__part627_behav;
