--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part9 is 
  Port (
    lo014: in std_logic;
    n772: inout std_logic
  );
end Cookbook__gearbox_67_40__part9;

architecture Cookbook__gearbox_67_40__part9_behav of Cookbook__gearbox_67_40__part9 is
begin
    n772 <= ( lo014 );
end Cookbook__gearbox_67_40__part9_behav;
