--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1333 is 
  Port (
    lo1402: in std_logic;
    n7309: inout std_logic
  );
end Cookbook__fec_check__part1333;

architecture Cookbook__fec_check__part1333_behav of Cookbook__fec_check__part1333 is
begin
    n7309 <= ( lo1402 );
end Cookbook__fec_check__part1333_behav;
