--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part939 is 
  Port (
    lo6784: in std_logic;
    n34259_1: inout std_logic
  );
end Other__carpat__part939;

architecture Other__carpat__part939_behav of Other__carpat__part939 is
begin
    n34259_1 <= ( lo6784 );
end Other__carpat__part939_behav;
