--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s967__part22 is 
  Port (
    lo27: in std_logic;
    po21: inout std_logic
  );
end ISCAS__s967__part22;

architecture ISCAS__s967__part22_behav of ISCAS__s967__part22 is
begin
    po21 <= ( lo27 );
end ISCAS__s967__part22_behav;
