--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part483 is 
  Port (
    lo3132: in std_logic;
    n9749: inout std_logic
  );
end Other__sudoku_check__part483;

architecture Other__sudoku_check__part483_behav of Other__sudoku_check__part483 is
begin
    n9749 <= ( lo3132 );
end Other__sudoku_check__part483_behav;
