--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part64 is 
  Port (
    lo00939: in std_logic;
    po065: inout std_logic
  );
end IWLS2005__ethernet__part64;

architecture IWLS2005__ethernet__part64_behav of IWLS2005__ethernet__part64 is
begin
    po065 <= ( lo00939 );
end IWLS2005__ethernet__part64_behav;
