--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part134 is 
  Port (
    lo260: in std_logic;
    po078: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part134;

architecture Cookbook__soft_ecc_ram_64bit__part134_behav of Cookbook__soft_ecc_ram_64bit__part134 is
begin
    po078 <= ( lo260 );
end Cookbook__soft_ecc_ram_64bit__part134_behav;
