--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1382 is 
  Port (
    lo3180: in std_logic;
    n20486: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1382;

architecture Other__ucsb_152_tap_fir__part1382_behav of Other__ucsb_152_tap_fir__part1382 is
begin
    n20486 <= ( lo3180 );
end Other__ucsb_152_tap_fir__part1382_behav;
