--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1491 is 
  Port (
    lo3405: in std_logic;
    n21531: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1491;

architecture Other__ucsb_152_tap_fir__part1491_behav of Other__ucsb_152_tap_fir__part1491 is
begin
    n21531 <= ( lo3405 );
end Other__ucsb_152_tap_fir__part1491_behav;
