--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part9 is 
  Port (
    lo30: in std_logic;
    po09: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part9;

architecture Cookbook__soft_ecc_ram_16bit__part9_behav of Cookbook__soft_ecc_ram_16bit__part9 is
begin
    po09 <= ( lo30 );
end Cookbook__soft_ecc_ram_16bit__part9_behav;
