--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part19 is 
  Port (
    lo060: in std_logic;
    n598: inout std_logic
  );
end ISCAS__s13207__part19;

architecture ISCAS__s13207__part19_behav of ISCAS__s13207__part19 is
begin
    n598 <= ( lo060 );
end ISCAS__s13207__part19_behav;
