--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part5 is 
  Port (
    lo00412: in std_logic;
    po22: inout std_logic
  );
end IWLS2005__vga_lcd__part5;

architecture IWLS2005__vga_lcd__part5_behav of IWLS2005__vga_lcd__part5 is
begin
    po22 <= ( lo00412 );
end IWLS2005__vga_lcd__part5_behav;
