--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part22 is 
  Port (
    lo060: in std_logic;
    po10: inout std_logic
  );
end Cookbook__fec_gen__part22;

architecture Cookbook__fec_gen__part22_behav of Cookbook__fec_gen__part22 is
begin
    po10 <= ( lo060 );
end Cookbook__fec_gen__part22_behav;
