--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part42 is 
  Port (
    lo40: in std_logic;
    n221: inout std_logic
  );
end Cookbook__pipeline_add__part42;

architecture Cookbook__pipeline_add__part42_behav of Cookbook__pipeline_add__part42 is
begin
    n221 <= ( lo40 );
end Cookbook__pipeline_add__part42_behav;
