--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part4 is 
  Port (
    pi26: in std_logic;
    n829: inout std_logic
  );
end Cookbook__ucrypt__part4;

architecture Cookbook__ucrypt__part4_behav of Cookbook__ucrypt__part4 is
begin
    n829 <= ( pi26 );
end Cookbook__ucrypt__part4_behav;
