--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part977 is 
  Port (
    lo4346: in std_logic;
    n17219: inout std_logic
  );
end Other__sudoku_check__part977;

architecture Other__sudoku_check__part977_behav of Other__sudoku_check__part977 is
begin
    n17219 <= ( lo4346 );
end Other__sudoku_check__part977_behav;
