--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part35 is 
  Port (
    lo2104: in std_logic;
    n5269: inout std_logic
  );
end Other__sudoku_check__part35;

architecture Other__sudoku_check__part35_behav of Other__sudoku_check__part35 is
begin
    n5269 <= ( lo2104 );
end Other__sudoku_check__part35_behav;
