--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2164 is 
  Port (
    lo4799: in std_logic;
    n28581: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2164;

architecture Other__ucsb_152_tap_fir__part2164_behav of Other__ucsb_152_tap_fir__part2164 is
begin
    n28581 <= ( lo4799 );
end Other__ucsb_152_tap_fir__part2164_behav;
