--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1408 is 
  Port (
    lo4777: in std_logic;
    n19374_1: inout std_logic
  );
end Other__sudoku_check__part1408;

architecture Other__sudoku_check__part1408_behav of Other__sudoku_check__part1408 is
begin
    n19374_1 <= ( lo4777 );
end Other__sudoku_check__part1408_behav;
