--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part801 is 
  Port (
    lo4170: in std_logic;
    n14659: inout std_logic
  );
end Other__sudoku_check__part801;

architecture Other__sudoku_check__part801_behav of Other__sudoku_check__part801 is
begin
    n14659 <= ( lo4170 );
end Other__sudoku_check__part801_behav;
