--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part47 is 
  Port (
    lo0115: in std_logic;
    po123: inout std_logic
  );
end Other__mem__part47;

architecture Other__mem__part47_behav of Other__mem__part47 is
begin
    po123 <= ( lo0115 );
end Other__mem__part47_behav;
