--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part77 is 
  Port (
    lo0146: in std_logic;
    n1029: inout std_logic
  );
end Cookbook__fec_check__part77;

architecture Cookbook__fec_check__part77_behav of Cookbook__fec_check__part77 is
begin
    n1029 <= ( lo0146 );
end Cookbook__fec_check__part77_behav;
