--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part125 is 
  Port (
    lo0825: in std_logic;
    n4739_1: inout std_logic
  );
end IWLS93__s38417__part125;

architecture IWLS93__s38417__part125_behav of IWLS93__s38417__part125 is
begin
    n4739_1 <= ( lo0825 );
end IWLS93__s38417__part125_behav;
