--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part469 is 
  Port (
    lo1307: in std_logic;
    n10124: inout std_logic
  );
end Other__carpat__part469;

architecture Other__carpat__part469_behav of Other__carpat__part469 is
begin
    n10124 <= ( lo1307 );
end Other__carpat__part469_behav;
