--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part125 is 
  Port (
    lo3296: in std_logic;
    n16929: inout std_logic
  );
end IWLS2005__pci_bridge32__part125;

architecture IWLS2005__pci_bridge32__part125_behav of IWLS2005__pci_bridge32__part125 is
begin
    n16929 <= ( lo3296 );
end IWLS2005__pci_bridge32__part125_behav;
