--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part68 is 
  Port (
    lo234: in std_logic;
    n1468: inout std_logic
  );
end ISCAS__s13207__part68;

architecture ISCAS__s13207__part68_behav of ISCAS__s13207__part68 is
begin
    n1468 <= ( lo234 );
end ISCAS__s13207__part68_behav;
