--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part81 is 
  Port (
    lo0602: in std_logic;
    n3284: inout std_logic
  );
end LGSynth91__s38417__part81;

architecture LGSynth91__s38417__part81_behav of LGSynth91__s38417__part81 is
begin
    n3284 <= ( lo0602 );
end LGSynth91__s38417__part81_behav;
