--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part629 is 
  Port (
    lo5017: in std_logic;
    n22229: inout std_logic
  );
end Other__carpat__part629;

architecture Other__carpat__part629_behav of Other__carpat__part629 is
begin
    n22229 <= ( lo5017 );
end Other__carpat__part629_behav;
