--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1855 is 
  Port (
    lo1924: in std_logic;
    n9919: inout std_logic
  );
end Cookbook__fec_check__part1855;

architecture Cookbook__fec_check__part1855_behav of Cookbook__fec_check__part1855 is
begin
    n9919 <= ( lo1924 );
end Cookbook__fec_check__part1855_behav;
