--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8: in std_logic;
    po0,po1,po2,po3,po4: inout std_logic
  );
end top;

architecture top_behav of top is
signal n15,n17,n19: std_logic;
begin
    po4 <= ( not pi8 and not pi6 and pi7 )
      or ( not pi8 and pi6 and not pi7 )
      or ( pi8 and not pi6 and not pi7 )
      or ( pi8 and pi6 and pi7 );
    n15 <= ( pi8 and pi6 )
      or ( pi8 and pi7 )
      or ( pi6 and pi7 );
    po3 <= ( not n15 and not pi2 and pi5 )
      or ( not n15 and pi2 and not pi5 )
      or ( n15 and not pi2 and not pi5 )
      or ( n15 and pi2 and pi5 );
    n17 <= ( n15 and pi2 )
      or ( n15 and pi5 )
      or ( pi2 and pi5 );
    po2 <= ( not n17 and not pi1 and pi4 )
      or ( not n17 and pi1 and not pi4 )
      or ( n17 and not pi1 and not pi4 )
      or ( n17 and pi1 and pi4 );
    n19 <= ( n17 and pi1 )
      or ( n17 and pi4 )
      or ( pi1 and pi4 );
    po1 <= ( not n19 and not pi0 and pi3 )
      or ( not n19 and pi0 and not pi3 )
      or ( n19 and not pi0 and not pi3 )
      or ( n19 and pi0 and pi3 );
    po0 <= ( n19 and pi0 )
      or ( n19 and pi3 )
      or ( pi0 and pi3 );
end top_behav;
