--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part52 is 
  Port (
    lo5745,lo5746,lo5747,lo5748: in std_logic;
    n27364_1,n27699_1,n27704_1,n27709_1,n27714_1,n27719_1,n27724_1,n27729_1,n27734_1: inout std_logic
  );
end Other__sudoku_check__part52;

architecture Other__sudoku_check__part52_behav of Other__sudoku_check__part52 is
begin
    n27364_1 <= ( lo5745 and not lo5746 and not lo5747 and not lo5748 );
    n27699_1 <= ( lo5745 and not lo5746 and not lo5747 and lo5748 );
    n27704_1 <= ( not lo5745 and not lo5746 and not lo5747 and lo5748 );
    n27709_1 <= ( lo5745 and lo5746 and lo5747 and not lo5748 );
    n27714_1 <= ( not lo5745 and lo5746 and lo5747 and not lo5748 );
    n27719_1 <= ( lo5745 and not lo5746 and lo5747 and not lo5748 );
    n27724_1 <= ( not lo5745 and not lo5746 and lo5747 and not lo5748 );
    n27729_1 <= ( lo5745 and lo5746 and not lo5747 and not lo5748 );
    n27734_1 <= ( not lo5745 and lo5746 and not lo5747 and not lo5748 );
end Other__sudoku_check__part52_behav;
