--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part38 is 
  Port (
    lo3466,lo3454,lo3478,lo3442,lo3430,lo3418,lo3406,lo3792: in std_logic;
    n18939: inout std_logic
  );
end Cookbook__fec_check__part38;

architecture Cookbook__fec_check__part38_behav of Cookbook__fec_check__part38 is
signal n13696,n13697,n13698,n13699,n13700,n13701: std_logic;
begin
    n13696 <= not (( not lo3466 and not lo3454 ));
    n13697 <= not (( not lo3478 and not n13696 ));
    n13698 <= not (( not lo3442 and not lo3430 ));
    n13699 <= not (( not lo3418 and not lo3406 ));
    n13700 <= not (( not n13698 and not n13699 ));
    n13701 <= not (( not n13697 and not n13700 ));
    n18939 <= not (( not n13701 and not lo3792 ));
end Cookbook__fec_check__part38_behav;
