--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part59 is 
  Port (
    lo3687,lo3675,lo3651,lo3639,lo3663,lo3615,lo3603,lo3627,lo3579,lo3567,lo3591: in std_logic;
    n19034: inout std_logic
  );
end Cookbook__fec_check__part59;

architecture Cookbook__fec_check__part59_behav of Cookbook__fec_check__part59 is
signal n13512,n13513,n13514,n13515,n13516,n13517,n13518,n13519,n13520: std_logic;
begin
    n13512 <= not (( not lo3687 and not lo3675 ));
    n13513 <= not (( not lo3651 and not lo3639 ));
    n13514 <= not (( not lo3663 and not n13513 ));
    n13515 <= not (( not n13512 and not n13514 ));
    n13516 <= not (( not lo3615 and not lo3603 ));
    n13517 <= not (( not lo3627 and not n13516 ));
    n13518 <= not (( not lo3579 and not lo3567 ));
    n13519 <= not (( not lo3591 and not n13518 ));
    n13520 <= not (( not n13517 and not n13519 ));
    n19034 <= not (( not n13515 and not n13520 ));
end Cookbook__fec_check__part59_behav;
