--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,lo0,lo1: in std_logic;
    po0,n7,n12_1: inout std_logic
  );
end top;

architecture top_behav of top is
signal n12,n13,n14,n15,n16,n17,n18,n19,n20: std_logic;
begin
    po0 <= ( not n12 );
    n7 <= ( not n13 );
    n12_1 <= ( not n14 );
    n12 <= ( not n15 and not n17 and not n18 and not n19 and not n20 );
    n13 <= ( not n15 and not n16 and not n17 and not n18 );
    n14 <= ( not n15 and not n16 and not n19 and not n20 );
    n15 <= ( not pi0 and not pi1 and lo0 );
    n16 <= ( pi0 and pi1 );
    n17 <= ( pi1 and not lo1 );
    n18 <= ( pi0 and not lo1 );
    n19 <= ( pi1 and lo1 );
    n20 <= ( pi0 and lo1 );
end top_behav;
