--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part61 is 
  Port (
    lo5781,lo5782,lo5783,lo5784: in std_logic;
    n27529_1,n29379_1,n29564_1,n29744_1,n29924,n30104_1,n30284,n30464,n30644: inout std_logic
  );
end Other__sudoku_check__part61;

architecture Other__sudoku_check__part61_behav of Other__sudoku_check__part61 is
begin
    n27529_1 <= ( lo5781 and not lo5782 and not lo5783 and not lo5784 );
    n29379_1 <= ( lo5781 and not lo5782 and not lo5783 and lo5784 );
    n29564_1 <= ( not lo5781 and not lo5782 and not lo5783 and lo5784 );
    n29744_1 <= ( lo5781 and lo5782 and lo5783 and not lo5784 );
    n29924 <= ( not lo5781 and lo5782 and lo5783 and not lo5784 );
    n30104_1 <= ( lo5781 and not lo5782 and lo5783 and not lo5784 );
    n30284 <= ( not lo5781 and not lo5782 and lo5783 and not lo5784 );
    n30464 <= ( lo5781 and lo5782 and not lo5783 and not lo5784 );
    n30644 <= ( not lo5781 and lo5782 and not lo5783 and not lo5784 );
end Other__sudoku_check__part61_behav;
