--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part44 is 
  Port (
    lo5713,lo5714,lo5715,lo5716: in std_logic;
    n27284_1,n27439_1,n27444_1,n27449_1,n27454_1,n27459_1,n27464_1,n27469_1,n27474_1: inout std_logic
  );
end Other__sudoku_check__part44;

architecture Other__sudoku_check__part44_behav of Other__sudoku_check__part44 is
begin
    n27284_1 <= ( lo5713 and not lo5714 and not lo5715 and not lo5716 );
    n27439_1 <= ( lo5713 and not lo5714 and not lo5715 and lo5716 );
    n27444_1 <= ( not lo5713 and not lo5714 and not lo5715 and lo5716 );
    n27449_1 <= ( lo5713 and lo5714 and lo5715 and not lo5716 );
    n27454_1 <= ( not lo5713 and lo5714 and lo5715 and not lo5716 );
    n27459_1 <= ( lo5713 and not lo5714 and lo5715 and not lo5716 );
    n27464_1 <= ( not lo5713 and not lo5714 and lo5715 and not lo5716 );
    n27469_1 <= ( lo5713 and lo5714 and not lo5715 and not lo5716 );
    n27474_1 <= ( not lo5713 and lo5714 and not lo5715 and not lo5716 );
end Other__sudoku_check__part44_behav;
