--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part53 is 
  Port (
    lo3621,lo3609,lo3585,lo3573,lo3597,lo3549,lo3537,lo3561,lo3513,lo3501,lo3525: in std_logic;
    n19004: inout std_logic
  );
end Cookbook__fec_check__part53;

architecture Cookbook__fec_check__part53_behav of Cookbook__fec_check__part53 is
signal n13572,n13573,n13574,n13575,n13576,n13577,n13578,n13579,n13580: std_logic;
begin
    n13572 <= not (( not lo3621 and not lo3609 ));
    n13573 <= not (( not lo3585 and not lo3573 ));
    n13574 <= not (( not lo3597 and not n13573 ));
    n13575 <= not (( not n13572 and not n13574 ));
    n13576 <= not (( not lo3549 and not lo3537 ));
    n13577 <= not (( not lo3561 and not n13576 ));
    n13578 <= not (( not lo3513 and not lo3501 ));
    n13579 <= not (( not lo3525 and not n13578 ));
    n13580 <= not (( not n13577 and not n13579 ));
    n19004 <= not (( not n13575 and not n13580 ));
end Cookbook__fec_check__part53_behav;
