--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part10 is 
  Port (
    lo04194,lo04196,lo04195,lo04193,lo04197: in std_logic;
    n27381,n27391,n27376,n27386,n27396: inout std_logic
  );
end QUIP__uoft_raytracer__part10;

architecture QUIP__uoft_raytracer__part10_behav of QUIP__uoft_raytracer__part10 is
signal n52662,n52663,n77342,n77343: std_logic;
begin
    n52662 <= ( lo04194 and lo04196 and not lo04195 );
    n52663 <= ( lo04193 and lo04197 and n52662 )
      or ( lo04197 and n77343 );
    n27381 <= ( not lo04194 and lo04193 and not n52663 )
      or ( lo04194 and not lo04193 and not n52663 );
    n27391 <= ( not lo04196 and n77342 and not n52663 )
      or ( lo04196 and not n77342 and not n52663 );
    n77342 <= ( lo04194 and lo04193 and lo04195 );
    n77343 <= ( lo04194 and lo04193 and lo04195 and lo04196 );
    n27376 <= ( not lo04193 and not lo04197 )
      or ( not lo04193 and not n77343 );
    n27386 <= ( not lo04194 and lo04195 and not n52663 )
      or ( lo04194 and lo04193 and not lo04195 and not n52663 )
      or ( not lo04193 and lo04195 and not n52663 );
    n27396 <= ( not lo04193 and lo04197 and not n77343 )
      or ( not lo04197 and n77343 )
      or ( lo04197 and not n77343 and not n52662 );
end QUIP__uoft_raytracer__part10_behav;
