--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    lo180,lo412,lo422,lo063,lo635,lo601,lo215,lo068,lo260,lo024,lo140,lo518,lo527: in std_logic;
    n862: inout std_logic
  );
end top;

architecture top_behav of top is
signal n4075,n4142,n4230: std_logic;
begin
    n862 <= ( not lo180 and not n4230 and not n4142 and not n4075 );
    n4075 <= not (( not lo412 and not lo422 and not lo063 and not lo635 ));
    n4142 <= not (( not lo601 and not lo215 and not lo068 and not lo260 ));
    n4230 <= not (( not lo024 and not lo140 and not lo518 and not lo527 ));
end top_behav;
