--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part77 is 
  Port (
    lo5845,lo5846,lo5847,lo5848: in std_logic;
    n27849_1,n29304,n29489_1,n29669_1,n29849_1,n30029_1,n30209,n30389,n30569: inout std_logic
  );
end Other__sudoku_check__part77;

architecture Other__sudoku_check__part77_behav of Other__sudoku_check__part77 is
begin
    n27849_1 <= ( lo5845 and not lo5846 and not lo5847 and not lo5848 );
    n29304 <= ( lo5845 and not lo5846 and not lo5847 and lo5848 );
    n29489_1 <= ( not lo5845 and not lo5846 and not lo5847 and lo5848 );
    n29669_1 <= ( lo5845 and lo5846 and lo5847 and not lo5848 );
    n29849_1 <= ( not lo5845 and lo5846 and lo5847 and not lo5848 );
    n30029_1 <= ( lo5845 and not lo5846 and lo5847 and not lo5848 );
    n30209 <= ( not lo5845 and not lo5846 and lo5847 and not lo5848 );
    n30389 <= ( lo5845 and lo5846 and not lo5847 and not lo5848 );
    n30569 <= ( not lo5845 and lo5846 and not lo5847 and not lo5848 );
end Other__sudoku_check__part77_behav;
