--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part75 is 
  Port (
    lo5837,lo5838,lo5839,lo5840: in std_logic;
    n27759_1,n29359_1,n29544,n29724,n29904,n30084,n30264,n30444,n30624: inout std_logic
  );
end Other__sudoku_check__part75;

architecture Other__sudoku_check__part75_behav of Other__sudoku_check__part75 is
begin
    n27759_1 <= ( lo5837 and not lo5838 and not lo5839 and not lo5840 );
    n29359_1 <= ( lo5837 and not lo5838 and not lo5839 and lo5840 );
    n29544 <= ( not lo5837 and not lo5838 and not lo5839 and lo5840 );
    n29724 <= ( lo5837 and lo5838 and lo5839 and not lo5840 );
    n29904 <= ( not lo5837 and lo5838 and lo5839 and not lo5840 );
    n30084 <= ( lo5837 and not lo5838 and lo5839 and not lo5840 );
    n30264 <= ( not lo5837 and not lo5838 and lo5839 and not lo5840 );
    n30444 <= ( lo5837 and lo5838 and not lo5839 and not lo5840 );
    n30624 <= ( not lo5837 and lo5838 and not lo5839 and not lo5840 );
end Other__sudoku_check__part75_behav;
