--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part56 is 
  Port (
    lo3654,lo3642,lo3618,lo3606,lo3630,lo3582,lo3570,lo3594,lo3546,lo3534,lo3558: in std_logic;
    n19019: inout std_logic
  );
end Cookbook__fec_check__part56;

architecture Cookbook__fec_check__part56_behav of Cookbook__fec_check__part56 is
signal n13542,n13543,n13544,n13545,n13546,n13547,n13548,n13549,n13550: std_logic;
begin
    n13542 <= not (( not lo3654 and not lo3642 ));
    n13543 <= not (( not lo3618 and not lo3606 ));
    n13544 <= not (( not lo3630 and not n13543 ));
    n13545 <= not (( not n13542 and not n13544 ));
    n13546 <= not (( not lo3582 and not lo3570 ));
    n13547 <= not (( not lo3594 and not n13546 ));
    n13548 <= not (( not lo3546 and not lo3534 ));
    n13549 <= not (( not lo3558 and not n13548 ));
    n13550 <= not (( not n13547 and not n13549 ));
    n19019 <= not (( not n13545 and not n13550 ));
end Cookbook__fec_check__part56_behav;
