--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part15 is 
  Port (
    lo5597,lo5598,lo5599,lo5600: in std_logic;
    n27104_1,n28544_1,n28549_1,n28554_1,n28559_1,n28564_1,n28569,n28574_1,n28579: inout std_logic
  );
end Other__sudoku_check__part15;

architecture Other__sudoku_check__part15_behav of Other__sudoku_check__part15 is
begin
    n27104_1 <= ( lo5597 and not lo5598 and not lo5599 and not lo5600 );
    n28544_1 <= ( lo5597 and not lo5598 and not lo5599 and lo5600 );
    n28549_1 <= ( not lo5597 and not lo5598 and not lo5599 and lo5600 );
    n28554_1 <= ( lo5597 and lo5598 and lo5599 and not lo5600 );
    n28559_1 <= ( not lo5597 and lo5598 and lo5599 and not lo5600 );
    n28564_1 <= ( lo5597 and not lo5598 and lo5599 and not lo5600 );
    n28569 <= ( not lo5597 and not lo5598 and lo5599 and not lo5600 );
    n28574_1 <= ( lo5597 and lo5598 and not lo5599 and not lo5600 );
    n28579 <= ( not lo5597 and lo5598 and not lo5599 and not lo5600 );
end Other__sudoku_check__part15_behav;
