--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part35 is 
  Port (
    lo5677,lo5678,lo5679,lo5680: in std_logic;
    n27239_1,n29324,n29509_1,n29689,n29869,n30049,n30229,n30409,n30589: inout std_logic
  );
end Other__sudoku_check__part35;

architecture Other__sudoku_check__part35_behav of Other__sudoku_check__part35 is
begin
    n27239_1 <= ( lo5677 and not lo5678 and not lo5679 and not lo5680 );
    n29324 <= ( lo5677 and not lo5678 and not lo5679 and lo5680 );
    n29509_1 <= ( not lo5677 and not lo5678 and not lo5679 and lo5680 );
    n29689 <= ( lo5677 and lo5678 and lo5679 and not lo5680 );
    n29869 <= ( not lo5677 and lo5678 and lo5679 and not lo5680 );
    n30049 <= ( lo5677 and not lo5678 and lo5679 and not lo5680 );
    n30229 <= ( not lo5677 and not lo5678 and lo5679 and not lo5680 );
    n30409 <= ( lo5677 and lo5678 and not lo5679 and not lo5680 );
    n30589 <= ( not lo5677 and lo5678 and not lo5679 and not lo5680 );
end Other__sudoku_check__part35_behav;
