--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,lo1,lo2: in std_logic;
    n5,n10: inout std_logic
  );
end top;

architecture top_behav of top is
signal n13,n14,n15,n16,n17,n18: std_logic;
begin
    n5 <= ( not n13 );
    n10 <= ( not n14 );
    n13 <= ( not n15 and not n16 );
    n14 <= ( not n17 and not n18 );
    n15 <= ( lo1 and not lo2 );
    n16 <= ( not lo1 and lo2 );
    n17 <= ( not pi0 and lo2 );
    n18 <= ( pi0 and not lo2 );
end top_behav;
