--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part28 is 
  Port (
    lo5649,lo5650,lo5651,lo5652: in std_logic;
    n27169_1,n29064_1,n29069,n29074_1,n29079_1,n29084,n29089_1,n29094_1,n29099_1: inout std_logic
  );
end Other__sudoku_check__part28;

architecture Other__sudoku_check__part28_behav of Other__sudoku_check__part28 is
begin
    n27169_1 <= ( lo5649 and not lo5650 and not lo5651 and not lo5652 );
    n29064_1 <= ( lo5649 and not lo5650 and not lo5651 and lo5652 );
    n29069 <= ( not lo5649 and not lo5650 and not lo5651 and lo5652 );
    n29074_1 <= ( lo5649 and lo5650 and lo5651 and not lo5652 );
    n29079_1 <= ( not lo5649 and lo5650 and lo5651 and not lo5652 );
    n29084 <= ( lo5649 and not lo5650 and lo5651 and not lo5652 );
    n29089_1 <= ( not lo5649 and not lo5650 and lo5651 and not lo5652 );
    n29094_1 <= ( lo5649 and lo5650 and not lo5651 and not lo5652 );
    n29099_1 <= ( not lo5649 and lo5650 and not lo5651 and not lo5652 );
end Other__sudoku_check__part28_behav;
