--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part55 is 
  Port (
    lo5757,lo5758,lo5759,lo5760: in std_logic;
    n27419_1,n29374_1,n29559_1,n29739,n29919_1,n30099,n30279,n30459,n30639: inout std_logic
  );
end Other__sudoku_check__part55;

architecture Other__sudoku_check__part55_behav of Other__sudoku_check__part55 is
begin
    n27419_1 <= ( lo5757 and not lo5758 and not lo5759 and not lo5760 );
    n29374_1 <= ( lo5757 and not lo5758 and not lo5759 and lo5760 );
    n29559_1 <= ( not lo5757 and not lo5758 and not lo5759 and lo5760 );
    n29739 <= ( lo5757 and lo5758 and lo5759 and not lo5760 );
    n29919_1 <= ( not lo5757 and lo5758 and lo5759 and not lo5760 );
    n30099 <= ( lo5757 and not lo5758 and lo5759 and not lo5760 );
    n30279 <= ( not lo5757 and not lo5758 and lo5759 and not lo5760 );
    n30459 <= ( lo5757 and lo5758 and not lo5759 and not lo5760 );
    n30639 <= ( not lo5757 and lo5758 and not lo5759 and not lo5760 );
end Other__sudoku_check__part55_behav;
