--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misj__part1 is 
  Port (
    pi06,pi21: in std_logic;
    po08: inout std_logic
  );
end Espresso__misj__part1;

architecture Espresso__misj__part1_behav of Espresso__misj__part1 is
begin
    po08 <= ( not pi06 )
      or ( not pi21 );
end Espresso__misj__part1_behav;
