--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part230 is 
  Port (
    pi2131, CLK: in std_logic;
    po2022: inout std_logic
  );
end Other__umass_weather__part230;

architecture Other__umass_weather__part230_behav of Other__umass_weather__part230 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4897,lo4969,lo5041,li4897,li4969,li5041: std_logic;
begin
    DFF0: DFF port map (li4897, CLK, lo4897);
    DFF1: DFF port map (li4969, CLK, lo4969);
    DFF2: DFF port map (li5041, CLK, lo5041);
    li4897 <= ( lo4969 );
    li4969 <= ( lo5041 );
    li5041 <= ( pi2131 );
    po2022 <= ( lo4897 );
end Other__umass_weather__part230_behav;
