--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__oc_pci__part11 is 
  Port (
    pi247, CLK: in std_logic;
    po327: inout std_logic
  );
end QUIP__oc_pci__part11;

architecture QUIP__oc_pci__part11_behav of QUIP__oc_pci__part11 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo1143,li1143: std_logic;
begin
    DFF0: DFF port map (li1143, CLK, lo1143);
    li1143 <= ( pi247 );
    po327 <= ( lo1143 );
end QUIP__oc_pci__part11_behav;
