--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i3__part1 is 
  Port (
    pi002,pi003: in std_logic;
    po1: inout std_logic
  );
end LGSynth91__i3__part1;

architecture LGSynth91__i3__part1_behav of LGSynth91__i3__part1 is
begin
    po1 <= ( pi002 )
      or ( pi003 );
end LGSynth91__i3__part1_behav;
