--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__screen_saver_cyclone__part2 is 
  Port (
    , CLK: in std_logic;
    po50: inout std_logic
  );
end Other__screen_saver_cyclone__part2;

architecture Other__screen_saver_cyclone__part2_behav of Other__screen_saver_cyclone__part2 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo11257,li11257: std_logic;
begin
    DFF0: DFF port map (li11257, CLK, lo11257);
    li11257 <= ( not lo11257 );
    po50 <= ( lo11257 );
end Other__screen_saver_cyclone__part2_behav;
