--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__x2dn__part4 is 
  Port (
    pi62,pi63,pi64,pi65,pi66: in std_logic;
    po32: inout std_logic
  );
end Espresso__x2dn__part4;

architecture Espresso__x2dn__part4_behav of Espresso__x2dn__part4 is
begin
    po32 <= ( pi63 and pi64 and pi66 )
      or ( pi63 and pi65 and pi66 )
      or ( pi62 and pi63 and not pi64 and not pi65 );
end Espresso__x2dn__part4_behav;
