--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part225 is 
  Port (
    pi2126, CLK: in std_logic;
    po2017: inout std_logic
  );
end Other__umass_weather__part225;

architecture Other__umass_weather__part225_behav of Other__umass_weather__part225 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4892,lo4921,lo4993,li4892,li4921,li4993: std_logic;
begin
    DFF0: DFF port map (li4892, CLK, lo4892);
    DFF1: DFF port map (li4921, CLK, lo4921);
    DFF2: DFF port map (li4993, CLK, lo4993);
    li4892 <= ( lo4921 );
    li4921 <= ( lo4993 );
    li4993 <= ( pi2126 );
    po2017 <= ( lo4892 );
end Other__umass_weather__part225_behav;
