--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part8 is 
  Port (
    pi30,pi31: in std_logic;
    po15: inout std_logic
  );
end Espresso__misg__part8;

architecture Espresso__misg__part8_behav of Espresso__misg__part8 is
begin
    po15 <= ( pi30 )
      or ( pi31 );
end Espresso__misg__part8_behav;
