--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi11,pi12,pi13,pi59,pi60,pi61,pi67,pi68: in std_logic;
    po04,po22,po24: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po04 <= ( not pi11 )
      or ( not pi12 and pi13 );
    po22 <= ( not pi68 )
      or ( not pi12 and not pi59 and not pi60 and not pi61 and pi67 );
    po24 <= ( not pi11 );
end top_behav;
