--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part9 is 
  Port (
    pi41,pi42: in std_logic;
    po18: inout std_logic
  );
end Espresso__misg__part9;

architecture Espresso__misg__part9_behav of Espresso__misg__part9 is
begin
    po18 <= ( not pi41 )
      or ( not pi42 );
end Espresso__misg__part9_behav;
