--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi16,pi17,pi18,pi19: in std_logic;
    po06: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po06 <= ( not pi16 )
      or ( not pi17 )
      or ( not pi18 )
      or ( not pi19 );
end top_behav;
