--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__RISC__part1 is 
  Port (
    pi7752: in std_logic;
    po7519: inout std_logic
  );
end IWLS2005__RISC__part1;

architecture IWLS2005__RISC__part1_behav of IWLS2005__RISC__part1 is
begin
    po7519 <= ( not pi7752 );
end IWLS2005__RISC__part1_behav;
