--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end top;

architecture top_behav of top is
signal n24,n25,n26,n27,n28,n29,n30,n31,n32,n33: std_logic;
begin
    po0 <= ( pi11 and pi10 and pi09 and not n24 );
    po1 <= ( pi15 )
      or ( not n25 );
    po2 <= ( not pi14 )
      or ( not n25 );
    po3 <= ( not pi15 and not pi14 and not pi13 and not n26 );
    n24 <= ( not pi01 )
      or ( not pi00 )
      or ( not n28 )
      or ( not n29 );
    n25 <= ( pi04 and pi05 and pi06 and not n27 )
      or ( pi04 and pi05 and not pi07 and not n27 )
      or ( pi04 and not pi06 and not pi07 and not n27 )
      or ( not pi05 and not pi06 and not pi07 and not n27 );
    n26 <= ( pi05 )
      or ( pi04 )
      or ( not n30 )
      or ( not n31 );
    n27 <= ( not n33 )
      or ( not pi07 and pi08 )
      or ( not pi08 and pi09 )
      or ( not pi09 and pi10 );
    n28 <= ( pi04 and pi03 and pi02 );
    n29 <= ( pi08 and pi07 and pi06 and pi05 );
    n30 <= ( not pi08 and not pi07 and not pi06 );
    n31 <= ( not pi12 and not pi11 and not pi10 and not pi09 );
    n32 <= ( not pi11 and pi12 )
      or ( not pi12 and pi13 )
      or ( not pi13 and pi14 )
      or ( pi04 and not pi15 );
    n33 <= ( not pi11 and not n32 )
      or ( pi10 and not n32 );
end top_behav;
