--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part229 is 
  Port (
    pi2130, CLK: in std_logic;
    po2021: inout std_logic
  );
end Other__umass_weather__part229;

architecture Other__umass_weather__part229_behav of Other__umass_weather__part229 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4896,lo4925,lo4997,li4896,li4925,li4997: std_logic;
begin
    DFF0: DFF port map (li4896, CLK, lo4896);
    DFF1: DFF port map (li4925, CLK, lo4925);
    DFF2: DFF port map (li4997, CLK, lo4997);
    li4896 <= ( lo4925 );
    li4925 <= ( lo4997 );
    li4997 <= ( pi2130 );
    po2021 <= ( lo4896 );
end Other__umass_weather__part229_behav;
