--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C17 is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1: inout std_logic
  );
end LGSynth91__C17;

architecture LGSynth91__C17_behav of LGSynth91__C17 is
signal n9,n10,n11,n12: std_logic;
begin
    po0 <= ( not n10 )
      or ( not n12 );
    po1 <= ( not n12 )
      or ( not n11 );
    n9 <= ( not pi2 )
      or ( not pi3 );
    n10 <= ( not pi0 )
      or ( not pi2 );
    n11 <= ( not n9 )
      or ( not pi4 );
    n12 <= ( not pi1 )
      or ( not n9 );
end LGSynth91__C17_behav;
