--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part1 is 
  Port (
    , CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11: inout std_logic
  );
end ISCAS__s15850__part1;

architecture ISCAS__s15850__part1_behav of ISCAS__s15850__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo021,lo034,lo035,lo036,lo037,lo038,lo039,lo040,lo041,lo117,lo118,lo119,lo120,lo121,lo122,lo123,lo124,lo125,lo126,lo127,lo128,lo595,lo596,li021,li034,li035,li036,li037,li038,li039,li040,li041,li117,li118,li119,li120,li121,li122,li123,li124,li125,li126,li127,li128,li595,li596,n4915,n4916,n4917: std_logic;
begin
    DFF0: DFF port map (li021, CLK, lo021);
    DFF1: DFF port map (li034, CLK, lo034);
    DFF2: DFF port map (li035, CLK, lo035);
    DFF3: DFF port map (li036, CLK, lo036);
    DFF4: DFF port map (li037, CLK, lo037);
    DFF5: DFF port map (li038, CLK, lo038);
    DFF6: DFF port map (li039, CLK, lo039);
    DFF7: DFF port map (li040, CLK, lo040);
    DFF8: DFF port map (li041, CLK, lo041);
    DFF9: DFF port map (li117, CLK, lo117);
    DFF10: DFF port map (li118, CLK, lo118);
    DFF11: DFF port map (li119, CLK, lo119);
    DFF12: DFF port map (li120, CLK, lo120);
    DFF13: DFF port map (li121, CLK, lo121);
    DFF14: DFF port map (li122, CLK, lo122);
    DFF15: DFF port map (li123, CLK, lo123);
    DFF16: DFF port map (li124, CLK, lo124);
    DFF17: DFF port map (li125, CLK, lo125);
    DFF18: DFF port map (li126, CLK, lo126);
    DFF19: DFF port map (li127, CLK, lo127);
    DFF20: DFF port map (li128, CLK, lo128);
    DFF21: DFF port map (li595, CLK, lo595);
    DFF22: DFF port map (li596, CLK, lo596);
    po00 <= ( lo123 );
    po01 <= ( lo120 );
    po02 <= ( lo121 );
    po03 <= ( lo122 );
    po04 <= ( lo124 );
    po05 <= ( lo125 );
    po06 <= ( lo126 );
    po07 <= ( lo127 );
    po08 <= ( lo128 );
    po09 <= ( lo117 );
    po10 <= ( lo118 );
    po11 <= ( lo119 );
    li021 <= ( lo021 );
    li034 <= ( lo034 );
    li035 <= ( lo035 );
    li036 <= ( lo036 );
    li037 <= ( lo037 );
    li038 <= ( lo038 );
    li039 <= ( lo039 );
    li040 <= ( lo040 );
    li041 <= ( lo041 );
    li117 <= ( lo036 );
    li118 <= ( lo037 );
    li119 <= ( lo038 );
    li120 <= ( lo039 );
    li121 <= ( lo040 );
    li122 <= ( lo041 );
    li123 <= ( lo036 );
    li124 <= ( lo037 );
    li125 <= ( lo038 );
    li126 <= ( lo039 );
    li127 <= ( lo040 );
    li128 <= ( lo041 );
    li595 <= ( not lo595 );
    li596 <= ( n4916 and n4917 );
    n4915 <= not (( lo595 and not lo596 ));
    n4916 <= not (( lo595 and n4915 ));
    n4917 <= not (( not lo596 and n4915 ));
end ISCAS__s15850__part1_behav;
