--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i10__part4 is 
  Port (
    pi210: in std_logic;
    po185: inout std_logic
  );
end LGSynth91__i10__part4;

architecture LGSynth91__i10__part4_behav of LGSynth91__i10__part4 is
begin
    po185 <= ( not pi210 );
end LGSynth91__i10__part4_behav;
