--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__C880__part1 is 
  Port (
    pi17,pi18: in std_logic;
    po03: inout std_logic
  );
end LGSynth91__C880__part1;

architecture LGSynth91__C880__part1_behav of LGSynth91__C880__part1 is
begin
    po03 <= ( pi17 and pi18 );
end LGSynth91__C880__part1_behav;
