--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__C7552__part1 is 
  Port (
    pi001,pi161,pi177,pi179,pi008: in std_logic;
    po57,po29,po30,po34,po56: inout std_logic
  );
end IWLS93__C7552__part1;

architecture IWLS93__C7552__part1_behav of IWLS93__C7552__part1 is
signal n296,n300,n1246,n1712,n1789,n2057: std_logic;
begin
    n296 <= ( not n1789 );
    n300 <= ( not n2057 );
    po57 <= ( not n1712 );
    n1246 <= ( pi001 and pi161 );
    n1712 <= ( not pi177 and not pi179 );
    n1789 <= ( not pi177 and n1246 );
    n2057 <= ( pi008 and not pi177 );
    po29 <= ( n296 );
    po30 <= ( n296 );
    po34 <= ( n300 );
    po56 <= ( n300 );
end IWLS93__C7552__part1_behav;
