--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part227 is 
  Port (
    pi2128, CLK: in std_logic;
    po2019: inout std_logic
  );
end Other__umass_weather__part227;

architecture Other__umass_weather__part227_behav of Other__umass_weather__part227 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4894,lo4923,lo4995,li4894,li4923,li4995: std_logic;
begin
    DFF0: DFF port map (li4894, CLK, lo4894);
    DFF1: DFF port map (li4923, CLK, lo4923);
    DFF2: DFF port map (li4995, CLK, lo4995);
    li4894 <= ( lo4923 );
    li4923 <= ( lo4995 );
    li4995 <= ( pi2128 );
    po2019 <= ( lo4894 );
end Other__umass_weather__part227_behav;
