--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part5 is 
  Port (
    pi21, CLK: in std_logic;
    po021: inout std_logic
  );
end Cookbook__lc_mult_signed__part5;

architecture Cookbook__lc_mult_signed__part5_behav of Cookbook__lc_mult_signed__part5 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo008,li008: std_logic;
begin
    DFF0: DFF port map (li008, CLK, lo008);
    li008 <= ( pi21 );
    po021 <= ( lo008 );
end Cookbook__lc_mult_signed__part5_behav;
