--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part2 is 
  Port (
    pi1783: in std_logic;
    po017: inout std_logic
  );
end Other__carpat__part2;

architecture Other__carpat__part2_behav of Other__carpat__part2 is
begin
    po017 <= ( not pi1783 );
end Other__carpat__part2_behav;
