--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7: in std_logic;
    po0: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po0 <= ( pi0 )
      or ( not pi1 )
      or ( pi2 )
      or ( pi3 and not pi4 and not pi5 )
      or ( pi3 and not pi4 and not pi6 )
      or ( pi3 and not pi5 and not pi6 )
      or ( pi3 and not pi4 and not pi7 )
      or ( pi3 and not pi5 and not pi7 );
end top_behav;
