--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__c7552__part3 is 
  Port (
    pi004: in std_logic;
    po00,po07,po10: inout std_logic
  );
end ISCAS__c7552__part3;

architecture ISCAS__c7552__part3_behav of ISCAS__c7552__part3 is
begin
    po00 <= ( not pi004 );
    po07 <= ( not pi004 );
    po10 <= ( not pi004 );
end ISCAS__c7552__part3_behav;
