--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ram_delay_reg is 
  Port (
    pi0, CLK: in std_logic;
    : inout std_logic
  );
end Cookbook__ram_delay_reg;

architecture Cookbook__ram_delay_reg_behav of Cookbook__ram_delay_reg is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,n13,n14,n15,n16,n17,li0,li1,li2,li3: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    n13 <= ( not lo0 and lo1 )
      or ( lo0 and not lo1 );
    n14 <= ( lo0 and lo1 );
    n15 <= ( not n14 and lo2 )
      or ( n14 and not lo2 );
    n16 <= ( n14 and lo2 );
    n17 <= ( not n16 and lo3 )
      or ( n16 and not lo3 );
    li0 <= ( not lo0 and pi0 )
      or ( lo0 and not pi0 );
    li1 <= ( lo1 and not pi0 )
      or ( n13 and pi0 );
    li2 <= ( lo2 and not pi0 )
      or ( n15 and pi0 );
    li3 <= ( lo3 and not pi0 )
      or ( n17 and pi0 );
end Cookbook__ram_delay_reg_behav;
