--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part2 is 
  Port (
    , CLK: in std_logic;
    po09,po10,po11,po12,po13,po14,po15,po16,po17,po18,po19,po20,po21,po22,po23,po24,po25,po26,po27,po28,po29,po30,po31: inout std_logic
  );
end Cookbook__approx_fp_div__part2;

architecture Cookbook__approx_fp_div__part2_behav of Cookbook__approx_fp_div__part2 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo53,lo54,lo55,lo56,lo57,lo58,lo59,lo60,lo61,lo62,lo63,lo64,lo65,lo66,lo67,lo68,lo69,lo70,lo71,lo72,lo73,lo74,lo75,li53,li54,li55,li56,li57,li58,li59,li60,li61,li62,li63,li64,li65,li66,li67,li68,li69,li70,li71,li72,li73,li74,li75: std_logic;
begin
    DFF0: DFF port map (li53, CLK, lo53);
    DFF1: DFF port map (li54, CLK, lo54);
    DFF2: DFF port map (li55, CLK, lo55);
    DFF3: DFF port map (li56, CLK, lo56);
    DFF4: DFF port map (li57, CLK, lo57);
    DFF5: DFF port map (li58, CLK, lo58);
    DFF6: DFF port map (li59, CLK, lo59);
    DFF7: DFF port map (li60, CLK, lo60);
    DFF8: DFF port map (li61, CLK, lo61);
    DFF9: DFF port map (li62, CLK, lo62);
    DFF10: DFF port map (li63, CLK, lo63);
    DFF11: DFF port map (li64, CLK, lo64);
    DFF12: DFF port map (li65, CLK, lo65);
    DFF13: DFF port map (li66, CLK, lo66);
    DFF14: DFF port map (li67, CLK, lo67);
    DFF15: DFF port map (li68, CLK, lo68);
    DFF16: DFF port map (li69, CLK, lo69);
    DFF17: DFF port map (li70, CLK, lo70);
    DFF18: DFF port map (li71, CLK, lo71);
    DFF19: DFF port map (li72, CLK, lo72);
    DFF20: DFF port map (li73, CLK, lo73);
    DFF21: DFF port map (li74, CLK, lo74);
    DFF22: DFF port map (li75, CLK, lo75);
    li53 <= '0';
    li54 <= '0';
    li55 <= '0';
    li56 <= '0';
    li57 <= '0';
    li58 <= '0';
    li59 <= '0';
    li60 <= '0';
    li61 <= '0';
    li62 <= '0';
    li63 <= '0';
    li64 <= '0';
    li65 <= '0';
    li66 <= '0';
    li67 <= '0';
    li68 <= '0';
    li69 <= '0';
    li70 <= '0';
    li71 <= '0';
    li72 <= '0';
    li73 <= '0';
    li74 <= '0';
    li75 <= '0';
    po09 <= ( lo75 );
    po10 <= ( lo74 );
    po11 <= ( lo73 );
    po12 <= ( lo72 );
    po13 <= ( lo71 );
    po14 <= ( lo70 );
    po15 <= ( lo69 );
    po16 <= ( lo68 );
    po17 <= ( lo67 );
    po18 <= ( lo66 );
    po19 <= ( lo65 );
    po20 <= ( lo64 );
    po21 <= ( lo63 );
    po22 <= ( lo62 );
    po23 <= ( lo61 );
    po24 <= ( lo60 );
    po25 <= ( lo59 );
    po26 <= ( lo58 );
    po27 <= ( lo57 );
    po28 <= ( lo56 );
    po29 <= ( lo55 );
    po30 <= ( lo54 );
    po31 <= ( lo53 );
end Cookbook__approx_fp_div__part2_behav;
