--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_5__part0 is 
  Port (
    pi09,pi04,pi07,pi02,pi00,pi17,pi16,pi14,pi12,pi11,pi05: in std_logic;
    po16,po14,po12,po11,po09,po07,po06,po04,po02,po00: inout std_logic
  );
end Cookbook__fec_rot_5__part0;

architecture Cookbook__fec_rot_5__part0_behav of Cookbook__fec_rot_5__part0 is
signal n36,n38: std_logic;
begin
    n36 <= ( not pi09 and pi04 )
      or ( pi09 and not pi04 );
    n38 <= ( not pi07 and pi02 )
      or ( pi07 and not pi02 );
    po16 <= ( not pi04 and pi02 )
      or ( pi04 and not pi02 );
    po14 <= ( not pi02 and pi00 )
      or ( pi02 and not pi00 );
    po12 <= ( not pi17 and pi00 )
      or ( pi17 and not pi00 );
    po11 <= ( not pi16 and pi04 )
      or ( pi16 and not pi04 );
    po09 <= ( not pi14 and pi02 )
      or ( pi14 and not pi02 );
    po07 <= ( not pi12 and pi00 )
      or ( pi12 and not pi00 );
    po06 <= ( not pi11 and pi04 )
      or ( pi11 and not pi04 );
    po04 <= ( not n36 and pi02 )
      or ( n36 and not pi02 );
    po02 <= ( not n38 and pi00 )
      or ( n38 and not pi00 );
    po00 <= ( not pi05 and pi00 )
      or ( pi05 and not pi00 );
end Cookbook__fec_rot_5__part0_behav;
