--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part58 is 
  Port (
    pi0149, CLK: in std_logic;
    po0401: inout std_logic
  );
end Other__umass_weather__part58;

architecture Other__umass_weather__part58_behav of Other__umass_weather__part58 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0495,li0495: std_logic;
begin
    DFF0: DFF port map (li0495, CLK, lo0495);
    li0495 <= ( pi0149 );
    po0401 <= ( lo0495 );
end Other__umass_weather__part58_behav;
