--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_crossing_fifo is 
  Port (
    pi0, CLK: in std_logic;
    po0: inout std_logic
  );
end Cookbook__clock_crossing_fifo;

architecture Cookbook__clock_crossing_fifo_behav of Cookbook__clock_crossing_fifo is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,n5,n6,li0: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    n5 <= not (( lo0 and not pi0 ));
    n6 <= ( lo0 and not pi0 );
    li0 <= not (( not n6 and not n5 ));
    po0 <= ( lo0 );
end Cookbook__clock_crossing_fifo_behav;
