--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part1 is 
  Port (
    , CLK: in std_logic;
    po00001: inout std_logic
  );
end Other__radar__part1;

architecture Other__radar__part1_behav of Other__radar__part1 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0001,lo0002,n34867,n34868,n34869,li0001,li0002: std_logic;
begin
    DFF0: DFF port map (li0001, CLK, lo0001);
    DFF1: DFF port map (li0002, CLK, lo0002);
    n34867 <= ( lo0001 and not lo0002 );
    n34868 <= ( not lo0001 and lo0002 );
    n34869 <= ( not n34867 and not n34868 );
    po00001 <= ( not n34869 );
    li0001 <= ( not lo0001 );
    li0002 <= ( not n34869 );
end Other__radar__part1_behav;
