--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi23,pi24,pi20,pi25,pi26,pi28,pi35,pi37,pi15,pi36,pi38,pi39,pi41,pi87,pi88,pi89,pi90: in std_logic;
    po08,po09,po13,po14,po32: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po08 <= ( not pi23 )
      or ( not pi24 );
    po09 <= ( not pi20 )
      or ( not pi28 )
      or ( pi23 and pi24 and pi25 and pi26 );
    po13 <= ( pi20 and pi35 and pi37 );
    po14 <= ( not pi15 and pi20 and pi36 )
      or ( pi20 and pi35 and pi37 )
      or ( pi20 and pi36 and not pi38 )
      or ( pi20 and pi36 and not pi39 )
      or ( pi20 and pi36 and not pi41 );
    po32 <= ( not pi38 )
      or ( pi15 and pi41 and pi87 and pi88 and pi89 and pi90 );
end top_behav;
