--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi62,pi63,pi64,pi65,pi66: in std_logic;
    po21: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po21 <= ( not pi62 )
      or ( not pi63 )
      or ( not pi64 )
      or ( not pi65 )
      or ( not pi66 );
end top_behav;
