--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi25,pi26: in std_logic;
    po11: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po11 <= ( not pi25 )
      or ( not pi26 );
end top_behav;
