--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi07,pi08,pi09,pi10: in std_logic;
    po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17,po18,po19,po20,po34: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po06 <= ( not pi07 and not pi08 and not pi09 and not pi10 );
    po07 <= ( not pi07 and not pi08 and not pi09 and pi10 );
    po08 <= ( not pi07 and not pi08 and pi09 and not pi10 );
    po09 <= ( not pi07 and not pi08 and pi09 and pi10 );
    po10 <= ( not pi07 and pi08 and not pi09 and pi10 );
    po11 <= ( not pi07 and pi08 and not pi09 and not pi10 );
    po12 <= ( not pi07 and pi08 and pi09 and pi10 );
    po13 <= ( pi07 and not pi08 and not pi09 and not pi10 );
    po14 <= ( pi07 and not pi08 and not pi09 and pi10 );
    po15 <= ( pi07 and not pi08 and pi09 and not pi10 );
    po16 <= ( pi07 and not pi08 and pi09 and pi10 );
    po17 <= ( pi07 and pi08 and not pi09 and not pi10 );
    po18 <= ( pi07 and pi08 and not pi09 and pi10 );
    po19 <= ( pi07 and pi08 and pi09 and not pi10 );
    po20 <= ( pi07 and pi08 and pi09 and pi10 );
    po34 <= ( not pi07 and pi08 and pi09 and not pi10 );
end top_behav;
