--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misg__part1 is 
  Port (
    pi08,pi14: in std_logic;
    po03: inout std_logic
  );
end Espresso__misg__part1;

architecture Espresso__misg__part1_behav of Espresso__misg__part1 is
begin
    po03 <= ( not pi08 )
      or ( not pi14 );
end Espresso__misg__part1_behav;
