--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_rot_7__part1 is 
  Port (
    pi12,pi05,pi10,pi03,pi01,pi24,pi21,pi19,pi17,pi14,pi08: in std_logic;
    po21,po19,po17,po14,po12,po10,po07,po05,po03,po01: inout std_logic
  );
end Cookbook__fec_rot_7__part1;

architecture Cookbook__fec_rot_7__part1_behav of Cookbook__fec_rot_7__part1 is
signal n49,n51: std_logic;
begin
    n49 <= ( not pi12 and pi05 )
      or ( pi12 and not pi05 );
    n51 <= ( not pi10 and pi03 )
      or ( pi10 and not pi03 );
    po21 <= ( not pi05 and pi03 )
      or ( pi05 and not pi03 );
    po19 <= ( not pi03 and pi01 )
      or ( pi03 and not pi01 );
    po17 <= ( not pi24 and pi01 )
      or ( pi24 and not pi01 );
    po14 <= ( not pi21 and pi05 )
      or ( pi21 and not pi05 );
    po12 <= ( not pi19 and pi03 )
      or ( pi19 and not pi03 );
    po10 <= ( not pi17 and pi01 )
      or ( pi17 and not pi01 );
    po07 <= ( not pi14 and pi05 )
      or ( pi14 and not pi05 );
    po05 <= ( not n49 and pi03 )
      or ( n49 and not pi03 );
    po03 <= ( not n51 and pi01 )
      or ( n51 and not pi01 );
    po01 <= ( not pi08 and pi01 )
      or ( pi08 and not pi01 );
end Cookbook__fec_rot_7__part1_behav;
