--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part234 is 
  Port (
    pi2135, CLK: in std_logic;
    po2026: inout std_logic
  );
end Other__umass_weather__part234;

architecture Other__umass_weather__part234_behav of Other__umass_weather__part234 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4901,lo4973,lo5045,li4901,li4973,li5045: std_logic;
begin
    DFF0: DFF port map (li4901, CLK, lo4901);
    DFF1: DFF port map (li4973, CLK, lo4973);
    DFF2: DFF port map (li5045, CLK, lo5045);
    li4901 <= ( lo4973 );
    li4973 <= ( lo5045 );
    li5045 <= ( pi2135 );
    po2026 <= ( lo4901 );
end Other__umass_weather__part234_behav;
