--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part3 is 
  Port (
    pi14: in std_logic;
    po05: inout std_logic
  );
end Espresso__mish__part3;

architecture Espresso__mish__part3_behav of Espresso__mish__part3 is
begin
    po05 <= ( not pi14 );
end Espresso__mish__part3_behav;
