--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__mish__part10 is 
  Port (
    pi40: in std_logic;
    po16: inout std_logic
  );
end Espresso__mish__part10;

architecture Espresso__mish__part10_behav of Espresso__mish__part10 is
begin
    po16 <= ( not pi40 );
end Espresso__mish__part10_behav;
