--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i3__part0 is 
  Port (
    pi000,pi001: in std_logic;
    po0: inout std_logic
  );
end LGSynth91__i3__part0;

architecture LGSynth91__i3__part0_behav of LGSynth91__i3__part0 is
begin
    po0 <= ( pi000 )
      or ( pi001 );
end LGSynth91__i3__part0_behav;
