--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi30,pi31,pi32,pi33,pi34,pi43,pi45,pi47: in std_logic;
    po12,po17: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po12 <= ( pi31 )
      or ( pi30 and pi32 and pi33 and pi34 );
    po17 <= ( not pi33 )
      or ( not pi43 )
      or ( not pi45 )
      or ( not pi47 );
end top_behav;
