--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi57,pi52,pi54: in std_logic;
    po104,po106: inout std_logic
  );
end top;

architecture top_behav of top is
signal n2643,n3337,n3843: std_logic;
begin
    po104 <= ( n2643 );
    po106 <= ( n2643 );
    n2643 <= not (( not n3843 and not n3337 ));
    n3337 <= ( pi57 and pi52 );
    n3843 <= ( pi54 and not pi52 );
end top_behav;
