--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi06,pi07,pi08,pi09,pi10: in std_logic;
    po03: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po03 <= ( not pi06 )
      or ( not pi07 )
      or ( not pi08 )
      or ( not pi09 )
      or ( not pi10 );
end top_behav;
