--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part194 is 
  Port (
    pi0425, CLK: in std_logic;
    po0481: inout std_logic
  );
end Other__umass_weather__part194;

architecture Other__umass_weather__part194_behav of Other__umass_weather__part194 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0568,li0568: std_logic;
begin
    DFF0: DFF port map (li0568, CLK, lo0568);
    li0568 <= ( pi0425 );
    po0481 <= ( lo0568 );
end Other__umass_weather__part194_behav;
