--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi150: in std_logic;
    po000,po005,po006: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po000 <= ( not pi150 );
    po005 <= ( not pi150 );
    po006 <= ( not pi150 );
end top_behav;
