--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part60 is 
  Port (
    pi0153, CLK: in std_logic;
    po0411: inout std_logic
  );
end Other__umass_weather__part60;

architecture Other__umass_weather__part60_behav of Other__umass_weather__part60 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0504,li0504: std_logic;
begin
    DFF0: DFF port map (li0504, CLK, lo0504);
    li0504 <= ( pi0153 );
    po0411 <= ( lo0504 );
end Other__umass_weather__part60_behav;
