--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part81 is 
  Port (
    pi0198, CLK: in std_logic;
    po0480: inout std_logic
  );
end Other__umass_weather__part81;

architecture Other__umass_weather__part81_behav of Other__umass_weather__part81 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0567,li0567: std_logic;
begin
    DFF0: DFF port map (li0567, CLK, lo0567);
    li0567 <= ( pi0198 );
    po0480 <= ( lo0567 );
end Other__umass_weather__part81_behav;
