--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__misj__part3 is 
  Port (
    pi17,pi18: in std_logic;
    po05: inout std_logic
  );
end Espresso__misj__part3;

architecture Espresso__misj__part3_behav of Espresso__misj__part3 is
begin
    po05 <= ( not pi17 )
      or ( not pi18 );
end Espresso__misj__part3_behav;
