--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__soar__part1 is 
  Port (
    pi21,pi22,pi23,pi24: in std_logic;
    po08,po09,po10,po11,po12: inout std_logic
  );
end Espresso__soar__part1;

architecture Espresso__soar__part1_behav of Espresso__soar__part1 is
begin
    po08 <= ( not pi21 );
    po09 <= ( not pi21 and pi22 and pi23 )
      or ( pi21 and not pi22 and pi23 )
      or ( pi21 and pi22 and not pi23 )
      or ( not pi21 and not pi22 and not pi23 );
    po10 <= ( not pi21 and not pi22 and pi23 )
      or ( pi21 and pi22 and not pi23 )
      or ( not pi21 and pi22 and pi24 )
      or ( pi21 and not pi22 and pi24 )
      or ( pi21 and pi22 and not pi24 )
      or ( not pi21 and not pi22 and not pi24 );
    po11 <= ( pi21 and pi22 )
      or ( not pi21 and not pi22 );
    po12 <= ( pi21 and pi24 )
      or ( pi22 and pi24 )
      or ( not pi21 and not pi22 and not pi24 );
end Espresso__soar__part1_behav;
