--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi48,pi49,pi50,pi51,pi52: in std_logic;
    po18: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po18 <= ( not pi48 )
      or ( not pi49 )
      or ( not pi50 )
      or ( not pi51 )
      or ( not pi52 );
end top_behav;
