--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part237 is 
  Port (
    pi2138, CLK: in std_logic;
    po2029: inout std_logic
  );
end Other__umass_weather__part237;

architecture Other__umass_weather__part237_behav of Other__umass_weather__part237 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4904,lo4976,lo5048,li4904,li4976,li5048: std_logic;
begin
    DFF0: DFF port map (li4904, CLK, lo4904);
    DFF1: DFF port map (li4976, CLK, lo4976);
    DFF2: DFF port map (li5048, CLK, lo5048);
    li4904 <= ( lo4976 );
    li4976 <= ( lo5048 );
    li5048 <= ( pi2138 );
    po2029 <= ( lo4904 );
end Other__umass_weather__part237_behav;
