--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__umass_weather__part232 is 
  Port (
    pi2133, CLK: in std_logic;
    po2024: inout std_logic
  );
end Other__umass_weather__part232;

architecture Other__umass_weather__part232_behav of Other__umass_weather__part232 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo4899,lo4971,lo5043,li4899,li4971,li5043: std_logic;
begin
    DFF0: DFF port map (li4899, CLK, lo4899);
    DFF1: DFF port map (li4971, CLK, lo4971);
    DFF2: DFF port map (li5043, CLK, lo5043);
    li4899 <= ( lo4971 );
    li4971 <= ( lo5043 );
    li5043 <= ( pi2133 );
    po2024 <= ( lo4899 );
end Other__umass_weather__part232_behav;
