--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__DSP__part4 is 
  Port (
    pi3210,pi3520,pi3475: in std_logic;
    po3442,po3758: inout std_logic
  );
end IWLS2005__DSP__part4;

architecture IWLS2005__DSP__part4_behav of IWLS2005__DSP__part4 is
signal n45724,n45725,n45726: std_logic;
begin
    n45724 <= ( pi3210 and not pi3520 );
    n45725 <= ( not pi3210 and pi3520 );
    n45726 <= ( pi3475 and not n45725 );
    po3442 <= ( not n45724 and not n45726 );
    po3758 <= ( not pi3210 );
end IWLS2005__DSP__part4_behav;
