--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__i1__part2 is 
  Port (
    pi20,pi21: in std_logic;
    po02: inout std_logic
  );
end LGSynth91__i1__part2;

architecture LGSynth91__i1__part2_behav of LGSynth91__i1__part2 is
begin
    po02 <= ( pi20 )
      or ( pi21 );
end LGSynth91__i1__part2_behav;
