--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi91,pi92,pi93: in std_logic;
    po33: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po33 <= ( pi91 and pi92 and pi93 );
end top_behav;
