--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20: in std_logic;
    po0: inout std_logic
  );
end top;

architecture top_behav of top is
signal n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37: std_logic;
begin
    po0 <= ( not n23 )
      or ( pi20 );
    n23 <= ( not pi19 and not n30 )
      or ( pi19 and not n37 )
      or ( not n30 and not n37 );
    n24 <= ( not pi00 and not pi01 )
      or ( not pi01 and pi16 )
      or ( not pi00 and not pi16 );
    n25 <= ( not pi02 and not pi03 )
      or ( not pi03 and pi16 )
      or ( not pi02 and not pi16 );
    n26 <= ( not pi04 and not pi05 )
      or ( not pi05 and pi16 )
      or ( not pi04 and not pi16 );
    n27 <= ( not pi06 and not pi07 )
      or ( not pi07 and pi16 )
      or ( not pi06 and not pi16 );
    n28 <= ( not pi17 and not n24 )
      or ( pi17 and not n25 )
      or ( not n24 and not n25 );
    n29 <= ( not pi17 and not n26 )
      or ( pi17 and not n27 )
      or ( not n26 and not n27 );
    n30 <= ( not pi18 and not n28 )
      or ( pi18 and not n29 )
      or ( not n28 and not n29 );
    n31 <= ( not pi08 and not pi09 )
      or ( not pi09 and pi16 )
      or ( not pi08 and not pi16 );
    n32 <= ( not pi10 and not pi11 )
      or ( not pi11 and pi16 )
      or ( not pi10 and not pi16 );
    n33 <= ( not pi12 and not pi13 )
      or ( not pi13 and pi16 )
      or ( not pi12 and not pi16 );
    n34 <= ( not pi14 and not pi15 )
      or ( not pi15 and pi16 )
      or ( not pi14 and not pi16 );
    n35 <= ( not pi17 and not n31 )
      or ( pi17 and not n32 )
      or ( not n31 and not n32 );
    n36 <= ( not pi17 and not n33 )
      or ( pi17 and not n34 )
      or ( not n33 and not n34 );
    n37 <= ( not pi18 and not n35 )
      or ( pi18 and not n36 )
      or ( not n35 and not n36 );
end top_behav;
