--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_sqrt is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7,po8,po9: inout std_logic
  );
end Cookbook__approx_fp_sqrt;

architecture Cookbook__approx_fp_sqrt_behav of Cookbook__approx_fp_sqrt is
signal n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n37,n39,n41,n43,n45,n47,n49: std_logic;
begin
    po9 <= ( not pi8 );
    n20 <= ( not pi8 and pi7 )
      or ( pi8 and not pi7 );
    n21 <= ( pi8 and pi7 );
    n22 <= ( not n21 and pi6 )
      or ( n21 and not pi6 );
    n23 <= ( n21 and pi6 );
    n24 <= ( not n23 and pi5 )
      or ( n23 and not pi5 );
    n25 <= ( n23 and pi5 );
    n26 <= ( not n25 and pi4 )
      or ( n25 and not pi4 );
    n27 <= ( n25 and pi4 );
    n28 <= ( not n27 and pi3 )
      or ( n27 and not pi3 );
    n29 <= ( n27 and pi3 );
    n30 <= ( not n29 and pi2 )
      or ( n29 and not pi2 );
    n31 <= ( n29 and pi2 );
    n32 <= ( not n31 and not pi1 )
      or ( n31 and pi1 );
    n33 <= not (( not n31 and not pi1 ));
    n34 <= ( not n33 and not pi0 )
      or ( n33 and pi0 );
    po8 <= ( not n20 );
    po7 <= ( not n20 and not n22 )
      or ( n20 and n22 );
    n37 <= not (( not n20 and not n22 ));
    po6 <= ( not n37 and not n24 )
      or ( n37 and n24 );
    n39 <= not (( not n37 and not n24 ));
    po5 <= ( not n39 and not n26 )
      or ( n39 and n26 );
    n41 <= not (( not n39 and not n26 ));
    po4 <= ( not n41 and not n28 )
      or ( n41 and n28 );
    n43 <= not (( not n41 and not n28 ));
    po3 <= ( not n43 and not n30 )
      or ( n43 and n30 );
    n45 <= not (( not n43 and not n30 ));
    po2 <= ( not n45 and not n32 )
      or ( n45 and n32 );
    n47 <= not (( not n45 and not n32 ));
    po1 <= ( not n47 and n34 )
      or ( n47 and not n34 );
    n49 <= ( n47 and n34 );
    po0 <= ( not n49 and n34 )
      or ( n49 and not n34 );
end Cookbook__approx_fp_sqrt_behav;
