--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__rot__part2 is 
  Port (
    pi025,pi056,pi022,pi023,pi034: in std_logic;
    po00,po43: inout std_logic
  );
end LGSynth91__rot__part2;

architecture LGSynth91__rot__part2_behav of LGSynth91__rot__part2 is
begin
    po00 <= ( pi025 and not pi022 )
      or ( pi025 and pi023 )
      or ( pi056 and pi022 and not pi023 );
    po43 <= ( pi034 and pi022 )
      or ( pi034 and not pi023 )
      or ( pi025 and not pi022 and pi023 );
end LGSynth91__rot__part2_behav;
