--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__cam_ram_block is 
  Port (
    pi0,pi1, CLK: in std_logic;
    po0: inout std_logic
  );
end Cookbook__cam_ram_block;

architecture Cookbook__cam_ram_block_behav of Cookbook__cam_ram_block is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,li11,li00,li01,li02,li03,li04,li05,li06,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,n108,n109,n110,n111,n112,n113,n114,n115,n116,n117,n118,n119,n120,n121,n122,n123,n124,n125,n126,n127,n128,n129,n130,n131,n132,n133,n134,n135,n136,n137,n138,n139,n140,n141,n142,li07,li08,li09,li10: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    n39 <= not (( lo01 and lo02 ));
    n40 <= not (( not lo00 and not n39 ));
    n41 <= not (( lo03 and lo04 ));
    n42 <= not (( lo05 and lo06 ));
    n43 <= not (( not n41 and not n42 ));
    n44 <= not (( not n40 and not n43 ));
    n45 <= not (( not lo11 and n44 ));
    n46 <= ( not lo00 and lo01 )
      or ( lo00 and not lo01 );
    n47 <= ( lo00 and lo01 );
    n48 <= ( not n47 and lo02 )
      or ( n47 and not lo02 );
    n49 <= ( n47 and lo02 );
    n50 <= ( not n49 and lo03 )
      or ( n49 and not lo03 );
    n51 <= ( n49 and lo03 );
    n52 <= ( not n51 and lo04 )
      or ( n51 and not lo04 );
    n53 <= ( n51 and lo04 );
    n54 <= ( not n53 and lo05 )
      or ( n53 and not lo05 );
    n55 <= ( n53 and lo05 );
    n56 <= ( not n55 and lo06 )
      or ( n55 and not lo06 );
    li11 <= ( n45 and not n109 );
    li00 <= ( not lo00 and not n109 );
    li01 <= ( n46 and not n109 );
    li02 <= ( n48 and not n109 );
    li03 <= ( n50 and not n109 );
    li04 <= ( n52 and not n109 );
    li05 <= ( n54 and not n109 );
    li06 <= ( n56 and not n109 );
    n65 <= ( lo07 and not lo11 );
    n66 <= not (( not lo08 and not lo11 ));
    n67 <= ( lo09 and not lo11 );
    n68 <= ( lo10 and not lo11 );
    n69 <= not (( not lo07 and not pi1 ));
    n70 <= not (( not lo08 and not pi1 ));
    n71 <= ( lo09 and not pi1 );
    n72 <= ( lo10 and not pi1 );
    n73 <= not (( not lo07 and not lo11 ));
    n74 <= ( lo08 and not lo11 );
    n75 <= not (( not lo09 and not lo11 ));
    n76 <= ( lo10 and not lo11 );
    n77 <= not (( not lo07 and not lo08 ));
    n78 <= not (( not lo09 and not lo10 ));
    n79 <= not (( not n77 and not n78 ));
    n80 <= not (( lo07 and not lo08 ));
    n81 <= not (( not lo09 and not lo10 ));
    n82 <= not (( not n80 and not n81 ));
    n83 <= not (( not lo07 and lo08 ));
    n84 <= not (( not lo09 and not lo10 ));
    n85 <= not (( not n83 and not n84 ));
    po0 <= ( not n85 );
    n87 <= not (( lo07 and lo08 ));
    n88 <= not (( not lo09 and not lo10 ));
    n89 <= not (( not n87 and not n88 ));
    n90 <= not (( not lo07 and not lo08 ));
    n91 <= not (( lo09 and not lo10 ));
    n92 <= not (( not n90 and not n91 ));
    n93 <= not (( lo07 and not lo08 ));
    n94 <= not (( lo09 and not lo10 ));
    n95 <= not (( not n93 and not n94 ));
    n96 <= not (( not lo07 and lo08 ));
    n97 <= not (( lo09 and not lo10 ));
    n98 <= not (( not n96 and not n97 ));
    n99 <= not (( n95 and n92 ));
    n100 <= not (( n98 and not n99 ));
    n101 <= not (( n89 and n85 ));
    n102 <= not (( n82 and n79 ));
    n103 <= not (( not n101 and not n102 ));
    n104 <= not (( not n100 and not n103 ));
    n105 <= not (( n79 and n98 ));
    n106 <= ( not pi1 and not n85 );
    n107 <= ( lo11 and not n82 );
    n108 <= not (( not n107 and not n105 ));
    n109 <= not (( not n106 and not n108 ));
    n110 <= ( lo07 and not n104 );
    n111 <= ( n73 and not n92 );
    n112 <= ( n69 and not n85 );
    n113 <= ( n65 and not n82 );
    n114 <= not (( not n110 and not n111 ));
    n115 <= not (( not n113 and n79 ));
    n116 <= not (( not n112 and not n115 ));
    n117 <= not (( not n114 and not n116 ));
    n118 <= ( lo08 and not n104 );
    n119 <= ( n74 and not n92 );
    n120 <= ( n70 and not n85 );
    n121 <= ( n66 and not n82 );
    n122 <= not (( not n118 and n98 ));
    n123 <= not (( n95 and not n119 ));
    n124 <= not (( not n122 and not n123 ));
    n125 <= not (( not n120 and not n121 ));
    n126 <= not (( not n124 and not n125 ));
    n127 <= ( lo09 and not n104 );
    n128 <= ( n75 and not n92 );
    n129 <= ( n71 and not n85 );
    n130 <= ( n67 and not n82 );
    n131 <= not (( n95 and not n128 ));
    n132 <= not (( not n127 and not n131 ));
    n133 <= not (( n89 and not n129 ));
    n134 <= not (( not n133 and not n130 ));
    n135 <= not (( not n132 and not n134 ));
    n136 <= ( lo10 and not n104 );
    n137 <= ( n76 and not n92 );
    n138 <= ( n72 and not n85 );
    n139 <= ( n68 and not n82 );
    n140 <= not (( not n136 and not n137 ));
    n141 <= not (( not n138 and not n139 ));
    n142 <= not (( not n140 and not n141 ));
    li07 <= ( n117 and not pi0 );
    li08 <= ( n126 and not pi0 );
    li09 <= ( n135 and not pi0 );
    li10 <= ( n142 and not pi0 );
end Cookbook__cam_ram_block_behav;
