--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Espresso__x2dn__part0 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16: inout std_logic
  );
end Espresso__x2dn__part0;

architecture Espresso__x2dn__part0_behav of Espresso__x2dn__part0 is
begin
    po00 <= ( not pi00 and not pi01 and pi02 );
    po01 <= ( not pi00 and pi03 and pi06 and not pi07 and not pi08 )
      or ( not pi00 and pi04 and pi06 and not pi07 and not pi08 )
      or ( not pi00 and pi05 and pi06 and not pi07 and not pi08 );
    po02 <= ( not pi00 and not pi01 and pi06 and not pi07 and not pi08 and pi09 )
      or ( not pi00 and not pi01 and pi06 and not pi07 and not pi08 and pi10 )
      or ( not pi00 and not pi01 and pi06 and not pi07 and not pi08 and pi11 );
    po03 <= ( pi03 and not pi08 )
      or ( pi04 and not pi08 )
      or ( pi05 and not pi08 );
    po04 <= ( not pi03 )
      or ( not pi04 )
      or ( pi05 );
    po05 <= ( not pi03 and pi05 )
      or ( pi03 and not pi04 and not pi05 );
    po06 <= ( not pi04 );
    po07 <= ( not pi03 and pi04 )
      or ( pi04 and pi05 );
    po08 <= ( pi09 and pi10 and pi11 );
    po09 <= ( not pi09 and not pi10 );
    po10 <= ( not pi09 and pi10 )
      or ( pi09 and not pi10 )
      or ( pi09 and not pi11 )
      or ( pi10 and not pi11 );
    po11 <= ( pi09 and pi10 and pi11 );
    po12 <= ( pi09 and pi10 and pi11 );
    po13 <= ( pi09 and pi10 and pi11 );
    po14 <= ( not pi09 )
      or ( not pi10 )
      or ( not pi11 );
    po15 <= ( pi09 and not pi10 )
      or ( pi09 and not pi11 );
    po16 <= ( not pi09 and pi10 )
      or ( pi10 and not pi11 );
end Espresso__x2dn__part0_behav;
