--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ternary_add is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7,po8,po9: inout std_logic
  );
end Cookbook__ternary_add;

architecture Cookbook__ternary_add_behav of Cookbook__ternary_add is
signal n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n51,n53,n55,n57,n59,n61,n63,n65: std_logic;
begin
    n34 <= ( not pi07 and pi15 )
      or ( pi07 and not pi15 );
    n35 <= ( pi07 and pi15 );
    n36 <= ( not n35 and not pi06 and pi14 )
      or ( not n35 and pi06 and not pi14 )
      or ( n35 and not pi06 and not pi14 )
      or ( n35 and pi06 and pi14 );
    n37 <= ( n35 and pi06 )
      or ( n35 and pi14 )
      or ( pi06 and pi14 );
    n38 <= ( not n37 and not pi05 and pi13 )
      or ( not n37 and pi05 and not pi13 )
      or ( n37 and not pi05 and not pi13 )
      or ( n37 and pi05 and pi13 );
    n39 <= ( n37 and pi05 )
      or ( n37 and pi13 )
      or ( pi05 and pi13 );
    n40 <= ( not n39 and not pi04 and pi12 )
      or ( not n39 and pi04 and not pi12 )
      or ( n39 and not pi04 and not pi12 )
      or ( n39 and pi04 and pi12 );
    n41 <= ( n39 and pi04 )
      or ( n39 and pi12 )
      or ( pi04 and pi12 );
    n42 <= ( not n41 and not pi03 and pi11 )
      or ( not n41 and pi03 and not pi11 )
      or ( n41 and not pi03 and not pi11 )
      or ( n41 and pi03 and pi11 );
    n43 <= ( n41 and pi03 )
      or ( n41 and pi11 )
      or ( pi03 and pi11 );
    n44 <= ( not n43 and not pi02 and pi10 )
      or ( not n43 and pi02 and not pi10 )
      or ( n43 and not pi02 and not pi10 )
      or ( n43 and pi02 and pi10 );
    n45 <= ( n43 and pi02 )
      or ( n43 and pi10 )
      or ( pi02 and pi10 );
    n46 <= ( not n45 and not pi01 and pi09 )
      or ( not n45 and pi01 and not pi09 )
      or ( n45 and not pi01 and not pi09 )
      or ( n45 and pi01 and pi09 );
    n47 <= ( n45 and pi01 )
      or ( n45 and pi09 )
      or ( pi01 and pi09 );
    n48 <= ( not n47 and not pi00 and pi08 )
      or ( not n47 and pi00 and not pi08 )
      or ( n47 and not pi00 and not pi08 )
      or ( n47 and pi00 and pi08 );
    n49 <= ( n47 and pi00 )
      or ( n47 and pi08 )
      or ( pi00 and pi08 );
    po9 <= ( not n34 and pi23 )
      or ( n34 and not pi23 );
    n51 <= ( n34 and pi23 );
    po8 <= ( not n51 and not n36 and pi22 )
      or ( not n51 and n36 and not pi22 )
      or ( n51 and not n36 and not pi22 )
      or ( n51 and n36 and pi22 );
    n53 <= ( n51 and n36 )
      or ( n51 and pi22 )
      or ( n36 and pi22 );
    po7 <= ( not n53 and not n38 and pi21 )
      or ( not n53 and n38 and not pi21 )
      or ( n53 and not n38 and not pi21 )
      or ( n53 and n38 and pi21 );
    n55 <= ( n53 and n38 )
      or ( n53 and pi21 )
      or ( n38 and pi21 );
    po6 <= ( not n55 and not n40 and pi20 )
      or ( not n55 and n40 and not pi20 )
      or ( n55 and not n40 and not pi20 )
      or ( n55 and n40 and pi20 );
    n57 <= ( n55 and n40 )
      or ( n55 and pi20 )
      or ( n40 and pi20 );
    po5 <= ( not n57 and not n42 and pi19 )
      or ( not n57 and n42 and not pi19 )
      or ( n57 and not n42 and not pi19 )
      or ( n57 and n42 and pi19 );
    n59 <= ( n57 and n42 )
      or ( n57 and pi19 )
      or ( n42 and pi19 );
    po4 <= ( not n59 and not n44 and pi18 )
      or ( not n59 and n44 and not pi18 )
      or ( n59 and not n44 and not pi18 )
      or ( n59 and n44 and pi18 );
    n61 <= ( n59 and n44 )
      or ( n59 and pi18 )
      or ( n44 and pi18 );
    po3 <= ( not n61 and not n46 and pi17 )
      or ( not n61 and n46 and not pi17 )
      or ( n61 and not n46 and not pi17 )
      or ( n61 and n46 and pi17 );
    n63 <= ( n61 and n46 )
      or ( n61 and pi17 )
      or ( n46 and pi17 );
    po2 <= ( not n63 and not n48 and pi16 )
      or ( not n63 and n48 and not pi16 )
      or ( n63 and not n48 and not pi16 )
      or ( n63 and n48 and pi16 );
    n65 <= ( n63 and n48 )
      or ( n63 and pi16 )
      or ( n48 and pi16 );
    po1 <= ( not n65 and n49 )
      or ( n65 and not n49 );
    po0 <= ( n65 and n49 );
end Cookbook__ternary_add_behav;
