--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__cm152a is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10: in std_logic;
    po0: inout std_logic
  );
end LGSynth91__cm152a;

architecture LGSynth91__cm152a_behav of LGSynth91__cm152a is
begin
    po0 <= ( not pi10 and not pi09 and pi01 and pi08 )
      or ( not pi10 and not pi09 and pi00 and not pi08 )
      or ( not pi10 and pi09 and not pi08 and pi02 )
      or ( not pi10 and pi09 and pi08 and pi03 )
      or ( pi10 and not pi09 and not pi08 and pi04 )
      or ( pi10 and not pi09 and pi08 and pi05 )
      or ( pi10 and pi09 and not pi08 and pi06 )
      or ( pi10 and pi09 and pi08 and pi07 );
end LGSynth91__cm152a_behav;
