--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi10,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi00,pi19,pi08,pi09: in std_logic;
    po00,po01,po03: inout std_logic
  );
end top;

architecture top_behav of top is
signal n51,n52,n53,n54,n55,n56,n57: std_logic;
begin
    po00 <= ( n55 )
      or ( n52 )
      or ( n54 );
    po01 <= ( n57 )
      or ( n56 );
    po03 <= ( n53 )
      or ( pi10 );
    n51 <= ( not pi01 and not pi02 and not pi03 and not pi04 and not pi05 and not pi06 and not pi07 );
    n52 <= ( not pi00 and pi19 );
    n53 <= ( not pi08 and pi19 and n51 );
    n54 <= ( not pi09 and n53 );
    n55 <= ( pi09 and n51 and pi19 and pi08 );
    n56 <= ( pi00 and pi19 and not n51 );
    n57 <= ( pi08 and not pi09 and pi19 and n51 );
end top_behav;
