--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi54,pi55,pi56,pi53,pi57,pi58,pi69,pi81,pi82,pi83,pi84,pi27,pi80,pi85,pi79,pi86,pi78: in std_logic;
    po19,po20,po23,po27,po28,po29,po30,po31: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po19 <= ( not pi54 )
      or ( not pi55 )
      or ( not pi56 );
    po20 <= ( not pi53 )
      or ( not pi57 );
    po23 <= ( not pi53 )
      or ( not pi58 )
      or ( not pi69 );
    po27 <= ( pi53 and not pi81 and pi82 and pi83 )
      or ( pi53 and pi82 and pi83 and not pi84 );
    po28 <= ( pi27 and pi53 )
      or ( pi53 and not pi81 and pi82 and pi83 )
      or ( pi53 and pi82 and pi83 and not pi84 );
    po29 <= ( not pi55 )
      or ( not pi80 )
      or ( not pi85 );
    po30 <= ( not pi53 )
      or ( not pi79 )
      or ( not pi86 );
    po31 <= ( not pi55 )
      or ( not pi78 )
      or ( not pi82 )
      or ( not pi85 );
end top_behav;
