--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi248,pi249,pi250,pi251: in std_logic;
    po015: inout std_logic
  );
end top;

architecture top_behav of top is
signal n869,n877,n1813,n1814,n1815,n1816: std_logic;
begin
    po015 <= ( not n869 and not n877 );
    n869 <= ( n1813 )
      or ( n1814 );
    n877 <= ( n1815 )
      or ( n1816 );
    n1813 <= ( pi248 and not pi249 );
    n1814 <= ( not pi248 and pi249 );
    n1815 <= ( pi250 and not pi251 );
    n1816 <= ( not pi250 and pi251 );
end top_behav;
