--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part4 is 
  Port (
    pi04,pi20,pi36: in std_logic;
    po04,po20: inout std_logic
  );
end Cookbook__compress_32__part4;

architecture Cookbook__compress_32__part4_behav of Cookbook__compress_32__part4 is
signal n91,n123,n139,n155,n171: std_logic;
begin
    n91 <= ( not pi04 and pi20 )
      or ( pi04 and not pi20 );
    po04 <= ( not n91 and pi36 )
      or ( n91 and not pi36 );
    n123 <= ( pi04 and pi36 );
    n139 <= ( pi04 and pi20 );
    n155 <= not (( not n139 and not n123 ));
    n171 <= ( pi20 and pi36 );
    po20 <= not (( not n155 and not n171 ));
end Cookbook__compress_32__part4_behav;
