--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi15,pi16,pi17,pi18: in std_logic;
    po18: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po18 <= ( pi15 and not pi18 )
      or ( pi16 and not pi18 )
      or ( not pi15 and not pi16 and not pi17 );
end top_behav;
