--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi21,pi22,pi74,pi75,pi76,pi77: in std_logic;
    po07,po10,po26: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po07 <= ( pi21 )
      or ( not pi22 );
    po10 <= ( not pi21 );
    po26 <= ( not pi21 and pi74 and pi76 )
      or ( pi74 and pi75 and pi77 );
end top_behav;
