.model Cookbook__ram_delay_reg
.inputs pi0
.outputs
.latch li0 lo0
.latch li1 lo1
.latch li2 lo2
.latch li3 lo3
.names lo0 lo1 n13
01 1
10 1
.names lo0 lo1 n14
11 1
.names n14 lo2 n15
01 1
10 1
.names n14 lo2 n16
11 1
.names n16 lo3 n17
01 1
10 1
.names lo0 pi0 li0
01 1
10 1
.names lo1 n13 pi0 li1
1-0 1
-11 1
.names lo2 n15 pi0 li2
1-0 1
-11 1
.names lo3 n17 pi0 li3
1-0 1
-11 1
.end
