--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__cm152a is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10: in std_logic;
    po0: inout std_logic
  );
end IWLS93__cm152a;

architecture IWLS93__cm152a_behav of IWLS93__cm152a is
signal n13,n14,n15,n16,n17,n18,n19,n20: std_logic;
begin
    po0 <= ( n16 )
      or ( n15 )
      or ( n13 )
      or ( n17 )
      or ( n20 )
      or ( n18 )
      or ( n14 )
      or ( n19 );
    n13 <= ( pi00 and not pi08 and not pi09 and not pi10 );
    n14 <= ( pi05 and pi08 and not pi09 and pi10 );
    n15 <= ( pi04 and not pi08 and not pi09 and pi10 );
    n16 <= ( pi03 and pi08 and pi09 and not pi10 );
    n17 <= ( pi02 and not pi08 and pi09 and not pi10 );
    n18 <= ( pi07 and pi08 and pi09 and pi10 );
    n19 <= ( pi06 and not pi08 and pi09 and pi10 );
    n20 <= ( pi01 and pi08 and not pi09 and not pi10 );
end IWLS93__cm152a_behav;
