--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__mlab_delay is 
  Port (
    pi0,lo0,lo1,lo2,lo3,lo4,lo5,lo6,lo7: in std_logic;
    n3,n8,n13,n18,n23,n28_1,n33,n38: inout std_logic
  );
end Cookbook__mlab_delay;

architecture Cookbook__mlab_delay_behav of Cookbook__mlab_delay is
signal n25,n26,n27,n28,n29: std_logic;
begin
    n25 <= ( not lo4 and lo5 )
      or ( lo4 and not lo5 );
    n26 <= ( lo4 and lo5 );
    n27 <= ( not n26 and lo6 )
      or ( n26 and not lo6 );
    n28 <= ( n26 and lo6 );
    n29 <= ( not n28 and lo7 )
      or ( n28 and not lo7 );
    n23 <= ( not lo4 and pi0 )
      or ( lo4 and not pi0 );
    n28_1 <= ( lo5 and not pi0 )
      or ( n25 and pi0 );
    n33 <= ( lo6 and not pi0 )
      or ( n27 and pi0 );
    n38 <= ( lo7 and not pi0 )
      or ( n29 and pi0 );
    n3 <= ( lo0 and not pi0 )
      or ( lo4 and pi0 );
    n8 <= ( lo1 and not pi0 )
      or ( lo5 and pi0 );
    n13 <= ( lo2 and not pi0 )
      or ( lo6 and pi0 );
    n18 <= ( lo3 and not pi0 )
      or ( not lo7 and pi0 );
end Cookbook__mlab_delay_behav;
