--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10: in std_logic;
    po0,po1,po2,po3,po4: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po0 <= ( pi01 )
      or ( pi03 and pi06 )
      or ( pi02 and pi05 and pi06 )
      or ( pi00 and pi04 and pi05 and pi06 );
    po1 <= ( pi03 )
      or ( pi02 and pi05 )
      or ( pi00 and pi04 and pi05 );
    po2 <= ( pi02 )
      or ( pi00 and pi04 );
    po3 <= ( pi10 )
      or ( pi07 and pi09 )
      or ( pi01 and pi08 and pi09 )
      or ( pi03 and pi06 and pi08 and pi09 )
      or ( pi02 and pi05 and pi06 and pi08 and pi09 )
      or ( pi00 and pi04 and pi05 and pi06 and pi08 and pi09 );
    po4 <= ( pi07 )
      or ( pi01 and pi08 )
      or ( pi03 and pi06 and pi08 )
      or ( pi02 and pi05 and pi06 and pi08 )
      or ( pi00 and pi04 and pi05 and pi06 and pi08 );
end top_behav;
