--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0,po1,po2: inout std_logic
  );
end top;

architecture top_behav of top is
signal n11,n12,n13: std_logic;
begin
    po0 <= ( not pi0 and n11 )
      or ( pi0 and not n11 );
    po1 <= ( n12 and n13 )
      or ( not n12 and not n13 );
    po2 <= ( not n12 and pi3 )
      or ( not n12 and pi4 )
      or ( pi3 and pi4 );
    n11 <= ( not pi1 and pi2 )
      or ( pi1 and not pi2 );
    n12 <= ( not pi0 and not pi1 )
      or ( not pi0 and not pi2 )
      or ( not pi1 and not pi2 );
    n13 <= ( not pi3 and pi4 )
      or ( pi3 and not pi4 );
end top_behav;
