--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s27 is 
  Port (
    pi0,pi1,pi2,pi3,lo0,lo1,lo2: in std_logic;
    po0,n11,n16,n21_1: inout std_logic
  );
end LGSynth91__s27;

architecture LGSynth91__s27_behav of LGSynth91__s27 is
signal n18,n19,n20,n21,n22: std_logic;
begin
    po0 <= ( not n16 );
    n11 <= ( pi0 and not n16 );
    n16 <= ( not lo0 and not n18 );
    n21_1 <= ( not pi2 and not n19 );
    n18 <= ( not n22 )
      or ( not n21 );
    n19 <= ( not pi1 and not lo2 );
    n20 <= ( not pi0 and lo1 );
    n21 <= ( n19 )
      or ( n20 );
    n22 <= ( pi3 )
      or ( n20 );
end LGSynth91__s27_behav;
