--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part56 is 
  Port (
    lo223: in std_logic;
    po27: inout std_logic
  );
end Cookbook__gearbox_67_40__part56;

architecture Cookbook__gearbox_67_40__part56_behav of Cookbook__gearbox_67_40__part56 is
begin
    po27 <= ( lo223 );
end Cookbook__gearbox_67_40__part56_behav;
