--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1063 is 
  Port (
    lo2484: in std_logic;
    n17011: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1063;

architecture Other__ucsb_152_tap_fir__part1063_behav of Other__ucsb_152_tap_fir__part1063 is
begin
    n17011 <= ( lo2484 );
end Other__ucsb_152_tap_fir__part1063_behav;
