--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part659 is 
  Port (
    lo5101: in std_logic;
    n23089: inout std_logic
  );
end Other__carpat__part659;

architecture Other__carpat__part659_behav of Other__carpat__part659 is
begin
    n23089 <= ( lo5101 );
end Other__carpat__part659_behav;
