--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part141 is 
  Port (
    lo0021: in std_logic;
    po21: inout std_logic
  );
end Other__desperf__part141;

architecture Other__desperf__part141_behav of Other__desperf__part141 is
begin
    po21 <= ( lo0021 );
end Other__desperf__part141_behav;
