--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part377 is 
  Port (
    lo2177: in std_logic;
    n11395: inout std_logic
  );
end IWLS2005__des_perf__part377;

architecture IWLS2005__des_perf__part377_behav of IWLS2005__des_perf__part377 is
begin
    n11395 <= ( lo2177 );
end IWLS2005__des_perf__part377_behav;
