--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1039 is 
  Port (
    lo5071: in std_logic;
    n25270: inout std_logic
  );
end IWLS2005__des_perf__part1039;

architecture IWLS2005__des_perf__part1039_behav of IWLS2005__des_perf__part1039 is
begin
    n25270 <= ( lo5071 );
end IWLS2005__des_perf__part1039_behav;
