--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1449 is 
  Port (
    lo4818: in std_logic;
    n19579_1: inout std_logic
  );
end Other__sudoku_check__part1449;

architecture Other__sudoku_check__part1449_behav of Other__sudoku_check__part1449 is
begin
    n19579_1 <= ( lo4818 );
end Other__sudoku_check__part1449_behav;
