--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_phy__part13 is 
  Port (
    lo52: in std_logic;
    n290,po15: inout std_logic
  );
end IWLS2005__usb_phy__part13;

architecture IWLS2005__usb_phy__part13_behav of IWLS2005__usb_phy__part13 is
begin
    n290 <= ( lo52 );
    po15 <= ( lo52 );
end IWLS2005__usb_phy__part13_behav;
