--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s953__part4 is 
  Port (
    lo04: in std_logic;
    po12: inout std_logic
  );
end IWLS93__s953__part4;

architecture IWLS93__s953__part4_behav of IWLS93__s953__part4 is
begin
    po12 <= ( lo04 );
end IWLS93__s953__part4_behav;
