--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2060 is 
  Port (
    lo4591: in std_logic;
    n27536: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2060;

architecture Other__ucsb_152_tap_fir__part2060_behav of Other__ucsb_152_tap_fir__part2060 is
begin
    n27536 <= ( lo4591 );
end Other__ucsb_152_tap_fir__part2060_behav;
