--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part10 is 
  Port (
    pi010: in std_logic;
    n43750_1: inout std_logic
  );
end IWLS2005__des_perf__part10;

architecture IWLS2005__des_perf__part10_behav of IWLS2005__des_perf__part10 is
begin
    n43750_1 <= ( pi010 );
end IWLS2005__des_perf__part10_behav;
