--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part777 is 
  Port (
    lo5739: in std_logic;
    n26484: inout std_logic
  );
end Other__carpat__part777;

architecture Other__carpat__part777_behav of Other__carpat__part777 is
begin
    n26484 <= ( lo5739 );
end Other__carpat__part777_behav;
