--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part23 is 
  Port (
    lo064: in std_logic;
    n618: inout std_logic
  );
end ISCAS__s13207__part23;

architecture ISCAS__s13207__part23_behav of ISCAS__s13207__part23 is
begin
    n618 <= ( lo064 );
end ISCAS__s13207__part23_behav;
