--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part970 is 
  Port (
    lo4339: in std_logic;
    n17184: inout std_logic
  );
end Other__sudoku_check__part970;

architecture Other__sudoku_check__part970_behav of Other__sudoku_check__part970 is
begin
    n17184 <= ( lo4339 );
end Other__sudoku_check__part970_behav;
