--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part363 is 
  Port (
    lo3012: in std_logic;
    n8549: inout std_logic
  );
end Other__sudoku_check__part363;

architecture Other__sudoku_check__part363_behav of Other__sudoku_check__part363 is
begin
    n8549 <= ( lo3012 );
end Other__sudoku_check__part363_behav;
