--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s967__part7 is 
  Port (
    lo12: in std_logic;
    po06: inout std_logic
  );
end ISCAS__s967__part7;

architecture ISCAS__s967__part7_behav of ISCAS__s967__part7 is
begin
    po06 <= ( lo12 );
end ISCAS__s967__part7_behav;
