--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part36 is 
  Port (
    lo0136: in std_logic;
    po459: inout std_logic
  );
end Other__cfft__part36;

architecture Other__cfft__part36_behav of Other__cfft__part36 is
begin
    po459 <= ( lo0136 );
end Other__cfft__part36_behav;
