--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part224 is 
  Port (
    lo210: in std_logic;
    po056: inout std_logic
  );
end Cookbook__lc_mult_signed__part224;

architecture Cookbook__lc_mult_signed__part224_behav of Cookbook__lc_mult_signed__part224 is
begin
    po056 <= ( lo210 );
end Cookbook__lc_mult_signed__part224_behav;
