--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part930 is 
  Port (
    lo0999: in std_logic;
    n5294: inout std_logic
  );
end Cookbook__fec_check__part930;

architecture Cookbook__fec_check__part930_behav of Cookbook__fec_check__part930 is
begin
    n5294 <= ( lo0999 );
end Cookbook__fec_check__part930_behav;
