--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part67 is 
  Port (
    lo234: in std_logic;
    po16: inout std_logic
  );
end Cookbook__gearbox_67_40__part67;

architecture Cookbook__gearbox_67_40__part67_behav of Cookbook__gearbox_67_40__part67 is
begin
    po16 <= ( lo234 );
end Cookbook__gearbox_67_40__part67_behav;
