--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1466 is 
  Port (
    lo8097: in std_logic;
    n44534_1: inout std_logic
  );
end Other__carpat__part1466;

architecture Other__carpat__part1466_behav of Other__carpat__part1466 is
begin
    n44534_1 <= ( lo8097 );
end Other__carpat__part1466_behav;
