--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part128 is 
  Port (
    lo1029: in std_logic;
    n5419: inout std_logic
  );
end ISCAS__s38417__part128;

architecture ISCAS__s38417__part128_behav of ISCAS__s38417__part128 is
begin
    n5419 <= ( lo1029 );
end ISCAS__s38417__part128_behav;
