--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2175 is 
  Port (
    lo2244: in std_logic;
    n11519: inout std_logic
  );
end Cookbook__fec_check__part2175;

architecture Cookbook__fec_check__part2175_behav of Cookbook__fec_check__part2175 is
begin
    n11519 <= ( lo2244 );
end Cookbook__fec_check__part2175_behav;
