--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part36 is 
  Port (
    lo0104: in std_logic;
    po112: inout std_logic
  );
end Other__mem__part36;

architecture Other__mem__part36_behav of Other__mem__part36 is
begin
    po112 <= ( lo0104 );
end Other__mem__part36_behav;
