--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1389 is 
  Port (
    lo1458: in std_logic;
    n7589: inout std_logic
  );
end Cookbook__fec_check__part1389;

architecture Cookbook__fec_check__part1389_behav of Cookbook__fec_check__part1389 is
begin
    n7589 <= ( lo1458 );
end Cookbook__fec_check__part1389_behav;
