--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part83 is 
  Port (
    lo209: in std_logic;
    po132: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part83;

architecture Cookbook__soft_ecc_ram_64bit__part83_behav of Cookbook__soft_ecc_ram_64bit__part83 is
begin
    po132 <= ( lo209 );
end Cookbook__soft_ecc_ram_64bit__part83_behav;
