--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1550 is 
  Port (
    lo8181: in std_logic;
    n45974_1: inout std_logic
  );
end Other__carpat__part1550;

architecture Other__carpat__part1550_behav of Other__carpat__part1550 is
begin
    n45974_1 <= ( lo8181 );
end Other__carpat__part1550_behav;
