--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part139 is 
  Port (
    lo01368: in std_logic;
    po2790,po2886,po2982,po4902,po4950,po4998,n21156: inout std_logic
  );
end Other__ray__part139;

architecture Other__ray__part139_behav of Other__ray__part139 is
begin
    po2790 <= ( lo01368 );
    po2886 <= ( lo01368 );
    po2982 <= ( lo01368 );
    po4902 <= ( lo01368 );
    po4950 <= ( lo01368 );
    po4998 <= ( lo01368 );
    n21156 <= ( lo01368 );
end Other__ray__part139_behav;
