--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part119 is 
  Port (
    lo002: in std_logic;
    po002: inout std_logic
  );
end Other__fpu__part119;

architecture Other__fpu__part119_behav of Other__fpu__part119 is
begin
    po002 <= ( lo002 );
end Other__fpu__part119_behav;
