--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part51 is 
  Port (
    pi51: in std_logic;
    n746747: inout std_logic
  );
end IWLS2005__leon2__part51;

architecture IWLS2005__leon2__part51_behav of IWLS2005__leon2__part51 is
begin
    n746747 <= ( pi51 );
end IWLS2005__leon2__part51_behav;
