--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part737 is 
  Port (
    lo5465: in std_logic;
    n25804: inout std_logic
  );
end Other__carpat__part737;

architecture Other__carpat__part737_behav of Other__carpat__part737 is
begin
    n25804 <= ( lo5465 );
end Other__carpat__part737_behav;
