--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part788 is 
  Port (
    lo4157: in std_logic;
    n13964: inout std_logic
  );
end Other__sudoku_check__part788;

architecture Other__sudoku_check__part788_behav of Other__sudoku_check__part788 is
begin
    n13964 <= ( lo4157 );
end Other__sudoku_check__part788_behav;
