--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part115 is 
  Port (
    lo209: in std_logic;
    po26: inout std_logic
  );
end Cookbook__gearbox_40_67__part115;

architecture Cookbook__gearbox_40_67__part115_behav of Cookbook__gearbox_40_67__part115 is
begin
    po26 <= ( lo209 );
end Cookbook__gearbox_40_67__part115_behav;
