--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part57 is 
  Port (
    lo0230: in std_logic;
    n2362: inout std_logic
  );
end Other__cfft__part57;

architecture Other__cfft__part57_behav of Other__cfft__part57 is
begin
    n2362 <= ( lo0230 );
end Other__cfft__part57_behav;
