--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part6 is 
  Port (
    pi22: in std_logic;
    n630: inout std_logic
  );
end Cookbook__lc_mult_signed__part6;

architecture Cookbook__lc_mult_signed__part6_behav of Cookbook__lc_mult_signed__part6 is
begin
    n630 <= ( pi22 );
end Cookbook__lc_mult_signed__part6_behav;
