--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1215 is 
  Port (
    lo1284: in std_logic;
    n6719: inout std_logic
  );
end Cookbook__fec_check__part1215;

architecture Cookbook__fec_check__part1215_behav of Cookbook__fec_check__part1215 is
begin
    n6719 <= ( lo1284 );
end Cookbook__fec_check__part1215_behav;
