--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part622 is 
  Port (
    lo4265: in std_logic;
    n21465: inout std_logic
  );
end IWLS2005__des_perf__part622;

architecture IWLS2005__des_perf__part622_behav of IWLS2005__des_perf__part622 is
begin
    n21465 <= ( lo4265 );
end IWLS2005__des_perf__part622_behav;
