--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part324 is 
  Port (
    lo0393: in std_logic;
    n2264: inout std_logic
  );
end Cookbook__fec_check__part324;

architecture Cookbook__fec_check__part324_behav of Cookbook__fec_check__part324 is
begin
    n2264 <= ( lo0393 );
end Cookbook__fec_check__part324_behav;
