--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1678 is 
  Port (
    lo3798: in std_logic;
    n23566: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1678;

architecture Other__ucsb_152_tap_fir__part1678_behav of Other__ucsb_152_tap_fir__part1678 is
begin
    n23566 <= ( lo3798 );
end Other__ucsb_152_tap_fir__part1678_behav;
