--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part913 is 
  Port (
    lo0982: in std_logic;
    n5209: inout std_logic
  );
end Cookbook__fec_check__part913;

architecture Cookbook__fec_check__part913_behav of Cookbook__fec_check__part913 is
begin
    n5209 <= ( lo0982 );
end Cookbook__fec_check__part913_behav;
