--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part10 is 
  Port (
    lo31: in std_logic;
    po08: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part10;

architecture Cookbook__soft_ecc_ram_16bit__part10_behav of Cookbook__soft_ecc_ram_16bit__part10 is
begin
    po08 <= ( lo31 );
end Cookbook__soft_ecc_ram_16bit__part10_behav;
