--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part278 is 
  Port (
    lo1361: in std_logic;
    n9740_1: inout std_logic
  );
end Other__fp_operators__part278;

architecture Other__fp_operators__part278_behav of Other__fp_operators__part278 is
begin
    n9740_1 <= ( lo1361 );
end Other__fp_operators__part278_behav;
