--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part144 is 
  Port (
    lo0023: in std_logic;
    po10: inout std_logic
  );
end IWLS2005__des_perf__part144;

architecture IWLS2005__des_perf__part144_behav of IWLS2005__des_perf__part144 is
begin
    po10 <= ( lo0023 );
end IWLS2005__des_perf__part144_behav;
