--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part19 is 
  Port (
    pi019: in std_logic;
    n43795_1: inout std_logic
  );
end IWLS2005__des_perf__part19;

architecture IWLS2005__des_perf__part19_behav of IWLS2005__des_perf__part19 is
begin
    n43795_1 <= ( pi019 );
end IWLS2005__des_perf__part19_behav;
