--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part127 is 
  Port (
    lo01356: in std_logic;
    po2786,po2882,po2978,po4326,po4374,po4422,n21061: inout std_logic
  );
end Other__ray__part127;

architecture Other__ray__part127_behav of Other__ray__part127 is
begin
    po2786 <= ( lo01356 );
    po2882 <= ( lo01356 );
    po2978 <= ( lo01356 );
    po4326 <= ( lo01356 );
    po4374 <= ( lo01356 );
    po4422 <= ( lo01356 );
    n21061 <= ( lo01356 );
end Other__ray__part127_behav;
