--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part20 is 
  Port (
    pi23: in std_logic;
    n97: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part20;

architecture Cookbook__ycbcr_to_rgb__part20_behav of Cookbook__ycbcr_to_rgb__part20 is
begin
    n97 <= ( pi23 );
end Cookbook__ycbcr_to_rgb__part20_behav;
