--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1199 is 
  Port (
    lo1268: in std_logic;
    n6639: inout std_logic
  );
end Cookbook__fec_check__part1199;

architecture Cookbook__fec_check__part1199_behav of Cookbook__fec_check__part1199 is
begin
    n6639 <= ( lo1268 );
end Cookbook__fec_check__part1199_behav;
