--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part124 is 
  Port (
    lo1011: in std_logic;
    n6019_1: inout std_logic
  );
end ISCAS__s38417__part124;

architecture ISCAS__s38417__part124_behav of ISCAS__s38417__part124 is
begin
    n6019_1 <= ( not lo1011 );
end ISCAS__s38417__part124_behav;
