--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1432 is 
  Port (
    lo3286: in std_logic;
    n21001: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1432;

architecture Other__ucsb_152_tap_fir__part1432_behav of Other__ucsb_152_tap_fir__part1432 is
begin
    n21001 <= ( lo3286 );
end Other__ucsb_152_tap_fir__part1432_behav;
