--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part207 is 
  Port (
    lo0910,lo0915: in std_logic;
    n6465,n6530,n6540,n6550,n6555,n6585,n6590,n6395,n6425: inout std_logic
  );
end Other__fp_operators__part207;

architecture Other__fp_operators__part207_behav of Other__fp_operators__part207 is
signal n6515,n24965,n24967: std_logic;
begin
    n6465 <= ( not lo0910 and lo0915 )
      or ( lo0910 and not lo0915 );
    n6515 <= ( lo0910 and lo0915 );
    n6530 <= ( not lo0910 and not lo0915 and n6515 )
      or ( not lo0910 and lo0915 and not n6515 )
      or ( lo0910 and not lo0915 and not n6515 )
      or ( lo0910 and lo0915 and n6515 );
    n6540 <= ( lo0915 and not n6515 );
    n24965 <= ( lo0915 and n6515 );
    n6550 <= ( lo0910 and not n24965 );
    n24967 <= ( lo0910 and n24965 );
    n6555 <= ( lo0915 and not n24967 );
    n6585 <= ( lo0910 and not n6515 );
    n6590 <= ( not lo0910 and lo0915 );
    n6395 <= ( lo0910 );
    n6425 <= ( lo0915 );
end Other__fp_operators__part207_behav;
