--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part131 is 
  Port (
    lo0987: in std_logic;
    po070: inout std_logic
  );
end IWLS2005__mem_ctrl__part131;

architecture IWLS2005__mem_ctrl__part131_behav of IWLS2005__mem_ctrl__part131 is
begin
    po070 <= ( lo0987 );
end IWLS2005__mem_ctrl__part131_behav;
