--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part137 is 
  Port (
    pi0547: in std_logic;
    n43281_1: inout std_logic
  );
end Other__radar__part137;

architecture Other__radar__part137_behav of Other__radar__part137 is
begin
    n43281_1 <= ( pi0547 );
end Other__radar__part137_behav;
