--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part1 is 
  Port (
    lo0428: in std_logic;
    po0451: inout std_logic
  );
end Other__top_rs_decode__part1;

architecture Other__top_rs_decode__part1_behav of Other__top_rs_decode__part1 is
begin
    po0451 <= ( lo0428 );
end Other__top_rs_decode__part1_behav;
