--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part39 is 
  Port (
    lo38: in std_logic;
    po38: inout std_logic
  );
end Other__idxlat03n_m12__part39;

architecture Other__idxlat03n_m12__part39_behav of Other__idxlat03n_m12__part39 is
begin
    po38 <= ( lo38 );
end Other__idxlat03n_m12__part39_behav;
