--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_22__part23 is 
  Port (
    lo64: in std_logic;
    po04: inout std_logic
  );
end Cookbook__gearbox_20_22__part23;

architecture Cookbook__gearbox_20_22__part23_behav of Cookbook__gearbox_20_22__part23 is
begin
    po04 <= ( lo64 );
end Cookbook__gearbox_20_22__part23_behav;
