--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1285 is 
  Port (
    lo5590: in std_logic;
    n27635_1: inout std_logic
  );
end IWLS2005__des_perf__part1285;

architecture IWLS2005__des_perf__part1285_behav of IWLS2005__des_perf__part1285 is
begin
    n27635_1 <= ( lo5590 );
end IWLS2005__des_perf__part1285_behav;
