--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1632 is 
  Port (
    lo6301: in std_logic;
    n31480_1: inout std_logic
  );
end IWLS2005__des_perf__part1632;

architecture IWLS2005__des_perf__part1632_behav of IWLS2005__des_perf__part1632 is
begin
    n31480_1 <= ( lo6301 );
end IWLS2005__des_perf__part1632_behav;
