--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__C7552__part2 is 
  Port (
    pi043,pi093: in std_logic;
    po06: inout std_logic
  );
end IWLS93__C7552__part2;

architecture IWLS93__C7552__part2_behav of IWLS93__C7552__part2 is
begin
    po06 <= ( pi043 and pi093 );
end IWLS93__C7552__part2_behav;
