--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part80 is 
  Port (
    lo0543: in std_logic;
    n3319: inout std_logic
  );
end IWLS93__s38417__part80;

architecture IWLS93__s38417__part80_behav of IWLS93__s38417__part80 is
begin
    n3319 <= ( lo0543 );
end IWLS93__s38417__part80_behav;
