--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1493 is 
  Port (
    lo4862: in std_logic;
    n19799_1: inout std_logic
  );
end Other__sudoku_check__part1493;

architecture Other__sudoku_check__part1493_behav of Other__sudoku_check__part1493 is
begin
    n19799_1 <= ( lo4862 );
end Other__sudoku_check__part1493_behav;
