--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part32 is 
  Port (
    pi0438: in std_logic;
    n42561_1: inout std_logic
  );
end Other__radar__part32;

architecture Other__radar__part32_behav of Other__radar__part32 is
begin
    n42561_1 <= ( pi0438 );
end Other__radar__part32_behav;
