--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2221 is 
  Port (
    lo4913: in std_logic;
    n29151: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2221;

architecture Other__ucsb_152_tap_fir__part2221_behav of Other__ucsb_152_tap_fir__part2221 is
begin
    n29151 <= ( lo4913 );
end Other__ucsb_152_tap_fir__part2221_behav;
