--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1014 is 
  Port (
    lo7107: in std_logic;
    n37709_1: inout std_logic
  );
end Other__carpat__part1014;

architecture Other__carpat__part1014_behav of Other__carpat__part1014 is
begin
    n37709_1 <= ( lo7107 );
end Other__carpat__part1014_behav;
