--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2031 is 
  Port (
    lo4532: in std_logic;
    n27246: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2031;

architecture Other__ucsb_152_tap_fir__part2031_behav of Other__ucsb_152_tap_fir__part2031 is
begin
    n27246 <= ( lo4532 );
end Other__ucsb_152_tap_fir__part2031_behav;
