--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1228 is 
  Port (
    lo4597: in std_logic;
    n18474: inout std_logic
  );
end Other__sudoku_check__part1228;

architecture Other__sudoku_check__part1228_behav of Other__sudoku_check__part1228 is
begin
    n18474 <= ( lo4597 );
end Other__sudoku_check__part1228_behav;
