--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1913 is 
  Port (
    lo1982: in std_logic;
    n10209: inout std_logic
  );
end Cookbook__fec_check__part1913;

architecture Cookbook__fec_check__part1913_behav of Cookbook__fec_check__part1913 is
begin
    n10209 <= ( lo1982 );
end Cookbook__fec_check__part1913_behav;
