--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2647 is 
  Port (
    lo7933: in std_logic;
    n39470_1: inout std_logic
  );
end IWLS2005__des_perf__part2647;

architecture IWLS2005__des_perf__part2647_behav of IWLS2005__des_perf__part2647 is
begin
    n39470_1 <= ( lo7933 );
end IWLS2005__des_perf__part2647_behav;
