--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part859 is 
  Port (
    lo4228: in std_logic;
    n16629: inout std_logic
  );
end Other__sudoku_check__part859;

architecture Other__sudoku_check__part859_behav of Other__sudoku_check__part859 is
begin
    n16629 <= ( lo4228 );
end Other__sudoku_check__part859_behav;
