--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1123 is 
  Port (
    lo2614: in std_logic;
    n17611: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1123;

architecture Other__ucsb_152_tap_fir__part1123_behav of Other__ucsb_152_tap_fir__part1123 is
begin
    n17611 <= ( lo2614 );
end Other__ucsb_152_tap_fir__part1123_behav;
