--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1657 is 
  Port (
    lo1726: in std_logic;
    n8929: inout std_logic
  );
end Cookbook__fec_check__part1657;

architecture Cookbook__fec_check__part1657_behav of Cookbook__fec_check__part1657 is
begin
    n8929 <= ( lo1726 );
end Cookbook__fec_check__part1657_behav;
