--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part710 is 
  Port (
    lo3359: in std_logic;
    n12019: inout std_logic
  );
end Other__sudoku_check__part710;

architecture Other__sudoku_check__part710_behav of Other__sudoku_check__part710 is
begin
    n12019 <= ( lo3359 );
end Other__sudoku_check__part710_behav;
