--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part631 is 
  Port (
    lo0700: in std_logic;
    n3799: inout std_logic
  );
end Cookbook__fec_check__part631;

architecture Cookbook__fec_check__part631_behav of Cookbook__fec_check__part631 is
begin
    n3799 <= ( lo0700 );
end Cookbook__fec_check__part631_behav;
