--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1394 is 
  Port (
    lo7844: in std_logic;
    n44099_1: inout std_logic
  );
end Other__carpat__part1394;

architecture Other__carpat__part1394_behav of Other__carpat__part1394 is
begin
    n44099_1 <= ( lo7844 );
end Other__carpat__part1394_behav;
