--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part141 is 
  Port (
    lo0320: in std_logic;
    n6091: inout std_logic
  );
end Other__ucsb_152_tap_fir__part141;

architecture Other__ucsb_152_tap_fir__part141_behav of Other__ucsb_152_tap_fir__part141 is
begin
    n6091 <= ( lo0320 );
end Other__ucsb_152_tap_fir__part141_behav;
