--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1537 is 
  Port (
    lo6124: in std_logic;
    n30880_1: inout std_logic
  );
end IWLS2005__des_perf__part1537;

architecture IWLS2005__des_perf__part1537_behav of IWLS2005__des_perf__part1537 is
begin
    n30880_1 <= ( lo6124 );
end IWLS2005__des_perf__part1537_behav;
