--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1952 is 
  Port (
    lo2021: in std_logic;
    n10404: inout std_logic
  );
end Cookbook__fec_check__part1952;

architecture Cookbook__fec_check__part1952_behav of Cookbook__fec_check__part1952 is
begin
    n10404 <= ( lo2021 );
end Cookbook__fec_check__part1952_behav;
