--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part496 is 
  Port (
    lo1831: in std_logic;
    n10414_1: inout std_logic
  );
end Cookbook__ucrypt__part496;

architecture Cookbook__ucrypt__part496_behav of Cookbook__ucrypt__part496 is
begin
    n10414_1 <= ( lo1831 );
end Cookbook__ucrypt__part496_behav;
