--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1696 is 
  Port (
    lo3846: in std_logic;
    n23811: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1696;

architecture Other__ucsb_152_tap_fir__part1696_behav of Other__ucsb_152_tap_fir__part1696 is
begin
    n23811 <= ( lo3846 );
end Other__ucsb_152_tap_fir__part1696_behav;
