--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part935 is 
  Port (
    lo4304: in std_logic;
    n17009: inout std_logic
  );
end Other__sudoku_check__part935;

architecture Other__sudoku_check__part935_behav of Other__sudoku_check__part935 is
begin
    n17009 <= ( lo4304 );
end Other__sudoku_check__part935_behav;
