--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1563 is 
  Port (
    lo8276: in std_logic;
    n46249_1: inout std_logic
  );
end Other__carpat__part1563;

architecture Other__carpat__part1563_behav of Other__carpat__part1563 is
begin
    n46249_1 <= ( lo8276 );
end Other__carpat__part1563_behav;
