--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1573 is 
  Port (
    lo3572: in std_logic;
    n22446: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1573;

architecture Other__ucsb_152_tap_fir__part1573_behav of Other__ucsb_152_tap_fir__part1573 is
begin
    n22446 <= ( lo3572 );
end Other__ucsb_152_tap_fir__part1573_behav;
