--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part612 is 
  Port (
    lo4980: in std_logic;
    n21979: inout std_logic
  );
end Other__carpat__part612;

architecture Other__carpat__part612_behav of Other__carpat__part612 is
begin
    n21979 <= ( lo4980 );
end Other__carpat__part612_behav;
