--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part29 is 
  Port (
    lo27: in std_logic;
    po12: inout std_logic
  );
end Cookbook__pipeline_add__part29;

architecture Cookbook__pipeline_add__part29_behav of Cookbook__pipeline_add__part29 is
begin
    po12 <= ( lo27 );
end Cookbook__pipeline_add__part29_behav;
