--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part797 is 
  Port (
    lo4570: in std_logic;
    n22890: inout std_logic
  );
end IWLS2005__des_perf__part797;

architecture IWLS2005__des_perf__part797_behav of IWLS2005__des_perf__part797 is
begin
    n22890 <= ( lo4570 );
end IWLS2005__des_perf__part797_behav;
