--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part25 is 
  Port (
    pi896: in std_logic;
    n10875_1: inout std_logic
  );
end Other__fp_operators__part25;

architecture Other__fp_operators__part25_behav of Other__fp_operators__part25 is
begin
    n10875_1 <= ( pi896 );
end Other__fp_operators__part25_behav;
