--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1038 is 
  Port (
    lo5070: in std_logic;
    n25300: inout std_logic
  );
end IWLS2005__des_perf__part1038;

architecture IWLS2005__des_perf__part1038_behav of IWLS2005__des_perf__part1038 is
begin
    n25300 <= ( lo5070 );
end IWLS2005__des_perf__part1038_behav;
