--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part96 is 
  Port (
    lo333: in std_logic;
    po093: inout std_logic
  );
end IWLS2005__aes_core__part96;

architecture IWLS2005__aes_core__part96_behav of IWLS2005__aes_core__part96 is
begin
    po093 <= ( lo333 );
end IWLS2005__aes_core__part96_behav;
