--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part950 is 
  Port (
    lo10531: in std_logic;
    n69196: inout std_logic
  );
end Other__ray__part950;

architecture Other__ray__part950_behav of Other__ray__part950 is
begin
    n69196 <= ( lo10531 );
end Other__ray__part950_behav;
