--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part148 is 
  Port (
    pi1038: in std_logic;
    n32034_1: inout std_logic
  );
end Other__carpat__part148;

architecture Other__carpat__part148_behav of Other__carpat__part148 is
begin
    n32034_1 <= ( pi1038 );
end Other__carpat__part148_behav;
