--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1157 is 
  Port (
    lo5315: in std_logic;
    n26555: inout std_logic
  );
end IWLS2005__des_perf__part1157;

architecture IWLS2005__des_perf__part1157_behav of IWLS2005__des_perf__part1157 is
begin
    n26555 <= ( lo5315 );
end IWLS2005__des_perf__part1157_behav;
