--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part585 is 
  Port (
    lo0654: in std_logic;
    n3569: inout std_logic
  );
end Cookbook__fec_check__part585;

architecture Cookbook__fec_check__part585_behav of Cookbook__fec_check__part585 is
begin
    n3569 <= ( lo0654 );
end Cookbook__fec_check__part585_behav;
