--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3260 is 
  Port (
    lo8603: in std_logic;
    n43410_1: inout std_logic
  );
end IWLS2005__des_perf__part3260;

architecture IWLS2005__des_perf__part3260_behav of IWLS2005__des_perf__part3260 is
begin
    n43410_1 <= ( lo8603 );
end IWLS2005__des_perf__part3260_behav;
