--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part858 is 
  Port (
    lo6489: in std_logic;
    n30814_1: inout std_logic
  );
end Other__carpat__part858;

architecture Other__carpat__part858_behav of Other__carpat__part858 is
begin
    n30814_1 <= ( lo6489 );
end Other__carpat__part858_behav;
