--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part16 is 
  Port (
    pi16: in std_logic;
    n746897: inout std_logic
  );
end IWLS2005__leon2__part16;

architecture IWLS2005__leon2__part16_behav of IWLS2005__leon2__part16 is
begin
    n746897 <= ( pi16 );
end IWLS2005__leon2__part16_behav;
