--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part17 is 
  Port (
    lo48: in std_logic;
    po09: inout std_logic
  );
end Cookbook__temp_sense_s5__part17;

architecture Cookbook__temp_sense_s5__part17_behav of Cookbook__temp_sense_s5__part17 is
begin
    po09 <= ( lo48 );
end Cookbook__temp_sense_s5__part17_behav;
