--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part8 is 
  Port (
    pi12: in std_logic;
    n424: inout std_logic
  );
end ISCAS__s38417__part8;

architecture ISCAS__s38417__part8_behav of ISCAS__s38417__part8 is
begin
    n424 <= ( pi12 );
end ISCAS__s38417__part8_behav;
