--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s3384__part8 is 
  Port (
    pi08: in std_logic;
    n464: inout std_logic
  );
end ISCAS__s3384__part8;

architecture ISCAS__s3384__part8_behav of ISCAS__s3384__part8 is
begin
    n464 <= ( pi08 );
end ISCAS__s3384__part8_behav;
