--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part826 is 
  Port (
    lo0895: in std_logic;
    n4774: inout std_logic
  );
end Cookbook__fec_check__part826;

architecture Cookbook__fec_check__part826_behav of Cookbook__fec_check__part826 is
begin
    n4774 <= ( lo0895 );
end Cookbook__fec_check__part826_behav;
