--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part61 is 
  Port (
    lo124: in std_logic;
    po012: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part61;

architecture Cookbook__soft_ecc_ram_64bit__part61_behav of Cookbook__soft_ecc_ram_64bit__part61 is
begin
    po012 <= ( lo124 );
end Cookbook__soft_ecc_ram_64bit__part61_behav;
