--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part287 is 
  Port (
    lo1559: in std_logic;
    n7304_1: inout std_logic
  );
end Other__desperf__part287;

architecture Other__desperf__part287_behav of Other__desperf__part287 is
begin
    n7304_1 <= ( lo1559 );
end Other__desperf__part287_behav;
