--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part883 is 
  Port (
    lo0952: in std_logic;
    n5059: inout std_logic
  );
end Cookbook__fec_check__part883;

architecture Cookbook__fec_check__part883_behav of Cookbook__fec_check__part883 is
begin
    n5059 <= ( lo0952 );
end Cookbook__fec_check__part883_behav;
