--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part21 is 
  Port (
    lo20: in std_logic;
    po20: inout std_logic
  );
end Other__idxlat10n_m12__part21;

architecture Other__idxlat10n_m12__part21_behav of Other__idxlat10n_m12__part21 is
begin
    po20 <= ( lo20 );
end Other__idxlat10n_m12__part21_behav;
