--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1938 is 
  Port (
    lo4365: in std_logic;
    n26326: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1938;

architecture Other__ucsb_152_tap_fir__part1938_behav of Other__ucsb_152_tap_fir__part1938 is
begin
    n26326 <= ( lo4365 );
end Other__ucsb_152_tap_fir__part1938_behav;
