--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part219 is 
  Port (
    lo323: in std_logic;
    n1127: inout std_logic
  );
end Other__fpu__part219;

architecture Other__fpu__part219_behav of Other__fpu__part219 is
begin
    n1127 <= ( lo323 );
end Other__fpu__part219_behav;
