--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1753 is 
  Port (
    lo1822: in std_logic;
    n9409: inout std_logic
  );
end Cookbook__fec_check__part1753;

architecture Cookbook__fec_check__part1753_behav of Cookbook__fec_check__part1753 is
begin
    n9409 <= ( lo1822 );
end Cookbook__fec_check__part1753_behav;
