--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part284 is 
  Port (
    lo474: in std_logic;
    n1647: inout std_logic
  );
end Other__fpu__part284;

architecture Other__fpu__part284_behav of Other__fpu__part284 is
begin
    n1647 <= ( lo474 );
end Other__fpu__part284_behav;
