--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part69 is 
  Port (
    lo0139: in std_logic;
    po148: inout std_logic
  );
end Other__mem__part69;

architecture Other__mem__part69_behav of Other__mem__part69 is
begin
    po148 <= ( lo0139 );
end Other__mem__part69_behav;
