--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1429 is 
  Port (
    lo4798: in std_logic;
    n19479_1: inout std_logic
  );
end Other__sudoku_check__part1429;

architecture Other__sudoku_check__part1429_behav of Other__sudoku_check__part1429 is
begin
    n19479_1 <= ( lo4798 );
end Other__sudoku_check__part1429_behav;
