--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part773 is 
  Port (
    lo4510: in std_logic;
    n22480: inout std_logic
  );
end IWLS2005__des_perf__part773;

architecture IWLS2005__des_perf__part773_behav of IWLS2005__des_perf__part773 is
begin
    n22480 <= ( lo4510 );
end IWLS2005__des_perf__part773_behav;
