--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part89 is 
  Port (
    lo075: in std_logic;
    po191: inout std_logic
  );
end Cookbook__lc_mult_signed__part89;

architecture Cookbook__lc_mult_signed__part89_behav of Cookbook__lc_mult_signed__part89 is
begin
    po191 <= ( lo075 );
end Cookbook__lc_mult_signed__part89_behav;
