--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part190 is 
  Port (
    lo0287: in std_logic;
    n1004: inout std_logic
  );
end Other__desperf__part190;

architecture Other__desperf__part190_behav of Other__desperf__part190 is
begin
    n1004 <= ( lo0287 );
end Other__desperf__part190_behav;
