--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part363 is 
  Port (
    pi1712: in std_logic;
    n48239_1: inout std_logic
  );
end Other__carpat__part363;

architecture Other__carpat__part363_behav of Other__carpat__part363 is
begin
    n48239_1 <= ( pi1712 );
end Other__carpat__part363_behav;
