--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part88 is 
  Port (
    pi0498: in std_logic;
    n43036_1: inout std_logic
  );
end Other__radar__part88;

architecture Other__radar__part88_behav of Other__radar__part88 is
begin
    n43036_1 <= ( pi0498 );
end Other__radar__part88_behav;
