--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1391 is 
  Port (
    lo7841: in std_logic;
    n44084: inout std_logic
  );
end Other__carpat__part1391;

architecture Other__carpat__part1391_behav of Other__carpat__part1391 is
begin
    n44084 <= ( lo7841 );
end Other__carpat__part1391_behav;
