--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part909 is 
  Port (
    lo4278: in std_logic;
    n16879: inout std_logic
  );
end Other__sudoku_check__part909;

architecture Other__sudoku_check__part909_behav of Other__sudoku_check__part909 is
begin
    n16879 <= ( lo4278 );
end Other__sudoku_check__part909_behav;
