--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part149 is 
  Port (
    lo0028: in std_logic;
    po52: inout std_logic
  );
end IWLS2005__des_perf__part149;

architecture IWLS2005__des_perf__part149_behav of IWLS2005__des_perf__part149 is
begin
    po52 <= ( lo0028 );
end IWLS2005__des_perf__part149_behav;
