--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1164 is 
  Port (
    lo1233: in std_logic;
    n6464: inout std_logic
  );
end Cookbook__fec_check__part1164;

architecture Cookbook__fec_check__part1164_behav of Cookbook__fec_check__part1164 is
begin
    n6464 <= ( lo1233 );
end Cookbook__fec_check__part1164_behav;
