--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part916 is 
  Port (
    lo6761: in std_logic;
    n34114_1: inout std_logic
  );
end Other__carpat__part916;

architecture Other__carpat__part916_behav of Other__carpat__part916 is
begin
    n34114_1 <= ( lo6761 );
end Other__carpat__part916_behav;
