--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part920 is 
  Port (
    lo4835: in std_logic;
    n24335: inout std_logic
  );
end IWLS2005__des_perf__part920;

architecture IWLS2005__des_perf__part920_behav of IWLS2005__des_perf__part920 is
begin
    n24335 <= ( lo4835 );
end IWLS2005__des_perf__part920_behav;
