--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2033 is 
  Port (
    lo7077: in std_logic;
    n35660: inout std_logic
  );
end IWLS2005__des_perf__part2033;

architecture IWLS2005__des_perf__part2033_behav of IWLS2005__des_perf__part2033 is
begin
    n35660 <= ( lo7077 );
end IWLS2005__des_perf__part2033_behav;
