--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part852 is 
  Port (
    lo6481: in std_logic;
    n30784_1: inout std_logic
  );
end Other__carpat__part852;

architecture Other__carpat__part852_behav of Other__carpat__part852 is
begin
    n30784_1 <= ( lo6481 );
end Other__carpat__part852_behav;
