--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1605 is 
  Port (
    lo3640: in std_logic;
    n22751: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1605;

architecture Other__ucsb_152_tap_fir__part1605_behav of Other__ucsb_152_tap_fir__part1605 is
begin
    n22751 <= ( lo3640 );
end Other__ucsb_152_tap_fir__part1605_behav;
