--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s382__part1 is 
  Port (
    lo02: in std_logic;
    po3: inout std_logic
  );
end ISCAS__s382__part1;

architecture ISCAS__s382__part1_behav of ISCAS__s382__part1 is
begin
    po3 <= ( lo02 );
end ISCAS__s382__part1_behav;
