--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part277 is 
  Port (
    lo465: in std_logic;
    n1612: inout std_logic
  );
end Other__fpu__part277;

architecture Other__fpu__part277_behav of Other__fpu__part277 is
begin
    n1612 <= ( lo465 );
end Other__fpu__part277_behav;
