--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part929 is 
  Port (
    lo4298: in std_logic;
    n16979: inout std_logic
  );
end Other__sudoku_check__part929;

architecture Other__sudoku_check__part929_behav of Other__sudoku_check__part929 is
begin
    n16979 <= ( lo4298 );
end Other__sudoku_check__part929_behav;
