--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ternary_sum_nine__part6 is 
  Port (
    lo32: in std_logic;
    po09: inout std_logic
  );
end Cookbook__ternary_sum_nine__part6;

architecture Cookbook__ternary_sum_nine__part6_behav of Cookbook__ternary_sum_nine__part6 is
begin
    po09 <= ( lo32 );
end Cookbook__ternary_sum_nine__part6_behav;
