--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1028 is 
  Port (
    lo4397: in std_logic;
    n17474: inout std_logic
  );
end Other__sudoku_check__part1028;

architecture Other__sudoku_check__part1028_behav of Other__sudoku_check__part1028 is
begin
    n17474 <= ( lo4397 );
end Other__sudoku_check__part1028_behav;
