--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part75 is 
  Port (
    lo061: in std_logic;
    po205: inout std_logic
  );
end Cookbook__lc_mult_signed__part75;

architecture Cookbook__lc_mult_signed__part75_behav of Cookbook__lc_mult_signed__part75 is
begin
    po205 <= ( lo061 );
end Cookbook__lc_mult_signed__part75_behav;
