--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2087 is 
  Port (
    lo2156: in std_logic;
    n11079: inout std_logic
  );
end Cookbook__fec_check__part2087;

architecture Cookbook__fec_check__part2087_behav of Cookbook__fec_check__part2087 is
begin
    n11079 <= ( lo2156 );
end Cookbook__fec_check__part2087_behav;
