--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part687 is 
  Port (
    lo0756: in std_logic;
    n4079: inout std_logic
  );
end Cookbook__fec_check__part687;

architecture Cookbook__fec_check__part687_behav of Cookbook__fec_check__part687 is
begin
    n4079 <= ( lo0756 );
end Cookbook__fec_check__part687_behav;
