--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2051 is 
  Port (
    lo2120: in std_logic;
    n10899: inout std_logic
  );
end Cookbook__fec_check__part2051;

architecture Cookbook__fec_check__part2051_behav of Cookbook__fec_check__part2051 is
begin
    n10899 <= ( lo2120 );
end Cookbook__fec_check__part2051_behav;
