--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_20__part36 is 
  Port (
    lo110: in std_logic;
    po05: inout std_logic
  );
end Cookbook__gearbox_66_20__part36;

architecture Cookbook__gearbox_66_20__part36_behav of Cookbook__gearbox_66_20__part36 is
begin
    po05 <= ( lo110 );
end Cookbook__gearbox_66_20__part36_behav;
