--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part158 is 
  Port (
    lo1016: in std_logic;
    po068: inout std_logic
  );
end IWLS2005__mem_ctrl__part158;

architecture IWLS2005__mem_ctrl__part158_behav of IWLS2005__mem_ctrl__part158 is
begin
    po068 <= ( lo1016 );
end IWLS2005__mem_ctrl__part158_behav;
