--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part469 is 
  Port (
    lo3118: in std_logic;
    n9609: inout std_logic
  );
end Other__sudoku_check__part469;

architecture Other__sudoku_check__part469_behav of Other__sudoku_check__part469 is
begin
    n9609 <= ( lo3118 );
end Other__sudoku_check__part469_behav;
