--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part27 is 
  Port (
    lo065: in std_logic;
    po05: inout std_logic
  );
end Cookbook__fec_gen__part27;

architecture Cookbook__fec_gen__part27_behav of Cookbook__fec_gen__part27 is
begin
    po05 <= ( lo065 );
end Cookbook__fec_gen__part27_behav;
