--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part52 is 
  Port (
    pi58: in std_logic;
    n869801: inout std_logic
  );
end IWLS2005__leon3__part52;

architecture IWLS2005__leon3__part52_behav of IWLS2005__leon3__part52 is
begin
    n869801 <= ( pi58 );
end IWLS2005__leon3__part52_behav;
