--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part331 is 
  Port (
    pi1646: in std_logic;
    n47229_1: inout std_logic
  );
end Other__carpat__part331;

architecture Other__carpat__part331_behav of Other__carpat__part331 is
begin
    n47229_1 <= ( pi1646 );
end Other__carpat__part331_behav;
