--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part116 is 
  Port (
    pi0961: in std_logic;
    n31279_1: inout std_logic
  );
end Other__carpat__part116;

architecture Other__carpat__part116_behav of Other__carpat__part116 is
begin
    n31279_1 <= ( pi0961 );
end Other__carpat__part116_behav;
