--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part69 is 
  Port (
    lo66: in std_logic;
    po18: inout std_logic
  );
end Cookbook__approx_fp_div__part69;

architecture Cookbook__approx_fp_div__part69_behav of Cookbook__approx_fp_div__part69 is
begin
    po18 <= ( lo66 );
end Cookbook__approx_fp_div__part69_behav;
