--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1151 is 
  Port (
    lo4520: in std_logic;
    n18089: inout std_logic
  );
end Other__sudoku_check__part1151;

architecture Other__sudoku_check__part1151_behav of Other__sudoku_check__part1151 is
begin
    n18089 <= ( lo4520 );
end Other__sudoku_check__part1151_behav;
