--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1306 is 
  Port (
    lo3026: in std_logic;
    n19626: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1306;

architecture Other__ucsb_152_tap_fir__part1306_behav of Other__ucsb_152_tap_fir__part1306 is
begin
    n19626 <= ( lo3026 );
end Other__ucsb_152_tap_fir__part1306_behav;
