--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part80 is 
  Port (
    lo0463: in std_logic;
    po135: inout std_logic
  );
end IWLS2005__mem_ctrl__part80;

architecture IWLS2005__mem_ctrl__part80_behav of IWLS2005__mem_ctrl__part80 is
begin
    po135 <= ( lo0463 );
end IWLS2005__mem_ctrl__part80_behav;
