--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part76 is 
  Port (
    lo0191: in std_logic;
    n3545: inout std_logic
  );
end Other__fp_operators__part76;

architecture Other__fp_operators__part76_behav of Other__fp_operators__part76 is
begin
    n3545 <= ( lo0191 );
end Other__fp_operators__part76_behav;
