--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part76 is 
  Port (
    lo0657: in std_logic;
    n4259: inout std_logic
  );
end ISCAS__s38417__part76;

architecture ISCAS__s38417__part76_behav of ISCAS__s38417__part76 is
begin
    n4259 <= ( not lo0657 );
end ISCAS__s38417__part76_behav;
