--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part49 is 
  Port (
    lo48: in std_logic;
    po48: inout std_logic
  );
end Other__idxlat10n_m12__part49;

architecture Other__idxlat10n_m12__part49_behav of Other__idxlat10n_m12__part49 is
begin
    po48 <= ( lo48 );
end Other__idxlat10n_m12__part49_behav;
