--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part115 is 
  Port (
    lo0223: in std_logic;
    n5561: inout std_logic
  );
end Other__ucsb_152_tap_fir__part115;

architecture Other__ucsb_152_tap_fir__part115_behav of Other__ucsb_152_tap_fir__part115 is
begin
    n5561 <= ( lo0223 );
end Other__ucsb_152_tap_fir__part115_behav;
