--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part734 is 
  Port (
    lo4457: in std_logic;
    n22460: inout std_logic
  );
end IWLS2005__des_perf__part734;

architecture IWLS2005__des_perf__part734_behav of IWLS2005__des_perf__part734 is
begin
    n22460 <= ( lo4457 );
end IWLS2005__des_perf__part734_behav;
