--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part449 is 
  Port (
    lo0805: in std_logic;
    n9484: inout std_logic
  );
end Other__carpat__part449;

architecture Other__carpat__part449_behav of Other__carpat__part449 is
begin
    n9484 <= ( lo0805 );
end Other__carpat__part449_behav;
