--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1865 is 
  Port (
    lo4192: in std_logic;
    n25546: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1865;

architecture Other__ucsb_152_tap_fir__part1865_behav of Other__ucsb_152_tap_fir__part1865 is
begin
    n25546 <= ( lo4192 );
end Other__ucsb_152_tap_fir__part1865_behav;
