--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part91 is 
  Port (
    lo185: in std_logic;
    po50: inout std_logic
  );
end Cookbook__gearbox_40_67__part91;

architecture Cookbook__gearbox_40_67__part91_behav of Cookbook__gearbox_40_67__part91 is
begin
    po50 <= ( lo185 );
end Cookbook__gearbox_40_67__part91_behav;
