--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part923 is 
  Port (
    lo0992: in std_logic;
    n5259: inout std_logic
  );
end Cookbook__fec_check__part923;

architecture Cookbook__fec_check__part923_behav of Cookbook__fec_check__part923 is
begin
    n5259 <= ( lo0992 );
end Cookbook__fec_check__part923_behav;
