--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1938 is 
  Port (
    lo2007: in std_logic;
    n10334: inout std_logic
  );
end Cookbook__fec_check__part1938;

architecture Cookbook__fec_check__part1938_behav of Cookbook__fec_check__part1938 is
begin
    n10334 <= ( lo2007 );
end Cookbook__fec_check__part1938_behav;
