--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part4 is 
  Port (
    pi105: in std_logic;
    n5296: inout std_logic
  );
end Other__mem__part4;

architecture Other__mem__part4_behav of Other__mem__part4 is
begin
    n5296 <= ( pi105 );
end Other__mem__part4_behav;
