--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3057 is 
  Port (
    lo8370: in std_logic;
    n42290_1: inout std_logic
  );
end IWLS2005__des_perf__part3057;

architecture IWLS2005__des_perf__part3057_behav of IWLS2005__des_perf__part3057 is
begin
    n42290_1 <= ( lo8370 );
end IWLS2005__des_perf__part3057_behav;
