--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part793 is 
  Port (
    lo4566: in std_logic;
    n23060: inout std_logic
  );
end IWLS2005__des_perf__part793;

architecture IWLS2005__des_perf__part793_behav of IWLS2005__des_perf__part793 is
begin
    n23060 <= ( lo4566 );
end IWLS2005__des_perf__part793_behav;
