--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1165 is 
  Port (
    lo5324: in std_logic;
    n26590_1: inout std_logic
  );
end IWLS2005__des_perf__part1165;

architecture IWLS2005__des_perf__part1165_behav of IWLS2005__des_perf__part1165 is
begin
    n26590_1 <= ( lo5324 );
end IWLS2005__des_perf__part1165_behav;
