--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1523 is 
  Port (
    lo1592: in std_logic;
    n8259: inout std_logic
  );
end Cookbook__fec_check__part1523;

architecture Cookbook__fec_check__part1523_behav of Cookbook__fec_check__part1523 is
begin
    n8259 <= ( lo1592 );
end Cookbook__fec_check__part1523_behav;
