--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part179 is 
  Port (
    pi0609: in std_logic;
    n44091: inout std_logic
  );
end Other__radar__part179;

architecture Other__radar__part179_behav of Other__radar__part179 is
begin
    n44091 <= ( pi0609 );
end Other__radar__part179_behav;
