--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1596 is 
  Port (
    lo8309: in std_logic;
    n46434_1: inout std_logic
  );
end Other__carpat__part1596;

architecture Other__carpat__part1596_behav of Other__carpat__part1596 is
begin
    n46434_1 <= ( lo8309 );
end Other__carpat__part1596_behav;
