--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part476 is 
  Port (
    lo3125: in std_logic;
    n9679: inout std_logic
  );
end Other__sudoku_check__part476;

architecture Other__sudoku_check__part476_behav of Other__sudoku_check__part476 is
begin
    n9679 <= ( lo3125 );
end Other__sudoku_check__part476_behav;
