--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part171 is 
  Port (
    lo2820: in std_logic;
    n6629: inout std_logic
  );
end Other__sudoku_check__part171;

architecture Other__sudoku_check__part171_behav of Other__sudoku_check__part171 is
begin
    n6629 <= ( lo2820 );
end Other__sudoku_check__part171_behav;
