--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part42 is 
  Port (
    lo156: in std_logic;
    po08: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part42;

architecture Cookbook__ycbcr_to_rgb__part42_behav of Cookbook__ycbcr_to_rgb__part42 is
begin
    po08 <= ( lo156 );
end Cookbook__ycbcr_to_rgb__part42_behav;
