--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1041 is 
  Port (
    lo5073: in std_logic;
    n25490: inout std_logic
  );
end IWLS2005__des_perf__part1041;

architecture IWLS2005__des_perf__part1041_behav of IWLS2005__des_perf__part1041 is
begin
    n25490 <= ( lo5073 );
end IWLS2005__des_perf__part1041_behav;
