--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part874 is 
  Port (
    lo4720: in std_logic;
    n23860: inout std_logic
  );
end IWLS2005__des_perf__part874;

architecture IWLS2005__des_perf__part874_behav of IWLS2005__des_perf__part874 is
begin
    n23860 <= ( lo4720 );
end IWLS2005__des_perf__part874_behav;
