--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part47 is 
  Port (
    lo046: in std_logic;
    n540: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part47;

architecture Cookbook__approx_fp_invsqrt__part47_behav of Cookbook__approx_fp_invsqrt__part47 is
begin
    n540 <= ( lo046 );
end Cookbook__approx_fp_invsqrt__part47_behav;
