--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part31 is 
  Port (
    lo0110: in std_logic;
    n5394_1: inout std_logic
  );
end IWLS93__s38417__part31;

architecture IWLS93__s38417__part31_behav of IWLS93__s38417__part31 is
begin
    n5394_1 <= ( lo0110 );
end IWLS93__s38417__part31_behav;
