--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part5 is 
  Port (
    pi0411: in std_logic;
    n42426: inout std_logic
  );
end Other__radar__part5;

architecture Other__radar__part5_behav of Other__radar__part5 is
begin
    n42426 <= ( pi0411 );
end Other__radar__part5_behav;
