--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part111 is 
  Port (
    lo0747: in std_logic;
    n5539_1: inout std_logic
  );
end IWLS93__s38417__part111;

architecture IWLS93__s38417__part111_behav of IWLS93__s38417__part111 is
begin
    n5539_1 <= ( lo0747 );
end IWLS93__s38417__part111_behav;
