--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part98 is 
  Port (
    lo224: in std_logic;
    po114: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part98;

architecture Cookbook__soft_ecc_ram_64bit__part98_behav of Cookbook__soft_ecc_ram_64bit__part98 is
begin
    po114 <= ( lo224 );
end Cookbook__soft_ecc_ram_64bit__part98_behav;
