--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part750 is 
  Port (
    lo4476: in std_logic;
    n22490: inout std_logic
  );
end IWLS2005__des_perf__part750;

architecture IWLS2005__des_perf__part750_behav of IWLS2005__des_perf__part750 is
begin
    n22490 <= ( lo4476 );
end IWLS2005__des_perf__part750_behav;
