--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part243 is 
  Port (
    lo2892: in std_logic;
    n7349: inout std_logic
  );
end Other__sudoku_check__part243;

architecture Other__sudoku_check__part243_behav of Other__sudoku_check__part243 is
begin
    n7349 <= ( lo2892 );
end Other__sudoku_check__part243_behav;
