--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part88 is 
  Port (
    lo0687: in std_logic;
    n3709: inout std_logic
  );
end ISCAS__s38417__part88;

architecture ISCAS__s38417__part88_behav of ISCAS__s38417__part88 is
begin
    n3709 <= ( lo0687 );
end ISCAS__s38417__part88_behav;
