--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part2 is 
  Port (
    pi04: in std_logic;
    n6894: inout std_logic
  );
end IWLS93__s38417__part2;

architecture IWLS93__s38417__part2_behav of IWLS93__s38417__part2 is
begin
    n6894 <= ( pi04 );
end IWLS93__s38417__part2_behav;
