--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part202 is 
  Port (
    lo188: in std_logic;
    po078: inout std_logic
  );
end Cookbook__lc_mult_signed__part202;

architecture Cookbook__lc_mult_signed__part202_behav of Cookbook__lc_mult_signed__part202 is
begin
    po078 <= ( lo188 );
end Cookbook__lc_mult_signed__part202_behav;
