--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part112 is 
  Port (
    lo206: in std_logic;
    po29: inout std_logic
  );
end Cookbook__gearbox_40_67__part112;

architecture Cookbook__gearbox_40_67__part112_behav of Cookbook__gearbox_40_67__part112 is
begin
    po29 <= ( lo206 );
end Cookbook__gearbox_40_67__part112_behav;
