--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part198 is 
  Port (
    lo03240: in std_logic;
    n34046: inout std_logic
  );
end Other__ray__part198;

architecture Other__ray__part198_behav of Other__ray__part198 is
begin
    n34046 <= ( lo03240 );
end Other__ray__part198_behav;
