--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2494 is 
  Port (
    lo7746: in std_logic;
    n38445_1: inout std_logic
  );
end IWLS2005__des_perf__part2494;

architecture IWLS2005__des_perf__part2494_behav of IWLS2005__des_perf__part2494 is
begin
    n38445_1 <= ( lo7746 );
end IWLS2005__des_perf__part2494_behav;
