--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part482 is 
  Port (
    lo05954: in std_logic;
    po1420,po1469,po1753,po1815: inout std_logic
  );
end Other__ray__part482;

architecture Other__ray__part482_behav of Other__ray__part482 is
begin
    po1420 <= ( lo05954 );
    po1469 <= ( lo05954 );
    po1753 <= ( lo05954 );
    po1815 <= ( lo05954 );
end Other__ray__part482_behav;
