--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part237 is 
  Port (
    lo1173: in std_logic;
    n7320_1: inout std_logic
  );
end Other__fp_operators__part237;

architecture Other__fp_operators__part237_behav of Other__fp_operators__part237 is
begin
    n7320_1 <= ( lo1173 );
end Other__fp_operators__part237_behav;
