--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part189 is 
  Port (
    lo03229: in std_logic;
    po1082: inout std_logic
  );
end Other__ray__part189;

architecture Other__ray__part189_behav of Other__ray__part189 is
begin
    po1082 <= ( lo03229 );
end Other__ray__part189_behav;
