--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part461 is 
  Port (
    lo4010: in std_logic;
    n20275: inout std_logic
  );
end IWLS2005__des_perf__part461;

architecture IWLS2005__des_perf__part461_behav of IWLS2005__des_perf__part461 is
begin
    n20275 <= ( lo4010 );
end IWLS2005__des_perf__part461_behav;
