--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1131 is 
  Port (
    lo4500: in std_logic;
    n17989: inout std_logic
  );
end Other__sudoku_check__part1131;

architecture Other__sudoku_check__part1131_behav of Other__sudoku_check__part1131 is
begin
    n17989 <= ( lo4500 );
end Other__sudoku_check__part1131_behav;
