--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part160 is 
  Port (
    lo146: in std_logic;
    po120: inout std_logic
  );
end Cookbook__lc_mult_signed__part160;

architecture Cookbook__lc_mult_signed__part160_behav of Cookbook__lc_mult_signed__part160 is
begin
    po120 <= ( lo146 );
end Cookbook__lc_mult_signed__part160_behav;
