--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1735 is 
  Port (
    lo8803: in std_logic;
    po246: inout std_logic
  );
end Other__carpat__part1735;

architecture Other__carpat__part1735_behav of Other__carpat__part1735 is
begin
    po246 <= ( lo8803 );
end Other__carpat__part1735_behav;
