--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part279 is 
  Port (
    lo0348: in std_logic;
    n2039: inout std_logic
  );
end Cookbook__fec_check__part279;

architecture Cookbook__fec_check__part279_behav of Cookbook__fec_check__part279 is
begin
    n2039 <= ( lo0348 );
end Cookbook__fec_check__part279_behav;
