--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2055 is 
  Port (
    lo2124: in std_logic;
    n10919: inout std_logic
  );
end Cookbook__fec_check__part2055;

architecture Cookbook__fec_check__part2055_behav of Cookbook__fec_check__part2055 is
begin
    n10919 <= ( lo2124 );
end Cookbook__fec_check__part2055_behav;
