--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1636 is 
  Port (
    lo1705: in std_logic;
    n8824: inout std_logic
  );
end Cookbook__fec_check__part1636;

architecture Cookbook__fec_check__part1636_behav of Cookbook__fec_check__part1636 is
begin
    n8824 <= ( lo1705 );
end Cookbook__fec_check__part1636_behav;
