--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1090 is 
  Port (
    lo7183: in std_logic;
    n38289_1: inout std_logic
  );
end Other__carpat__part1090;

architecture Other__carpat__part1090_behav of Other__carpat__part1090 is
begin
    n38289_1 <= ( lo7183 );
end Other__carpat__part1090_behav;
