--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part10 is 
  Port (
    lo09: in std_logic;
    po09: inout std_logic
  );
end Other__idxlat03n_m12__part10;

architecture Other__idxlat03n_m12__part10_behav of Other__idxlat03n_m12__part10 is
begin
    po09 <= ( lo09 );
end Other__idxlat03n_m12__part10_behav;
