--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2272 is 
  Port (
    lo7469: in std_logic;
    n37145_1: inout std_logic
  );
end IWLS2005__des_perf__part2272;

architecture IWLS2005__des_perf__part2272_behav of IWLS2005__des_perf__part2272 is
begin
    n37145_1 <= ( lo7469 );
end IWLS2005__des_perf__part2272_behav;
