--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part221 is 
  Port (
    lo1483: in std_logic;
    n40996_1: inout std_logic
  );
end Other__radar__part221;

architecture Other__radar__part221_behav of Other__radar__part221 is
begin
    n40996_1 <= ( lo1483 );
end Other__radar__part221_behav;
