--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part106 is 
  Port (
    lo0672: in std_logic;
    n3634: inout std_logic
  );
end LGSynth91__s38417__part106;

architecture LGSynth91__s38417__part106_behav of LGSynth91__s38417__part106 is
begin
    n3634 <= ( lo0672 );
end LGSynth91__s38417__part106_behav;
