--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1139 is 
  Port (
    lo4508: in std_logic;
    n18029: inout std_logic
  );
end Other__sudoku_check__part1139;

architecture Other__sudoku_check__part1139_behav of Other__sudoku_check__part1139 is
begin
    n18029 <= ( lo4508 );
end Other__sudoku_check__part1139_behav;
