--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part504 is 
  Port (
    lo3153: in std_logic;
    n9959: inout std_logic
  );
end Other__sudoku_check__part504;

architecture Other__sudoku_check__part504_behav of Other__sudoku_check__part504 is
begin
    n9959 <= ( lo3153 );
end Other__sudoku_check__part504_behav;
