--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part245 is 
  Port (
    lo0885: in std_logic;
    n5534: inout std_logic
  );
end Cookbook__ucrypt__part245;

architecture Cookbook__ucrypt__part245_behav of Cookbook__ucrypt__part245 is
begin
    n5534 <= ( lo0885 );
end Cookbook__ucrypt__part245_behav;
