--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1639 is 
  Port (
    lo8431: in std_logic;
    n47054_1: inout std_logic
  );
end Other__carpat__part1639;

architecture Other__carpat__part1639_behav of Other__carpat__part1639 is
begin
    n47054_1 <= ( lo8431 );
end Other__carpat__part1639_behav;
