--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1011 is 
  Port (
    lo4975: in std_logic;
    n24545: inout std_logic
  );
end IWLS2005__des_perf__part1011;

architecture IWLS2005__des_perf__part1011_behav of IWLS2005__des_perf__part1011 is
begin
    n24545 <= ( lo4975 );
end IWLS2005__des_perf__part1011_behav;
