--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1256 is 
  Port (
    lo4625: in std_logic;
    n18614: inout std_logic
  );
end Other__sudoku_check__part1256;

architecture Other__sudoku_check__part1256_behav of Other__sudoku_check__part1256 is
begin
    n18614 <= ( lo4625 );
end Other__sudoku_check__part1256_behav;
