--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part135 is 
  Port (
    lo0939: in std_logic;
    n4969_1: inout std_logic
  );
end LGSynth91__s38417__part135;

architecture LGSynth91__s38417__part135_behav of LGSynth91__s38417__part135 is
begin
    n4969_1 <= ( lo0939 );
end LGSynth91__s38417__part135_behav;
