--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part807 is 
  Port (
    lo6375: in std_logic;
    po535: inout std_logic
  );
end Other__carpat__part807;

architecture Other__carpat__part807_behav of Other__carpat__part807 is
begin
    po535 <= ( lo6375 );
end Other__carpat__part807_behav;
