--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2016 is 
  Port (
    lo2085: in std_logic;
    n10724: inout std_logic
  );
end Cookbook__fec_check__part2016;

architecture Cookbook__fec_check__part2016_behav of Cookbook__fec_check__part2016 is
begin
    n10724 <= ( lo2085 );
end Cookbook__fec_check__part2016_behav;
