--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1483 is 
  Port (
    lo1552: in std_logic;
    n8059: inout std_logic
  );
end Cookbook__fec_check__part1483;

architecture Cookbook__fec_check__part1483_behav of Cookbook__fec_check__part1483 is
begin
    n8059 <= ( lo1552 );
end Cookbook__fec_check__part1483_behav;
