--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1338 is 
  Port (
    lo4707: in std_logic;
    n19024: inout std_logic
  );
end Other__sudoku_check__part1338;

architecture Other__sudoku_check__part1338_behav of Other__sudoku_check__part1338 is
begin
    n19024 <= ( lo4707 );
end Other__sudoku_check__part1338_behav;
