--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1326 is 
  Port (
    lo3046: in std_logic;
    n19726: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1326;

architecture Other__ucsb_152_tap_fir__part1326_behav of Other__ucsb_152_tap_fir__part1326 is
begin
    n19726 <= ( lo3046 );
end Other__ucsb_152_tap_fir__part1326_behav;
