--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1159 is 
  Port (
    lo5318: in std_logic;
    n26470: inout std_logic
  );
end IWLS2005__des_perf__part1159;

architecture IWLS2005__des_perf__part1159_behav of IWLS2005__des_perf__part1159 is
begin
    n26470 <= ( lo5318 );
end IWLS2005__des_perf__part1159_behav;
