--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part370 is 
  Port (
    pi1736: in std_logic;
    n48314_1: inout std_logic
  );
end Other__carpat__part370;

architecture Other__carpat__part370_behav of Other__carpat__part370 is
begin
    n48314_1 <= ( pi1736 );
end Other__carpat__part370_behav;
