--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part79 is 
  Port (
    lo1723: in std_logic;
    n6596_1: inout std_logic
  );
end Other__mem__part79;

architecture Other__mem__part79_behav of Other__mem__part79 is
begin
    n6596_1 <= ( lo1723 );
end Other__mem__part79_behav;
