--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part885 is 
  Port (
    lo0954: in std_logic;
    n5069: inout std_logic
  );
end Cookbook__fec_check__part885;

architecture Cookbook__fec_check__part885_behav of Cookbook__fec_check__part885 is
begin
    n5069 <= ( lo0954 );
end Cookbook__fec_check__part885_behav;
