--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part780 is 
  Port (
    lo5742: in std_logic;
    n26499: inout std_logic
  );
end Other__carpat__part780;

architecture Other__carpat__part780_behav of Other__carpat__part780 is
begin
    n26499 <= ( lo5742 );
end Other__carpat__part780_behav;
