--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part292 is 
  Port (
    lo1067: in std_logic;
    n6594: inout std_logic
  );
end Cookbook__ucrypt__part292;

architecture Cookbook__ucrypt__part292_behav of Cookbook__ucrypt__part292 is
begin
    n6594 <= ( lo1067 );
end Cookbook__ucrypt__part292_behav;
