--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part468 is 
  Port (
    lo4017: in std_logic;
    n20440: inout std_logic
  );
end IWLS2005__des_perf__part468;

architecture IWLS2005__des_perf__part468_behav of IWLS2005__des_perf__part468 is
begin
    n20440 <= ( lo4017 );
end IWLS2005__des_perf__part468_behav;
