--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part303 is 
  Port (
    lo1078: in std_logic;
    n6649: inout std_logic
  );
end Cookbook__ucrypt__part303;

architecture Cookbook__ucrypt__part303_behav of Cookbook__ucrypt__part303 is
begin
    n6649 <= ( lo1078 );
end Cookbook__ucrypt__part303_behav;
