--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part525 is 
  Port (
    lo4108: in std_logic;
    n20745: inout std_logic
  );
end IWLS2005__des_perf__part525;

architecture IWLS2005__des_perf__part525_behav of IWLS2005__des_perf__part525 is
begin
    n20745 <= ( lo4108 );
end IWLS2005__des_perf__part525_behav;
