--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part856 is 
  Port (
    lo6485: in std_logic;
    n30804_1: inout std_logic
  );
end Other__carpat__part856;

architecture Other__carpat__part856_behav of Other__carpat__part856 is
begin
    n30804_1 <= ( lo6485 );
end Other__carpat__part856_behav;
