--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1579 is 
  Port (
    lo3578: in std_logic;
    n22476: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1579;

architecture Other__ucsb_152_tap_fir__part1579_behav of Other__ucsb_152_tap_fir__part1579 is
begin
    n22476 <= ( lo3578 );
end Other__ucsb_152_tap_fir__part1579_behav;
