--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part10 is 
  Port (
    pi14: in std_logic;
    n409: inout std_logic
  );
end ISCAS__s38417__part10;

architecture ISCAS__s38417__part10_behav of ISCAS__s38417__part10 is
begin
    n409 <= ( pi14 );
end ISCAS__s38417__part10_behav;
