--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part102 is 
  Port (
    lo184832: in std_logic;
    n923946: inout std_logic
  );
end IWLS2005__leon3__part102;

architecture IWLS2005__leon3__part102_behav of IWLS2005__leon3__part102 is
begin
    n923946 <= ( lo184832 );
end IWLS2005__leon3__part102_behav;
