--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part212 is 
  Port (
    lo0101: in std_logic;
    n690: inout std_logic
  );
end IWLS2005__des_perf__part212;

architecture IWLS2005__des_perf__part212_behav of IWLS2005__des_perf__part212 is
begin
    n690 <= ( not lo0101 );
end IWLS2005__des_perf__part212_behav;
