--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part510 is 
  Port (
    lo0579: in std_logic;
    n3194: inout std_logic
  );
end Cookbook__fec_check__part510;

architecture Cookbook__fec_check__part510_behav of Cookbook__fec_check__part510 is
begin
    n3194 <= ( lo0579 );
end Cookbook__fec_check__part510_behav;
