--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part33 is 
  Port (
    lo97668,lo97786: in std_logic;
    n489065_1,n488355_1,n488895_1: inout std_logic
  );
end IWLS2005__netcard__part33;

architecture IWLS2005__netcard__part33_behav of IWLS2005__netcard__part33 is
begin
    n489065_1 <= ( lo97668 );
    n488355_1 <= ( not lo97786 and lo97668 );
    n488895_1 <= ( lo97668 );
end IWLS2005__netcard__part33_behav;
