--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part14 is 
  Port (
    lo13: in std_logic;
    po13: inout std_logic
  );
end Other__idxlat03n_m12__part14;

architecture Other__idxlat03n_m12__part14_behav of Other__idxlat03n_m12__part14 is
begin
    po13 <= ( lo13 );
end Other__idxlat03n_m12__part14_behav;
