--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part909 is 
  Port (
    lo0978: in std_logic;
    n5189: inout std_logic
  );
end Cookbook__fec_check__part909;

architecture Cookbook__fec_check__part909_behav of Cookbook__fec_check__part909 is
begin
    n5189 <= ( lo0978 );
end Cookbook__fec_check__part909_behav;
