--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part42 is 
  Port (
    lo15740: in std_logic;
    po80: inout std_logic
  );
end IWLS2005__vga_lcd__part42;

architecture IWLS2005__vga_lcd__part42_behav of IWLS2005__vga_lcd__part42 is
begin
    po80 <= ( lo15740 );
end IWLS2005__vga_lcd__part42_behav;
