--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part1 is 
  Port (
    lo158: in std_logic;
    po013: inout std_logic
  );
end IWLS2005__aes_core__part1;

architecture IWLS2005__aes_core__part1_behav of IWLS2005__aes_core__part1 is
begin
    po013 <= ( lo158 );
end IWLS2005__aes_core__part1_behav;
