--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part29 is 
  Port (
    lo015: in std_logic;
    po014: inout std_logic
  );
end Cookbook__lc_mult_signed__part29;

architecture Cookbook__lc_mult_signed__part29_behav of Cookbook__lc_mult_signed__part29 is
begin
    po014 <= ( lo015 );
end Cookbook__lc_mult_signed__part29_behav;
