--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part241 is 
  Port (
    lo0856: in std_logic;
    n5389: inout std_logic
  );
end Cookbook__ucrypt__part241;

architecture Cookbook__ucrypt__part241_behav of Cookbook__ucrypt__part241 is
begin
    n5389 <= ( lo0856 );
end Cookbook__ucrypt__part241_behav;
