--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1571 is 
  Port (
    lo5893,lo5894,lo5895,lo5896: in std_logic;
    n27989_1,n28299_1,n28304_1,n28309_1,n28314_1,n28319_1,n28324_1,n28329_1,n28334_1: inout std_logic
  );
end Other__sudoku_check__part1571;

architecture Other__sudoku_check__part1571_behav of Other__sudoku_check__part1571 is
begin
    n27989_1 <= ( lo5893 and not lo5894 and not lo5895 and not lo5896 );
    n28299_1 <= ( lo5893 and not lo5894 and not lo5895 and lo5896 );
    n28304_1 <= ( not lo5893 and not lo5894 and not lo5895 and lo5896 );
    n28309_1 <= ( lo5893 and lo5894 and lo5895 and not lo5896 );
    n28314_1 <= ( not lo5893 and lo5894 and lo5895 and not lo5896 );
    n28319_1 <= ( lo5893 and not lo5894 and lo5895 and not lo5896 );
    n28324_1 <= ( not lo5893 and not lo5894 and lo5895 and not lo5896 );
    n28329_1 <= ( lo5893 and lo5894 and not lo5895 and not lo5896 );
    n28334_1 <= ( not lo5893 and lo5894 and not lo5895 and not lo5896 );
end Other__sudoku_check__part1571_behav;
