--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1775 is 
  Port (
    lo4013: in std_logic;
    n24576: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1775;

architecture Other__ucsb_152_tap_fir__part1775_behav of Other__ucsb_152_tap_fir__part1775 is
begin
    n24576 <= ( lo4013 );
end Other__ucsb_152_tap_fir__part1775_behav;
