--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part236 is 
  Port (
    lo1172: in std_logic;
    n7315_1: inout std_logic
  );
end Other__fp_operators__part236;

architecture Other__fp_operators__part236_behav of Other__fp_operators__part236 is
begin
    n7315_1 <= ( lo1172 );
end Other__fp_operators__part236_behav;
