--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part28 is 
  Port (
    lo27: in std_logic;
    po27: inout std_logic
  );
end Other__idxlat00n_m12__part28;

architecture Other__idxlat00n_m12__part28_behav of Other__idxlat00n_m12__part28 is
begin
    po27 <= ( lo27 );
end Other__idxlat00n_m12__part28_behav;
