--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1041 is 
  Port (
    lo1110: in std_logic;
    n5849: inout std_logic
  );
end Cookbook__fec_check__part1041;

architecture Cookbook__fec_check__part1041_behav of Cookbook__fec_check__part1041 is
begin
    n5849 <= ( lo1110 );
end Cookbook__fec_check__part1041_behav;
