--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part34 is 
  Port (
    lo033: in std_logic;
    n475: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part34;

architecture Cookbook__approx_fp_invsqrt__part34_behav of Cookbook__approx_fp_invsqrt__part34 is
begin
    n475 <= ( lo033 );
end Cookbook__approx_fp_invsqrt__part34_behav;
