--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part660 is 
  Port (
    lo0729: in std_logic;
    n3944: inout std_logic
  );
end Cookbook__fec_check__part660;

architecture Cookbook__fec_check__part660_behav of Cookbook__fec_check__part660 is
begin
    n3944 <= ( lo0729 );
end Cookbook__fec_check__part660_behav;
