--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1692 is 
  Port (
    lo3842: in std_logic;
    n23791: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1692;

architecture Other__ucsb_152_tap_fir__part1692_behav of Other__ucsb_152_tap_fir__part1692 is
begin
    n23791 <= ( lo3842 );
end Other__ucsb_152_tap_fir__part1692_behav;
