--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part396 is 
  Port (
    lo0010: in std_logic;
    po010: inout std_logic
  );
end Other__carpat__part396;

architecture Other__carpat__part396_behav of Other__carpat__part396 is
begin
    po010 <= ( lo0010 );
end Other__carpat__part396_behav;
