--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2892 is 
  Port (
    lo8205: in std_logic;
    n41595_1: inout std_logic
  );
end IWLS2005__des_perf__part2892;

architecture IWLS2005__des_perf__part2892_behav of IWLS2005__des_perf__part2892 is
begin
    n41595_1 <= ( lo8205 );
end IWLS2005__des_perf__part2892_behav;
