--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part707 is 
  Port (
    lo5231: in std_logic;
    n25159: inout std_logic
  );
end Other__carpat__part707;

architecture Other__carpat__part707_behav of Other__carpat__part707 is
begin
    n25159 <= ( lo5231 );
end Other__carpat__part707_behav;
