--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part8 is 
  Port (
    pi08: in std_logic;
    n746837: inout std_logic
  );
end IWLS2005__leon2__part8;

architecture IWLS2005__leon2__part8_behav of IWLS2005__leon2__part8 is
begin
    n746837 <= ( pi08 );
end IWLS2005__leon2__part8_behav;
