--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part284 is 
  Port (
    lo1407: in std_logic;
    n9985_1: inout std_logic
  );
end Other__fp_operators__part284;

architecture Other__fp_operators__part284_behav of Other__fp_operators__part284 is
begin
    n9985_1 <= ( lo1407 );
end Other__fp_operators__part284_behav;
