--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part77 is 
  Port (
    lo269: in std_logic;
    n1643: inout std_logic
  );
end ISCAS__s13207__part77;

architecture ISCAS__s13207__part77_behav of ISCAS__s13207__part77 is
begin
    n1643 <= ( lo269 );
end ISCAS__s13207__part77_behav;
