--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part28 is 
  Port (
    lo066: in std_logic;
    po04: inout std_logic
  );
end Cookbook__fec_gen__part28;

architecture Cookbook__fec_gen__part28_behav of Cookbook__fec_gen__part28 is
begin
    po04 <= ( lo066 );
end Cookbook__fec_gen__part28_behav;
