--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part7 is 
  Port (
    pi099: in std_logic;
    n9114_1: inout std_logic
  );
end IWLS2005__usb_funct__part7;

architecture IWLS2005__usb_funct__part7_behav of IWLS2005__usb_funct__part7 is
begin
    n9114_1 <= ( pi099 );
end IWLS2005__usb_funct__part7_behav;
