--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part92 is 
  Port (
    lo0661: in std_logic;
    po010: inout std_logic
  );
end IWLS2005__mem_ctrl__part92;

architecture IWLS2005__mem_ctrl__part92_behav of IWLS2005__mem_ctrl__part92 is
begin
    po010 <= ( lo0661 );
end IWLS2005__mem_ctrl__part92_behav;
