--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part233 is 
  Port (
    lo1169: in std_logic;
    n7300_1: inout std_logic
  );
end Other__fp_operators__part233;

architecture Other__fp_operators__part233_behav of Other__fp_operators__part233 is
begin
    n7300_1 <= ( lo1169 );
end Other__fp_operators__part233_behav;
