--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part154 is 
  Port (
    lo1297: in std_logic;
    po017,n6779,n6759_1: inout std_logic
  );
end ISCAS__s38417__part154;

architecture ISCAS__s38417__part154_behav of ISCAS__s38417__part154 is
begin
    po017 <= ( lo1297 );
    n6779 <= ( lo1297 );
    n6759_1 <= ( lo1297 );
end ISCAS__s38417__part154_behav;
