--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part23 is 
  Port (
    lo0021: in std_logic;
    po0025: inout std_logic
  );
end Other__ether__part23;

architecture Other__ether__part23_behav of Other__ether__part23 is
begin
    po0025 <= ( lo0021 );
end Other__ether__part23_behav;
