--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s953__part20 is 
  Port (
    lo25: in std_logic;
    po07: inout std_logic
  );
end IWLS93__s953__part20;

architecture IWLS93__s953__part20_behav of IWLS93__s953__part20 is
begin
    po07 <= ( lo25 );
end IWLS93__s953__part20_behav;
