--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part29 is 
  Port (
    pi0340: in std_logic;
    n19669: inout std_logic
  );
end Other__carpat__part29;

architecture Other__carpat__part29_behav of Other__carpat__part29 is
begin
    n19669 <= ( pi0340 );
end Other__carpat__part29_behav;
