--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part507 is 
  Port (
    lo1842: in std_logic;
    n10469_1: inout std_logic
  );
end Cookbook__ucrypt__part507;

architecture Cookbook__ucrypt__part507_behav of Cookbook__ucrypt__part507 is
begin
    n10469_1 <= ( lo1842 );
end Cookbook__ucrypt__part507_behav;
