--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3335 is 
  Port (
    lo8743: in std_logic;
    n43620_1: inout std_logic
  );
end IWLS2005__des_perf__part3335;

architecture IWLS2005__des_perf__part3335_behav of IWLS2005__des_perf__part3335 is
begin
    n43620_1 <= ( lo8743 );
end IWLS2005__des_perf__part3335_behav;
