--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part49 is 
  Port (
    lo46: in std_logic;
    n486: inout std_logic
  );
end Cookbook__approx_fp_div__part49;

architecture Cookbook__approx_fp_div__part49_behav of Cookbook__approx_fp_div__part49 is
begin
    n486 <= ( lo46 );
end Cookbook__approx_fp_div__part49_behav;
