--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1699 is 
  Port (
    lo1768: in std_logic;
    n9139: inout std_logic
  );
end Cookbook__fec_check__part1699;

architecture Cookbook__fec_check__part1699_behav of Cookbook__fec_check__part1699 is
begin
    n9139 <= ( lo1768 );
end Cookbook__fec_check__part1699_behav;
