--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part311 is 
  Port (
    pi1609: in std_logic;
    n47359_1: inout std_logic
  );
end Other__carpat__part311;

architecture Other__carpat__part311_behav of Other__carpat__part311 is
begin
    n47359_1 <= ( pi1609 );
end Other__carpat__part311_behav;
