--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s400__part4 is 
  Port (
    lo05: in std_logic;
    po5: inout std_logic
  );
end LGSynth91__s400__part4;

architecture LGSynth91__s400__part4_behav of LGSynth91__s400__part4 is
begin
    po5 <= ( lo05 );
end LGSynth91__s400__part4_behav;
