--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part244 is 
  Port (
    lo416: in std_logic;
    n1412: inout std_logic
  );
end Other__fpu__part244;

architecture Other__fpu__part244_behav of Other__fpu__part244 is
begin
    n1412 <= ( lo416 );
end Other__fpu__part244_behav;
