--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part520 is 
  Port (
    lo3259: in std_logic;
    n15359: inout std_logic
  );
end Other__carpat__part520;

architecture Other__carpat__part520_behav of Other__carpat__part520 is
begin
    n15359 <= ( lo3259 );
end Other__carpat__part520_behav;
