--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part967 is 
  Port (
    lo4336: in std_logic;
    n17169: inout std_logic
  );
end Other__sudoku_check__part967;

architecture Other__sudoku_check__part967_behav of Other__sudoku_check__part967 is
begin
    n17169 <= ( lo4336 );
end Other__sudoku_check__part967_behav;
