--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part53 is 
  Port (
    lo52: in std_logic;
    po52: inout std_logic
  );
end Other__idxlat01n_m12__part53;

architecture Other__idxlat01n_m12__part53_behav of Other__idxlat01n_m12__part53 is
begin
    po52 <= ( lo52 );
end Other__idxlat01n_m12__part53_behav;
