--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part422 is 
  Port (
    lo3071: in std_logic;
    n9139: inout std_logic
  );
end Other__sudoku_check__part422;

architecture Other__sudoku_check__part422_behav of Other__sudoku_check__part422 is
begin
    n9139 <= ( lo3071 );
end Other__sudoku_check__part422_behav;
