--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part65 is 
  Port (
    lo64: in std_logic;
    po64: inout std_logic
  );
end Other__idxlat03n_m12__part65;

architecture Other__idxlat03n_m12__part65_behav of Other__idxlat03n_m12__part65 is
begin
    po64 <= ( lo64 );
end Other__idxlat03n_m12__part65_behav;
