--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s15850__part3 is 
  Port (
    lo034: in std_logic;
    n345: inout std_logic
  );
end ISCAS__s15850__part3;

architecture ISCAS__s15850__part3_behav of ISCAS__s15850__part3 is
begin
    n345 <= ( lo034 );
end ISCAS__s15850__part3_behav;
