--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part161 is 
  Port (
    lo147: in std_logic;
    po119: inout std_logic
  );
end Cookbook__lc_mult_signed__part161;

architecture Cookbook__lc_mult_signed__part161_behav of Cookbook__lc_mult_signed__part161 is
begin
    po119 <= ( lo147 );
end Cookbook__lc_mult_signed__part161_behav;
