--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1670 is 
  Port (
    lo3790: in std_logic;
    n23526: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1670;

architecture Other__ucsb_152_tap_fir__part1670_behav of Other__ucsb_152_tap_fir__part1670 is
begin
    n23526 <= ( lo3790 );
end Other__ucsb_152_tap_fir__part1670_behav;
