--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part178 is 
  Port (
    lo0247: in std_logic;
    n1534: inout std_logic
  );
end Cookbook__fec_check__part178;

architecture Cookbook__fec_check__part178_behav of Cookbook__fec_check__part178 is
begin
    n1534 <= ( lo0247 );
end Cookbook__fec_check__part178_behav;
