--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part103 is 
  Port (
    lo01330: in std_logic;
    po2778,po2874,po2970,po3174,po3222,po3270,n20876: inout std_logic
  );
end Other__ray__part103;

architecture Other__ray__part103_behav of Other__ray__part103 is
begin
    po2778 <= ( lo01330 );
    po2874 <= ( lo01330 );
    po2970 <= ( lo01330 );
    po3174 <= ( lo01330 );
    po3222 <= ( lo01330 );
    po3270 <= ( lo01330 );
    n20876 <= ( lo01330 );
end Other__ray__part103_behav;
