--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1661 is 
  Port (
    lo8606: in std_logic;
    n48529_1: inout std_logic
  );
end Other__carpat__part1661;

architecture Other__carpat__part1661_behav of Other__carpat__part1661 is
begin
    n48529_1 <= ( lo8606 );
end Other__carpat__part1661_behav;
