--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1296 is 
  Port (
    lo1365: in std_logic;
    n7124: inout std_logic
  );
end Cookbook__fec_check__part1296;

architecture Cookbook__fec_check__part1296_behav of Cookbook__fec_check__part1296 is
begin
    n7124 <= ( lo1365 );
end Cookbook__fec_check__part1296_behav;
