--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part823 is 
  Port (
    lo6452: in std_logic;
    n30514: inout std_logic
  );
end Other__carpat__part823;

architecture Other__carpat__part823_behav of Other__carpat__part823 is
begin
    n30514 <= ( lo6452 );
end Other__carpat__part823_behav;
