--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part159 is 
  Port (
    lo01390: in std_logic;
    po2722,po2818,po2914,po5894,po5942,po5990,n21306: inout std_logic
  );
end Other__ray__part159;

architecture Other__ray__part159_behav of Other__ray__part159 is
begin
    po2722 <= ( lo01390 );
    po2818 <= ( lo01390 );
    po2914 <= ( lo01390 );
    po5894 <= ( lo01390 );
    po5942 <= ( lo01390 );
    po5990 <= ( lo01390 );
    n21306 <= ( lo01390 );
end Other__ray__part159_behav;
