--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1485 is 
  Port (
    lo8116: in std_logic;
    n44629_1: inout std_logic
  );
end Other__carpat__part1485;

architecture Other__carpat__part1485_behav of Other__carpat__part1485 is
begin
    n44629_1 <= ( lo8116 );
end Other__carpat__part1485_behav;
