--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi67,pi68,pi69,pi70,pi71,pi72,pi73: in std_logic;
    po37: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po37 <= ( pi67 and pi68 and pi71 and not pi72 and not pi73 )
      or ( pi67 and pi69 and pi71 and not pi72 and not pi73 )
      or ( pi67 and not pi68 and not pi69 and pi70 and not pi72 and not pi73 );
end top_behav;
