--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part63 is 
  Port (
    lo126: in std_logic;
    po010: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part63;

architecture Cookbook__soft_ecc_ram_64bit__part63_behav of Cookbook__soft_ecc_ram_64bit__part63 is
begin
    po010 <= ( lo126 );
end Cookbook__soft_ecc_ram_64bit__part63_behav;
