--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part888 is 
  Port (
    lo4257: in std_logic;
    n16774: inout std_logic
  );
end Other__sudoku_check__part888;

architecture Other__sudoku_check__part888_behav of Other__sudoku_check__part888 is
begin
    n16774 <= ( lo4257 );
end Other__sudoku_check__part888_behav;
