--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part140 is 
  Port (
    lo0209: in std_logic;
    n1344: inout std_logic
  );
end Cookbook__fec_check__part140;

architecture Cookbook__fec_check__part140_behav of Cookbook__fec_check__part140 is
begin
    n1344 <= ( lo0209 );
end Cookbook__fec_check__part140_behav;
