--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1840 is 
  Port (
    lo1909: in std_logic;
    n9844: inout std_logic
  );
end Cookbook__fec_check__part1840;

architecture Cookbook__fec_check__part1840_behav of Cookbook__fec_check__part1840 is
begin
    n9844 <= ( lo1909 );
end Cookbook__fec_check__part1840_behav;
