--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part949 is 
  Port (
    lo6794: in std_logic;
    n34309_1: inout std_logic
  );
end Other__carpat__part949;

architecture Other__carpat__part949_behav of Other__carpat__part949 is
begin
    n34309_1 <= ( lo6794 );
end Other__carpat__part949_behav;
