--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part55 is 
  Port (
    lo162: in std_logic;
    n1108: inout std_logic
  );
end ISCAS__s13207__part55;

architecture ISCAS__s13207__part55_behav of ISCAS__s13207__part55 is
begin
    n1108 <= ( lo162 );
end ISCAS__s13207__part55_behav;
