--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part155 is 
  Port (
    lo1348: in std_logic;
    n7014_1: inout std_logic
  );
end ISCAS__s38417__part155;

architecture ISCAS__s38417__part155_behav of ISCAS__s38417__part155 is
begin
    n7014_1 <= ( lo1348 );
end ISCAS__s38417__part155_behav;
