--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2685 is 
  Port (
    lo7998: in std_logic;
    n39825_1: inout std_logic
  );
end IWLS2005__des_perf__part2685;

architecture IWLS2005__des_perf__part2685_behav of IWLS2005__des_perf__part2685 is
begin
    n39825_1 <= ( lo7998 );
end IWLS2005__des_perf__part2685_behav;
