--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part30 is 
  Port (
    lo0098: in std_logic;
    po106: inout std_logic
  );
end Other__mem__part30;

architecture Other__mem__part30_behav of Other__mem__part30 is
begin
    po106 <= ( lo0098 );
end Other__mem__part30_behav;
