--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part71 is 
  Port (
    lo0592: in std_logic;
    n3234: inout std_logic
  );
end LGSynth91__s38417__part71;

architecture LGSynth91__s38417__part71_behav of LGSynth91__s38417__part71 is
begin
    n3234 <= ( lo0592 );
end LGSynth91__s38417__part71_behav;
