--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1354 is 
  Port (
    lo7804: in std_logic;
    n43899_1: inout std_logic
  );
end Other__carpat__part1354;

architecture Other__carpat__part1354_behav of Other__carpat__part1354 is
begin
    n43899_1 <= ( lo7804 );
end Other__carpat__part1354_behav;
