--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part210 is 
  Port (
    lo196: in std_logic;
    po070: inout std_logic
  );
end Cookbook__lc_mult_signed__part210;

architecture Cookbook__lc_mult_signed__part210_behav of Cookbook__lc_mult_signed__part210 is
begin
    po070 <= ( lo196 );
end Cookbook__lc_mult_signed__part210_behav;
