--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1449 is 
  Port (
    lo1518: in std_logic;
    n7889: inout std_logic
  );
end Cookbook__fec_check__part1449;

architecture Cookbook__fec_check__part1449_behav of Cookbook__fec_check__part1449 is
begin
    n7889 <= ( lo1518 );
end Cookbook__fec_check__part1449_behav;
