--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1665 is 
  Port (
    lo8610: in std_logic;
    n48549_1: inout std_logic
  );
end Other__carpat__part1665;

architecture Other__carpat__part1665_behav of Other__carpat__part1665 is
begin
    n48549_1 <= ( lo8610 );
end Other__carpat__part1665_behav;
