--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1706 is 
  Port (
    lo1775: in std_logic;
    n9174: inout std_logic
  );
end Cookbook__fec_check__part1706;

architecture Cookbook__fec_check__part1706_behav of Cookbook__fec_check__part1706 is
begin
    n9174 <= ( lo1775 );
end Cookbook__fec_check__part1706_behav;
