--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part748 is 
  Port (
    lo3397: in std_logic;
    n12399: inout std_logic
  );
end Other__sudoku_check__part748;

architecture Other__sudoku_check__part748_behav of Other__sudoku_check__part748 is
begin
    n12399 <= ( lo3397 );
end Other__sudoku_check__part748_behav;
