--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1010 is 
  Port (
    lo1079: in std_logic;
    n5694: inout std_logic
  );
end Cookbook__fec_check__part1010;

architecture Cookbook__fec_check__part1010_behav of Cookbook__fec_check__part1010 is
begin
    n5694 <= ( lo1079 );
end Cookbook__fec_check__part1010_behav;
