--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part486 is 
  Port (
    lo1800: in std_logic;
    n10109_1: inout std_logic
  );
end Cookbook__ucrypt__part486;

architecture Cookbook__ucrypt__part486_behav of Cookbook__ucrypt__part486 is
begin
    n10109_1 <= ( lo1800 );
end Cookbook__ucrypt__part486_behav;
