--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part15 is 
  Port (
    lo0474: in std_logic;
    n3384: inout std_logic
  );
end Other__sudoku_check__part15;

architecture Other__sudoku_check__part15_behav of Other__sudoku_check__part15 is
begin
    n3384 <= ( lo0474 );
end Other__sudoku_check__part15_behav;
