--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1151 is 
  Port (
    lo1220: in std_logic;
    n6399: inout std_logic
  );
end Cookbook__fec_check__part1151;

architecture Cookbook__fec_check__part1151_behav of Cookbook__fec_check__part1151 is
begin
    n6399 <= ( lo1220 );
end Cookbook__fec_check__part1151_behav;
