--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part227 is 
  Port (
    lo0296: in std_logic;
    n1779: inout std_logic
  );
end Cookbook__fec_check__part227;

architecture Cookbook__fec_check__part227_behav of Cookbook__fec_check__part227 is
begin
    n1779 <= ( lo0296 );
end Cookbook__fec_check__part227_behav;
