--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part752 is 
  Port (
    lo5486: in std_logic;
    n25879: inout std_logic
  );
end Other__carpat__part752;

architecture Other__carpat__part752_behav of Other__carpat__part752 is
begin
    n25879 <= ( lo5486 );
end Other__carpat__part752_behav;
