--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1608 is 
  Port (
    lo6277: in std_logic;
    n31335_1: inout std_logic
  );
end IWLS2005__des_perf__part1608;

architecture IWLS2005__des_perf__part1608_behav of IWLS2005__des_perf__part1608 is
begin
    n31335_1 <= ( lo6277 );
end IWLS2005__des_perf__part1608_behav;
