--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part744 is 
  Port (
    lo06424: in std_logic;
    n48216: inout std_logic
  );
end Other__ray__part744;

architecture Other__ray__part744_behav of Other__ray__part744 is
begin
    n48216 <= ( lo06424 );
end Other__ray__part744_behav;
