--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part164 is 
  Port (
    lo0044: in std_logic;
    po44: inout std_logic
  );
end Other__desperf__part164;

architecture Other__desperf__part164_behav of Other__desperf__part164 is
begin
    po44 <= ( lo0044 );
end Other__desperf__part164_behav;
