--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part228 is 
  Port (
    lo03289: in std_logic;
    n34151: inout std_logic
  );
end Other__ray__part228;

architecture Other__ray__part228_behav of Other__ray__part228 is
begin
    n34151 <= ( lo03289 );
end Other__ray__part228_behav;
