--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part646 is 
  Port (
    lo5059: in std_logic;
    n22504: inout std_logic
  );
end Other__carpat__part646;

architecture Other__carpat__part646_behav of Other__carpat__part646 is
begin
    n22504 <= ( lo5059 );
end Other__carpat__part646_behav;
