--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part73 is 
  Port (
    lo1210: in std_logic;
    n5406: inout std_logic
  );
end Other__mem__part73;

architecture Other__mem__part73_behav of Other__mem__part73 is
begin
    n5406 <= ( lo1210 );
end Other__mem__part73_behav;
