--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1295 is 
  Port (
    lo1364: in std_logic;
    n7119: inout std_logic
  );
end Cookbook__fec_check__part1295;

architecture Cookbook__fec_check__part1295_behav of Cookbook__fec_check__part1295 is
begin
    n7119 <= ( lo1364 );
end Cookbook__fec_check__part1295_behav;
