--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part74 is 
  Port (
    pi074: in std_logic;
    n10019_1: inout std_logic
  );
end Other__desperf__part74;

architecture Other__desperf__part74_behav of Other__desperf__part74 is
begin
    n10019_1 <= ( pi074 );
end Other__desperf__part74_behav;
