--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part185 is 
  Port (
    lo0441: in std_logic;
    n6666: inout std_logic
  );
end Other__ucsb_152_tap_fir__part185;

architecture Other__ucsb_152_tap_fir__part185_behav of Other__ucsb_152_tap_fir__part185 is
begin
    n6666 <= ( lo0441 );
end Other__ucsb_152_tap_fir__part185_behav;
