--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part434 is 
  Port (
    lo0542: in std_logic;
    n7189: inout std_logic
  );
end Other__carpat__part434;

architecture Other__carpat__part434_behav of Other__carpat__part434 is
begin
    n7189 <= ( lo0542 );
end Other__carpat__part434_behav;
