--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1750 is 
  Port (
    lo1819: in std_logic;
    n9394: inout std_logic
  );
end Cookbook__fec_check__part1750;

architecture Cookbook__fec_check__part1750_behav of Cookbook__fec_check__part1750 is
begin
    n9394 <= ( lo1819 );
end Cookbook__fec_check__part1750_behav;
