--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part582 is 
  Port (
    lo3587: in std_logic;
    n16949: inout std_logic
  );
end Other__carpat__part582;

architecture Other__carpat__part582_behav of Other__carpat__part582 is
begin
    n16949 <= ( lo3587 );
end Other__carpat__part582_behav;
