--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part490 is 
  Port (
    lo1825: in std_logic;
    n10384_1: inout std_logic
  );
end Cookbook__ucrypt__part490;

architecture Cookbook__ucrypt__part490_behav of Cookbook__ucrypt__part490 is
begin
    n10384_1 <= ( lo1825 );
end Cookbook__ucrypt__part490_behav;
