--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part141 is 
  Port (
    lo2790: in std_logic;
    n6329: inout std_logic
  );
end Other__sudoku_check__part141;

architecture Other__sudoku_check__part141_behav of Other__sudoku_check__part141 is
begin
    n6329 <= ( lo2790 );
end Other__sudoku_check__part141_behav;
