--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part101 is 
  Port (
    pi156: in std_logic;
    n44185_1: inout std_logic
  );
end IWLS2005__des_perf__part101;

architecture IWLS2005__des_perf__part101_behav of IWLS2005__des_perf__part101 is
begin
    n44185_1 <= ( pi156 );
end IWLS2005__des_perf__part101_behav;
