--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2128 is 
  Port (
    lo2197: in std_logic;
    n11284: inout std_logic
  );
end Cookbook__fec_check__part2128;

architecture Cookbook__fec_check__part2128_behav of Cookbook__fec_check__part2128 is
begin
    n11284 <= ( lo2197 );
end Cookbook__fec_check__part2128_behav;
