--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part769 is 
  Port (
    lo3802: in std_logic;
    n12879: inout std_logic
  );
end Other__sudoku_check__part769;

architecture Other__sudoku_check__part769_behav of Other__sudoku_check__part769 is
begin
    n12879 <= ( lo3802 );
end Other__sudoku_check__part769_behav;
