--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part48 is 
  Port (
    lo0808: in std_logic;
    n5553_1: inout std_logic
  );
end Other__ether__part48;

architecture Other__ether__part48_behav of Other__ether__part48 is
begin
    n5553_1 <= ( lo0808 );
end Other__ether__part48_behav;
