--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part108 is 
  Port (
    lo3258: in std_logic;
    n16759: inout std_logic
  );
end IWLS2005__pci_bridge32__part108;

architecture IWLS2005__pci_bridge32__part108_behav of IWLS2005__pci_bridge32__part108 is
begin
    n16759 <= ( lo3258 );
end IWLS2005__pci_bridge32__part108_behav;
