--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part443 is 
  Port (
    lo0551: in std_logic;
    n7279: inout std_logic
  );
end Other__carpat__part443;

architecture Other__carpat__part443_behav of Other__carpat__part443 is
begin
    n7279 <= ( lo0551 );
end Other__carpat__part443_behav;
