--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add__part12 is 
  Port (
    pi21: in std_logic;
    n211: inout std_logic
  );
end Cookbook__pipeline_add__part12;

architecture Cookbook__pipeline_add__part12_behav of Cookbook__pipeline_add__part12 is
begin
    n211 <= ( pi21 );
end Cookbook__pipeline_add__part12_behav;
