--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part138 is 
  Port (
    lo021: in std_logic;
    po021: inout std_logic
  );
end Other__fpu__part138;

architecture Other__fpu__part138_behav of Other__fpu__part138 is
begin
    po021 <= ( lo021 );
end Other__fpu__part138_behav;
