--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part3 is 
  Port (
    lo00091: in std_logic;
    po010: inout std_logic
  );
end IWLS2005__ethernet__part3;

architecture IWLS2005__ethernet__part3_behav of IWLS2005__ethernet__part3 is
begin
    po010 <= ( lo00091 );
end IWLS2005__ethernet__part3_behav;
