--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part40 is 
  Port (
    lo251: in std_logic;
    po111: inout std_logic
  );
end IWLS2005__aes_core__part40;

architecture IWLS2005__aes_core__part40_behav of IWLS2005__aes_core__part40 is
begin
    po111 <= ( lo251 );
end IWLS2005__aes_core__part40_behav;
