--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1202 is 
  Port (
    lo7449: in std_logic;
    n41424_1: inout std_logic
  );
end Other__carpat__part1202;

architecture Other__carpat__part1202_behav of Other__carpat__part1202 is
begin
    n41424_1 <= ( lo7449 );
end Other__carpat__part1202_behav;
