--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1957 is 
  Port (
    lo2026: in std_logic;
    n10429: inout std_logic
  );
end Cookbook__fec_check__part1957;

architecture Cookbook__fec_check__part1957_behav of Cookbook__fec_check__part1957 is
begin
    n10429 <= ( lo2026 );
end Cookbook__fec_check__part1957_behav;
