--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2198 is 
  Port (
    lo2267: in std_logic;
    n11634: inout std_logic
  );
end Cookbook__fec_check__part2198;

architecture Cookbook__fec_check__part2198_behav of Cookbook__fec_check__part2198 is
begin
    n11634 <= ( lo2267 );
end Cookbook__fec_check__part2198_behav;
