--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part80 is 
  Port (
    lo0236: in std_logic;
    n3895: inout std_logic
  );
end Other__fp_operators__part80;

architecture Other__fp_operators__part80_behav of Other__fp_operators__part80 is
begin
    n3895 <= ( lo0236 );
end Other__fp_operators__part80_behav;
