--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part870 is 
  Port (
    lo06629: in std_logic;
    n49481_1: inout std_logic
  );
end Other__ray__part870;

architecture Other__ray__part870_behav of Other__ray__part870 is
begin
    n49481_1 <= ( lo06629 );
end Other__ray__part870_behav;
