--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part997 is 
  Port (
    lo1066: in std_logic;
    n5629: inout std_logic
  );
end Cookbook__fec_check__part997;

architecture Cookbook__fec_check__part997_behav of Cookbook__fec_check__part997 is
begin
    n5629 <= ( lo1066 );
end Cookbook__fec_check__part997_behav;
