--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part175 is 
  Port (
    lo2824: in std_logic;
    n6669: inout std_logic
  );
end Other__sudoku_check__part175;

architecture Other__sudoku_check__part175_behav of Other__sudoku_check__part175 is
begin
    n6669 <= ( lo2824 );
end Other__sudoku_check__part175_behav;
