--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1025 is 
  Port (
    lo1094: in std_logic;
    n5769: inout std_logic
  );
end Cookbook__fec_check__part1025;

architecture Cookbook__fec_check__part1025_behav of Cookbook__fec_check__part1025 is
begin
    n5769 <= ( lo1094 );
end Cookbook__fec_check__part1025_behav;
