--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part28 is 
  Port (
    lo17: in std_logic;
    po06: inout std_logic
  );
end Cookbook__font_rom__part28;

architecture Cookbook__font_rom__part28_behav of Cookbook__font_rom__part28 is
begin
    po06 <= ( lo17 );
end Cookbook__font_rom__part28_behav;
