--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part621 is 
  Port (
    lo3270: in std_logic;
    n11129: inout std_logic
  );
end Other__sudoku_check__part621;

architecture Other__sudoku_check__part621_behav of Other__sudoku_check__part621 is
begin
    n11129 <= ( lo3270 );
end Other__sudoku_check__part621_behav;
