--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part135 is 
  Port (
    lo3325: in std_logic;
    n16964: inout std_logic
  );
end IWLS2005__pci_bridge32__part135;

architecture IWLS2005__pci_bridge32__part135_behav of IWLS2005__pci_bridge32__part135 is
begin
    n16964 <= ( lo3325 );
end IWLS2005__pci_bridge32__part135_behav;
