--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1674 is 
  Port (
    lo3794: in std_logic;
    n23546: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1674;

architecture Other__ucsb_152_tap_fir__part1674_behav of Other__ucsb_152_tap_fir__part1674 is
begin
    n23546 <= ( lo3794 );
end Other__ucsb_152_tap_fir__part1674_behav;
