--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1052 is 
  Port (
    lo1121: in std_logic;
    n5904: inout std_logic
  );
end Cookbook__fec_check__part1052;

architecture Cookbook__fec_check__part1052_behav of Cookbook__fec_check__part1052 is
begin
    n5904 <= ( lo1121 );
end Cookbook__fec_check__part1052_behav;
