--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part94 is 
  Port (
    pi094: in std_logic;
    n10119_1: inout std_logic
  );
end Other__desperf__part94;

architecture Other__desperf__part94_behav of Other__desperf__part94 is
begin
    n10119_1 <= ( pi094 );
end Other__desperf__part94_behav;
