--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part5 is 
  Port (
    pi05: in std_logic;
    n143: inout std_logic
  );
end Cookbook__pipeline_add_msb__part5;

architecture Cookbook__pipeline_add_msb__part5_behav of Cookbook__pipeline_add_msb__part5 is
begin
    n143 <= ( pi05 );
end Cookbook__pipeline_add_msb__part5_behav;
