--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3279 is 
  Port (
    lo8624: in std_logic;
    n43225_1: inout std_logic
  );
end IWLS2005__des_perf__part3279;

architecture IWLS2005__des_perf__part3279_behav of IWLS2005__des_perf__part3279 is
begin
    n43225_1 <= ( lo8624 );
end IWLS2005__des_perf__part3279_behav;
