--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part115 is 
  Port (
    lo1002: in std_logic;
    n5284: inout std_logic
  );
end ISCAS__s38417__part115;

architecture ISCAS__s38417__part115_behav of ISCAS__s38417__part115 is
begin
    n5284 <= ( lo1002 );
end ISCAS__s38417__part115_behav;
