--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part448 is 
  Port (
    lo05920: in std_logic;
    po1386,po1451,po1717,po1786: inout std_logic
  );
end Other__ray__part448;

architecture Other__ray__part448_behav of Other__ray__part448 is
begin
    po1386 <= ( lo05920 );
    po1451 <= ( lo05920 );
    po1717 <= ( lo05920 );
    po1786 <= ( lo05920 );
end Other__ray__part448_behav;
