--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part270 is 
  Port (
    lo1331: in std_logic;
    n9260_1: inout std_logic
  );
end Other__fp_operators__part270;

architecture Other__fp_operators__part270_behav of Other__fp_operators__part270 is
begin
    n9260_1 <= ( lo1331 );
end Other__fp_operators__part270_behav;
