--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part132 is 
  Port (
    lo258: in std_logic;
    po080: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part132;

architecture Cookbook__soft_ecc_ram_64bit__part132_behav of Cookbook__soft_ecc_ram_64bit__part132 is
begin
    po080 <= ( lo258 );
end Cookbook__soft_ecc_ram_64bit__part132_behav;
