--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part319 is 
  Port (
    lo1094: in std_logic;
    n6729: inout std_logic
  );
end Cookbook__ucrypt__part319;

architecture Cookbook__ucrypt__part319_behav of Cookbook__ucrypt__part319 is
begin
    n6729 <= ( lo1094 );
end Cookbook__ucrypt__part319_behav;
