--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part16 is 
  Port (
    lo204: in std_logic;
    po047: inout std_logic
  );
end IWLS2005__aes_core__part16;

architecture IWLS2005__aes_core__part16_behav of IWLS2005__aes_core__part16 is
begin
    po047 <= ( lo204 );
end IWLS2005__aes_core__part16_behav;
