--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1946 is 
  Port (
    lo2015: in std_logic;
    n10374: inout std_logic
  );
end Cookbook__fec_check__part1946;

architecture Cookbook__fec_check__part1946_behav of Cookbook__fec_check__part1946 is
begin
    n10374 <= ( lo2015 );
end Cookbook__fec_check__part1946_behav;
