--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part23 is 
  Port (
    lo05: in std_logic;
    po0: inout std_logic
  );
end Cookbook__pipe_equal__part23;

architecture Cookbook__pipe_equal__part23_behav of Cookbook__pipe_equal__part23 is
begin
    po0 <= ( lo05 );
end Cookbook__pipe_equal__part23_behav;
