--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part673 is 
  Port (
    lo3322: in std_logic;
    n11649: inout std_logic
  );
end Other__sudoku_check__part673;

architecture Other__sudoku_check__part673_behav of Other__sudoku_check__part673 is
begin
    n11649 <= ( lo3322 );
end Other__sudoku_check__part673_behav;
