--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part180 is 
  Port (
    lo1257: in std_logic;
    n6559_1: inout std_logic
  );
end LGSynth91__s38417__part180;

architecture LGSynth91__s38417__part180_behav of LGSynth91__s38417__part180 is
begin
    n6559_1 <= ( lo1257 );
end LGSynth91__s38417__part180_behav;
