--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_mux__part7 is 
  Port (
    lo09: in std_logic;
    n69: inout std_logic
  );
end Cookbook__clock_mux__part7;

architecture Cookbook__clock_mux__part7_behav of Cookbook__clock_mux__part7 is
begin
    n69 <= ( lo09 );
end Cookbook__clock_mux__part7_behav;
