--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fifo__part10 is 
  Port (
    lo070: in std_logic;
    po10: inout std_logic
  );
end Cookbook__fifo__part10;

architecture Cookbook__fifo__part10_behav of Cookbook__fifo__part10 is
begin
    po10 <= ( lo070 );
end Cookbook__fifo__part10_behav;
