--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part45 is 
  Port (
    lo2202: in std_logic;
    n5369: inout std_logic
  );
end Other__sudoku_check__part45;

architecture Other__sudoku_check__part45_behav of Other__sudoku_check__part45 is
begin
    n5369 <= ( lo2202 );
end Other__sudoku_check__part45_behav;
