--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2177 is 
  Port (
    lo2246: in std_logic;
    n11529: inout std_logic
  );
end Cookbook__fec_check__part2177;

architecture Cookbook__fec_check__part2177_behav of Cookbook__fec_check__part2177 is
begin
    n11529 <= ( lo2246 );
end Cookbook__fec_check__part2177_behav;
