--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part175 is 
  Port (
    pi1119: in std_logic;
    n31949: inout std_logic
  );
end Other__carpat__part175;

architecture Other__carpat__part175_behav of Other__carpat__part175 is
begin
    n31949 <= ( pi1119 );
end Other__carpat__part175_behav;
