--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part49 is 
  Port (
    pi049: in std_logic;
    n2472_1: inout std_logic
  );
end Other__fpu__part49;

architecture Other__fpu__part49_behav of Other__fpu__part49 is
begin
    n2472_1 <= ( pi049 );
end Other__fpu__part49_behav;
