--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part14 is 
  Port (
    pi17: in std_logic;
    n127: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part14;

architecture Cookbook__ycbcr_to_rgb__part14_behav of Cookbook__ycbcr_to_rgb__part14 is
begin
    n127 <= ( pi17 );
end Cookbook__ycbcr_to_rgb__part14_behav;
