--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part828 is 
  Port (
    lo4625: in std_logic;
    n23230: inout std_logic
  );
end IWLS2005__des_perf__part828;

architecture IWLS2005__des_perf__part828_behav of IWLS2005__des_perf__part828 is
begin
    n23230 <= ( lo4625 );
end IWLS2005__des_perf__part828_behav;
