--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1504 is 
  Port (
    lo5625,lo5626,lo5627,lo5628: in std_logic;
    n27139_1,n28744_1,n28749_1,n28754_1,n28759_1,n28764_1,n28769,n28774_1,n28779_1: inout std_logic
  );
end Other__sudoku_check__part1504;

architecture Other__sudoku_check__part1504_behav of Other__sudoku_check__part1504 is
begin
    n27139_1 <= ( lo5625 and not lo5626 and not lo5627 and not lo5628 );
    n28744_1 <= ( lo5625 and not lo5626 and not lo5627 and lo5628 );
    n28749_1 <= ( not lo5625 and not lo5626 and not lo5627 and lo5628 );
    n28754_1 <= ( lo5625 and lo5626 and lo5627 and not lo5628 );
    n28759_1 <= ( not lo5625 and lo5626 and lo5627 and not lo5628 );
    n28764_1 <= ( lo5625 and not lo5626 and lo5627 and not lo5628 );
    n28769 <= ( not lo5625 and not lo5626 and lo5627 and not lo5628 );
    n28774_1 <= ( lo5625 and lo5626 and not lo5627 and not lo5628 );
    n28779_1 <= ( not lo5625 and lo5626 and not lo5627 and not lo5628 );
end Other__sudoku_check__part1504_behav;
