--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part78 is 
  Port (
    lo0517: in std_logic;
    n2499: inout std_logic
  );
end IWLS93__s38417__part78;

architecture IWLS93__s38417__part78_behav of IWLS93__s38417__part78 is
begin
    n2499 <= ( lo0517 );
end IWLS93__s38417__part78_behav;
