--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part116 is 
  Port (
    lo0417: in std_logic;
    n4565: inout std_logic
  );
end Other__fp_operators__part116;

architecture Other__fp_operators__part116_behav of Other__fp_operators__part116 is
begin
    n4565 <= ( lo0417 );
end Other__fp_operators__part116_behav;
