--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__aqua__part5 is 
  Port (
    lo1143,lo1144: in std_logic;
    n12040_1,n12215_1: inout std_logic
  );
end Other__aqua__part5;

architecture Other__aqua__part5_behav of Other__aqua__part5 is
begin
    n12040_1 <= ( lo1143 and not lo1144 );
    n12215_1 <= ( lo1143 );
end Other__aqua__part5_behav;
