--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part86 is 
  Port (
    lo072: in std_logic;
    po194: inout std_logic
  );
end Cookbook__lc_mult_signed__part86;

architecture Cookbook__lc_mult_signed__part86_behav of Cookbook__lc_mult_signed__part86 is
begin
    po194 <= ( lo072 );
end Cookbook__lc_mult_signed__part86_behav;
