--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part11 is 
  Port (
    pi58: in std_logic;
    n488255_1,n488260_1: inout std_logic
  );
end IWLS2005__netcard__part11;

architecture IWLS2005__netcard__part11_behav of IWLS2005__netcard__part11 is
begin
    n488255_1 <= ( pi58 );
    n488260_1 <= ( pi58 );
end IWLS2005__netcard__part11_behav;
