--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1069 is 
  Port (
    lo7162: in std_logic;
    n38004_1: inout std_logic
  );
end Other__carpat__part1069;

architecture Other__carpat__part1069_behav of Other__carpat__part1069 is
begin
    n38004_1 <= ( lo7162 );
end Other__carpat__part1069_behav;
