--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part4 is 
  Port (
    pi07: in std_logic;
    n922_1: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part4;

architecture Cookbook__ycbcr_to_rgb__part4_behav of Cookbook__ycbcr_to_rgb__part4 is
begin
    n922_1 <= ( pi07 );
end Cookbook__ycbcr_to_rgb__part4_behav;
