--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part115 is 
  Port (
    pi0960: in std_logic;
    n31284: inout std_logic
  );
end Other__carpat__part115;

architecture Other__carpat__part115_behav of Other__carpat__part115 is
begin
    n31284 <= ( pi0960 );
end Other__carpat__part115_behav;
