--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part161 is 
  Port (
    lo0230: in std_logic;
    n1449: inout std_logic
  );
end Cookbook__fec_check__part161;

architecture Cookbook__fec_check__part161_behav of Cookbook__fec_check__part161 is
begin
    n1449 <= ( lo0230 );
end Cookbook__fec_check__part161_behav;
