--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1680 is 
  Port (
    lo6385: in std_logic;
    n31915_1: inout std_logic
  );
end IWLS2005__des_perf__part1680;

architecture IWLS2005__des_perf__part1680_behav of IWLS2005__des_perf__part1680 is
begin
    n31915_1 <= ( lo6385 );
end IWLS2005__des_perf__part1680_behav;
