--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1606 is 
  Port (
    lo3642: in std_logic;
    n22756: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1606;

architecture Other__ucsb_152_tap_fir__part1606_behav of Other__ucsb_152_tap_fir__part1606 is
begin
    n22756 <= ( lo3642 );
end Other__ucsb_152_tap_fir__part1606_behav;
