--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part186 is 
  Port (
    lo03224: in std_logic;
    n34026: inout std_logic
  );
end Other__ray__part186;

architecture Other__ray__part186_behav of Other__ray__part186 is
begin
    n34026 <= ( lo03224 );
end Other__ray__part186_behav;
