--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part861 is 
  Port (
    lo4703: in std_logic;
    n23505: inout std_logic
  );
end IWLS2005__des_perf__part861;

architecture IWLS2005__des_perf__part861_behav of IWLS2005__des_perf__part861 is
begin
    n23505 <= ( lo4703 );
end IWLS2005__des_perf__part861_behav;
