--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part948 is 
  Port (
    lo1017: in std_logic;
    n5384: inout std_logic
  );
end Cookbook__fec_check__part948;

architecture Cookbook__fec_check__part948_behav of Cookbook__fec_check__part948 is
begin
    n5384 <= ( lo1017 );
end Cookbook__fec_check__part948_behav;
