--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part976 is 
  Port (
    lo6931: in std_logic;
    n36219_1: inout std_logic
  );
end Other__carpat__part976;

architecture Other__carpat__part976_behav of Other__carpat__part976 is
begin
    n36219_1 <= ( lo6931 );
end Other__carpat__part976_behav;
