--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2118 is 
  Port (
    lo2187: in std_logic;
    n11234: inout std_logic
  );
end Cookbook__fec_check__part2118;

architecture Cookbook__fec_check__part2118_behav of Cookbook__fec_check__part2118 is
begin
    n11234 <= ( lo2187 );
end Cookbook__fec_check__part2118_behav;
