--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1839 is 
  Port (
    lo1908: in std_logic;
    n9839: inout std_logic
  );
end Cookbook__fec_check__part1839;

architecture Cookbook__fec_check__part1839_behav of Cookbook__fec_check__part1839 is
begin
    n9839 <= ( lo1908 );
end Cookbook__fec_check__part1839_behav;
