--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part709 is 
  Port (
    lo4394: in std_logic;
    n21985: inout std_logic
  );
end IWLS2005__des_perf__part709;

architecture IWLS2005__des_perf__part709_behav of IWLS2005__des_perf__part709 is
begin
    n21985 <= ( lo4394 );
end IWLS2005__des_perf__part709_behav;
