--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part367 is 
  Port (
    lo1348: in std_logic;
    n7849_1: inout std_logic
  );
end Cookbook__ucrypt__part367;

architecture Cookbook__ucrypt__part367_behav of Cookbook__ucrypt__part367 is
begin
    n7849_1 <= ( lo1348 );
end Cookbook__ucrypt__part367_behav;
