--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part680 is 
  Port (
    lo0749: in std_logic;
    n4044: inout std_logic
  );
end Cookbook__fec_check__part680;

architecture Cookbook__fec_check__part680_behav of Cookbook__fec_check__part680 is
begin
    n4044 <= ( lo0749 );
end Cookbook__fec_check__part680_behav;
