--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1713 is 
  Port (
    lo8739: in std_logic;
    po191: inout std_logic
  );
end Other__carpat__part1713;

architecture Other__carpat__part1713_behav of Other__carpat__part1713 is
begin
    po191 <= ( lo8739 );
end Other__carpat__part1713_behav;
