--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part244 is 
  Port (
    lo0313: in std_logic;
    n1864: inout std_logic
  );
end Cookbook__fec_check__part244;

architecture Cookbook__fec_check__part244_behav of Cookbook__fec_check__part244 is
begin
    n1864 <= ( lo0313 );
end Cookbook__fec_check__part244_behav;
