--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part376 is 
  Port (
    lo2171: in std_logic;
    n11385: inout std_logic
  );
end IWLS2005__des_perf__part376;

architecture IWLS2005__des_perf__part376_behav of IWLS2005__des_perf__part376 is
begin
    n11385 <= ( lo2171 );
end IWLS2005__des_perf__part376_behav;
