--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1297 is 
  Port (
    lo4666: in std_logic;
    n18819: inout std_logic
  );
end Other__sudoku_check__part1297;

architecture Other__sudoku_check__part1297_behav of Other__sudoku_check__part1297 is
begin
    n18819 <= ( lo4666 );
end Other__sudoku_check__part1297_behav;
