--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1542 is 
  Port (
    lo8173: in std_logic;
    n45934_1: inout std_logic
  );
end Other__carpat__part1542;

architecture Other__carpat__part1542_behav of Other__carpat__part1542 is
begin
    n45934_1 <= ( lo8173 );
end Other__carpat__part1542_behav;
