--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part198 is 
  Port (
    lo0464: in std_logic;
    n6771: inout std_logic
  );
end Other__ucsb_152_tap_fir__part198;

architecture Other__ucsb_152_tap_fir__part198_behav of Other__ucsb_152_tap_fir__part198 is
begin
    n6771 <= ( lo0464 );
end Other__ucsb_152_tap_fir__part198_behav;
