--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part418 is 
  Port (
    lo0487: in std_logic;
    n2734: inout std_logic
  );
end Cookbook__fec_check__part418;

architecture Cookbook__fec_check__part418_behav of Cookbook__fec_check__part418 is
begin
    n2734 <= ( lo0487 );
end Cookbook__fec_check__part418_behav;
