--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part61 is 
  Port (
    lo185: in std_logic;
    po54: inout std_logic
  );
end IWLS2005__systemcdes__part61;

architecture IWLS2005__systemcdes__part61_behav of IWLS2005__systemcdes__part61 is
begin
    po54 <= ( lo185 );
end IWLS2005__systemcdes__part61_behav;
