--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1179 is 
  Port (
    lo2730: in std_logic;
    n18241: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1179;

architecture Other__ucsb_152_tap_fir__part1179_behav of Other__ucsb_152_tap_fir__part1179 is
begin
    n18241 <= ( lo2730 );
end Other__ucsb_152_tap_fir__part1179_behav;
