--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1485 is 
  Port (
    lo4854: in std_logic;
    n19759_1: inout std_logic
  );
end Other__sudoku_check__part1485;

architecture Other__sudoku_check__part1485_behav of Other__sudoku_check__part1485 is
begin
    n19759_1 <= ( lo4854 );
end Other__sudoku_check__part1485_behav;
