--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part39 is 
  Port (
    lo2160: in std_logic;
    n5309: inout std_logic
  );
end Other__sudoku_check__part39;

architecture Other__sudoku_check__part39_behav of Other__sudoku_check__part39 is
begin
    n5309 <= ( lo2160 );
end Other__sudoku_check__part39_behav;
