--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part269 is 
  Port (
    lo1319: in std_logic;
    n6104: inout std_logic
  );
end Other__desperf__part269;

architecture Other__desperf__part269_behav of Other__desperf__part269 is
begin
    n6104 <= ( lo1319 );
end Other__desperf__part269_behav;
