--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part246 is 
  Port (
    lo1024: in std_logic;
    n5605: inout std_logic
  );
end IWLS2005__des_perf__part246;

architecture IWLS2005__des_perf__part246_behav of IWLS2005__des_perf__part246 is
begin
    n5605 <= ( lo1024 );
end IWLS2005__des_perf__part246_behav;
