--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part46 is 
  Port (
    lo0800: in std_logic;
    n5338_1: inout std_logic
  );
end Other__ether__part46;

architecture Other__ether__part46_behav of Other__ether__part46 is
begin
    n5338_1 <= ( lo0800 );
end Other__ether__part46_behav;
