--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part76 is 
  Port (
    lo2473: in std_logic;
    n5679: inout std_logic
  );
end Other__sudoku_check__part76;

architecture Other__sudoku_check__part76_behav of Other__sudoku_check__part76 is
begin
    n5679 <= ( lo2473 );
end Other__sudoku_check__part76_behav;
