--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1659 is 
  Port (
    lo1728: in std_logic;
    n8939: inout std_logic
  );
end Cookbook__fec_check__part1659;

architecture Cookbook__fec_check__part1659_behav of Cookbook__fec_check__part1659 is
begin
    n8939 <= ( lo1728 );
end Cookbook__fec_check__part1659_behav;
