--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part875 is 
  Port (
    lo0944: in std_logic;
    n5019: inout std_logic
  );
end Cookbook__fec_check__part875;

architecture Cookbook__fec_check__part875_behav of Cookbook__fec_check__part875 is
begin
    n5019 <= ( lo0944 );
end Cookbook__fec_check__part875_behav;
