--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part552 is 
  Port (
    lo1999: in std_logic;
    n11254_1: inout std_logic
  );
end Cookbook__ucrypt__part552;

architecture Cookbook__ucrypt__part552_behav of Cookbook__ucrypt__part552 is
begin
    n11254_1 <= ( lo1999 );
end Cookbook__ucrypt__part552_behav;
