--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1020 is 
  Port (
    lo10741: in std_logic;
    n71851_1: inout std_logic
  );
end Other__ray__part1020;

architecture Other__ray__part1020_behav of Other__ray__part1020 is
begin
    n71851_1 <= ( lo10741 );
end Other__ray__part1020_behav;
