--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part236 is 
  Port (
    lo0156: in std_logic;
    n705: inout std_logic
  );
end IWLS2005__des_perf__part236;

architecture IWLS2005__des_perf__part236_behav of IWLS2005__des_perf__part236 is
begin
    n705 <= ( lo0156 );
end IWLS2005__des_perf__part236_behav;
