--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2156 is 
  Port (
    lo2225: in std_logic;
    n11424: inout std_logic
  );
end Cookbook__fec_check__part2156;

architecture Cookbook__fec_check__part2156_behav of Cookbook__fec_check__part2156 is
begin
    n11424 <= ( lo2225 );
end Cookbook__fec_check__part2156_behav;
