--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part477 is 
  Port (
    lo3126: in std_logic;
    n9689: inout std_logic
  );
end Other__sudoku_check__part477;

architecture Other__sudoku_check__part477_behav of Other__sudoku_check__part477 is
begin
    n9689 <= ( lo3126 );
end Other__sudoku_check__part477_behav;
