--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2138 is 
  Port (
    lo2207: in std_logic;
    n11334: inout std_logic
  );
end Cookbook__fec_check__part2138;

architecture Cookbook__fec_check__part2138_behav of Cookbook__fec_check__part2138 is
begin
    n11334 <= ( lo2207 );
end Cookbook__fec_check__part2138_behav;
