--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part464 is 
  Port (
    lo1687: in std_logic;
    n9694_1: inout std_logic
  );
end Cookbook__ucrypt__part464;

architecture Cookbook__ucrypt__part464_behav of Cookbook__ucrypt__part464 is
begin
    n9694_1 <= ( lo1687 );
end Cookbook__ucrypt__part464_behav;
