--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1498 is 
  Port (
    lo5601,lo5602,lo5603,lo5604: in std_logic;
    n27109_1,n28984_1,n28989_1,n28994_1,n28999_1,n29004_1,n29009_1,n29014_1,n29019_1: inout std_logic
  );
end Other__sudoku_check__part1498;

architecture Other__sudoku_check__part1498_behav of Other__sudoku_check__part1498 is
begin
    n27109_1 <= ( lo5601 and not lo5602 and not lo5603 and not lo5604 );
    n28984_1 <= ( lo5601 and not lo5602 and not lo5603 and lo5604 );
    n28989_1 <= ( not lo5601 and not lo5602 and not lo5603 and lo5604 );
    n28994_1 <= ( lo5601 and lo5602 and lo5603 and not lo5604 );
    n28999_1 <= ( not lo5601 and lo5602 and lo5603 and not lo5604 );
    n29004_1 <= ( lo5601 and not lo5602 and lo5603 and not lo5604 );
    n29009_1 <= ( not lo5601 and not lo5602 and lo5603 and not lo5604 );
    n29014_1 <= ( lo5601 and lo5602 and not lo5603 and not lo5604 );
    n29019_1 <= ( not lo5601 and lo5602 and not lo5603 and not lo5604 );
end Other__sudoku_check__part1498_behav;
