--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1737 is 
  Port (
    lo6521: in std_logic;
    n32475_1: inout std_logic
  );
end IWLS2005__des_perf__part1737;

architecture IWLS2005__des_perf__part1737_behav of IWLS2005__des_perf__part1737 is
begin
    n32475_1 <= ( lo6521 );
end IWLS2005__des_perf__part1737_behav;
