--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part558 is 
  Port (
    lo3207: in std_logic;
    n10499: inout std_logic
  );
end Other__sudoku_check__part558;

architecture Other__sudoku_check__part558_behav of Other__sudoku_check__part558 is
begin
    n10499 <= ( lo3207 );
end Other__sudoku_check__part558_behav;
