--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2825 is 
  Port (
    lo8138: in std_logic;
    n40970_1: inout std_logic
  );
end IWLS2005__des_perf__part2825;

architecture IWLS2005__des_perf__part2825_behav of IWLS2005__des_perf__part2825 is
begin
    n40970_1 <= ( lo8138 );
end IWLS2005__des_perf__part2825_behav;
