--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part35 is 
  Port (
    lo15579: in std_logic;
    po96: inout std_logic
  );
end IWLS2005__vga_lcd__part35;

architecture IWLS2005__vga_lcd__part35_behav of IWLS2005__vga_lcd__part35 is
begin
    po96 <= ( lo15579 );
end IWLS2005__vga_lcd__part35_behav;
