--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part369 is 
  Port (
    lo3018: in std_logic;
    n8609: inout std_logic
  );
end Other__sudoku_check__part369;

architecture Other__sudoku_check__part369_behav of Other__sudoku_check__part369 is
begin
    n8609 <= ( lo3018 );
end Other__sudoku_check__part369_behav;
