--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1851 is 
  Port (
    lo4178: in std_logic;
    n25476: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1851;

architecture Other__ucsb_152_tap_fir__part1851_behav of Other__ucsb_152_tap_fir__part1851 is
begin
    n25476 <= ( lo4178 );
end Other__ucsb_152_tap_fir__part1851_behav;
