--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1662 is 
  Port (
    lo1731: in std_logic;
    n8954: inout std_logic
  );
end Cookbook__fec_check__part1662;

architecture Cookbook__fec_check__part1662_behav of Cookbook__fec_check__part1662 is
begin
    n8954 <= ( lo1731 );
end Cookbook__fec_check__part1662_behav;
