--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part146 is 
  Port (
    lo1004: in std_logic;
    po084: inout std_logic
  );
end IWLS2005__mem_ctrl__part146;

architecture IWLS2005__mem_ctrl__part146_behav of IWLS2005__mem_ctrl__part146 is
begin
    po084 <= ( lo1004 );
end IWLS2005__mem_ctrl__part146_behav;
