--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1345 is 
  Port (
    lo1414: in std_logic;
    n7369: inout std_logic
  );
end Cookbook__fec_check__part1345;

architecture Cookbook__fec_check__part1345_behav of Cookbook__fec_check__part1345 is
begin
    n7369 <= ( lo1414 );
end Cookbook__fec_check__part1345_behav;
