--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part30 is 
  Port (
    lo241: in std_logic;
    po014: inout std_logic
  );
end IWLS2005__aes_core__part30;

architecture IWLS2005__aes_core__part30_behav of IWLS2005__aes_core__part30 is
begin
    po014 <= ( lo241 );
end IWLS2005__aes_core__part30_behav;
