--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38584__part2 is 
  Port (
    lo0064: in std_logic;
    n836: inout std_logic
  );
end ISCAS__s38584__part2;

architecture ISCAS__s38584__part2_behav of ISCAS__s38584__part2 is
begin
    n836 <= ( lo0064 );
end ISCAS__s38584__part2_behav;
