--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part327 is 
  Port (
    pi1642: in std_logic;
    n47249_1: inout std_logic
  );
end Other__carpat__part327;

architecture Other__carpat__part327_behav of Other__carpat__part327 is
begin
    n47249_1 <= ( pi1642 );
end Other__carpat__part327_behav;
