--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part34 is 
  Port (
    lo0102: in std_logic;
    po110: inout std_logic
  );
end Other__mem__part34;

architecture Other__mem__part34_behav of Other__mem__part34 is
begin
    po110 <= ( lo0102 );
end Other__mem__part34_behav;
