--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part2 is 
  Port (
    pi02: in std_logic;
    n131: inout std_logic
  );
end Cookbook__approx_fp_div__part2;

architecture Cookbook__approx_fp_div__part2_behav of Cookbook__approx_fp_div__part2 is
begin
    n131 <= ( pi02 );
end Cookbook__approx_fp_div__part2_behav;
