--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1700 is 
  Port (
    lo8704: in std_logic;
    n49024_1: inout std_logic
  );
end Other__carpat__part1700;

architecture Other__carpat__part1700_behav of Other__carpat__part1700 is
begin
    n49024_1 <= ( lo8704 );
end Other__carpat__part1700_behav;
