--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part88 is 
  Port (
    lo2593: in std_logic;
    n5799: inout std_logic
  );
end Other__sudoku_check__part88;

architecture Other__sudoku_check__part88_behav of Other__sudoku_check__part88 is
begin
    n5799 <= ( lo2593 );
end Other__sudoku_check__part88_behav;
