--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part649 is 
  Port (
    lo3298: in std_logic;
    n11409: inout std_logic
  );
end Other__sudoku_check__part649;

architecture Other__sudoku_check__part649_behav of Other__sudoku_check__part649 is
begin
    n11409 <= ( lo3298 );
end Other__sudoku_check__part649_behav;
