--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1430 is 
  Port (
    lo4799: in std_logic;
    n19484_1: inout std_logic
  );
end Other__sudoku_check__part1430;

architecture Other__sudoku_check__part1430_behav of Other__sudoku_check__part1430 is
begin
    n19484_1 <= ( lo4799 );
end Other__sudoku_check__part1430_behav;
