--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part805 is 
  Port (
    lo6373: in std_logic;
    po533: inout std_logic
  );
end Other__carpat__part805;

architecture Other__carpat__part805_behav of Other__carpat__part805 is
begin
    po533 <= ( lo6373 );
end Other__carpat__part805_behav;
