--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part317 is 
  Port (
    lo2966: in std_logic;
    n8089: inout std_logic
  );
end Other__sudoku_check__part317;

architecture Other__sudoku_check__part317_behav of Other__sudoku_check__part317 is
begin
    n8089 <= ( lo2966 );
end Other__sudoku_check__part317_behav;
