--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part84 is 
  Port (
    lo0611: in std_logic;
    n3329: inout std_logic
  );
end LGSynth91__s38417__part84;

architecture LGSynth91__s38417__part84_behav of LGSynth91__s38417__part84 is
begin
    n3329 <= ( lo0611 );
end LGSynth91__s38417__part84_behav;
