--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2604 is 
  Port (
    lo7861: in std_logic;
    n39095_1: inout std_logic
  );
end IWLS2005__des_perf__part2604;

architecture IWLS2005__des_perf__part2604_behav of IWLS2005__des_perf__part2604 is
begin
    n39095_1 <= ( lo7861 );
end IWLS2005__des_perf__part2604_behav;
