--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part529 is 
  Port (
    lo4112: in std_logic;
    n20755: inout std_logic
  );
end IWLS2005__des_perf__part529;

architecture IWLS2005__des_perf__part529_behav of IWLS2005__des_perf__part529 is
begin
    n20755 <= ( lo4112 );
end IWLS2005__des_perf__part529_behav;
