--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2191 is 
  Port (
    lo4854: in std_logic;
    n28861: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2191;

architecture Other__ucsb_152_tap_fir__part2191_behav of Other__ucsb_152_tap_fir__part2191 is
begin
    n28861 <= ( lo4854 );
end Other__ucsb_152_tap_fir__part2191_behav;
