--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1566 is 
  Port (
    lo6155: in std_logic;
    n30965_1: inout std_logic
  );
end IWLS2005__des_perf__part1566;

architecture IWLS2005__des_perf__part1566_behav of IWLS2005__des_perf__part1566 is
begin
    n30965_1 <= ( lo6155 );
end IWLS2005__des_perf__part1566_behav;
