--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part73 is 
  Port (
    lo136: in std_logic;
    po000: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part73;

architecture Cookbook__soft_ecc_ram_64bit__part73_behav of Cookbook__soft_ecc_ram_64bit__part73 is
begin
    po000 <= ( lo136 );
end Cookbook__soft_ecc_ram_64bit__part73_behav;
