--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part5 is 
  Port (
    lo043: in std_logic;
    po27: inout std_logic
  );
end Cookbook__fec_gen__part5;

architecture Cookbook__fec_gen__part5_behav of Cookbook__fec_gen__part5 is
begin
    po27 <= ( lo043 );
end Cookbook__fec_gen__part5_behav;
