--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s400__part6 is 
  Port (
    lo07: in std_logic;
    po3: inout std_logic
  );
end LGSynth91__s400__part6;

architecture LGSynth91__s400__part6_behav of LGSynth91__s400__part6 is
begin
    po3 <= ( lo07 );
end LGSynth91__s400__part6_behav;
