--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part627 is 
  Port (
    lo0696: in std_logic;
    n3779: inout std_logic
  );
end Cookbook__fec_check__part627;

architecture Cookbook__fec_check__part627_behav of Cookbook__fec_check__part627 is
begin
    n3779 <= ( lo0696 );
end Cookbook__fec_check__part627_behav;
