--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3336 is 
  Port (
    lo8744: in std_logic;
    n43720_1: inout std_logic
  );
end IWLS2005__des_perf__part3336;

architecture IWLS2005__des_perf__part3336_behav of IWLS2005__des_perf__part3336 is
begin
    n43720_1 <= ( lo8744 );
end IWLS2005__des_perf__part3336_behav;
