--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part54 is 
  Port (
    lo53: in std_logic;
    po53: inout std_logic
  );
end Other__idxlat01n_m12__part54;

architecture Other__idxlat01n_m12__part54_behav of Other__idxlat01n_m12__part54 is
begin
    po53 <= ( lo53 );
end Other__idxlat01n_m12__part54_behav;
