--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part233 is 
  Port (
    lo0135: in std_logic;
    n710: inout std_logic
  );
end IWLS2005__des_perf__part233;

architecture IWLS2005__des_perf__part233_behav of IWLS2005__des_perf__part233 is
begin
    n710 <= ( lo0135 );
end IWLS2005__des_perf__part233_behav;
