--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1272 is 
  Port (
    lo1341: in std_logic;
    n7004: inout std_logic
  );
end Cookbook__fec_check__part1272;

architecture Cookbook__fec_check__part1272_behav of Cookbook__fec_check__part1272 is
begin
    n7004 <= ( lo1341 );
end Cookbook__fec_check__part1272_behav;
