--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1400 is 
  Port (
    lo7850: in std_logic;
    n44129_1: inout std_logic
  );
end Other__carpat__part1400;

architecture Other__carpat__part1400_behav of Other__carpat__part1400 is
begin
    n44129_1 <= ( lo7850 );
end Other__carpat__part1400_behav;
