--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1776 is 
  Port (
    lo4014: in std_logic;
    n24581: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1776;

architecture Other__ucsb_152_tap_fir__part1776_behav of Other__ucsb_152_tap_fir__part1776 is
begin
    n24581 <= ( lo4014 );
end Other__ucsb_152_tap_fir__part1776_behav;
