--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part105 is 
  Port (
    lo0676: in std_logic;
    po015: inout std_logic
  );
end IWLS2005__mem_ctrl__part105;

architecture IWLS2005__mem_ctrl__part105_behav of IWLS2005__mem_ctrl__part105 is
begin
    po015 <= ( lo0676 );
end IWLS2005__mem_ctrl__part105_behav;
