--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1691 is 
  Port (
    lo8636: in std_logic;
    n48679_1: inout std_logic
  );
end Other__carpat__part1691;

architecture Other__carpat__part1691_behav of Other__carpat__part1691 is
begin
    n48679_1 <= ( lo8636 );
end Other__carpat__part1691_behav;
