--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part275 is 
  Port (
    lo1358: in std_logic;
    n9705_1: inout std_logic
  );
end Other__fp_operators__part275;

architecture Other__fp_operators__part275_behav of Other__fp_operators__part275 is
begin
    n9705_1 <= ( lo1358 );
end Other__fp_operators__part275_behav;
