--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__frequency_monitor__part4 is 
  Port (
    lo045: in std_logic;
    n391: inout std_logic
  );
end Cookbook__frequency_monitor__part4;

architecture Cookbook__frequency_monitor__part4_behav of Cookbook__frequency_monitor__part4 is
begin
    n391 <= ( lo045 );
end Cookbook__frequency_monitor__part4_behav;
