--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1235 is 
  Port (
    lo5457: in std_logic;
    n27195_1: inout std_logic
  );
end IWLS2005__des_perf__part1235;

architecture IWLS2005__des_perf__part1235_behav of IWLS2005__des_perf__part1235 is
begin
    n27195_1 <= ( lo5457 );
end IWLS2005__des_perf__part1235_behav;
