--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part10 is 
  Port (
    lo008: in std_logic;
    n333,n708: inout std_logic
  );
end ISCAS__s13207__part10;

architecture ISCAS__s13207__part10_behav of ISCAS__s13207__part10 is
begin
    n333 <= ( lo008 );
    n708 <= ( lo008 );
end ISCAS__s13207__part10_behav;
