--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part116 is 
  Port (
    lo210: in std_logic;
    po25: inout std_logic
  );
end Cookbook__gearbox_40_67__part116;

architecture Cookbook__gearbox_40_67__part116_behav of Cookbook__gearbox_40_67__part116 is
begin
    po25 <= ( lo210 );
end Cookbook__gearbox_40_67__part116_behav;
