--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1081 is 
  Port (
    lo1150: in std_logic;
    n6049: inout std_logic
  );
end Cookbook__fec_check__part1081;

architecture Cookbook__fec_check__part1081_behav of Cookbook__fec_check__part1081 is
begin
    n6049 <= ( lo1150 );
end Cookbook__fec_check__part1081_behav;
