--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1529 is 
  Port (
    lo1598: in std_logic;
    n8289: inout std_logic
  );
end Cookbook__fec_check__part1529;

architecture Cookbook__fec_check__part1529_behav of Cookbook__fec_check__part1529 is
begin
    n8289 <= ( lo1598 );
end Cookbook__fec_check__part1529_behav;
