--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part19 is 
  Port (
    lo18: in std_logic;
    po18: inout std_logic
  );
end Other__idxlat10n_m12__part19;

architecture Other__idxlat10n_m12__part19_behav of Other__idxlat10n_m12__part19 is
begin
    po18 <= ( lo18 );
end Other__idxlat10n_m12__part19_behav;
