--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part53 is 
  Port (
    pi053: in std_logic;
    n2492_1: inout std_logic
  );
end Other__fpu__part53;

architecture Other__fpu__part53_behav of Other__fpu__part53 is
begin
    n2492_1 <= ( pi053 );
end Other__fpu__part53_behav;
