--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2015 is 
  Port (
    lo4511: in std_logic;
    n27136: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2015;

architecture Other__ucsb_152_tap_fir__part2015_behav of Other__ucsb_152_tap_fir__part2015 is
begin
    n27136 <= ( lo4511 );
end Other__ucsb_152_tap_fir__part2015_behav;
