--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part47 is 
  Port (
    pi0535: in std_logic;
    n20354: inout std_logic
  );
end Other__carpat__part47;

architecture Other__carpat__part47_behav of Other__carpat__part47 is
begin
    n20354 <= ( pi0535 );
end Other__carpat__part47_behav;
