--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part447 is 
  Port (
    lo3864: in std_logic;
    n19655: inout std_logic
  );
end IWLS2005__des_perf__part447;

architecture IWLS2005__des_perf__part447_behav of IWLS2005__des_perf__part447 is
begin
    n19655 <= ( lo3864 );
end IWLS2005__des_perf__part447_behav;
