--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part41 is 
  Port (
    lo40: in std_logic;
    po40: inout std_logic
  );
end Other__idxlat02n_m12__part41;

architecture Other__idxlat02n_m12__part41_behav of Other__idxlat02n_m12__part41 is
begin
    po40 <= ( lo40 );
end Other__idxlat02n_m12__part41_behav;
