--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part19 is 
  Port (
    lo0017: in std_logic;
    po0021: inout std_logic
  );
end Other__ether__part19;

architecture Other__ether__part19_behav of Other__ether__part19 is
begin
    po0021 <= ( lo0017 );
end Other__ether__part19_behav;
