--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__clock_mux__part3 is 
  Port (
    lo03: in std_logic;
    n39: inout std_logic
  );
end Cookbook__clock_mux__part3;

architecture Cookbook__clock_mux__part3_behav of Cookbook__clock_mux__part3 is
begin
    n39 <= ( lo03 );
end Cookbook__clock_mux__part3_behav;
