--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part340 is 
  Port (
    lo0409: in std_logic;
    n2344: inout std_logic
  );
end Cookbook__fec_check__part340;

architecture Cookbook__fec_check__part340_behav of Cookbook__fec_check__part340 is
begin
    n2344 <= ( lo0409 );
end Cookbook__fec_check__part340_behav;
