--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1316 is 
  Port (
    lo3036: in std_logic;
    n19676: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1316;

architecture Other__ucsb_152_tap_fir__part1316_behav of Other__ucsb_152_tap_fir__part1316 is
begin
    n19676 <= ( lo3036 );
end Other__ucsb_152_tap_fir__part1316_behav;
