--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1303 is 
  Port (
    lo1372: in std_logic;
    n7159: inout std_logic
  );
end Cookbook__fec_check__part1303;

architecture Cookbook__fec_check__part1303_behav of Cookbook__fec_check__part1303 is
begin
    n7159 <= ( lo1372 );
end Cookbook__fec_check__part1303_behav;
