--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part290 is 
  Port (
    pi1571: in std_logic;
    n46729_1: inout std_logic
  );
end Other__carpat__part290;

architecture Other__carpat__part290_behav of Other__carpat__part290 is
begin
    n46729_1 <= ( pi1571 );
end Other__carpat__part290_behav;
