--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1050 is 
  Port (
    lo1119: in std_logic;
    n5894: inout std_logic
  );
end Cookbook__fec_check__part1050;

architecture Cookbook__fec_check__part1050_behav of Cookbook__fec_check__part1050 is
begin
    n5894 <= ( lo1119 );
end Cookbook__fec_check__part1050_behav;
