--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part749 is 
  Port (
    lo3398: in std_logic;
    n12409: inout std_logic
  );
end Other__sudoku_check__part749;

architecture Other__sudoku_check__part749_behav of Other__sudoku_check__part749 is
begin
    n12409 <= ( lo3398 );
end Other__sudoku_check__part749_behav;
