--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part127 is 
  Port (
    lo0436: in std_logic;
    n3289: inout std_logic
  );
end Cookbook__ucrypt__part127;

architecture Cookbook__ucrypt__part127_behav of Cookbook__ucrypt__part127 is
begin
    n3289 <= ( lo0436 );
end Cookbook__ucrypt__part127_behav;
