--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1865 is 
  Port (
    lo1934: in std_logic;
    n9969: inout std_logic
  );
end Cookbook__fec_check__part1865;

architecture Cookbook__fec_check__part1865_behav of Cookbook__fec_check__part1865 is
begin
    n9969 <= ( lo1934 );
end Cookbook__fec_check__part1865_behav;
