--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part55 is 
  Port (
    lo149302,lo149348,lo149341: in std_logic;
    n746492,n746727,n746922: inout std_logic
  );
end IWLS2005__leon2__part55;

architecture IWLS2005__leon2__part55_behav of IWLS2005__leon2__part55 is
signal n953608: std_logic;
begin
    n746492 <= ( not n953608 and lo149302 );
    n953608 <= not (( lo149348 and lo149341 ));
    n746727 <= ( lo149341 );
    n746922 <= ( lo149348 );
end IWLS2005__leon2__part55_behav;
