--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part49 is 
  Port (
    pi55: in std_logic;
    n869446: inout std_logic
  );
end IWLS2005__leon3__part49;

architecture IWLS2005__leon3__part49_behav of IWLS2005__leon3__part49 is
begin
    n869446 <= ( pi55 );
end IWLS2005__leon3__part49_behav;
