--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part453 is 
  Port (
    lo05925: in std_logic;
    po1391,po1456,po1722,po1791: inout std_logic
  );
end Other__ray__part453;

architecture Other__ray__part453_behav of Other__ray__part453 is
begin
    po1391 <= ( lo05925 );
    po1456 <= ( lo05925 );
    po1722 <= ( lo05925 );
    po1791 <= ( lo05925 );
end Other__ray__part453_behav;
