--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1854 is 
  Port (
    lo1923: in std_logic;
    n9914: inout std_logic
  );
end Cookbook__fec_check__part1854;

architecture Cookbook__fec_check__part1854_behav of Cookbook__fec_check__part1854 is
begin
    n9914 <= ( lo1923 );
end Cookbook__fec_check__part1854_behav;
