--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1036 is 
  Port (
    lo5068: in std_logic;
    n25435: inout std_logic
  );
end IWLS2005__des_perf__part1036;

architecture IWLS2005__des_perf__part1036_behav of IWLS2005__des_perf__part1036 is
begin
    n25435 <= ( lo5068 );
end IWLS2005__des_perf__part1036_behav;
