--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part470 is 
  Port (
    lo1337: in std_logic;
    n10134: inout std_logic
  );
end Other__carpat__part470;

architecture Other__carpat__part470_behav of Other__carpat__part470 is
begin
    n10134 <= ( lo1337 );
end Other__carpat__part470_behav;
