--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2143 is 
  Port (
    lo2212: in std_logic;
    n11359: inout std_logic
  );
end Cookbook__fec_check__part2143;

architecture Cookbook__fec_check__part2143_behav of Cookbook__fec_check__part2143 is
begin
    n11359 <= ( lo2212 );
end Cookbook__fec_check__part2143_behav;
