--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part90 is 
  Port (
    pi0905: in std_logic;
    n31109: inout std_logic
  );
end Other__carpat__part90;

architecture Other__carpat__part90_behav of Other__carpat__part90 is
begin
    n31109 <= ( pi0905 );
end Other__carpat__part90_behav;
