--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1457 is 
  Port (
    lo3327: in std_logic;
    n21151: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1457;

architecture Other__ucsb_152_tap_fir__part1457_behav of Other__ucsb_152_tap_fir__part1457 is
begin
    n21151 <= ( lo3327 );
end Other__ucsb_152_tap_fir__part1457_behav;
