--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part508 is 
  Port (
    lo05980: in std_logic;
    po1495,po1529: inout std_logic
  );
end Other__ray__part508;

architecture Other__ray__part508_behav of Other__ray__part508 is
begin
    po1495 <= ( lo05980 );
    po1529 <= ( lo05980 );
end Other__ray__part508_behav;
