--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part683 is 
  Port (
    lo4360: in std_logic;
    n22115: inout std_logic
  );
end IWLS2005__des_perf__part683;

architecture IWLS2005__des_perf__part683_behav of IWLS2005__des_perf__part683 is
begin
    n22115 <= ( lo4360 );
end IWLS2005__des_perf__part683_behav;
