--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part77 is 
  Port (
    lo063: in std_logic;
    po203: inout std_logic
  );
end Cookbook__lc_mult_signed__part77;

architecture Cookbook__lc_mult_signed__part77_behav of Cookbook__lc_mult_signed__part77 is
begin
    po203 <= ( lo063 );
end Cookbook__lc_mult_signed__part77_behav;
