--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2216 is 
  Port (
    lo7407: in std_logic;
    n37025_1: inout std_logic
  );
end IWLS2005__des_perf__part2216;

architecture IWLS2005__des_perf__part2216_behav of IWLS2005__des_perf__part2216 is
begin
    n37025_1 <= ( lo7407 );
end IWLS2005__des_perf__part2216_behav;
