--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s1238__part1 is 
  Port (
    lo12: in std_logic;
    po05: inout std_logic
  );
end ISCAS__s1238__part1;

architecture ISCAS__s1238__part1_behav of ISCAS__s1238__part1 is
begin
    po05 <= ( not lo12 );
end ISCAS__s1238__part1_behav;
