--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part38 is 
  Port (
    lo0071: in std_logic;
    po051: inout std_logic
  );
end Other__fp_operators__part38;

architecture Other__fp_operators__part38_behav of Other__fp_operators__part38 is
begin
    po051 <= ( lo0071 );
end Other__fp_operators__part38_behav;
