--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__frequency_monitor__part11 is 
  Port (
    lo118: in std_logic;
    n756: inout std_logic
  );
end Cookbook__frequency_monitor__part11;

architecture Cookbook__frequency_monitor__part11_behav of Cookbook__frequency_monitor__part11 is
begin
    n756 <= ( lo118 );
end Cookbook__frequency_monitor__part11_behav;
