--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part984 is 
  Port (
    lo10681: in std_logic;
    n71516_1: inout std_logic
  );
end Other__ray__part984;

architecture Other__ray__part984_behav of Other__ray__part984 is
begin
    n71516_1 <= ( lo10681 );
end Other__ray__part984_behav;
