--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1434 is 
  Port (
    lo3291: in std_logic;
    n21036: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1434;

architecture Other__ucsb_152_tap_fir__part1434_behav of Other__ucsb_152_tap_fir__part1434 is
begin
    n21036 <= ( lo3291 );
end Other__ucsb_152_tap_fir__part1434_behav;
