--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2898 is 
  Port (
    lo8211: in std_logic;
    n41325_1: inout std_logic
  );
end IWLS2005__des_perf__part2898;

architecture IWLS2005__des_perf__part2898_behav of IWLS2005__des_perf__part2898 is
begin
    n41325_1 <= ( lo8211 );
end IWLS2005__des_perf__part2898_behav;
