--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__c7552__part1 is 
  Port (
    pi020,pi001,pi164,pi067,pi066: in std_logic;
    po01,po06,po08,po09,po11: inout std_logic
  );
end ISCAS__c7552__part1;

architecture ISCAS__c7552__part1_behav of ISCAS__c7552__part1 is
signal n326: std_logic;
begin
    po01 <= not (( not pi020 and not pi001 ));
    po06 <= not (( pi164 and not pi001 ));
    po08 <= not (( pi164 and not pi001 ));
    po09 <= not (( n326 and not pi001 ));
    n326 <= ( pi067 and pi066 );
    po11 <= not (( n326 and not pi001 ));
end ISCAS__c7552__part1_behav;
