--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part397 is 
  Port (
    lo1396: in std_logic;
    n8239_1: inout std_logic
  );
end Cookbook__ucrypt__part397;

architecture Cookbook__ucrypt__part397_behav of Cookbook__ucrypt__part397 is
begin
    n8239_1 <= ( lo1396 );
end Cookbook__ucrypt__part397_behav;
