--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2055 is 
  Port (
    lo4586: in std_logic;
    n27511: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2055;

architecture Other__ucsb_152_tap_fir__part2055_behav of Other__ucsb_152_tap_fir__part2055 is
begin
    n27511 <= ( lo4586 );
end Other__ucsb_152_tap_fir__part2055_behav;
