--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1186 is 
  Port (
    lo2737: in std_logic;
    n18276: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1186;

architecture Other__ucsb_152_tap_fir__part1186_behav of Other__ucsb_152_tap_fir__part1186 is
begin
    n18276 <= ( lo2737 );
end Other__ucsb_152_tap_fir__part1186_behav;
