--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1680 is 
  Port (
    lo3800: in std_logic;
    n23576: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1680;

architecture Other__ucsb_152_tap_fir__part1680_behav of Other__ucsb_152_tap_fir__part1680 is
begin
    n23576 <= ( lo3800 );
end Other__ucsb_152_tap_fir__part1680_behav;
