--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1286 is 
  Port (
    lo4655: in std_logic;
    n18764: inout std_logic
  );
end Other__sudoku_check__part1286;

architecture Other__sudoku_check__part1286_behav of Other__sudoku_check__part1286 is
begin
    n18764 <= ( lo4655 );
end Other__sudoku_check__part1286_behav;
