--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat03n_m12__part23 is 
  Port (
    lo22: in std_logic;
    po22: inout std_logic
  );
end Other__idxlat03n_m12__part23;

architecture Other__idxlat03n_m12__part23_behav of Other__idxlat03n_m12__part23 is
begin
    po22 <= ( lo22 );
end Other__idxlat03n_m12__part23_behav;
