--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1427 is 
  Port (
    lo3257: in std_logic;
    n20856: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1427;

architecture Other__ucsb_152_tap_fir__part1427_behav of Other__ucsb_152_tap_fir__part1427 is
begin
    n20856 <= ( lo3257 );
end Other__ucsb_152_tap_fir__part1427_behav;
