--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part37 is 
  Port (
    lo0106: in std_logic;
    n829: inout std_logic
  );
end Cookbook__fec_check__part37;

architecture Cookbook__fec_check__part37_behav of Cookbook__fec_check__part37 is
begin
    n829 <= ( lo0106 );
end Cookbook__fec_check__part37_behav;
