--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__mem__part77 is 
  Port (
    lo1217: in std_logic;
    n6141_1: inout std_logic
  );
end Other__mem__part77;

architecture Other__mem__part77_behav of Other__mem__part77 is
begin
    n6141_1 <= ( lo1217 );
end Other__mem__part77_behav;
