--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_66_40__part8 is 
  Port (
    lo013: in std_logic;
    po35: inout std_logic
  );
end Cookbook__gearbox_66_40__part8;

architecture Cookbook__gearbox_66_40__part8_behav of Cookbook__gearbox_66_40__part8 is
begin
    po35 <= ( lo013 );
end Cookbook__gearbox_66_40__part8_behav;
