--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part284 is 
  Port (
    pi1565: in std_logic;
    n46699_1: inout std_logic
  );
end Other__carpat__part284;

architecture Other__carpat__part284_behav of Other__carpat__part284 is
begin
    n46699_1 <= ( pi1565 );
end Other__carpat__part284_behav;
