--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part22 is 
  Port (
    lo18: in std_logic;
    po11: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part22;

architecture Cookbook__x4_encoder_8b10b__part22_behav of Cookbook__x4_encoder_8b10b__part22 is
begin
    po11 <= ( lo18 );
end Cookbook__x4_encoder_8b10b__part22_behav;
