--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part673 is 
  Port (
    lo06170: in std_logic;
    po1831,po1926: inout std_logic
  );
end Other__ray__part673;

architecture Other__ray__part673_behav of Other__ray__part673 is
begin
    po1831 <= ( lo06170 );
    po1926 <= ( lo06170 );
end Other__ray__part673_behav;
