--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part17 is 
  Port (
    pi083: in std_logic;
    n5789_1: inout std_logic
  );
end IWLS2005__mem_ctrl__part17;

architecture IWLS2005__mem_ctrl__part17_behav of IWLS2005__mem_ctrl__part17 is
begin
    n5789_1 <= ( pi083 );
end IWLS2005__mem_ctrl__part17_behav;
