--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part45 is 
  Port (
    pi045: in std_logic;
    n2452_1: inout std_logic
  );
end Other__fpu__part45;

architecture Other__fpu__part45_behav of Other__fpu__part45 is
begin
    n2452_1 <= ( pi045 );
end Other__fpu__part45_behav;
