--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2743 is 
  Port (
    lo8056: in std_logic;
    n40700_1: inout std_logic
  );
end IWLS2005__des_perf__part2743;

architecture IWLS2005__des_perf__part2743_behav of IWLS2005__des_perf__part2743 is
begin
    n40700_1 <= ( lo8056 );
end IWLS2005__des_perf__part2743_behav;
