--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_rx__part10 is 
  Port (
    pi10: in std_logic;
    n235: inout std_logic
  );
end Cookbook__lane_rx__part10;

architecture Cookbook__lane_rx__part10_behav of Cookbook__lane_rx__part10 is
begin
    n235 <= ( pi10 );
end Cookbook__lane_rx__part10_behav;
