--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part663 is 
  Port (
    lo5183: in std_logic;
    n23449: inout std_logic
  );
end Other__carpat__part663;

architecture Other__carpat__part663_behav of Other__carpat__part663 is
begin
    n23449 <= ( lo5183 );
end Other__carpat__part663_behav;
