--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part614 is 
  Port (
    lo4229: in std_logic;
    n21035: inout std_logic
  );
end IWLS2005__des_perf__part614;

architecture IWLS2005__des_perf__part614_behav of IWLS2005__des_perf__part614 is
begin
    n21035 <= ( lo4229 );
end IWLS2005__des_perf__part614_behav;
