--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_16bit__part23 is 
  Port (
    lo65: in std_logic;
    po31: inout std_logic
  );
end Cookbook__soft_ecc_ram_16bit__part23;

architecture Cookbook__soft_ecc_ram_16bit__part23_behav of Cookbook__soft_ecc_ram_16bit__part23 is
begin
    po31 <= ( lo65 );
end Cookbook__soft_ecc_ram_16bit__part23_behav;
