--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ternary_sum_nine__part15 is 
  Port (
    lo41: in std_logic;
    po00: inout std_logic
  );
end Cookbook__ternary_sum_nine__part15;

architecture Cookbook__ternary_sum_nine__part15_behav of Cookbook__ternary_sum_nine__part15 is
begin
    po00 <= ( lo41 );
end Cookbook__ternary_sum_nine__part15_behav;
