--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part85 is 
  Port (
    pi0886: in std_logic;
    n31159: inout std_logic
  );
end Other__carpat__part85;

architecture Other__carpat__part85_behav of Other__carpat__part85 is
begin
    n31159 <= ( pi0886 );
end Other__carpat__part85_behav;
