--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part113 is 
  Port (
    lo362: in std_logic;
    po114: inout std_logic
  );
end IWLS2005__aes_core__part113;

architecture IWLS2005__aes_core__part113_behav of IWLS2005__aes_core__part113 is
begin
    po114 <= ( lo362 );
end IWLS2005__aes_core__part113_behav;
