--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part221 is 
  Port (
    lo2870: in std_logic;
    n7129: inout std_logic
  );
end Other__sudoku_check__part221;

architecture Other__sudoku_check__part221_behav of Other__sudoku_check__part221 is
begin
    n7129 <= ( lo2870 );
end Other__sudoku_check__part221_behav;
