--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part26 is 
  Port (
    pi026: in std_logic;
    n9779_1: inout std_logic
  );
end Other__desperf__part26;

architecture Other__desperf__part26_behav of Other__desperf__part26 is
begin
    n9779_1 <= ( pi026 );
end Other__desperf__part26_behav;
