--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part419 is 
  Port (
    lo2278: in std_logic;
    n11240: inout std_logic
  );
end IWLS2005__des_perf__part419;

architecture IWLS2005__des_perf__part419_behav of IWLS2005__des_perf__part419 is
begin
    n11240 <= ( lo2278 );
end IWLS2005__des_perf__part419_behav;
