--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1405 is 
  Port (
    lo4774: in std_logic;
    n19359: inout std_logic
  );
end Other__sudoku_check__part1405;

architecture Other__sudoku_check__part1405_behav of Other__sudoku_check__part1405 is
begin
    n19359 <= ( lo4774 );
end Other__sudoku_check__part1405_behav;
