--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part53 is 
  Port (
    lo067: in std_logic;
    po26: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part53;

architecture Cookbook__approx_fp_invsqrt__part53_behav of Cookbook__approx_fp_invsqrt__part53 is
begin
    po26 <= ( lo067 );
end Cookbook__approx_fp_invsqrt__part53_behav;
