--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_20_22__part0 is 
  Port (
    pi21,lo00,pi00,pi20,pi19,pi18,pi17,pi16,pi15,pi14,pi13,pi12,pi11,pi10,pi09,pi08,pi07,pi06,pi05,pi04,pi03,pi02: in std_logic;
    n436,n441_1,n446,n451_1,n456_1,n461_1,n466_1,n471_1,n476_1,n481_1,n486_1,n491_1,n496_1,n501_1,n506_1,n511_1,n516_1,n521_1,n526,n531_1,n91: inout std_logic
  );
end Cookbook__gearbox_20_22__part0;

architecture Cookbook__gearbox_20_22__part0_behav of Cookbook__gearbox_20_22__part0 is
begin
    n436 <= ( pi21 and not pi00 )
      or ( lo00 and pi00 );
    n441_1 <= ( pi20 and not pi00 )
      or ( pi21 and pi00 );
    n446 <= ( pi19 and not pi00 )
      or ( pi20 and pi00 );
    n451_1 <= ( pi18 and not pi00 )
      or ( pi19 and pi00 );
    n456_1 <= ( pi17 and not pi00 )
      or ( pi18 and pi00 );
    n461_1 <= ( pi16 and not pi00 )
      or ( pi17 and pi00 );
    n466_1 <= ( pi15 and not pi00 )
      or ( pi16 and pi00 );
    n471_1 <= ( pi14 and not pi00 )
      or ( pi15 and pi00 );
    n476_1 <= ( pi13 and not pi00 )
      or ( pi14 and pi00 );
    n481_1 <= ( pi12 and not pi00 )
      or ( pi13 and pi00 );
    n486_1 <= ( pi11 and not pi00 )
      or ( pi12 and pi00 );
    n491_1 <= ( pi10 and not pi00 )
      or ( pi11 and pi00 );
    n496_1 <= ( pi09 and not pi00 )
      or ( pi10 and pi00 );
    n501_1 <= ( pi08 and not pi00 )
      or ( pi09 and pi00 );
    n506_1 <= ( pi07 and not pi00 )
      or ( pi08 and pi00 );
    n511_1 <= ( pi06 and not pi00 )
      or ( pi07 and pi00 );
    n516_1 <= ( pi05 and not pi00 )
      or ( pi06 and pi00 );
    n521_1 <= ( pi04 and not pi00 )
      or ( pi05 and pi00 );
    n526 <= ( pi03 and not pi00 )
      or ( pi04 and pi00 );
    n531_1 <= ( pi02 and not pi00 )
      or ( pi03 and pi00 );
    n91 <= ( lo00 and not pi00 )
      or ( pi02 and pi00 );
end Cookbook__gearbox_20_22__part0_behav;
