--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1469 is 
  Port (
    lo3383: in std_logic;
    n21421: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1469;

architecture Other__ucsb_152_tap_fir__part1469_behav of Other__ucsb_152_tap_fir__part1469 is
begin
    n21421 <= ( lo3383 );
end Other__ucsb_152_tap_fir__part1469_behav;
