--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part70 is 
  Port (
    lo0651: in std_logic;
    n4244: inout std_logic
  );
end ISCAS__s38417__part70;

architecture ISCAS__s38417__part70_behav of ISCAS__s38417__part70 is
begin
    n4244 <= ( not lo0651 );
end ISCAS__s38417__part70_behav;
