--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1466 is 
  Port (
    lo4835: in std_logic;
    n19664_1: inout std_logic
  );
end Other__sudoku_check__part1466;

architecture Other__sudoku_check__part1466_behav of Other__sudoku_check__part1466 is
begin
    n19664_1 <= ( lo4835 );
end Other__sudoku_check__part1466_behav;
