--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1596 is 
  Port (
    lo1665: in std_logic;
    n8624: inout std_logic
  );
end Cookbook__fec_check__part1596;

architecture Cookbook__fec_check__part1596_behav of Cookbook__fec_check__part1596 is
begin
    n8624 <= ( lo1665 );
end Cookbook__fec_check__part1596_behav;
