--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1635 is 
  Port (
    lo8427: in std_logic;
    n47034_1: inout std_logic
  );
end Other__carpat__part1635;

architecture Other__carpat__part1635_behav of Other__carpat__part1635 is
begin
    n47034_1 <= ( lo8427 );
end Other__carpat__part1635_behav;
