--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part111 is 
  Port (
    lo0213: in std_logic;
    n5506: inout std_logic
  );
end Other__ucsb_152_tap_fir__part111;

architecture Other__ucsb_152_tap_fir__part111_behav of Other__ucsb_152_tap_fir__part111 is
begin
    n5506 <= ( lo0213 );
end Other__ucsb_152_tap_fir__part111_behav;
