--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1987 is 
  Port (
    lo2056: in std_logic;
    n10579: inout std_logic
  );
end Cookbook__fec_check__part1987;

architecture Cookbook__fec_check__part1987_behav of Cookbook__fec_check__part1987 is
begin
    n10579 <= ( lo2056 );
end Cookbook__fec_check__part1987_behav;
