--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part68 is 
  Port (
    lo037: in std_logic;
    n669: inout std_logic
  );
end Cookbook__gearbox_40_67__part68;

architecture Cookbook__gearbox_40_67__part68_behav of Cookbook__gearbox_40_67__part68 is
begin
    n669 <= ( lo037 );
end Cookbook__gearbox_40_67__part68_behav;
