--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1854 is 
  Port (
    lo9127: in std_logic;
    po491: inout std_logic
  );
end Other__carpat__part1854;

architecture Other__carpat__part1854_behav of Other__carpat__part1854 is
begin
    po491 <= ( lo9127 );
end Other__carpat__part1854_behav;
