--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part72 is 
  Port (
    lo71: in std_logic;
    po71: inout std_logic
  );
end Other__idxlat01n_m12__part72;

architecture Other__idxlat01n_m12__part72_behav of Other__idxlat01n_m12__part72 is
begin
    po71 <= ( lo71 );
end Other__idxlat01n_m12__part72_behav;
