--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_decoder_8b10b__part20 is 
  Port (
    lo19: in std_logic;
    po09: inout std_logic
  );
end Cookbook__x4_decoder_8b10b__part20;

architecture Cookbook__x4_decoder_8b10b__part20_behav of Cookbook__x4_decoder_8b10b__part20 is
begin
    po09 <= ( lo19 );
end Cookbook__x4_decoder_8b10b__part20_behav;
