--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part854 is 
  Port (
    lo0923: in std_logic;
    n4914: inout std_logic
  );
end Cookbook__fec_check__part854;

architecture Cookbook__fec_check__part854_behav of Cookbook__fec_check__part854 is
begin
    n4914 <= ( lo0923 );
end Cookbook__fec_check__part854_behav;
