--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1183 is 
  Port (
    lo4552: in std_logic;
    n18249: inout std_logic
  );
end Other__sudoku_check__part1183;

architecture Other__sudoku_check__part1183_behav of Other__sudoku_check__part1183 is
begin
    n18249 <= ( lo4552 );
end Other__sudoku_check__part1183_behav;
