--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part338 is 
  Port (
    pi1670: in std_logic;
    n47934_1: inout std_logic
  );
end Other__carpat__part338;

architecture Other__carpat__part338_behav of Other__carpat__part338 is
begin
    n47934_1 <= ( pi1670 );
end Other__carpat__part338_behav;
