--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1079 is 
  Port (
    lo7172: in std_logic;
    n38234_1: inout std_logic
  );
end Other__carpat__part1079;

architecture Other__carpat__part1079_behav of Other__carpat__part1079 is
begin
    n38234_1 <= ( lo7172 );
end Other__carpat__part1079_behav;
