--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1370 is 
  Port (
    lo4739: in std_logic;
    n19184: inout std_logic
  );
end Other__sudoku_check__part1370;

architecture Other__sudoku_check__part1370_behav of Other__sudoku_check__part1370 is
begin
    n19184 <= ( lo4739 );
end Other__sudoku_check__part1370_behav;
