--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part418 is 
  Port (
    lo05890: in std_logic;
    po1307,po1341: inout std_logic
  );
end Other__ray__part418;

architecture Other__ray__part418_behav of Other__ray__part418 is
begin
    po1307 <= ( lo05890 );
    po1341 <= ( lo05890 );
end Other__ray__part418_behav;
