--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1431 is 
  Port (
    lo7881: in std_logic;
    n44284_1: inout std_logic
  );
end Other__carpat__part1431;

architecture Other__carpat__part1431_behav of Other__carpat__part1431 is
begin
    n44284_1 <= ( lo7881 );
end Other__carpat__part1431_behav;
