--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part83 is 
  Port (
    lo0269: in std_logic;
    n3945: inout std_logic
  );
end Other__fp_operators__part83;

architecture Other__fp_operators__part83_behav of Other__fp_operators__part83 is
begin
    n3945 <= ( lo0269 );
end Other__fp_operators__part83_behav;
