--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1020 is 
  Port (
    lo2413: in std_logic;
    n16646: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1020;

architecture Other__ucsb_152_tap_fir__part1020_behav of Other__ucsb_152_tap_fir__part1020 is
begin
    n16646 <= ( lo2413 );
end Other__ucsb_152_tap_fir__part1020_behav;
