--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part162 is 
  Port (
    lo0563: in std_logic;
    n3924: inout std_logic
  );
end Cookbook__ucrypt__part162;

architecture Cookbook__ucrypt__part162_behav of Cookbook__ucrypt__part162 is
begin
    n3924 <= ( lo0563 );
end Cookbook__ucrypt__part162_behav;
