--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2544 is 
  Port (
    lo7801: in std_logic;
    n38850_1: inout std_logic
  );
end IWLS2005__des_perf__part2544;

architecture IWLS2005__des_perf__part2544_behav of IWLS2005__des_perf__part2544 is
begin
    n38850_1 <= ( lo7801 );
end IWLS2005__des_perf__part2544_behav;
