--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part97 is 
  Port (
    lo083: in std_logic;
    po183: inout std_logic
  );
end Cookbook__lc_mult_signed__part97;

architecture Cookbook__lc_mult_signed__part97_behav of Cookbook__lc_mult_signed__part97 is
begin
    po183 <= ( lo083 );
end Cookbook__lc_mult_signed__part97_behav;
