--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part55 is 
  Port (
    lo0881: in std_logic;
    n6158_1: inout std_logic
  );
end Other__ether__part55;

architecture Other__ether__part55_behav of Other__ether__part55 is
begin
    n6158_1 <= ( lo0881 );
end Other__ether__part55_behav;
