--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part239 is 
  Port (
    pi1353: in std_logic;
    n33344_1: inout std_logic
  );
end Other__carpat__part239;

architecture Other__carpat__part239_behav of Other__carpat__part239 is
begin
    n33344_1 <= ( pi1353 );
end Other__carpat__part239_behav;
