--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1744 is 
  Port (
    lo8812: in std_logic;
    po267: inout std_logic
  );
end Other__carpat__part1744;

architecture Other__carpat__part1744_behav of Other__carpat__part1744 is
begin
    po267 <= ( lo8812 );
end Other__carpat__part1744_behav;
