--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part161 is 
  Port (
    lo0571: in std_logic;
    n5450: inout std_logic
  );
end Other__fp_operators__part161;

architecture Other__fp_operators__part161_behav of Other__fp_operators__part161 is
begin
    n5450 <= ( lo0571 );
end Other__fp_operators__part161_behav;
