--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s9234__part9 is 
  Port (
    lo143: in std_logic;
    n793: inout std_logic
  );
end ISCAS__s9234__part9;

architecture ISCAS__s9234__part9_behav of ISCAS__s9234__part9 is
begin
    n793 <= ( lo143 );
end ISCAS__s9234__part9_behav;
