--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1980 is 
  Port (
    lo4407: in std_logic;
    n26536: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1980;

architecture Other__ucsb_152_tap_fir__part1980_behav of Other__ucsb_152_tap_fir__part1980 is
begin
    n26536 <= ( lo4407 );
end Other__ucsb_152_tap_fir__part1980_behav;
