--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3301 is 
  Port (
    lo8670: in std_logic;
    n43440_1: inout std_logic
  );
end IWLS2005__des_perf__part3301;

architecture IWLS2005__des_perf__part3301_behav of IWLS2005__des_perf__part3301 is
begin
    n43440_1 <= ( lo8670 );
end IWLS2005__des_perf__part3301_behav;
