--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1565 is 
  Port (
    lo3536: in std_logic;
    n22261: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1565;

architecture Other__ucsb_152_tap_fir__part1565_behav of Other__ucsb_152_tap_fir__part1565 is
begin
    n22261 <= ( lo3536 );
end Other__ucsb_152_tap_fir__part1565_behav;
