--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part48 is 
  Port (
    pi0536: in std_logic;
    n20364: inout std_logic
  );
end Other__carpat__part48;

architecture Other__carpat__part48_behav of Other__carpat__part48 is
begin
    n20364 <= ( pi0536 );
end Other__carpat__part48_behav;
