--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part814 is 
  Port (
    lo6427: in std_logic;
    n30399: inout std_logic
  );
end Other__carpat__part814;

architecture Other__carpat__part814_behav of Other__carpat__part814 is
begin
    n30399 <= ( lo6427 );
end Other__carpat__part814_behav;
