--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1416 is 
  Port (
    lo7866: in std_logic;
    n44209_1: inout std_logic
  );
end Other__carpat__part1416;

architecture Other__carpat__part1416_behav of Other__carpat__part1416 is
begin
    n44209_1 <= ( lo7866 );
end Other__carpat__part1416_behav;
