--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1074 is 
  Port (
    lo4443: in std_logic;
    n17704: inout std_logic
  );
end Other__sudoku_check__part1074;

architecture Other__sudoku_check__part1074_behav of Other__sudoku_check__part1074 is
begin
    n17704 <= ( lo4443 );
end Other__sudoku_check__part1074_behav;
