--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part200 is 
  Port (
    lo0087: in std_logic;
    n855: inout std_logic
  );
end IWLS2005__des_perf__part200;

architecture IWLS2005__des_perf__part200_behav of IWLS2005__des_perf__part200 is
begin
    n855 <= ( lo0087 );
end IWLS2005__des_perf__part200_behav;
