--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part499 is 
  Port (
    lo05971: in std_logic;
    po1486,po1551,po1843,po1912: inout std_logic
  );
end Other__ray__part499;

architecture Other__ray__part499_behav of Other__ray__part499 is
begin
    po1486 <= ( lo05971 );
    po1551 <= ( lo05971 );
    po1843 <= ( lo05971 );
    po1912 <= ( lo05971 );
end Other__ray__part499_behav;
