--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part97 is 
  Port (
    lo0669: in std_logic;
    n3924: inout std_logic
  );
end IWLS93__s38417__part97;

architecture IWLS93__s38417__part97_behav of IWLS93__s38417__part97 is
begin
    n3924 <= ( lo0669 );
end IWLS93__s38417__part97_behav;
