--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1533 is 
  Port (
    lo5741,lo5742,lo5743,lo5744: in std_logic;
    n27354_1,n27919_1,n27924_1,n27929_1,n27934_1,n27939_1,n27944_1,n27949_1,n27954_1: inout std_logic
  );
end Other__sudoku_check__part1533;

architecture Other__sudoku_check__part1533_behav of Other__sudoku_check__part1533 is
begin
    n27354_1 <= ( lo5741 and not lo5742 and not lo5743 and not lo5744 );
    n27919_1 <= ( lo5741 and not lo5742 and not lo5743 and lo5744 );
    n27924_1 <= ( not lo5741 and not lo5742 and not lo5743 and lo5744 );
    n27929_1 <= ( lo5741 and lo5742 and lo5743 and not lo5744 );
    n27934_1 <= ( not lo5741 and lo5742 and lo5743 and not lo5744 );
    n27939_1 <= ( lo5741 and not lo5742 and lo5743 and not lo5744 );
    n27944_1 <= ( not lo5741 and not lo5742 and lo5743 and not lo5744 );
    n27949_1 <= ( lo5741 and lo5742 and not lo5743 and not lo5744 );
    n27954_1 <= ( not lo5741 and lo5742 and not lo5743 and not lo5744 );
end Other__sudoku_check__part1533_behav;
