--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1380 is 
  Port (
    lo1449: in std_logic;
    n7544: inout std_logic
  );
end Cookbook__fec_check__part1380;

architecture Cookbook__fec_check__part1380_behav of Cookbook__fec_check__part1380 is
begin
    n7544 <= ( lo1449 );
end Cookbook__fec_check__part1380_behav;
