--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part27 is 
  Port (
    lo0025: in std_logic;
    po0029: inout std_logic
  );
end Other__ether__part27;

architecture Other__ether__part27_behav of Other__ether__part27 is
begin
    po0029 <= ( lo0025 );
end Other__ether__part27_behav;
