--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part385 is 
  Port (
    lo3034: in std_logic;
    n8769: inout std_logic
  );
end Other__sudoku_check__part385;

architecture Other__sudoku_check__part385_behav of Other__sudoku_check__part385 is
begin
    n8769 <= ( lo3034 );
end Other__sudoku_check__part385_behav;
