--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part92 is 
  Port (
    lo0650: in std_logic;
    n5249_1: inout std_logic
  );
end IWLS93__s38417__part92;

architecture IWLS93__s38417__part92_behav of IWLS93__s38417__part92 is
begin
    n5249_1 <= ( not lo0650 );
end IWLS93__s38417__part92_behav;
