--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1902 is 
  Port (
    lo1971: in std_logic;
    n10154: inout std_logic
  );
end Cookbook__fec_check__part1902;

architecture Cookbook__fec_check__part1902_behav of Cookbook__fec_check__part1902 is
begin
    n10154 <= ( lo1971 );
end Cookbook__fec_check__part1902_behav;
