--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part571 is 
  Port (
    lo2130: in std_logic;
    n11869_1: inout std_logic
  );
end Cookbook__ucrypt__part571;

architecture Cookbook__ucrypt__part571_behav of Cookbook__ucrypt__part571 is
begin
    n11869_1 <= ( lo2130 );
end Cookbook__ucrypt__part571_behav;
