--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part143 is 
  Port (
    lo0023: in std_logic;
    po23: inout std_logic
  );
end Other__desperf__part143;

architecture Other__desperf__part143_behav of Other__desperf__part143 is
begin
    po23 <= ( lo0023 );
end Other__desperf__part143_behav;
