--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2783 is 
  Port (
    lo8096: in std_logic;
    n40785_1: inout std_logic
  );
end IWLS2005__des_perf__part2783;

architecture IWLS2005__des_perf__part2783_behav of IWLS2005__des_perf__part2783 is
begin
    n40785_1 <= ( lo8096 );
end IWLS2005__des_perf__part2783_behav;
