--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part33 is 
  Port (
    lo0121: in std_logic;
    po018: inout std_logic
  );
end IWLS2005__pci_bridge32__part33;

architecture IWLS2005__pci_bridge32__part33_behav of IWLS2005__pci_bridge32__part33 is
begin
    po018 <= ( lo0121 );
end IWLS2005__pci_bridge32__part33_behav;
