--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3081 is 
  Port (
    lo8394: in std_logic;
    n42180_1: inout std_logic
  );
end IWLS2005__des_perf__part3081;

architecture IWLS2005__des_perf__part3081_behav of IWLS2005__des_perf__part3081 is
begin
    n42180_1 <= ( lo8394 );
end IWLS2005__des_perf__part3081_behav;
