--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part526 is 
  Port (
    lo05998: in std_logic;
    po1513,po1562,po1872,po1934: inout std_logic
  );
end Other__ray__part526;

architecture Other__ray__part526_behav of Other__ray__part526 is
begin
    po1513 <= ( lo05998 );
    po1562 <= ( lo05998 );
    po1872 <= ( lo05998 );
    po1934 <= ( lo05998 );
end Other__ray__part526_behav;
