--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part79 is 
  Port (
    lo065: in std_logic;
    po201: inout std_logic
  );
end Cookbook__lc_mult_signed__part79;

architecture Cookbook__lc_mult_signed__part79_behav of Cookbook__lc_mult_signed__part79 is
begin
    po201 <= ( lo065 );
end Cookbook__lc_mult_signed__part79_behav;
