--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part79 is 
  Port (
    lo78: in std_logic;
    po78: inout std_logic
  );
end Other__idxlat10n_m12__part79;

architecture Other__idxlat10n_m12__part79_behav of Other__idxlat10n_m12__part79 is
begin
    po78 <= ( lo78 );
end Other__idxlat10n_m12__part79_behav;
