--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part119 is 
  Port (
    lo213: in std_logic;
    po22: inout std_logic
  );
end Cookbook__gearbox_40_67__part119;

architecture Cookbook__gearbox_40_67__part119_behav of Cookbook__gearbox_40_67__part119 is
begin
    po22 <= ( lo213 );
end Cookbook__gearbox_40_67__part119_behav;
