--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part56 is 
  Port (
    lo1410: in std_logic;
    n6689_1: inout std_logic
  );
end IWLS2005__usb_funct__part56;

architecture IWLS2005__usb_funct__part56_behav of IWLS2005__usb_funct__part56 is
begin
    n6689_1 <= ( lo1410 );
end IWLS2005__usb_funct__part56_behav;
