--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part844 is 
  Port (
    lo4653: in std_logic;
    n22955: inout std_logic
  );
end IWLS2005__des_perf__part844;

architecture IWLS2005__des_perf__part844_behav of IWLS2005__des_perf__part844 is
begin
    n22955 <= ( lo4653 );
end IWLS2005__des_perf__part844_behav;
