--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1441 is 
  Port (
    lo8072: in std_logic;
    n44409_1: inout std_logic
  );
end Other__carpat__part1441;

architecture Other__carpat__part1441_behav of Other__carpat__part1441 is
begin
    n44409_1 <= ( lo8072 );
end Other__carpat__part1441_behav;
