--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1083 is 
  Port (
    lo5159: in std_logic;
    n26010: inout std_logic
  );
end IWLS2005__des_perf__part1083;

architecture IWLS2005__des_perf__part1083_behav of IWLS2005__des_perf__part1083 is
begin
    n26010 <= ( lo5159 );
end IWLS2005__des_perf__part1083_behav;
