--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part355 is 
  Port (
    lo2116: in std_logic;
    n11050: inout std_logic
  );
end IWLS2005__des_perf__part355;

architecture IWLS2005__des_perf__part355_behav of IWLS2005__des_perf__part355 is
begin
    n11050 <= ( lo2116 );
end IWLS2005__des_perf__part355_behav;
