--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part76 is 
  Port (
    lo528: in std_logic;
    n2818: inout std_logic
  );
end Cookbook__lane_tx__part76;

architecture Cookbook__lane_tx__part76_behav of Cookbook__lane_tx__part76 is
begin
    n2818 <= ( lo528 );
end Cookbook__lane_tx__part76_behav;
