--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part38 is 
  Port (
    lo0107: in std_logic;
    n834: inout std_logic
  );
end Cookbook__fec_check__part38;

architecture Cookbook__fec_check__part38_behav of Cookbook__fec_check__part38 is
begin
    n834 <= ( lo0107 );
end Cookbook__fec_check__part38_behav;
