--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1775 is 
  Port (
    lo8870: in std_logic;
    po305: inout std_logic
  );
end Other__carpat__part1775;

architecture Other__carpat__part1775_behav of Other__carpat__part1775 is
begin
    po305 <= ( lo8870 );
end Other__carpat__part1775_behav;
