--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part46 is 
  Port (
    lo0956: in std_logic;
    po029: inout std_logic
  );
end IWLS2005__usb_funct__part46;

architecture IWLS2005__usb_funct__part46_behav of IWLS2005__usb_funct__part46 is
begin
    po029 <= ( lo0956 );
end IWLS2005__usb_funct__part46_behav;
