--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part128 is 
  Port (
    lo0008: in std_logic;
    po08: inout std_logic
  );
end Other__desperf__part128;

architecture Other__desperf__part128_behav of Other__desperf__part128 is
begin
    po08 <= ( lo0008 );
end Other__desperf__part128_behav;
