--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__compress_32__part7 is 
  Port (
    pi07,pi23,pi39: in std_logic;
    po07,po23: inout std_logic
  );
end Cookbook__compress_32__part7;

architecture Cookbook__compress_32__part7_behav of Cookbook__compress_32__part7 is
signal n88,n120,n136,n152,n168: std_logic;
begin
    n88 <= ( not pi07 and pi23 )
      or ( pi07 and not pi23 );
    po07 <= ( not n88 and pi39 )
      or ( n88 and not pi39 );
    n120 <= ( pi07 and pi39 );
    n136 <= ( pi07 and pi23 );
    n152 <= not (( not n136 and not n120 ));
    n168 <= ( pi23 and pi39 );
    po23 <= not (( not n152 and not n168 ));
end Cookbook__compress_32__part7_behav;
