--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1290 is 
  Port (
    lo4659: in std_logic;
    n18784: inout std_logic
  );
end Other__sudoku_check__part1290;

architecture Other__sudoku_check__part1290_behav of Other__sudoku_check__part1290 is
begin
    n18784 <= ( lo4659 );
end Other__sudoku_check__part1290_behav;
