--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part42 is 
  Port (
    pi042: in std_logic;
    n9859_1: inout std_logic
  );
end Other__desperf__part42;

architecture Other__desperf__part42_behav of Other__desperf__part42 is
begin
    n9859_1 <= ( pi042 );
end Other__desperf__part42_behav;
