--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1193 is 
  Port (
    lo4562: in std_logic;
    n18299: inout std_logic
  );
end Other__sudoku_check__part1193;

architecture Other__sudoku_check__part1193_behav of Other__sudoku_check__part1193 is
begin
    n18299 <= ( lo4562 );
end Other__sudoku_check__part1193_behav;
