--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__font_rom__part32 is 
  Port (
    lo21: in std_logic;
    po02: inout std_logic
  );
end Cookbook__font_rom__part32;

architecture Cookbook__font_rom__part32_behav of Cookbook__font_rom__part32 is
begin
    po02 <= ( lo21 );
end Cookbook__font_rom__part32_behav;
