--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1879 is 
  Port (
    lo6811: in std_logic;
    n34365_1: inout std_logic
  );
end IWLS2005__des_perf__part1879;

architecture IWLS2005__des_perf__part1879_behav of IWLS2005__des_perf__part1879 is
begin
    n34365_1 <= ( lo6811 );
end IWLS2005__des_perf__part1879_behav;
