--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part18 is 
  Port (
    lo0009: in std_logic;
    n1304: inout std_logic
  );
end Cookbook__ucrypt__part18;

architecture Cookbook__ucrypt__part18_behav of Cookbook__ucrypt__part18 is
begin
    n1304 <= ( lo0009 );
end Cookbook__ucrypt__part18_behav;
