--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1497 is 
  Port (
    lo8128: in std_logic;
    n44689_1: inout std_logic
  );
end Other__carpat__part1497;

architecture Other__carpat__part1497_behav of Other__carpat__part1497 is
begin
    n44689_1 <= ( lo8128 );
end Other__carpat__part1497_behav;
