--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part561 is 
  Port (
    lo3210: in std_logic;
    n10529: inout std_logic
  );
end Other__sudoku_check__part561;

architecture Other__sudoku_check__part561_behav of Other__sudoku_check__part561 is
begin
    n10529 <= ( lo3210 );
end Other__sudoku_check__part561_behav;
