--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1375 is 
  Port (
    lo1444: in std_logic;
    n7519: inout std_logic
  );
end Cookbook__fec_check__part1375;

architecture Cookbook__fec_check__part1375_behav of Cookbook__fec_check__part1375 is
begin
    n7519 <= ( lo1444 );
end Cookbook__fec_check__part1375_behav;
