--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part59 is 
  Port (
    lo135: in std_logic;
    po43: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part59;

architecture Cookbook__soft_ecc_ram_32bit__part59_behav of Cookbook__soft_ecc_ram_32bit__part59 is
begin
    po43 <= ( lo135 );
end Cookbook__soft_ecc_ram_32bit__part59_behav;
