--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part216 is 
  Port (
    lo0767: in std_logic;
    n5094: inout std_logic
  );
end Cookbook__ucrypt__part216;

architecture Cookbook__ucrypt__part216_behav of Cookbook__ucrypt__part216 is
begin
    n5094 <= ( lo0767 );
end Cookbook__ucrypt__part216_behav;
