--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1407 is 
  Port (
    lo3235: in std_logic;
    n20751: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1407;

architecture Other__ucsb_152_tap_fir__part1407_behav of Other__ucsb_152_tap_fir__part1407 is
begin
    n20751 <= ( lo3235 );
end Other__ucsb_152_tap_fir__part1407_behav;
