--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part494 is 
  Port (
    lo3143: in std_logic;
    n9859: inout std_logic
  );
end Other__sudoku_check__part494;

architecture Other__sudoku_check__part494_behav of Other__sudoku_check__part494 is
begin
    n9859 <= ( lo3143 );
end Other__sudoku_check__part494_behav;
