--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part180 is 
  Port (
    lo279: in std_logic;
    n907: inout std_logic
  );
end Other__fpu__part180;

architecture Other__fpu__part180_behav of Other__fpu__part180 is
begin
    n907 <= ( lo279 );
end Other__fpu__part180_behav;
