--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part432 is 
  Port (
    lo05904: in std_logic;
    po1321,po1370,po1628,po1690: inout std_logic
  );
end Other__ray__part432;

architecture Other__ray__part432_behav of Other__ray__part432 is
begin
    po1321 <= ( lo05904 );
    po1370 <= ( lo05904 );
    po1628 <= ( lo05904 );
    po1690 <= ( lo05904 );
end Other__ray__part432_behav;
