--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi70,pi71,pi72,pi73: in std_logic;
    po25: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po25 <= ( not pi70 )
      or ( not pi71 )
      or ( not pi72 )
      or ( not pi73 );
end top_behav;
