--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1808 is 
  Port (
    lo1877: in std_logic;
    n9684: inout std_logic
  );
end Cookbook__fec_check__part1808;

architecture Cookbook__fec_check__part1808_behav of Cookbook__fec_check__part1808 is
begin
    n9684 <= ( lo1877 );
end Cookbook__fec_check__part1808_behav;
