--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part29 is 
  Port (
    lo084: in std_logic;
    n718: inout std_logic
  );
end ISCAS__s13207__part29;

architecture ISCAS__s13207__part29_behav of ISCAS__s13207__part29 is
begin
    n718 <= ( lo084 );
end ISCAS__s13207__part29_behav;
