--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1421 is 
  Port (
    lo4790: in std_logic;
    n19439_1: inout std_logic
  );
end Other__sudoku_check__part1421;

architecture Other__sudoku_check__part1421_behav of Other__sudoku_check__part1421 is
begin
    n19439_1 <= ( lo4790 );
end Other__sudoku_check__part1421_behav;
