--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part277 is 
  Port (
    lo0940: in std_logic;
    n5959: inout std_logic
  );
end Cookbook__ucrypt__part277;

architecture Cookbook__ucrypt__part277_behav of Cookbook__ucrypt__part277 is
begin
    n5959 <= ( lo0940 );
end Cookbook__ucrypt__part277_behav;
