--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part247 is 
  Port (
    lo03530: in std_logic;
    n34991: inout std_logic
  );
end Other__ray__part247;

architecture Other__ray__part247_behav of Other__ray__part247 is
begin
    n34991 <= ( lo03530 );
end Other__ray__part247_behav;
