--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1359 is 
  Port (
    lo4728: in std_logic;
    n19129: inout std_logic
  );
end Other__sudoku_check__part1359;

architecture Other__sudoku_check__part1359_behav of Other__sudoku_check__part1359 is
begin
    n19129 <= ( lo4728 );
end Other__sudoku_check__part1359_behav;
