--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part345 is 
  Port (
    lo0414: in std_logic;
    n2369: inout std_logic
  );
end Cookbook__fec_check__part345;

architecture Cookbook__fec_check__part345_behav of Cookbook__fec_check__part345 is
begin
    n2369 <= ( lo0414 );
end Cookbook__fec_check__part345_behav;
