--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part726 is 
  Port (
    lo06406: in std_logic;
    n47961: inout std_logic
  );
end Other__ray__part726;

architecture Other__ray__part726_behav of Other__ray__part726 is
begin
    n47961 <= ( lo06406 );
end Other__ray__part726_behav;
