--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part477 is 
  Port (
    lo1700: in std_logic;
    n9759_1: inout std_logic
  );
end Cookbook__ucrypt__part477;

architecture Cookbook__ucrypt__part477_behav of Cookbook__ucrypt__part477 is
begin
    n9759_1 <= ( lo1700 );
end Cookbook__ucrypt__part477_behav;
