--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part103 is 
  Port (
    lo3252: in std_logic;
    n16714: inout std_logic
  );
end IWLS2005__pci_bridge32__part103;

architecture IWLS2005__pci_bridge32__part103_behav of IWLS2005__pci_bridge32__part103 is
begin
    n16714 <= ( lo3252 );
end IWLS2005__pci_bridge32__part103_behav;
