--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat01n_m12__part75 is 
  Port (
    lo74: in std_logic;
    po74: inout std_logic
  );
end Other__idxlat01n_m12__part75;

architecture Other__idxlat01n_m12__part75_behav of Other__idxlat01n_m12__part75 is
begin
    po74 <= ( lo74 );
end Other__idxlat01n_m12__part75_behav;
