--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part628 is 
  Port (
    lo4274: in std_logic;
    n21715: inout std_logic
  );
end IWLS2005__des_perf__part628;

architecture IWLS2005__des_perf__part628_behav of IWLS2005__des_perf__part628 is
begin
    n21715 <= ( lo4274 );
end IWLS2005__des_perf__part628_behav;
