--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1220 is 
  Port (
    lo4589: in std_logic;
    n18434: inout std_logic
  );
end Other__sudoku_check__part1220;

architecture Other__sudoku_check__part1220_behav of Other__sudoku_check__part1220 is
begin
    n18434 <= ( lo4589 );
end Other__sudoku_check__part1220_behav;
