--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part487 is 
  Port (
    lo3136: in std_logic;
    n9789: inout std_logic
  );
end Other__sudoku_check__part487;

architecture Other__sudoku_check__part487_behav of Other__sudoku_check__part487 is
begin
    n9789 <= ( lo3136 );
end Other__sudoku_check__part487_behav;
