--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part197 is 
  Port (
    lo0359: in std_logic;
    n1304: inout std_logic
  );
end Other__desperf__part197;

architecture Other__desperf__part197_behav of Other__desperf__part197 is
begin
    n1304 <= ( lo0359 );
end Other__desperf__part197_behav;
