--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2043 is 
  Port (
    lo4545: in std_logic;
    n27306: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2043;

architecture Other__ucsb_152_tap_fir__part2043_behav of Other__ucsb_152_tap_fir__part2043 is
begin
    n27306 <= ( lo4545 );
end Other__ucsb_152_tap_fir__part2043_behav;
