--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1400 is 
  Port (
    lo3223: in std_logic;
    n20701: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1400;

architecture Other__ucsb_152_tap_fir__part1400_behav of Other__ucsb_152_tap_fir__part1400 is
begin
    n20701 <= ( lo3223 );
end Other__ucsb_152_tap_fir__part1400_behav;
