--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1606 is 
  Port (
    lo8398: in std_logic;
    n46889_1: inout std_logic
  );
end Other__carpat__part1606;

architecture Other__carpat__part1606_behav of Other__carpat__part1606 is
begin
    n46889_1 <= ( lo8398 );
end Other__carpat__part1606_behav;
