--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part77 is 
  Port (
    pi1172: in std_logic;
    n71996_1: inout std_logic
  );
end Other__ray__part77;

architecture Other__ray__part77_behav of Other__ray__part77 is
begin
    n71996_1 <= ( pi1172 );
end Other__ray__part77_behav;
