--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1280 is 
  Port (
    lo5582: in std_logic;
    n27525_1: inout std_logic
  );
end IWLS2005__des_perf__part1280;

architecture IWLS2005__des_perf__part1280_behav of IWLS2005__des_perf__part1280 is
begin
    n27525_1 <= ( lo5582 );
end IWLS2005__des_perf__part1280_behav;
