--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part842 is 
  Port (
    lo4651: in std_logic;
    n22995: inout std_logic
  );
end IWLS2005__des_perf__part842;

architecture IWLS2005__des_perf__part842_behav of IWLS2005__des_perf__part842 is
begin
    n22995 <= ( lo4651 );
end IWLS2005__des_perf__part842_behav;
