--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part308 is 
  Port (
    lo03698: in std_logic;
    po6249,po6316,po6555,po6622: inout std_logic
  );
end Other__ray__part308;

architecture Other__ray__part308_behav of Other__ray__part308 is
begin
    po6249 <= ( lo03698 );
    po6316 <= ( lo03698 );
    po6555 <= ( lo03698 );
    po6622 <= ( lo03698 );
end Other__ray__part308_behav;
