--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1512 is 
  Port (
    lo1581: in std_logic;
    n8204: inout std_logic
  );
end Cookbook__fec_check__part1512;

architecture Cookbook__fec_check__part1512_behav of Cookbook__fec_check__part1512 is
begin
    n8204 <= ( lo1581 );
end Cookbook__fec_check__part1512_behav;
