--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part113 is 
  Port (
    pi168: in std_logic;
    n44155_1: inout std_logic
  );
end IWLS2005__des_perf__part113;

architecture IWLS2005__des_perf__part113_behav of IWLS2005__des_perf__part113 is
begin
    n44155_1 <= ( pi168 );
end IWLS2005__des_perf__part113_behav;
