--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part43 is 
  Port (
    lo254: in std_logic;
    po125: inout std_logic
  );
end IWLS2005__aes_core__part43;

architecture IWLS2005__aes_core__part43_behav of IWLS2005__aes_core__part43 is
begin
    po125 <= ( lo254 );
end IWLS2005__aes_core__part43_behav;
