--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1 is 
  Port (
    pi01: in std_logic;
    n19119: inout std_logic
  );
end Cookbook__fec_check__part1;

architecture Cookbook__fec_check__part1_behav of Cookbook__fec_check__part1 is
begin
    n19119 <= ( pi01 );
end Cookbook__fec_check__part1_behav;
