--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2982 is 
  Port (
    lo8295: in std_logic;
    n41880_1: inout std_logic
  );
end IWLS2005__des_perf__part2982;

architecture IWLS2005__des_perf__part2982_behav of IWLS2005__des_perf__part2982 is
begin
    n41880_1 <= ( lo8295 );
end IWLS2005__des_perf__part2982_behav;
