--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part13 is 
  Port (
    lo12: in std_logic;
    po12: inout std_logic
  );
end Other__idxlat00n_m12__part13;

architecture Other__idxlat00n_m12__part13_behav of Other__idxlat00n_m12__part13 is
begin
    po12 <= ( lo12 );
end Other__idxlat00n_m12__part13_behav;
