--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part111 is 
  Port (
    lo237: in std_logic;
    po101: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part111;

architecture Cookbook__soft_ecc_ram_64bit__part111_behav of Cookbook__soft_ecc_ram_64bit__part111 is
begin
    po101 <= ( lo237 );
end Cookbook__soft_ecc_ram_64bit__part111_behav;
