--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part64 is 
  Port (
    lo0393: in std_logic;
    n3264: inout std_logic
  );
end IWLS93__s38417__part64;

architecture IWLS93__s38417__part64_behav of IWLS93__s38417__part64 is
begin
    n3264 <= ( lo0393 );
end IWLS93__s38417__part64_behav;
