--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1561 is 
  Port (
    lo3532: in std_logic;
    n22241: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1561;

architecture Other__ucsb_152_tap_fir__part1561_behav of Other__ucsb_152_tap_fir__part1561 is
begin
    n22241 <= ( lo3532 );
end Other__ucsb_152_tap_fir__part1561_behav;
