--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part3 is 
  Port (
    pi07: in std_logic;
    n444: inout std_logic
  );
end LGSynth91__s38417__part3;

architecture LGSynth91__s38417__part3_behav of LGSynth91__s38417__part3 is
begin
    n444 <= ( pi07 );
end LGSynth91__s38417__part3_behav;
