--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part664 is 
  Port (
    lo3313: in std_logic;
    n11559: inout std_logic
  );
end Other__sudoku_check__part664;

architecture Other__sudoku_check__part664_behav of Other__sudoku_check__part664 is
begin
    n11559 <= ( lo3313 );
end Other__sudoku_check__part664_behav;
