--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ac97_ctrl__part19 is 
  Port (
    pi21: in std_logic;
    n11183_1: inout std_logic
  );
end IWLS2005__ac97_ctrl__part19;

architecture IWLS2005__ac97_ctrl__part19_behav of IWLS2005__ac97_ctrl__part19 is
begin
    n11183_1 <= ( pi21 );
end IWLS2005__ac97_ctrl__part19_behav;
