--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__top_rs_decode__part16 is 
  Port (
    lo2877: in std_logic;
    n13652: inout std_logic
  );
end Other__top_rs_decode__part16;

architecture Other__top_rs_decode__part16_behav of Other__top_rs_decode__part16 is
begin
    n13652 <= ( lo2877 );
end Other__top_rs_decode__part16_behav;
