--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2014 is 
  Port (
    lo2083: in std_logic;
    n10714: inout std_logic
  );
end Cookbook__fec_check__part2014;

architecture Cookbook__fec_check__part2014_behav of Cookbook__fec_check__part2014 is
begin
    n10714 <= ( lo2083 );
end Cookbook__fec_check__part2014_behav;
