--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part299 is 
  Port (
    lo1074: in std_logic;
    n6629: inout std_logic
  );
end Cookbook__ucrypt__part299;

architecture Cookbook__ucrypt__part299_behav of Cookbook__ucrypt__part299 is
begin
    n6629 <= ( lo1074 );
end Cookbook__ucrypt__part299_behav;
