--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part42 is 
  Port (
    lo0111: in std_logic;
    n854: inout std_logic
  );
end Cookbook__fec_check__part42;

architecture Cookbook__fec_check__part42_behav of Cookbook__fec_check__part42 is
begin
    n854 <= ( lo0111 );
end Cookbook__fec_check__part42_behav;
