--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part152 is 
  Port (
    lo0479: in std_logic;
    n3654: inout std_logic
  );
end Cookbook__ucrypt__part152;

architecture Cookbook__ucrypt__part152_behav of Cookbook__ucrypt__part152 is
begin
    n3654 <= ( lo0479 );
end Cookbook__ucrypt__part152_behav;
