--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part323 is 
  Port (
    pi1638: in std_logic;
    n47269_1: inout std_logic
  );
end Other__carpat__part323;

architecture Other__carpat__part323_behav of Other__carpat__part323 is
begin
    n47269_1 <= ( pi1638 );
end Other__carpat__part323_behav;
