--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3124 is 
  Port (
    lo8437: in std_logic;
    n42700: inout std_logic
  );
end IWLS2005__des_perf__part3124;

architecture IWLS2005__des_perf__part3124_behav of IWLS2005__des_perf__part3124 is
begin
    n42700 <= ( lo8437 );
end IWLS2005__des_perf__part3124_behav;
