--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__vga_lcd__part77 is 
  Port (
    lo17067: in std_logic;
    n85647_1: inout std_logic
  );
end IWLS2005__vga_lcd__part77;

architecture IWLS2005__vga_lcd__part77_behav of IWLS2005__vga_lcd__part77 is
begin
    n85647_1 <= ( lo17067 );
end IWLS2005__vga_lcd__part77_behav;
