--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part231 is 
  Port (
    lo1167: in std_logic;
    n7290_1: inout std_logic
  );
end Other__fp_operators__part231;

architecture Other__fp_operators__part231_behav of Other__fp_operators__part231 is
begin
    n7290_1 <= ( lo1167 );
end Other__fp_operators__part231_behav;
