--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part96 is 
  Port (
    lo0311: in std_logic;
    n2814: inout std_logic
  );
end Cookbook__ucrypt__part96;

architecture Cookbook__ucrypt__part96_behav of Cookbook__ucrypt__part96 is
begin
    n2814 <= ( lo0311 );
end Cookbook__ucrypt__part96_behav;
