--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part56 is 
  Port (
    lo119: in std_logic;
    po017: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part56;

architecture Cookbook__soft_ecc_ram_64bit__part56_behav of Cookbook__soft_ecc_ram_64bit__part56 is
begin
    po017 <= ( lo119 );
end Cookbook__soft_ecc_ram_64bit__part56_behav;
