--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part35 is 
  Port (
    lo073: in std_logic;
    po66: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part35;

architecture Cookbook__soft_ecc_ram_32bit__part35_behav of Cookbook__soft_ecc_ram_32bit__part35 is
begin
    po66 <= ( lo073 );
end Cookbook__soft_ecc_ram_32bit__part35_behav;
