--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part118 is 
  Port (
    lo3268: in std_logic;
    n16814: inout std_logic
  );
end IWLS2005__pci_bridge32__part118;

architecture IWLS2005__pci_bridge32__part118_behav of IWLS2005__pci_bridge32__part118 is
begin
    n16814 <= ( lo3268 );
end IWLS2005__pci_bridge32__part118_behav;
