--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part757 is 
  Port (
    lo3406: in std_logic;
    n12519: inout std_logic
  );
end Other__sudoku_check__part757;

architecture Other__sudoku_check__part757_behav of Other__sudoku_check__part757 is
begin
    n12519 <= ( lo3406 );
end Other__sudoku_check__part757_behav;
