--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part455 is 
  Port (
    lo1678: in std_logic;
    n9649: inout std_logic
  );
end Cookbook__ucrypt__part455;

architecture Cookbook__ucrypt__part455_behav of Cookbook__ucrypt__part455 is
begin
    n9649 <= ( lo1678 );
end Cookbook__ucrypt__part455_behav;
