--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1262 is 
  Port (
    lo2891: in std_logic;
    n19016: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1262;

architecture Other__ucsb_152_tap_fir__part1262_behav of Other__ucsb_152_tap_fir__part1262 is
begin
    n19016 <= ( lo2891 );
end Other__ucsb_152_tap_fir__part1262_behav;
