--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part211 is 
  Port (
    lo0001,lo0002: in std_logic;
    po00001,n33736,n33741: inout std_logic
  );
end Other__radar__part211;

architecture Other__radar__part211_behav of Other__radar__part211 is
signal n34867,n34868,n34869: std_logic;
begin
    n34867 <= ( lo0001 and not lo0002 );
    n34868 <= ( not lo0001 and lo0002 );
    n34869 <= ( not n34867 and not n34868 );
    po00001 <= ( not n34869 );
    n33736 <= ( not lo0001 );
    n33741 <= ( not n34869 );
end Other__radar__part211_behav;
