--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part80 is 
  Port (
    lo066: in std_logic;
    po200: inout std_logic
  );
end Cookbook__lc_mult_signed__part80;

architecture Cookbook__lc_mult_signed__part80_behav of Cookbook__lc_mult_signed__part80 is
begin
    po200 <= ( lo066 );
end Cookbook__lc_mult_signed__part80_behav;
