--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part266 is 
  Port (
    lo0335: in std_logic;
    n1974: inout std_logic
  );
end Cookbook__fec_check__part266;

architecture Cookbook__fec_check__part266_behav of Cookbook__fec_check__part266 is
begin
    n1974 <= ( lo0335 );
end Cookbook__fec_check__part266_behav;
