--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1047 is 
  Port (
    lo7140: in std_logic;
    n37884_1: inout std_logic
  );
end Other__carpat__part1047;

architecture Other__carpat__part1047_behav of Other__carpat__part1047 is
begin
    n37884_1 <= ( lo7140 );
end Other__carpat__part1047_behav;
