--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1438 is 
  Port (
    lo3296: in std_logic;
    n21056: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1438;

architecture Other__ucsb_152_tap_fir__part1438_behav of Other__ucsb_152_tap_fir__part1438 is
begin
    n21056 <= ( lo3296 );
end Other__ucsb_152_tap_fir__part1438_behav;
