--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ITC99__b01__part2 is 
  Port (
    lo4: in std_logic;
    po0: inout std_logic
  );
end ITC99__b01__part2;

architecture ITC99__b01__part2_behav of ITC99__b01__part2 is
begin
    po0 <= ( lo4 );
end ITC99__b01__part2_behav;
