--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1029 is 
  Port (
    lo4398: in std_logic;
    n17479: inout std_logic
  );
end Other__sudoku_check__part1029;

architecture Other__sudoku_check__part1029_behav of Other__sudoku_check__part1029 is
begin
    n17479 <= ( lo4398 );
end Other__sudoku_check__part1029_behav;
