--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part986 is 
  Port (
    lo4355: in std_logic;
    n17264: inout std_logic
  );
end Other__sudoku_check__part986;

architecture Other__sudoku_check__part986_behav of Other__sudoku_check__part986 is
begin
    n17264 <= ( lo4355 );
end Other__sudoku_check__part986_behav;
