--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    lo433: in std_logic;
    n915: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    n915 <= ( lo433 );
end top_behav;
