--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part54 is 
  Port (
    lo068: in std_logic;
    po25: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part54;

architecture Cookbook__approx_fp_invsqrt__part54_behav of Cookbook__approx_fp_invsqrt__part54 is
begin
    po25 <= ( lo068 );
end Cookbook__approx_fp_invsqrt__part54_behav;
