--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi15: in std_logic;
    po07: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po07 <= ( not pi15 );
end top_behav;
