--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part511 is 
  Port (
    lo3160: in std_logic;
    n10029: inout std_logic
  );
end Other__sudoku_check__part511;

architecture Other__sudoku_check__part511_behav of Other__sudoku_check__part511 is
begin
    n10029 <= ( lo3160 );
end Other__sudoku_check__part511_behav;
