--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2548 is 
  Port (
    lo7805: in std_logic;
    n38870_1: inout std_logic
  );
end IWLS2005__des_perf__part2548;

architecture IWLS2005__des_perf__part2548_behav of IWLS2005__des_perf__part2548 is
begin
    n38870_1 <= ( lo7805 );
end IWLS2005__des_perf__part2548_behav;
