--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part328 is 
  Port (
    lo1195: in std_logic;
    n5660: inout std_logic
  );
end IWLS2005__des_perf__part328;

architecture IWLS2005__des_perf__part328_behav of IWLS2005__des_perf__part328 is
begin
    n5660 <= ( lo1195 );
end IWLS2005__des_perf__part328_behav;
