--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part6 is 
  Port (
    lo011: in std_logic;
    n757: inout std_logic
  );
end Cookbook__gearbox_67_40__part6;

architecture Cookbook__gearbox_67_40__part6_behav of Cookbook__gearbox_67_40__part6 is
begin
    n757 <= ( lo011 );
end Cookbook__gearbox_67_40__part6_behav;
