--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part99 is 
  Port (
    pi0509: in std_logic;
    n43091_1: inout std_logic
  );
end Other__radar__part99;

architecture Other__radar__part99_behav of Other__radar__part99 is
begin
    n43091_1 <= ( pi0509 );
end Other__radar__part99_behav;
