--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1184 is 
  Port (
    lo4553: in std_logic;
    n18254: inout std_logic
  );
end Other__sudoku_check__part1184;

architecture Other__sudoku_check__part1184_behav of Other__sudoku_check__part1184 is
begin
    n18254 <= ( lo4553 );
end Other__sudoku_check__part1184_behav;
