--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s13207__part66 is 
  Port (
    lo229: in std_logic;
    n1443: inout std_logic
  );
end ISCAS__s13207__part66;

architecture ISCAS__s13207__part66_behav of ISCAS__s13207__part66 is
begin
    n1443 <= ( lo229 );
end ISCAS__s13207__part66_behav;
