--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part700 is 
  Port (
    lo4380: in std_logic;
    n22095: inout std_logic
  );
end IWLS2005__des_perf__part700;

architecture IWLS2005__des_perf__part700_behav of IWLS2005__des_perf__part700 is
begin
    n22095 <= ( lo4380 );
end IWLS2005__des_perf__part700_behav;
