--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part684 is 
  Port (
    lo5207: in std_logic;
    n25044: inout std_logic
  );
end Other__carpat__part684;

architecture Other__carpat__part684_behav of Other__carpat__part684 is
begin
    n25044 <= ( lo5207 );
end Other__carpat__part684_behav;
