--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1532 is 
  Port (
    lo8163: in std_logic;
    n45884_1: inout std_logic
  );
end Other__carpat__part1532;

architecture Other__carpat__part1532_behav of Other__carpat__part1532 is
begin
    n45884_1 <= ( lo8163 );
end Other__carpat__part1532_behav;
