--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part269 is 
  Port (
    lo0932: in std_logic;
    n5919: inout std_logic
  );
end Cookbook__ucrypt__part269;

architecture Cookbook__ucrypt__part269_behav of Cookbook__ucrypt__part269 is
begin
    n5919 <= ( lo0932 );
end Cookbook__ucrypt__part269_behav;
