--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part135 is 
  Port (
    lo261: in std_logic;
    po077: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part135;

architecture Cookbook__soft_ecc_ram_64bit__part135_behav of Cookbook__soft_ecc_ram_64bit__part135 is
begin
    po077 <= ( lo261 );
end Cookbook__soft_ecc_ram_64bit__part135_behav;
