--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part438 is 
  Port (
    lo0507: in std_logic;
    n2834: inout std_logic
  );
end Cookbook__fec_check__part438;

architecture Cookbook__fec_check__part438_behav of Cookbook__fec_check__part438 is
begin
    n2834 <= ( lo0507 );
end Cookbook__fec_check__part438_behav;
