--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1365 is 
  Port (
    lo7815: in std_logic;
    n43954: inout std_logic
  );
end Other__carpat__part1365;

architecture Other__carpat__part1365_behav of Other__carpat__part1365 is
begin
    n43954 <= ( lo7815 );
end Other__carpat__part1365_behav;
