--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part55 is 
  Port (
    lo131: in std_logic;
    po47: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part55;

architecture Cookbook__soft_ecc_ram_32bit__part55_behav of Cookbook__soft_ecc_ram_32bit__part55 is
begin
    po47 <= ( lo131 );
end Cookbook__soft_ecc_ram_32bit__part55_behav;
