--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__frequency_monitor__part3 is 
  Port (
    lo044: in std_logic;
    n386: inout std_logic
  );
end Cookbook__frequency_monitor__part3;

architecture Cookbook__frequency_monitor__part3_behav of Cookbook__frequency_monitor__part3 is
begin
    n386 <= ( lo044 );
end Cookbook__frequency_monitor__part3_behav;
