--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1534 is 
  Port (
    lo1603: in std_logic;
    n8314: inout std_logic
  );
end Cookbook__fec_check__part1534;

architecture Cookbook__fec_check__part1534_behav of Cookbook__fec_check__part1534 is
begin
    n8314 <= ( lo1603 );
end Cookbook__fec_check__part1534_behav;
