--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part608 is 
  Port (
    lo4218: in std_logic;
    n21125: inout std_logic
  );
end IWLS2005__des_perf__part608;

architecture IWLS2005__des_perf__part608_behav of IWLS2005__des_perf__part608 is
begin
    n21125 <= ( lo4218 );
end IWLS2005__des_perf__part608_behav;
