--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part2 is 
  Port (
    lo094: in std_logic;
    po49: inout std_logic
  );
end IWLS2005__systemcdes__part2;

architecture IWLS2005__systemcdes__part2_behav of IWLS2005__systemcdes__part2 is
begin
    po49 <= ( lo094 );
end IWLS2005__systemcdes__part2_behav;
