--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part89 is 
  Port (
    lo10490: in std_logic;
    n52688_1: inout std_logic
  );
end IWLS2005__ethernet__part89;

architecture IWLS2005__ethernet__part89_behav of IWLS2005__ethernet__part89 is
begin
    n52688_1 <= ( lo10490 );
end IWLS2005__ethernet__part89_behav;
