--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1119 is 
  Port (
    lo1188: in std_logic;
    n6239: inout std_logic
  );
end Cookbook__fec_check__part1119;

architecture Cookbook__fec_check__part1119_behav of Cookbook__fec_check__part1119 is
begin
    n6239 <= ( lo1188 );
end Cookbook__fec_check__part1119_behav;
