--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part456 is 
  Port (
    lo4005: in std_logic;
    n20435: inout std_logic
  );
end IWLS2005__des_perf__part456;

architecture IWLS2005__des_perf__part456_behav of IWLS2005__des_perf__part456 is
begin
    n20435 <= ( lo4005 );
end IWLS2005__des_perf__part456_behav;
