--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__pci_bridge32__part38 is 
  Port (
    lo0220: in std_logic;
    po025: inout std_logic
  );
end IWLS2005__pci_bridge32__part38;

architecture IWLS2005__pci_bridge32__part38_behav of IWLS2005__pci_bridge32__part38 is
begin
    po025 <= ( lo0220 );
end IWLS2005__pci_bridge32__part38_behav;
