--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3109 is 
  Port (
    lo8422: in std_logic;
    n42250_1: inout std_logic
  );
end IWLS2005__des_perf__part3109;

architecture IWLS2005__des_perf__part3109_behav of IWLS2005__des_perf__part3109 is
begin
    n42250_1 <= ( lo8422 );
end IWLS2005__des_perf__part3109_behav;
