--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__usb_funct__part67 is 
  Port (
    lo1724: in std_logic;
    n8854_1: inout std_logic
  );
end IWLS2005__usb_funct__part67;

architecture IWLS2005__usb_funct__part67_behav of IWLS2005__usb_funct__part67 is
begin
    n8854_1 <= ( lo1724 );
end IWLS2005__usb_funct__part67_behav;
