--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part807 is 
  Port (
    lo4176: in std_logic;
    n14899: inout std_logic
  );
end Other__sudoku_check__part807;

architecture Other__sudoku_check__part807_behav of Other__sudoku_check__part807 is
begin
    n14899 <= ( lo4176 );
end Other__sudoku_check__part807_behav;
