--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2420 is 
  Port (
    lo7654: in std_logic;
    n37940_1: inout std_logic
  );
end IWLS2005__des_perf__part2420;

architecture IWLS2005__des_perf__part2420_behav of IWLS2005__des_perf__part2420 is
begin
    n37940_1 <= ( lo7654 );
end IWLS2005__des_perf__part2420_behav;
