--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part109 is 
  Port (
    lo203: in std_logic;
    po32: inout std_logic
  );
end Cookbook__gearbox_40_67__part109;

architecture Cookbook__gearbox_40_67__part109_behav of Cookbook__gearbox_40_67__part109 is
begin
    po32 <= ( lo203 );
end Cookbook__gearbox_40_67__part109_behav;
