--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1395 is 
  Port (
    lo5835: in std_logic;
    n29090_1: inout std_logic
  );
end IWLS2005__des_perf__part1395;

architecture IWLS2005__des_perf__part1395_behav of IWLS2005__des_perf__part1395 is
begin
    n29090_1 <= ( lo5835 );
end IWLS2005__des_perf__part1395_behav;
