--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_gen__part8 is 
  Port (
    lo046: in std_logic;
    po24: inout std_logic
  );
end Cookbook__fec_gen__part8;

architecture Cookbook__fec_gen__part8_behav of Cookbook__fec_gen__part8 is
begin
    po24 <= ( lo046 );
end Cookbook__fec_gen__part8_behav;
