--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part891 is 
  Port (
    lo6727: in std_logic;
    n32879_1: inout std_logic
  );
end Other__carpat__part891;

architecture Other__carpat__part891_behav of Other__carpat__part891 is
begin
    n32879_1 <= ( lo6727 );
end Other__carpat__part891_behav;
