--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s444__part1 is 
  Port (
    lo14: in std_logic;
    po2: inout std_logic
  );
end LGSynth91__s444__part1;

architecture LGSynth91__s444__part1_behav of LGSynth91__s444__part1 is
begin
    po2 <= ( lo14 );
end LGSynth91__s444__part1_behav;
