--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2823 is 
  Port (
    lo8136: in std_logic;
    n40825_1: inout std_logic
  );
end IWLS2005__des_perf__part2823;

architecture IWLS2005__des_perf__part2823_behav of IWLS2005__des_perf__part2823 is
begin
    n40825_1 <= ( lo8136 );
end IWLS2005__des_perf__part2823_behav;
