--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part531 is 
  Port (
    lo0600: in std_logic;
    n3299: inout std_logic
  );
end Cookbook__fec_check__part531;

architecture Cookbook__fec_check__part531_behav of Cookbook__fec_check__part531 is
begin
    n3299 <= ( lo0600 );
end Cookbook__fec_check__part531_behav;
