--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part691 is 
  Port (
    lo3340: in std_logic;
    n11829: inout std_logic
  );
end Other__sudoku_check__part691;

architecture Other__sudoku_check__part691_behav of Other__sudoku_check__part691 is
begin
    n11829 <= ( lo3340 );
end Other__sudoku_check__part691_behav;
