--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1205 is 
  Port (
    lo4574: in std_logic;
    n18359: inout std_logic
  );
end Other__sudoku_check__part1205;

architecture Other__sudoku_check__part1205_behav of Other__sudoku_check__part1205 is
begin
    n18359 <= ( lo4574 );
end Other__sudoku_check__part1205_behav;
