--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part69 is 
  Port (
    lo2424: in std_logic;
    n5609: inout std_logic
  );
end Other__sudoku_check__part69;

architecture Other__sudoku_check__part69_behav of Other__sudoku_check__part69 is
begin
    n5609 <= ( lo2424 );
end Other__sudoku_check__part69_behav;
