--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1142 is 
  Port (
    lo5300: in std_logic;
    n26655_1: inout std_logic
  );
end IWLS2005__des_perf__part1142;

architecture IWLS2005__des_perf__part1142_behav of IWLS2005__des_perf__part1142 is
begin
    n26655_1 <= ( lo5300 );
end IWLS2005__des_perf__part1142_behav;
