--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part927 is 
  Port (
    lo0996: in std_logic;
    n5279: inout std_logic
  );
end Cookbook__fec_check__part927;

architecture Cookbook__fec_check__part927_behav of Cookbook__fec_check__part927 is
begin
    n5279 <= ( lo0996 );
end Cookbook__fec_check__part927_behav;
