--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part3160 is 
  Port (
    lo8476: in std_logic;
    n42675: inout std_logic
  );
end IWLS2005__des_perf__part3160;

architecture IWLS2005__des_perf__part3160_behav of IWLS2005__des_perf__part3160 is
begin
    n42675 <= ( lo8476 );
end IWLS2005__des_perf__part3160_behav;
