--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__x4_encoder_8b10b__part12 is 
  Port (
    lo08: in std_logic;
    po01: inout std_logic
  );
end Cookbook__x4_encoder_8b10b__part12;

architecture Cookbook__x4_encoder_8b10b__part12_behav of Cookbook__x4_encoder_8b10b__part12 is
begin
    po01 <= ( lo08 );
end Cookbook__x4_encoder_8b10b__part12_behav;
