--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part250 is 
  Port (
    lo03546: in std_logic;
    n35276: inout std_logic
  );
end Other__ray__part250;

architecture Other__ray__part250_behav of Other__ray__part250 is
begin
    n35276 <= ( lo03546 );
end Other__ray__part250_behav;
