--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part13 is 
  Port (
    pi17: in std_logic;
    n389: inout std_logic
  );
end LGSynth91__s38417__part13;

architecture LGSynth91__s38417__part13_behav of LGSynth91__s38417__part13 is
begin
    n389 <= ( pi17 );
end LGSynth91__s38417__part13_behav;
