--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part22 is 
  Port (
    pi022: in std_logic;
    n2337_1: inout std_logic
  );
end Other__fpu__part22;

architecture Other__fpu__part22_behav of Other__fpu__part22 is
begin
    n2337_1 <= ( pi022 );
end Other__fpu__part22_behav;
