--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part66 is 
  Port (
    pi72: in std_logic;
    n869431: inout std_logic
  );
end IWLS2005__leon3__part66;

architecture IWLS2005__leon3__part66_behav of IWLS2005__leon3__part66 is
begin
    n869431 <= ( pi72 );
end IWLS2005__leon3__part66_behav;
