--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lane_tx__part42 is 
  Port (
    lo494: in std_logic;
    n2648_1: inout std_logic
  );
end Cookbook__lane_tx__part42;

architecture Cookbook__lane_tx__part42_behav of Cookbook__lane_tx__part42 is
begin
    n2648_1 <= ( lo494 );
end Cookbook__lane_tx__part42_behav;
