--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1439 is 
  Port (
    lo1508: in std_logic;
    n7839: inout std_logic
  );
end Cookbook__fec_check__part1439;

architecture Cookbook__fec_check__part1439_behav of Cookbook__fec_check__part1439 is
begin
    n7839 <= ( lo1508 );
end Cookbook__fec_check__part1439_behav;
