--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part601 is 
  Port (
    lo3250: in std_logic;
    n10929: inout std_logic
  );
end Other__sudoku_check__part601;

architecture Other__sudoku_check__part601_behav of Other__sudoku_check__part601 is
begin
    n10929 <= ( lo3250 );
end Other__sudoku_check__part601_behav;
