--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part98 is 
  Port (
    lo10516: in std_logic;
    n52613_1: inout std_logic
  );
end IWLS2005__ethernet__part98;

architecture IWLS2005__ethernet__part98_behav of IWLS2005__ethernet__part98 is
begin
    n52613_1 <= ( lo10516 );
end IWLS2005__ethernet__part98_behav;
