--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2131 is 
  Port (
    lo2200: in std_logic;
    n11299: inout std_logic
  );
end Cookbook__fec_check__part2131;

architecture Cookbook__fec_check__part2131_behav of Cookbook__fec_check__part2131 is
begin
    n11299 <= ( lo2200 );
end Cookbook__fec_check__part2131_behav;
