--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part60 is 
  Port (
    pi0755: in std_logic;
    n24879: inout std_logic
  );
end Other__carpat__part60;

architecture Other__carpat__part60_behav of Other__carpat__part60 is
begin
    n24879 <= ( pi0755 );
end Other__carpat__part60_behav;
