--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part84 is 
  Port (
    lo81: in std_logic;
    po03: inout std_logic
  );
end Cookbook__approx_fp_div__part84;

architecture Cookbook__approx_fp_div__part84_behav of Cookbook__approx_fp_div__part84 is
begin
    po03 <= ( lo81 );
end Cookbook__approx_fp_div__part84_behav;
