--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2084 is 
  Port (
    lo2153: in std_logic;
    n11064: inout std_logic
  );
end Cookbook__fec_check__part2084;

architecture Cookbook__fec_check__part2084_behav of Cookbook__fec_check__part2084 is
begin
    n11064 <= ( lo2153 );
end Cookbook__fec_check__part2084_behav;
