--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2057 is 
  Port (
    lo7198: in std_logic;
    n36175_1: inout std_logic
  );
end IWLS2005__des_perf__part2057;

architecture IWLS2005__des_perf__part2057_behav of IWLS2005__des_perf__part2057 is
begin
    n36175_1 <= ( lo7198 );
end IWLS2005__des_perf__part2057_behav;
