--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1163 is 
  Port (
    lo1232: in std_logic;
    n6459: inout std_logic
  );
end Cookbook__fec_check__part1163;

architecture Cookbook__fec_check__part1163_behav of Cookbook__fec_check__part1163 is
begin
    n6459 <= ( lo1232 );
end Cookbook__fec_check__part1163_behav;
