--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part251 is 
  Port (
    lo03591: in std_logic;
    n36036: inout std_logic
  );
end Other__ray__part251;

architecture Other__ray__part251_behav of Other__ray__part251 is
begin
    n36036 <= ( lo03591 );
end Other__ray__part251_behav;
