--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part188 is 
  Port (
    lo0271: in std_logic;
    n819: inout std_logic
  );
end Other__desperf__part188;

architecture Other__desperf__part188_behav of Other__desperf__part188 is
begin
    n819 <= ( lo0271 );
end Other__desperf__part188_behav;
