--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part854 is 
  Port (
    lo6483: in std_logic;
    n30794_1: inout std_logic
  );
end Other__carpat__part854;

architecture Other__carpat__part854_behav of Other__carpat__part854 is
begin
    n30794_1 <= ( lo6483 );
end Other__carpat__part854_behav;
