--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part487 is 
  Port (
    lo4038: in std_logic;
    n20340: inout std_logic
  );
end IWLS2005__des_perf__part487;

architecture IWLS2005__des_perf__part487_behav of IWLS2005__des_perf__part487 is
begin
    n20340 <= ( lo4038 );
end IWLS2005__des_perf__part487_behav;
