--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part685 is 
  Port (
    lo4363: in std_logic;
    n22145: inout std_logic
  );
end IWLS2005__des_perf__part685;

architecture IWLS2005__des_perf__part685_behav of IWLS2005__des_perf__part685 is
begin
    n22145 <= ( lo4363 );
end IWLS2005__des_perf__part685_behav;
