--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1424 is 
  Port (
    lo3252: in std_logic;
    n20836: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1424;

architecture Other__ucsb_152_tap_fir__part1424_behav of Other__ucsb_152_tap_fir__part1424 is
begin
    n20836 <= ( lo3252 );
end Other__ucsb_152_tap_fir__part1424_behav;
