--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1817 is 
  Port (
    lo9063: in std_logic;
    po448: inout std_logic
  );
end Other__carpat__part1817;

architecture Other__carpat__part1817_behav of Other__carpat__part1817 is
begin
    po448 <= ( lo9063 );
end Other__carpat__part1817_behav;
