--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part379 is 
  Port (
    lo2186: in std_logic;
    n11445: inout std_logic
  );
end IWLS2005__des_perf__part379;

architecture IWLS2005__des_perf__part379_behav of IWLS2005__des_perf__part379 is
begin
    n11445 <= ( lo2186 );
end IWLS2005__des_perf__part379_behav;
