--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part581 is 
  Port (
    lo06062: in std_logic;
    po1583,po1678: inout std_logic
  );
end Other__ray__part581;

architecture Other__ray__part581_behav of Other__ray__part581 is
begin
    po1583 <= ( lo06062 );
    po1678 <= ( lo06062 );
end Other__ray__part581_behav;
