--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part24 is 
  Port (
    pi24: in std_logic;
    n1609_1: inout std_logic
  );
end Cookbook__gearbox_40_67__part24;

architecture Cookbook__gearbox_40_67__part24_behav of Cookbook__gearbox_40_67__part24 is
begin
    n1609_1 <= ( pi24 );
end Cookbook__gearbox_40_67__part24_behav;
