--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part133 is 
  Port (
    lo0202: in std_logic;
    n1309: inout std_logic
  );
end Cookbook__fec_check__part133;

architecture Cookbook__fec_check__part133_behav of Cookbook__fec_check__part133 is
begin
    n1309 <= ( lo0202 );
end Cookbook__fec_check__part133_behav;
