--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part31 is 
  Port (
    lo97658: in std_logic;
    n488205_1: inout std_logic
  );
end IWLS2005__netcard__part31;

architecture IWLS2005__netcard__part31_behav of IWLS2005__netcard__part31 is
begin
    n488205_1 <= ( lo97658 );
end IWLS2005__netcard__part31_behav;
