--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part744 is 
  Port (
    lo3393: in std_logic;
    n12359: inout std_logic
  );
end Other__sudoku_check__part744;

architecture Other__sudoku_check__part744_behav of Other__sudoku_check__part744 is
begin
    n12359 <= ( lo3393 );
end Other__sudoku_check__part744_behav;
