--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part171 is 
  Port (
    lo03072: in std_logic;
    po0988: inout std_logic
  );
end Other__ray__part171;

architecture Other__ray__part171_behav of Other__ray__part171 is
begin
    po0988 <= ( lo03072 );
end Other__ray__part171_behav;
