--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1949 is 
  Port (
    lo2018: in std_logic;
    n10389: inout std_logic
  );
end Cookbook__fec_check__part1949;

architecture Cookbook__fec_check__part1949_behav of Cookbook__fec_check__part1949 is
begin
    n10389 <= ( lo2018 );
end Cookbook__fec_check__part1949_behav;
