--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    lo301: in std_logic;
    po000,po001,po002,po003,po004,po005: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po000 <= ( lo301 );
    po001 <= ( lo301 );
    po002 <= ( lo301 );
    po003 <= ( lo301 );
    po004 <= ( lo301 );
    po005 <= ( lo301 );
end top_behav;
