--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part77 is 
  Port (
    lo76: in std_logic;
    po76: inout std_logic
  );
end Other__idxlat00n_m12__part77;

architecture Other__idxlat00n_m12__part77_behav of Other__idxlat00n_m12__part77 is
begin
    po76 <= ( lo76 );
end Other__idxlat00n_m12__part77_behav;
