--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part136 is 
  Port (
    lo0205: in std_logic;
    n1324: inout std_logic
  );
end Cookbook__fec_check__part136;

architecture Cookbook__fec_check__part136_behav of Cookbook__fec_check__part136 is
begin
    n1324 <= ( lo0205 );
end Cookbook__fec_check__part136_behav;
