--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1415 is 
  Port (
    lo1484: in std_logic;
    n7719: inout std_logic
  );
end Cookbook__fec_check__part1415;

architecture Cookbook__fec_check__part1415_behav of Cookbook__fec_check__part1415 is
begin
    n7719 <= ( lo1484 );
end Cookbook__fec_check__part1415_behav;
