--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2907 is 
  Port (
    lo8220: in std_logic;
    n41400: inout std_logic
  );
end IWLS2005__des_perf__part2907;

architecture IWLS2005__des_perf__part2907_behav of IWLS2005__des_perf__part2907 is
begin
    n41400 <= ( lo8220 );
end IWLS2005__des_perf__part2907_behav;
