--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1415 is 
  Port (
    lo3243: in std_logic;
    n20791: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1415;

architecture Other__ucsb_152_tap_fir__part1415_behav of Other__ucsb_152_tap_fir__part1415 is
begin
    n20791 <= ( lo3243 );
end Other__ucsb_152_tap_fir__part1415_behav;
