--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part303 is 
  Port (
    lo0372: in std_logic;
    n2159: inout std_logic
  );
end Cookbook__fec_check__part303;

architecture Cookbook__fec_check__part303_behav of Cookbook__fec_check__part303 is
begin
    n2159 <= ( lo0372 );
end Cookbook__fec_check__part303_behav;
