--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part46 is 
  Port (
    lo0341: in std_logic;
    n1979: inout std_logic
  );
end ISCAS__s38417__part46;

architecture ISCAS__s38417__part46_behav of ISCAS__s38417__part46 is
begin
    n1979 <= ( lo0341 );
end ISCAS__s38417__part46_behav;
