--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part550 is 
  Port (
    lo3341: in std_logic;
    n15759: inout std_logic
  );
end Other__carpat__part550;

architecture Other__carpat__part550_behav of Other__carpat__part550 is
begin
    n15759 <= ( lo3341 );
end Other__carpat__part550_behav;
