--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1880 is 
  Port (
    lo1949: in std_logic;
    n10044: inout std_logic
  );
end Cookbook__fec_check__part1880;

architecture Cookbook__fec_check__part1880_behav of Cookbook__fec_check__part1880 is
begin
    n10044 <= ( lo1949 );
end Cookbook__fec_check__part1880_behav;
