--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part508 is 
  Port (
    lo3157: in std_logic;
    n9999: inout std_logic
  );
end Other__sudoku_check__part508;

architecture Other__sudoku_check__part508_behav of Other__sudoku_check__part508 is
begin
    n9999 <= ( lo3157 );
end Other__sudoku_check__part508_behav;
