--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part296 is 
  Port (
    lo03686: in std_logic;
    po6186,po6237,po6492,po6543: inout std_logic
  );
end Other__ray__part296;

architecture Other__ray__part296_behav of Other__ray__part296 is
begin
    po6186 <= ( lo03686 );
    po6237 <= ( lo03686 );
    po6492 <= ( lo03686 );
    po6543 <= ( lo03686 );
end Other__ray__part296_behav;
