--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1343 is 
  Port (
    lo4712: in std_logic;
    n19049: inout std_logic
  );
end Other__sudoku_check__part1343;

architecture Other__sudoku_check__part1343_behav of Other__sudoku_check__part1343 is
begin
    n19049 <= ( lo4712 );
end Other__sudoku_check__part1343_behav;
