--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part104 is 
  Port (
    pi0514: in std_logic;
    n43116_1: inout std_logic
  );
end Other__radar__part104;

architecture Other__radar__part104_behav of Other__radar__part104 is
begin
    n43116_1 <= ( pi0514 );
end Other__radar__part104_behav;
