--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part126 is 
  Port (
    lo2775: in std_logic;
    n6179: inout std_logic
  );
end Other__sudoku_check__part126;

architecture Other__sudoku_check__part126_behav of Other__sudoku_check__part126 is
begin
    n6179 <= ( lo2775 );
end Other__sudoku_check__part126_behav;
