--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part31 is 
  Port (
    lo242: in std_logic;
    po116: inout std_logic
  );
end IWLS2005__aes_core__part31;

architecture IWLS2005__aes_core__part31_behav of IWLS2005__aes_core__part31 is
begin
    po116 <= ( lo242 );
end IWLS2005__aes_core__part31_behav;
