--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1661 is 
  Port (
    lo1730: in std_logic;
    n8949: inout std_logic
  );
end Cookbook__fec_check__part1661;

architecture Cookbook__fec_check__part1661_behav of Cookbook__fec_check__part1661 is
begin
    n8949 <= ( lo1730 );
end Cookbook__fec_check__part1661_behav;
