--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity LGSynth91__s38417__part156 is 
  Port (
    lo1213: in std_logic;
    n6909: inout std_logic
  );
end LGSynth91__s38417__part156;

architecture LGSynth91__s38417__part156_behav of LGSynth91__s38417__part156 is
begin
    n6909 <= ( not lo1213 );
end LGSynth91__s38417__part156_behav;
