--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part190 is 
  Port (
    lo0452: in std_logic;
    n6716: inout std_logic
  );
end Other__ucsb_152_tap_fir__part190;

architecture Other__ucsb_152_tap_fir__part190_behav of Other__ucsb_152_tap_fir__part190 is
begin
    n6716 <= ( lo0452 );
end Other__ucsb_152_tap_fir__part190_behav;
