--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part957 is 
  Port (
    lo4883: in std_logic;
    n24295: inout std_logic
  );
end IWLS2005__des_perf__part957;

architecture IWLS2005__des_perf__part957_behav of IWLS2005__des_perf__part957 is
begin
    n24295 <= ( lo4883 );
end IWLS2005__des_perf__part957_behav;
