--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part889 is 
  Port (
    lo4258: in std_logic;
    n16779: inout std_logic
  );
end Other__sudoku_check__part889;

architecture Other__sudoku_check__part889_behav of Other__sudoku_check__part889 is
begin
    n16779 <= ( lo4258 );
end Other__sudoku_check__part889_behav;
