--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part7 is 
  Port (
    lo0462: in std_logic;
    n3259: inout std_logic
  );
end Other__sudoku_check__part7;

architecture Other__sudoku_check__part7_behav of Other__sudoku_check__part7 is
begin
    n3259 <= ( lo0462 );
end Other__sudoku_check__part7_behav;
