--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1433 is 
  Port (
    lo3287: in std_logic;
    n21006: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1433;

architecture Other__ucsb_152_tap_fir__part1433_behav of Other__ucsb_152_tap_fir__part1433 is
begin
    n21006 <= ( lo3287 );
end Other__ucsb_152_tap_fir__part1433_behav;
