--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part27 is 
  Port (
    lo00255: in std_logic;
    po020: inout std_logic
  );
end IWLS2005__ethernet__part27;

architecture IWLS2005__ethernet__part27_behav of IWLS2005__ethernet__part27 is
begin
    po020 <= ( lo00255 );
end IWLS2005__ethernet__part27_behav;
