--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part69 is 
  Port (
    lo132: in std_logic;
    po004: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part69;

architecture Cookbook__soft_ecc_ram_64bit__part69_behav of Cookbook__soft_ecc_ram_64bit__part69 is
begin
    po004 <= ( lo132 );
end Cookbook__soft_ecc_ram_64bit__part69_behav;
