--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part969 is 
  Port (
    lo10655: in std_logic;
    n71221_1: inout std_logic
  );
end Other__ray__part969;

architecture Other__ray__part969_behav of Other__ray__part969 is
begin
    n71221_1 <= ( lo10655 );
end Other__ray__part969_behav;
