--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part100 is 
  Port (
    lo0342: in std_logic;
    n4180: inout std_logic
  );
end Other__fp_operators__part100;

architecture Other__fp_operators__part100_behav of Other__fp_operators__part100 is
begin
    n4180 <= ( lo0342 );
end Other__fp_operators__part100_behav;
