--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part509 is 
  Port (
    lo3158: in std_logic;
    n10009: inout std_logic
  );
end Other__sudoku_check__part509;

architecture Other__sudoku_check__part509_behav of Other__sudoku_check__part509 is
begin
    n10009 <= ( lo3158 );
end Other__sudoku_check__part509_behav;
