--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1288 is 
  Port (
    lo7727: in std_logic;
    n42624_1: inout std_logic
  );
end Other__carpat__part1288;

architecture Other__carpat__part1288_behav of Other__carpat__part1288 is
begin
    n42624_1 <= ( lo7727 );
end Other__carpat__part1288_behav;
