--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part398 is 
  Port (
    lo1397: in std_logic;
    n8244_1: inout std_logic
  );
end Cookbook__ucrypt__part398;

architecture Cookbook__ucrypt__part398_behav of Cookbook__ucrypt__part398 is
begin
    n8244_1 <= ( lo1397 );
end Cookbook__ucrypt__part398_behav;
