--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1294 is 
  Port (
    lo3011: in std_logic;
    n19546: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1294;

architecture Other__ucsb_152_tap_fir__part1294_behav of Other__ucsb_152_tap_fir__part1294 is
begin
    n19546 <= ( lo3011 );
end Other__ucsb_152_tap_fir__part1294_behav;
