--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part138 is 
  Port (
    pi1010: in std_logic;
    n32019_1: inout std_logic
  );
end Other__carpat__part138;

architecture Other__carpat__part138_behav of Other__carpat__part138 is
begin
    n32019_1 <= ( pi1010 );
end Other__carpat__part138_behav;
