--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part277 is 
  Port (
    lo0346: in std_logic;
    n2029: inout std_logic
  );
end Cookbook__fec_check__part277;

architecture Cookbook__fec_check__part277_behav of Cookbook__fec_check__part277 is
begin
    n2029 <= ( lo0346 );
end Cookbook__fec_check__part277_behav;
