--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1643 is 
  Port (
    lo3728: in std_logic;
    n23176: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1643;

architecture Other__ucsb_152_tap_fir__part1643_behav of Other__ucsb_152_tap_fir__part1643 is
begin
    n23176 <= ( lo3728 );
end Other__ucsb_152_tap_fir__part1643_behav;
