--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part969 is 
  Port (
    lo1038: in std_logic;
    n5489: inout std_logic
  );
end Cookbook__fec_check__part969;

architecture Cookbook__fec_check__part969_behav of Cookbook__fec_check__part969 is
begin
    n5489 <= ( lo1038 );
end Cookbook__fec_check__part969_behav;
