--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1780 is 
  Port (
    lo4018: in std_logic;
    n24601: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1780;

architecture Other__ucsb_152_tap_fir__part1780_behav of Other__ucsb_152_tap_fir__part1780 is
begin
    n24601 <= ( lo4018 );
end Other__ucsb_152_tap_fir__part1780_behav;
