--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1285 is 
  Port (
    lo1354: in std_logic;
    n7069: inout std_logic
  );
end Cookbook__fec_check__part1285;

architecture Cookbook__fec_check__part1285_behav of Cookbook__fec_check__part1285 is
begin
    n7069 <= ( lo1354 );
end Cookbook__fec_check__part1285_behav;
