--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2749 is 
  Port (
    lo8062: in std_logic;
    n40590_1: inout std_logic
  );
end IWLS2005__des_perf__part2749;

architecture IWLS2005__des_perf__part2749_behav of IWLS2005__des_perf__part2749 is
begin
    n40590_1 <= ( lo8062 );
end IWLS2005__des_perf__part2749_behav;
