--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part57 is 
  Port (
    lo54: in std_logic;
    po30: inout std_logic
  );
end Cookbook__approx_fp_div__part57;

architecture Cookbook__approx_fp_div__part57_behav of Cookbook__approx_fp_div__part57 is
begin
    po30 <= ( lo54 );
end Cookbook__approx_fp_div__part57_behav;
