--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part146 is 
  Port (
    lo0026: in std_logic;
    po26: inout std_logic
  );
end Other__desperf__part146;

architecture Other__desperf__part146_behav of Other__desperf__part146 is
begin
    po26 <= ( lo0026 );
end Other__desperf__part146_behav;
