--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part195 is 
  Port (
    lo03237: in std_logic;
    po1113: inout std_logic
  );
end Other__ray__part195;

architecture Other__ray__part195_behav of Other__ray__part195 is
begin
    po1113 <= ( lo03237 );
end Other__ray__part195_behav;
