--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1654 is 
  Port (
    lo3744: in std_logic;
    n23231: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1654;

architecture Other__ucsb_152_tap_fir__part1654_behav of Other__ucsb_152_tap_fir__part1654 is
begin
    n23231 <= ( lo3744 );
end Other__ucsb_152_tap_fir__part1654_behav;
