--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part528 is 
  Port (
    lo3177: in std_logic;
    n10199: inout std_logic
  );
end Other__sudoku_check__part528;

architecture Other__sudoku_check__part528_behav of Other__sudoku_check__part528 is
begin
    n10199 <= ( lo3177 );
end Other__sudoku_check__part528_behav;
