--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1357 is 
  Port (
    lo3125: in std_logic;
    n20181: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1357;

architecture Other__ucsb_152_tap_fir__part1357_behav of Other__ucsb_152_tap_fir__part1357 is
begin
    n20181 <= ( lo3125 );
end Other__ucsb_152_tap_fir__part1357_behav;
