--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part557 is 
  Port (
    lo0626: in std_logic;
    n3429: inout std_logic
  );
end Cookbook__fec_check__part557;

architecture Cookbook__fec_check__part557_behav of Cookbook__fec_check__part557 is
begin
    n3429 <= ( lo0626 );
end Cookbook__fec_check__part557_behav;
