--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part983 is 
  Port (
    lo4352: in std_logic;
    n17249: inout std_logic
  );
end Other__sudoku_check__part983;

architecture Other__sudoku_check__part983_behav of Other__sudoku_check__part983 is
begin
    n17249 <= ( lo4352 );
end Other__sudoku_check__part983_behav;
