--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2078 is 
  Port (
    lo2147: in std_logic;
    n11034: inout std_logic
  );
end Cookbook__fec_check__part2078;

architecture Cookbook__fec_check__part2078_behav of Cookbook__fec_check__part2078 is
begin
    n11034 <= ( lo2147 );
end Cookbook__fec_check__part2078_behav;
