--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part872 is 
  Port (
    lo0941: in std_logic;
    n5004: inout std_logic
  );
end Cookbook__fec_check__part872;

architecture Cookbook__fec_check__part872_behav of Cookbook__fec_check__part872 is
begin
    n5004 <= ( lo0941 );
end Cookbook__fec_check__part872_behav;
