--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part31 is 
  Port (
    lo036: in std_logic;
    n882: inout std_logic
  );
end Cookbook__gearbox_67_40__part31;

architecture Cookbook__gearbox_67_40__part31_behav of Cookbook__gearbox_67_40__part31 is
begin
    n882 <= ( lo036 );
end Cookbook__gearbox_67_40__part31_behav;
