--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part168 is 
  Port (
    lo03056: in std_logic;
    n32166: inout std_logic
  );
end Other__ray__part168;

architecture Other__ray__part168_behav of Other__ray__part168 is
begin
    n32166 <= ( lo03056 );
end Other__ray__part168_behav;
