--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat00n_m12__part31 is 
  Port (
    lo30: in std_logic;
    po30: inout std_logic
  );
end Other__idxlat00n_m12__part31;

architecture Other__idxlat00n_m12__part31_behav of Other__idxlat00n_m12__part31 is
begin
    po30 <= ( lo30 );
end Other__idxlat00n_m12__part31_behav;
