--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part473 is 
  Port (
    lo1696: in std_logic;
    n9739_1: inout std_logic
  );
end Cookbook__ucrypt__part473;

architecture Cookbook__ucrypt__part473_behav of Cookbook__ucrypt__part473 is
begin
    n9739_1 <= ( lo1696 );
end Cookbook__ucrypt__part473_behav;
