--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1138 is 
  Port (
    lo12985: in std_logic;
    po1963,po1997,po2143,po2177,n51656_1: inout std_logic
  );
end Other__ray__part1138;

architecture Other__ray__part1138_behav of Other__ray__part1138 is
begin
    po1963 <= ( lo12985 );
    po1997 <= ( lo12985 );
    po2143 <= ( lo12985 );
    po2177 <= ( lo12985 );
    n51656_1 <= ( lo12985 );
end Other__ray__part1138_behav;
