--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1326 is 
  Port (
    lo5689: in std_logic;
    n28560_1: inout std_logic
  );
end IWLS2005__des_perf__part1326;

architecture IWLS2005__des_perf__part1326_behav of IWLS2005__des_perf__part1326 is
begin
    n28560_1 <= ( lo5689 );
end IWLS2005__des_perf__part1326_behav;
