--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part48 is 
  Port (
    lo124: in std_logic;
    po54: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part48;

architecture Cookbook__soft_ecc_ram_32bit__part48_behav of Cookbook__soft_ecc_ram_32bit__part48 is
begin
    po54 <= ( lo124 );
end Cookbook__soft_ecc_ram_32bit__part48_behav;
