--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part18 is 
  Port (
    lo97289: in std_logic;
    n472340_1: inout std_logic
  );
end IWLS2005__netcard__part18;

architecture IWLS2005__netcard__part18_behav of IWLS2005__netcard__part18 is
begin
    n472340_1 <= ( lo97289 );
end IWLS2005__netcard__part18_behav;
