--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part56 is 
  Port (
    lo0125: in std_logic;
    n924: inout std_logic
  );
end Cookbook__fec_check__part56;

architecture Cookbook__fec_check__part56_behav of Cookbook__fec_check__part56 is
begin
    n924 <= ( lo0125 );
end Cookbook__fec_check__part56_behav;
