--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__radar__part153 is 
  Port (
    pi0579: in std_logic;
    n43911: inout std_logic
  );
end Other__radar__part153;

architecture Other__radar__part153_behav of Other__radar__part153 is
begin
    n43911 <= ( pi0579 );
end Other__radar__part153_behav;
