--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part563 is 
  Port (
    lo3212: in std_logic;
    n10549: inout std_logic
  );
end Other__sudoku_check__part563;

architecture Other__sudoku_check__part563_behav of Other__sudoku_check__part563 is
begin
    n10549 <= ( lo3212 );
end Other__sudoku_check__part563_behav;
