--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1167 is 
  Port (
    lo1236: in std_logic;
    n6479: inout std_logic
  );
end Cookbook__fec_check__part1167;

architecture Cookbook__fec_check__part1167_behav of Cookbook__fec_check__part1167 is
begin
    n6479 <= ( lo1236 );
end Cookbook__fec_check__part1167_behav;
