--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__spi__part17 is 
  Port (
    lo212: in std_logic;
    po26: inout std_logic
  );
end IWLS2005__spi__part17;

architecture IWLS2005__spi__part17_behav of IWLS2005__spi__part17 is
begin
    po26 <= ( lo212 );
end IWLS2005__spi__part17_behav;
