--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__netcard__part69 is 
  Port (
    lo97789: in std_logic;
    n488625_1: inout std_logic
  );
end IWLS2005__netcard__part69;

architecture IWLS2005__netcard__part69_behav of IWLS2005__netcard__part69 is
begin
    n488625_1 <= ( lo97789 );
end IWLS2005__netcard__part69_behav;
