--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part666 is 
  Port (
    lo3315: in std_logic;
    n11579: inout std_logic
  );
end Other__sudoku_check__part666;

architecture Other__sudoku_check__part666_behav of Other__sudoku_check__part666 is
begin
    n11579 <= ( lo3315 );
end Other__sudoku_check__part666_behav;
