--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part15 is 
  Port (
    lo0006: in std_logic;
    n1289: inout std_logic
  );
end Cookbook__ucrypt__part15;

architecture Cookbook__ucrypt__part15_behav of Cookbook__ucrypt__part15 is
begin
    n1289 <= ( lo0006 );
end Cookbook__ucrypt__part15_behav;
