--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part54 is 
  Port (
    lo2265: in std_logic;
    n5459: inout std_logic
  );
end Other__sudoku_check__part54;

architecture Other__sudoku_check__part54_behav of Other__sudoku_check__part54 is
begin
    n5459 <= ( lo2265 );
end Other__sudoku_check__part54_behav;
