--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part819 is 
  Port (
    lo0888: in std_logic;
    n4739: inout std_logic
  );
end Cookbook__fec_check__part819;

architecture Cookbook__fec_check__part819_behav of Cookbook__fec_check__part819 is
begin
    n4739 <= ( lo0888 );
end Cookbook__fec_check__part819_behav;
