--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__cfft__part54 is 
  Port (
    lo0226: in std_logic;
    n2352: inout std_logic
  );
end Other__cfft__part54;

architecture Other__cfft__part54_behav of Other__cfft__part54 is
begin
    n2352 <= ( lo0226 );
end Other__cfft__part54_behav;
