--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_32bit__part70 is 
  Port (
    lo146: in std_logic;
    po32: inout std_logic
  );
end Cookbook__soft_ecc_ram_32bit__part70;

architecture Cookbook__soft_ecc_ram_32bit__part70_behav of Cookbook__soft_ecc_ram_32bit__part70 is
begin
    po32 <= ( lo146 );
end Cookbook__soft_ecc_ram_32bit__part70_behav;
