--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1221 is 
  Port (
    lo7660: in std_logic;
    n42264: inout std_logic
  );
end Other__carpat__part1221;

architecture Other__carpat__part1221_behav of Other__carpat__part1221 is
begin
    n42264 <= ( lo7660 );
end Other__carpat__part1221_behav;
