--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part152 is 
  Port (
    lo035: in std_logic;
    po038: inout std_logic
  );
end Other__fpu__part152;

architecture Other__fpu__part152_behav of Other__fpu__part152 is
begin
    po038 <= ( lo035 );
end Other__fpu__part152_behav;
