--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__mem_ctrl__part82 is 
  Port (
    lo0465: in std_logic;
    po099: inout std_logic
  );
end IWLS2005__mem_ctrl__part82;

architecture IWLS2005__mem_ctrl__part82_behav of IWLS2005__mem_ctrl__part82 is
begin
    po099 <= ( lo0465 );
end IWLS2005__mem_ctrl__part82_behav;
