--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon3__part136 is 
  Port (
    lo184950: in std_logic;
    n924631: inout std_logic
  );
end IWLS2005__leon3__part136;

architecture IWLS2005__leon3__part136_behav of IWLS2005__leon3__part136 is
begin
    n924631 <= ( lo184950 );
end IWLS2005__leon3__part136_behav;
