--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1481 is 
  Port (
    lo1550: in std_logic;
    n8049: inout std_logic
  );
end Cookbook__fec_check__part1481;

architecture Cookbook__fec_check__part1481_behav of Cookbook__fec_check__part1481 is
begin
    n8049 <= ( lo1550 );
end Cookbook__fec_check__part1481_behav;
