--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1063 is 
  Port (
    lo4432: in std_logic;
    n17649: inout std_logic
  );
end Other__sudoku_check__part1063;

architecture Other__sudoku_check__part1063_behav of Other__sudoku_check__part1063 is
begin
    n17649 <= ( lo4432 );
end Other__sudoku_check__part1063_behav;
