--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part72 is 
  Port (
    pi072: in std_logic;
    n2202: inout std_logic
  );
end Other__fpu__part72;

architecture Other__fpu__part72_behav of Other__fpu__part72 is
begin
    n2202 <= ( pi072 );
end Other__fpu__part72_behav;
