--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part2132 is 
  Port (
    lo2201: in std_logic;
    n11304: inout std_logic
  );
end Cookbook__fec_check__part2132;

architecture Cookbook__fec_check__part2132_behav of Cookbook__fec_check__part2132 is
begin
    n11304 <= ( lo2201 );
end Cookbook__fec_check__part2132_behav;
