--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1239 is 
  Port (
    lo2866: in std_logic;
    n18896: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1239;

architecture Other__ucsb_152_tap_fir__part1239_behav of Other__ucsb_152_tap_fir__part1239 is
begin
    n18896 <= ( lo2866 );
end Other__ucsb_152_tap_fir__part1239_behav;
