--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat10n_m12__part80 is 
  Port (
    lo79: in std_logic;
    po79: inout std_logic
  );
end Other__idxlat10n_m12__part80;

architecture Other__idxlat10n_m12__part80_behav of Other__idxlat10n_m12__part80 is
begin
    po79 <= ( lo79 );
end Other__idxlat10n_m12__part80_behav;
