--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part431 is 
  Port (
    lo1542: in std_logic;
    n8969_1: inout std_logic
  );
end Cookbook__ucrypt__part431;

architecture Cookbook__ucrypt__part431_behav of Cookbook__ucrypt__part431 is
begin
    n8969_1 <= ( lo1542 );
end Cookbook__ucrypt__part431_behav;
