--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1767 is 
  Port (
    lo1836: in std_logic;
    n9479: inout std_logic
  );
end Cookbook__fec_check__part1767;

architecture Cookbook__fec_check__part1767_behav of Cookbook__fec_check__part1767 is
begin
    n9479 <= ( lo1836 );
end Cookbook__fec_check__part1767_behav;
