--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__soft_ecc_ram_64bit__part102 is 
  Port (
    lo228: in std_logic;
    po110: inout std_logic
  );
end Cookbook__soft_ecc_ram_64bit__part102;

architecture Cookbook__soft_ecc_ram_64bit__part102_behav of Cookbook__soft_ecc_ram_64bit__part102 is
begin
    po110 <= ( lo228 );
end Cookbook__soft_ecc_ram_64bit__part102_behav;
