--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part341 is 
  Port (
    lo1228: in std_logic;
    n7399_1: inout std_logic
  );
end Cookbook__ucrypt__part341;

architecture Cookbook__ucrypt__part341_behav of Cookbook__ucrypt__part341 is
begin
    n7399_1 <= ( lo1228 );
end Cookbook__ucrypt__part341_behav;
