--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part39 is 
  Port (
    pi039: in std_logic;
    n9844_1: inout std_logic
  );
end Other__desperf__part39;

architecture Other__desperf__part39_behav of Other__desperf__part39 is
begin
    n9844_1 <= ( pi039 );
end Other__desperf__part39_behav;
