--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part244 is 
  Port (
    lo0875: in std_logic;
    n5484: inout std_logic
  );
end Cookbook__ucrypt__part244;

architecture Cookbook__ucrypt__part244_behav of Cookbook__ucrypt__part244 is
begin
    n5484 <= ( lo0875 );
end Cookbook__ucrypt__part244_behav;
