--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part153 is 
  Port (
    pi1061: in std_logic;
    n31879: inout std_logic
  );
end Other__carpat__part153;

architecture Other__carpat__part153_behav of Other__carpat__part153 is
begin
    n31879 <= ( pi1061 );
end Other__carpat__part153_behav;
