--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1748 is 
  Port (
    lo6532: in std_logic;
    n32665_1: inout std_logic
  );
end IWLS2005__des_perf__part1748;

architecture IWLS2005__des_perf__part1748_behav of IWLS2005__des_perf__part1748 is
begin
    n32665_1 <= ( lo6532 );
end IWLS2005__des_perf__part1748_behav;
