--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part165 is 
  Port (
    lo264: in std_logic;
    n832: inout std_logic
  );
end Other__fpu__part165;

architecture Other__fpu__part165_behav of Other__fpu__part165 is
begin
    n832 <= ( lo264 );
end Other__fpu__part165_behav;
