--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__idxlat02n_m12__part42 is 
  Port (
    lo41: in std_logic;
    po41: inout std_logic
  );
end Other__idxlat02n_m12__part42;

architecture Other__idxlat02n_m12__part42_behav of Other__idxlat02n_m12__part42 is
begin
    po41 <= ( lo41 );
end Other__idxlat02n_m12__part42_behav;
