--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1111 is 
  Port (
    lo1180: in std_logic;
    n6199: inout std_logic
  );
end Cookbook__fec_check__part1111;

architecture Cookbook__fec_check__part1111_behav of Cookbook__fec_check__part1111 is
begin
    n6199 <= ( lo1180 );
end Cookbook__fec_check__part1111_behav;
