--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part409 is 
  Port (
    lo0478: in std_logic;
    n2689: inout std_logic
  );
end Cookbook__fec_check__part409;

architecture Cookbook__fec_check__part409_behav of Cookbook__fec_check__part409 is
begin
    n2689 <= ( lo0478 );
end Cookbook__fec_check__part409_behav;
