--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1642 is 
  Port (
    lo1711: in std_logic;
    n8854: inout std_logic
  );
end Cookbook__fec_check__part1642;

architecture Cookbook__fec_check__part1642_behav of Cookbook__fec_check__part1642 is
begin
    n8854 <= ( lo1711 );
end Cookbook__fec_check__part1642_behav;
