--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part65 is 
  Port (
    lo034: in std_logic;
    n654: inout std_logic
  );
end Cookbook__gearbox_40_67__part65;

architecture Cookbook__gearbox_40_67__part65_behav of Cookbook__gearbox_40_67__part65 is
begin
    n654 <= ( lo034 );
end Cookbook__gearbox_40_67__part65_behav;
