--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__prolog__part3 is 
  Port (
    pi18,pi19: in std_logic;
    n455: inout std_logic
  );
end ISCAS__prolog__part3;

architecture ISCAS__prolog__part3_behav of ISCAS__prolog__part3 is
begin
    n455 <= ( pi18 and pi19 );
end ISCAS__prolog__part3_behav;
