--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1142 is 
  Port (
    lo12989: in std_logic;
    po1967,po2001,po2147,po2181,n51676: inout std_logic
  );
end Other__ray__part1142;

architecture Other__ray__part1142_behav of Other__ray__part1142 is
begin
    po1967 <= ( lo12989 );
    po2001 <= ( lo12989 );
    po2147 <= ( lo12989 );
    po2181 <= ( lo12989 );
    n51676 <= ( lo12989 );
end Other__ray__part1142_behav;
