--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part13 is 
  Port (
    lo0011: in std_logic;
    po0015: inout std_logic
  );
end Other__ether__part13;

architecture Other__ether__part13_behav of Other__ether__part13 is
begin
    po0015 <= ( lo0011 );
end Other__ether__part13_behav;
