--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part201 is 
  Port (
    lo0270: in std_logic;
    n1649: inout std_logic
  );
end Cookbook__fec_check__part201;

architecture Cookbook__fec_check__part201_behav of Cookbook__fec_check__part201 is
begin
    n1649 <= ( lo0270 );
end Cookbook__fec_check__part201_behav;
