--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part8 is 
  Port (
    lo00108: in std_logic;
    po008: inout std_logic
  );
end IWLS2005__ethernet__part8;

architecture IWLS2005__ethernet__part8_behav of IWLS2005__ethernet__part8 is
begin
    po008 <= ( lo00108 );
end IWLS2005__ethernet__part8_behav;
