--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part29 is 
  Port (
    lo0027: in std_logic;
    po0031: inout std_logic
  );
end Other__ether__part29;

architecture Other__ether__part29_behav of Other__ether__part29 is
begin
    po0031 <= ( lo0027 );
end Other__ether__part29_behav;
