--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part347 is 
  Port (
    lo2104: in std_logic;
    n11010: inout std_logic
  );
end IWLS2005__des_perf__part347;

architecture IWLS2005__des_perf__part347_behav of IWLS2005__des_perf__part347 is
begin
    n11010 <= ( lo2104 );
end IWLS2005__des_perf__part347_behav;
