--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part216 is 
  Port (
    lo0515: in std_logic;
    n7151: inout std_logic
  );
end Other__ucsb_152_tap_fir__part216;

architecture Other__ucsb_152_tap_fir__part216_behav of Other__ucsb_152_tap_fir__part216 is
begin
    n7151 <= ( lo0515 );
end Other__ucsb_152_tap_fir__part216_behav;
