--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part100 is 
  Port (
    lo10518: in std_logic;
    n52693: inout std_logic
  );
end IWLS2005__ethernet__part100;

architecture IWLS2005__ethernet__part100_behav of IWLS2005__ethernet__part100 is
begin
    n52693 <= ( lo10518 );
end IWLS2005__ethernet__part100_behav;
