--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2145 is 
  Port (
    lo7291: in std_logic;
    n36265_1: inout std_logic
  );
end IWLS2005__des_perf__part2145;

architecture IWLS2005__des_perf__part2145_behav of IWLS2005__des_perf__part2145 is
begin
    n36265_1 <= ( lo7291 );
end IWLS2005__des_perf__part2145_behav;
