--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part366 is 
  Port (
    lo3015: in std_logic;
    n8579: inout std_logic
  );
end Other__sudoku_check__part366;

architecture Other__sudoku_check__part366_behav of Other__sudoku_check__part366 is
begin
    n8579 <= ( lo3015 );
end Other__sudoku_check__part366_behav;
