--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__ethernet__part75 is 
  Port (
    lo10384,lo10447: in std_logic;
    n52083_1,n52333_1: inout std_logic
  );
end IWLS2005__ethernet__part75;

architecture IWLS2005__ethernet__part75_behav of IWLS2005__ethernet__part75 is
begin
    n52083_1 <= ( not lo10384 and lo10447 );
    n52333_1 <= ( lo10447 );
end IWLS2005__ethernet__part75_behav;
