--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1409 is 
  Port (
    lo4778: in std_logic;
    n19379_1: inout std_logic
  );
end Other__sudoku_check__part1409;

architecture Other__sudoku_check__part1409_behav of Other__sudoku_check__part1409 is
begin
    n19379_1 <= ( lo4778 );
end Other__sudoku_check__part1409_behav;
