--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part110 is 
  Port (
    lo0746: in std_logic;
    n3689: inout std_logic
  );
end IWLS93__s38417__part110;

architecture IWLS93__s38417__part110_behav of IWLS93__s38417__part110 is
begin
    n3689 <= ( lo0746 );
end IWLS93__s38417__part110_behav;
