--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part588 is 
  Port (
    lo2147: in std_logic;
    n11954_1: inout std_logic
  );
end Cookbook__ucrypt__part588;

architecture Cookbook__ucrypt__part588_behav of Cookbook__ucrypt__part588 is
begin
    n11954_1 <= ( lo2147 );
end Cookbook__ucrypt__part588_behav;
