--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part887 is 
  Port (
    lo4734: in std_logic;
    n23755: inout std_logic
  );
end IWLS2005__des_perf__part887;

architecture IWLS2005__des_perf__part887_behav of IWLS2005__des_perf__part887 is
begin
    n23755 <= ( lo4734 );
end IWLS2005__des_perf__part887_behav;
