--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part1151 is 
  Port (
    lo5309: in std_logic;
    n26270: inout std_logic
  );
end IWLS2005__des_perf__part1151;

architecture IWLS2005__des_perf__part1151_behav of IWLS2005__des_perf__part1151 is
begin
    n26270 <= ( lo5309 );
end IWLS2005__des_perf__part1151_behav;
