--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ether__part3 is 
  Port (
    lo0001: in std_logic;
    po0001: inout std_logic
  );
end Other__ether__part3;

architecture Other__ether__part3_behav of Other__ether__part3 is
begin
    po0001 <= ( lo0001 );
end Other__ether__part3_behav;
