--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part1141 is 
  Port (
    lo2665: in std_logic;
    n17906: inout std_logic
  );
end Other__ucsb_152_tap_fir__part1141;

architecture Other__ucsb_152_tap_fir__part1141_behav of Other__ucsb_152_tap_fir__part1141 is
begin
    n17906 <= ( lo2665 );
end Other__ucsb_152_tap_fir__part1141_behav;
