--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fpu__part246 is 
  Port (
    lo420: in std_logic;
    n1432: inout std_logic
  );
end Other__fpu__part246;

architecture Other__fpu__part246_behav of Other__fpu__part246 is
begin
    n1432 <= ( lo420 );
end Other__fpu__part246_behav;
