--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part4 is 
  Port (
    pi06: in std_logic;
    n6834_1: inout std_logic
  );
end IWLS93__s38417__part4;

architecture IWLS93__s38417__part4_behav of IWLS93__s38417__part4 is
begin
    n6834_1 <= ( pi06 );
end IWLS93__s38417__part4_behav;
