--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part429 is 
  Port (
    lo3078: in std_logic;
    n9209: inout std_logic
  );
end Other__sudoku_check__part429;

architecture Other__sudoku_check__part429_behav of Other__sudoku_check__part429 is
begin
    n9209 <= ( lo3078 );
end Other__sudoku_check__part429_behav;
