--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_div__part51 is 
  Port (
    lo48: in std_logic;
    n496: inout std_logic
  );
end Cookbook__approx_fp_div__part51;

architecture Cookbook__approx_fp_div__part51_behav of Cookbook__approx_fp_div__part51 is
begin
    n496 <= ( lo48 );
end Cookbook__approx_fp_div__part51_behav;
