--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part895 is 
  Port (
    lo6731: in std_logic;
    n33034_1: inout std_logic
  );
end Other__carpat__part895;

architecture Other__carpat__part895_behav of Other__carpat__part895 is
begin
    n33034_1 <= ( lo6731 );
end Other__carpat__part895_behav;
