--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1148 is 
  Port (
    lo1217: in std_logic;
    n6384: inout std_logic
  );
end Cookbook__fec_check__part1148;

architecture Cookbook__fec_check__part1148_behav of Cookbook__fec_check__part1148 is
begin
    n6384 <= ( lo1217 );
end Cookbook__fec_check__part1148_behav;
