--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part296 is 
  Port (
    lo1147: in std_logic;
    n6230: inout std_logic
  );
end IWLS2005__des_perf__part296;

architecture IWLS2005__des_perf__part296_behav of IWLS2005__des_perf__part296 is
begin
    n6230 <= ( lo1147 );
end IWLS2005__des_perf__part296_behav;
