--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part916 is 
  Port (
    lo10077: in std_logic;
    n65831_1: inout std_logic
  );
end Other__ray__part916;

architecture Other__ray__part916_behav of Other__ray__part916 is
begin
    n65831_1 <= ( lo10077 );
end Other__ray__part916_behav;
