--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part61 is 
  Port (
    lo0348: in std_logic;
    n1544: inout std_logic
  );
end IWLS93__s38417__part61;

architecture IWLS93__s38417__part61_behav of IWLS93__s38417__part61 is
begin
    n1544 <= ( lo0348 );
end IWLS93__s38417__part61_behav;
