--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part319 is 
  Port (
    lo03724: in std_logic;
    po6275,po6326,po6581,po6632: inout std_logic
  );
end Other__ray__part319;

architecture Other__ray__part319_behav of Other__ray__part319 is
begin
    po6275 <= ( lo03724 );
    po6326 <= ( lo03724 );
    po6581 <= ( lo03724 );
    po6632 <= ( lo03724 );
end Other__ray__part319_behav;
