--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__temp_sense_s5__part4 is 
  Port (
    lo21: in std_logic;
    n178: inout std_logic
  );
end Cookbook__temp_sense_s5__part4;

architecture Cookbook__temp_sense_s5__part4_behav of Cookbook__temp_sense_s5__part4 is
begin
    n178 <= ( lo21 );
end Cookbook__temp_sense_s5__part4_behav;
