--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part628 is 
  Port (
    lo0697: in std_logic;
    n3784: inout std_logic
  );
end Cookbook__fec_check__part628;

architecture Cookbook__fec_check__part628_behav of Cookbook__fec_check__part628 is
begin
    n3784 <= ( lo0697 );
end Cookbook__fec_check__part628_behav;
