--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__leon2__part21 is 
  Port (
    pi21: in std_logic;
    n746827: inout std_logic
  );
end IWLS2005__leon2__part21;

architecture IWLS2005__leon2__part21_behav of IWLS2005__leon2__part21 is
begin
    n746827 <= ( pi21 );
end IWLS2005__leon2__part21_behav;
