--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2026 is 
  Port (
    lo7065: in std_logic;
    n35630_1: inout std_logic
  );
end IWLS2005__des_perf__part2026;

architecture IWLS2005__des_perf__part2026_behav of IWLS2005__des_perf__part2026 is
begin
    n35630_1 <= ( lo7065 );
end IWLS2005__des_perf__part2026_behav;
