--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part612 is 
  Port (
    lo06093: in std_logic;
    n38411: inout std_logic
  );
end Other__ray__part612;

architecture Other__ray__part612_behav of Other__ray__part612 is
begin
    n38411 <= ( lo06093 );
end Other__ray__part612_behav;
