--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part112 is 
  Port (
    lo0214: in std_logic;
    n5516: inout std_logic
  );
end Other__ucsb_152_tap_fir__part112;

architecture Other__ucsb_152_tap_fir__part112_behav of Other__ucsb_152_tap_fir__part112 is
begin
    n5516 <= ( lo0214 );
end Other__ucsb_152_tap_fir__part112_behav;
