--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2578 is 
  Port (
    lo7835: in std_logic;
    n39225_1: inout std_logic
  );
end IWLS2005__des_perf__part2578;

architecture IWLS2005__des_perf__part2578_behav of IWLS2005__des_perf__part2578 is
begin
    n39225_1 <= ( lo7835 );
end IWLS2005__des_perf__part2578_behav;
