--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part1125 is 
  Port (
    lo12972: in std_logic;
    po1950,po2013,po2130,po2193,n51591_1: inout std_logic
  );
end Other__ray__part1125;

architecture Other__ray__part1125_behav of Other__ray__part1125 is
begin
    po1950 <= ( lo12972 );
    po2013 <= ( lo12972 );
    po2130 <= ( lo12972 );
    po2193 <= ( lo12972 );
    n51591_1 <= ( lo12972 );
end Other__ray__part1125_behav;
