--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__min_max__part12 is 
  Port (
    lo11: in std_logic;
    po04: inout std_logic
  );
end Cookbook__min_max__part12;

architecture Cookbook__min_max__part12_behav of Cookbook__min_max__part12 is
begin
    po04 <= ( lo11 );
end Cookbook__min_max__part12_behav;
