--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part639 is 
  Port (
    lo5052: in std_logic;
    n22469: inout std_logic
  );
end Other__carpat__part639;

architecture Other__carpat__part639_behav of Other__carpat__part639 is
begin
    n22469 <= ( lo5052 );
end Other__carpat__part639_behav;
