--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part952 is 
  Port (
    lo10615: in std_logic;
    n71011_1: inout std_logic
  );
end Other__ray__part952;

architecture Other__ray__part952_behav of Other__ray__part952 is
begin
    n71011_1 <= ( lo10615 );
end Other__ray__part952_behav;
