--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part126 is 
  Port (
    pi0981: in std_logic;
    n31994_1: inout std_logic
  );
end Other__carpat__part126;

architecture Other__carpat__part126_behav of Other__carpat__part126 is
begin
    n31994_1 <= ( pi0981 );
end Other__carpat__part126_behav;
