--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part2728 is 
  Port (
    lo8041: in std_logic;
    n40540_1: inout std_logic
  );
end IWLS2005__des_perf__part2728;

architecture IWLS2005__des_perf__part2728_behav of IWLS2005__des_perf__part2728 is
begin
    n40540_1 <= ( lo8041 );
end IWLS2005__des_perf__part2728_behav;
