--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part717 is 
  Port (
    lo4402: in std_logic;
    n22200: inout std_logic
  );
end IWLS2005__des_perf__part717;

architecture IWLS2005__des_perf__part717_behav of IWLS2005__des_perf__part717 is
begin
    n22200 <= ( lo4402 );
end IWLS2005__des_perf__part717_behav;
