--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_67_40__part55 is 
  Port (
    lo222: in std_logic;
    po28: inout std_logic
  );
end Cookbook__gearbox_67_40__part55;

architecture Cookbook__gearbox_67_40__part55_behav of Cookbook__gearbox_67_40__part55 is
begin
    po28 <= ( lo222 );
end Cookbook__gearbox_67_40__part55_behav;
