--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part601 is 
  Port (
    lo4211: in std_logic;
    n21165: inout std_logic
  );
end IWLS2005__des_perf__part601;

architecture IWLS2005__des_perf__part601_behav of IWLS2005__des_perf__part601 is
begin
    n21165 <= ( lo4211 );
end IWLS2005__des_perf__part601_behav;
