--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__desperf__part147 is 
  Port (
    lo0027: in std_logic;
    po27: inout std_logic
  );
end Other__desperf__part147;

architecture Other__desperf__part147_behav of Other__desperf__part147 is
begin
    po27 <= ( lo0027 );
end Other__desperf__part147_behav;
