--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part788 is 
  Port (
    lo0857: in std_logic;
    n4584: inout std_logic
  );
end Cookbook__fec_check__part788;

architecture Cookbook__fec_check__part788_behav of Cookbook__fec_check__part788 is
begin
    n4584 <= ( lo0857 );
end Cookbook__fec_check__part788_behav;
