--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part1418 is 
  Port (
    lo7868: in std_logic;
    n44219_1: inout std_logic
  );
end Other__carpat__part1418;

architecture Other__carpat__part1418_behav of Other__carpat__part1418 is
begin
    n44219_1 <= ( lo7868 );
end Other__carpat__part1418_behav;
