--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part11 is 
  Port (
    lo0080: in std_logic;
    n699: inout std_logic
  );
end Cookbook__fec_check__part11;

architecture Cookbook__fec_check__part11_behav of Cookbook__fec_check__part11 is
begin
    n699 <= ( lo0080 );
end Cookbook__fec_check__part11_behav;
