--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ray__part946 is 
  Port (
    lo10527: in std_logic;
    n69176_1: inout std_logic
  );
end Other__ray__part946;

architecture Other__ray__part946_behav of Other__ray__part946 is
begin
    n69176_1 <= ( lo10527 );
end Other__ray__part946_behav;
