--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part328 is 
  Port (
    lo2977: in std_logic;
    n8199: inout std_logic
  );
end Other__sudoku_check__part328;

architecture Other__sudoku_check__part328_behav of Other__sudoku_check__part328 is
begin
    n8199 <= ( lo2977 );
end Other__sudoku_check__part328_behav;
