--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipeline_add_msb__part11 is 
  Port (
    pi20: in std_logic;
    n218: inout std_logic
  );
end Cookbook__pipeline_add_msb__part11;

architecture Cookbook__pipeline_add_msb__part11_behav of Cookbook__pipeline_add_msb__part11 is
begin
    n218 <= ( pi20 );
end Cookbook__pipeline_add_msb__part11_behav;
