--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part677 is 
  Port (
    lo3326: in std_logic;
    n11689: inout std_logic
  );
end Other__sudoku_check__part677;

architecture Other__sudoku_check__part677_behav of Other__sudoku_check__part677 is
begin
    n11689 <= ( lo3326 );
end Other__sudoku_check__part677_behav;
