--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part213 is 
  Port (
    lo0947: in std_logic;
    n6680_1: inout std_logic
  );
end Other__fp_operators__part213;

architecture Other__fp_operators__part213_behav of Other__fp_operators__part213 is
begin
    n6680_1 <= ( lo0947 );
end Other__fp_operators__part213_behav;
