--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__approx_fp_invsqrt__part39 is 
  Port (
    lo038: in std_logic;
    n500: inout std_logic
  );
end Cookbook__approx_fp_invsqrt__part39;

architecture Cookbook__approx_fp_invsqrt__part39_behav of Cookbook__approx_fp_invsqrt__part39 is
begin
    n500 <= ( lo038 );
end Cookbook__approx_fp_invsqrt__part39_behav;
