--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__aes_core__part106 is 
  Port (
    lo344: in std_logic;
    po123: inout std_logic
  );
end IWLS2005__aes_core__part106;

architecture IWLS2005__aes_core__part106_behav of IWLS2005__aes_core__part106 is
begin
    po123 <= ( lo344 );
end IWLS2005__aes_core__part106_behav;
