--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part614 is 
  Port (
    lo5002: in std_logic;
    n22109: inout std_logic
  );
end Other__carpat__part614;

architecture Other__carpat__part614_behav of Other__carpat__part614 is
begin
    n22109 <= ( lo5002 );
end Other__carpat__part614_behav;
