--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__systemcdes__part60 is 
  Port (
    lo184: in std_logic;
    po06: inout std_logic
  );
end IWLS2005__systemcdes__part60;

architecture IWLS2005__systemcdes__part60_behav of IWLS2005__systemcdes__part60 is
begin
    po06 <= ( lo184 );
end IWLS2005__systemcdes__part60_behav;
