--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ucrypt__part503 is 
  Port (
    lo1838: in std_logic;
    n10449_1: inout std_logic
  );
end Cookbook__ucrypt__part503;

architecture Cookbook__ucrypt__part503_behav of Cookbook__ucrypt__part503 is
begin
    n10449_1 <= ( lo1838 );
end Cookbook__ucrypt__part503_behav;
