--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ucsb_152_tap_fir__part2186 is 
  Port (
    lo4849: in std_logic;
    n28836: inout std_logic
  );
end Other__ucsb_152_tap_fir__part2186;

architecture Other__ucsb_152_tap_fir__part2186_behav of Other__ucsb_152_tap_fir__part2186 is
begin
    n28836 <= ( lo4849 );
end Other__ucsb_152_tap_fir__part2186_behav;
