--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part1258 is 
  Port (
    lo4627: in std_logic;
    n18624: inout std_logic
  );
end Other__sudoku_check__part1258;

architecture Other__sudoku_check__part1258_behav of Other__sudoku_check__part1258 is
begin
    n18624 <= ( lo4627 );
end Other__sudoku_check__part1258_behav;
