--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part551 is 
  Port (
    lo0620: in std_logic;
    n3399: inout std_logic
  );
end Cookbook__fec_check__part551;

architecture Cookbook__fec_check__part551_behav of Cookbook__fec_check__part551 is
begin
    n3399 <= ( lo0620 );
end Cookbook__fec_check__part551_behav;
