--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ISCAS__s38417__part15 is 
  Port (
    pi19: in std_logic;
    n384: inout std_logic
  );
end ISCAS__s38417__part15;

architecture ISCAS__s38417__part15_behav of ISCAS__s38417__part15 is
begin
    n384 <= ( pi19 );
end ISCAS__s38417__part15_behav;
