--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part1448 is 
  Port (
    lo1517: in std_logic;
    n7884: inout std_logic
  );
end Cookbook__fec_check__part1448;

architecture Cookbook__fec_check__part1448_behav of Cookbook__fec_check__part1448 is
begin
    n7884 <= ( lo1517 );
end Cookbook__fec_check__part1448_behav;
