--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part215 is 
  Port (
    lo0949: in std_logic;
    n6690_1: inout std_logic
  );
end Other__fp_operators__part215;

architecture Other__fp_operators__part215_behav of Other__fp_operators__part215 is
begin
    n6690_1 <= ( lo0949 );
end Other__fp_operators__part215_behav;
