--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS93__s38417__part29 is 
  Port (
    lo0091: in std_logic;
    n1214: inout std_logic
  );
end IWLS93__s38417__part29;

architecture IWLS93__s38417__part29_behav of IWLS93__s38417__part29 is
begin
    n1214 <= ( lo0091 );
end IWLS93__s38417__part29_behav;
