--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity IWLS2005__des_perf__part759 is 
  Port (
    lo4495: in std_logic;
    n22380: inout std_logic
  );
end IWLS2005__des_perf__part759;

architecture IWLS2005__des_perf__part759_behav of IWLS2005__des_perf__part759 is
begin
    n22380 <= ( lo4495 );
end IWLS2005__des_perf__part759_behav;
