--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part150 is 
  Port (
    lo2799: in std_logic;
    n6419: inout std_logic
  );
end Other__sudoku_check__part150;

architecture Other__sudoku_check__part150_behav of Other__sudoku_check__part150 is
begin
    n6419 <= ( lo2799 );
end Other__sudoku_check__part150_behav;
