--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__lc_mult_signed__part25 is 
  Port (
    lo011: in std_logic;
    po018: inout std_logic
  );
end Cookbook__lc_mult_signed__part25;

architecture Cookbook__lc_mult_signed__part25_behav of Cookbook__lc_mult_signed__part25 is
begin
    po018 <= ( lo011 );
end Cookbook__lc_mult_signed__part25_behav;
