--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__ava__part3 is 
  Port (
    lo0719: in std_logic;
    n2697: inout std_logic
  );
end Other__ava__part3;

architecture Other__ava__part3_behav of Other__ava__part3 is
begin
    n2697 <= ( lo0719 );
end Other__ava__part3_behav;
