--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi02,pi09,pi16,pi26,pi33,pi40,pi50,pi57,pi64: in std_logic;
    po02,po09: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po02 <= ( not pi26 and pi33 and not pi40 )
      or ( not pi09 and pi33 and not pi57 )
      or ( pi09 and not pi16 and pi33 and pi40 and not pi50 )
      or ( not pi16 and pi26 and pi33 and pi40 and not pi50 )
      or ( pi09 and not pi16 and pi33 and not pi50 and pi57 )
      or ( not pi16 and pi26 and pi33 and not pi50 and pi57 )
      or ( not pi02 and pi09 and pi26 and pi33 and not pi64 )
      or ( not pi02 and pi26 and pi33 and pi40 and not pi64 )
      or ( not pi02 and pi09 and pi33 and pi57 and not pi64 )
      or ( not pi02 and pi33 and pi40 and pi57 and not pi64 );
    po09 <= ( pi26 and not pi33 and pi40 )
      or ( pi09 and not pi33 and pi57 )
      or ( not pi09 and pi16 and not pi33 and not pi40 and pi50 )
      or ( pi16 and not pi26 and not pi33 and not pi40 and pi50 )
      or ( not pi09 and pi16 and not pi33 and pi50 and not pi57 )
      or ( pi16 and not pi26 and not pi33 and pi50 and not pi57 )
      or ( pi02 and not pi09 and not pi26 and not pi33 and pi64 )
      or ( pi02 and not pi26 and not pi33 and not pi40 and pi64 )
      or ( pi02 and not pi09 and not pi33 and not pi57 and pi64 )
      or ( pi02 and not pi33 and not pi40 and not pi57 and pi64 );
end top_behav;
