--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part72 is 
  Port (
    lo5825,lo5826,lo5827,lo5828: in std_logic;
    n27744_1,n29419,n29604_1,n29784,n29964,n30144,n30324,n30504,n30684: inout std_logic
  );
end Other__sudoku_check__part72;

architecture Other__sudoku_check__part72_behav of Other__sudoku_check__part72 is
begin
    n27744_1 <= ( lo5825 and not lo5826 and not lo5827 and not lo5828 );
    n29419 <= ( lo5825 and not lo5826 and not lo5827 and lo5828 );
    n29604_1 <= ( not lo5825 and not lo5826 and not lo5827 and lo5828 );
    n29784 <= ( lo5825 and lo5826 and lo5827 and not lo5828 );
    n29964 <= ( not lo5825 and lo5826 and lo5827 and not lo5828 );
    n30144 <= ( lo5825 and not lo5826 and lo5827 and not lo5828 );
    n30324 <= ( not lo5825 and not lo5826 and lo5827 and not lo5828 );
    n30504 <= ( lo5825 and lo5826 and not lo5827 and not lo5828 );
    n30684 <= ( not lo5825 and lo5826 and not lo5827 and not lo5828 );
end Other__sudoku_check__part72_behav;
