--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po0 <= ( not pi00 )
      or ( not pi04 and not pi10 )
      or ( pi04 and not pi11 );
    po1 <= ( not pi01 )
      or ( not pi05 and not pi10 )
      or ( pi05 and not pi11 );
    po2 <= ( not pi02 )
      or ( not pi06 and not pi10 )
      or ( pi06 and not pi11 );
    po3 <= ( not pi03 )
      or ( not pi07 and not pi10 )
      or ( pi07 and not pi11 );
    po4 <= ( not pi00 and pi04 and not pi08 )
      or ( not pi00 and not pi04 and not pi09 );
    po5 <= ( not pi01 and pi05 and not pi08 )
      or ( not pi01 and not pi05 and not pi09 );
    po6 <= ( not pi02 and pi06 and not pi08 )
      or ( not pi02 and not pi06 and not pi09 );
    po7 <= ( not pi03 and pi07 and not pi08 );
end top_behav;
