--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part11 is 
  Port (
    lo04199,lo04202,lo04201,lo04200,lo04203: in std_logic;
    n27406,n27411,n27421,n27416,n27426: inout std_logic
  );
end QUIP__uoft_raytracer__part11;

architecture QUIP__uoft_raytracer__part11_behav of QUIP__uoft_raytracer__part11 is
signal n52716,n52717,n77348,n77349: std_logic;
begin
    n52716 <= ( not lo04199 and lo04202 and not lo04201 );
    n52717 <= ( lo04200 and lo04203 and n52716 )
      or ( lo04203 and n77349 );
    n27406 <= ( not lo04199 and not n52717 );
    n27411 <= ( not lo04200 and lo04199 and not n52717 )
      or ( lo04200 and not lo04199 and not n52717 );
    n27421 <= ( not lo04202 and n77348 and not n52717 )
      or ( lo04202 and not n77348 and not n52717 );
    n77348 <= ( lo04200 and lo04199 and lo04201 );
    n77349 <= ( lo04200 and lo04199 and lo04201 and lo04202 );
    n27416 <= ( not lo04200 and lo04201 and not n52717 )
      or ( lo04200 and lo04199 and not lo04201 and not n52717 )
      or ( not lo04199 and lo04201 and not n52717 );
    n27426 <= ( not lo04200 and lo04203 and not n77349 )
      or ( not lo04203 and n77349 )
      or ( lo04203 and not n77349 and not n52716 );
end QUIP__uoft_raytracer__part11_behav;
