--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__ycbcr_to_rgb__part0 is 
  Port (
    pi03,pi02,pi01,pi00: in std_logic;
    n942,n947_1,n952_1,n957_1,n962_1: inout std_logic
  );
end Cookbook__ycbcr_to_rgb__part0;

architecture Cookbook__ycbcr_to_rgb__part0_behav of Cookbook__ycbcr_to_rgb__part0 is
signal n577,n579: std_logic;
begin
    n942 <= ( not pi03 );
    n947_1 <= ( not pi03 and not pi02 )
      or ( pi03 and pi02 );
    n577 <= not (( not pi03 and not pi02 ));
    n952_1 <= ( not n577 and not pi01 )
      or ( n577 and pi01 );
    n579 <= not (( not n577 and not pi01 ));
    n957_1 <= ( not n579 and not pi00 )
      or ( n579 and pi00 );
    n962_1 <= ( not n579 and not pi00 );
end Cookbook__ycbcr_to_rgb__part0_behav;
