--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__uoft_raytracer__part22 is 
  Port (
    lo04265,lo04266,lo04267,lo04268: in std_logic;
    n27736,n27741,n27746,n27751: inout std_logic
  );
end QUIP__uoft_raytracer__part22;

architecture QUIP__uoft_raytracer__part22_behav of QUIP__uoft_raytracer__part22 is
begin
    n27736 <= ( not lo04265 );
    n27741 <= ( not lo04266 and lo04265 )
      or ( lo04266 and not lo04265 );
    n27746 <= ( not lo04266 and lo04267 )
      or ( lo04266 and lo04265 and not lo04267 )
      or ( not lo04265 and lo04267 );
    n27751 <= ( not lo04266 and lo04268 )
      or ( lo04266 and lo04265 and lo04267 and not lo04268 )
      or ( not lo04265 and lo04268 )
      or ( not lo04267 and lo04268 );
end QUIP__uoft_raytracer__part22_behav;
