--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part81 is 
  Port (
    lo5861,lo5862,lo5863,lo5864: in std_logic;
    n27869_1,n29424,n29609_1,n29789_1,n29969_1,n30149,n30329,n30509,n30689: inout std_logic
  );
end Other__sudoku_check__part81;

architecture Other__sudoku_check__part81_behav of Other__sudoku_check__part81 is
begin
    n27869_1 <= ( lo5861 and not lo5862 and not lo5863 and not lo5864 );
    n29424 <= ( lo5861 and not lo5862 and not lo5863 and lo5864 );
    n29609_1 <= ( not lo5861 and not lo5862 and not lo5863 and lo5864 );
    n29789_1 <= ( lo5861 and lo5862 and lo5863 and not lo5864 );
    n29969_1 <= ( not lo5861 and lo5862 and lo5863 and not lo5864 );
    n30149 <= ( lo5861 and not lo5862 and lo5863 and not lo5864 );
    n30329 <= ( not lo5861 and not lo5862 and lo5863 and not lo5864 );
    n30509 <= ( lo5861 and lo5862 and not lo5863 and not lo5864 );
    n30689 <= ( not lo5861 and lo5862 and not lo5863 and not lo5864 );
end Other__sudoku_check__part81_behav;
