--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part27 is 
  Port (
    lo5645,lo5646,lo5647,lo5648: in std_logic;
    n27164_1,n28504_1,n28509_1,n28514,n28519_1,n28524_1,n28529,n28534_1,n28539_1: inout std_logic
  );
end Other__sudoku_check__part27;

architecture Other__sudoku_check__part27_behav of Other__sudoku_check__part27 is
begin
    n27164_1 <= ( lo5645 and not lo5646 and not lo5647 and not lo5648 );
    n28504_1 <= ( lo5645 and not lo5646 and not lo5647 and lo5648 );
    n28509_1 <= ( not lo5645 and not lo5646 and not lo5647 and lo5648 );
    n28514 <= ( lo5645 and lo5646 and lo5647 and not lo5648 );
    n28519_1 <= ( not lo5645 and lo5646 and lo5647 and not lo5648 );
    n28524_1 <= ( lo5645 and not lo5646 and lo5647 and not lo5648 );
    n28529 <= ( not lo5645 and not lo5646 and lo5647 and not lo5648 );
    n28534_1 <= ( lo5645 and lo5646 and not lo5647 and not lo5648 );
    n28539_1 <= ( not lo5645 and lo5646 and not lo5647 and not lo5648 );
end Other__sudoku_check__part27_behav;
