--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__fec_check__part64 is 
  Port (
    lo3742,lo3730,lo3706,lo3694,lo3718,lo3670,lo3658,lo3682,lo3634,lo3622,lo3646: in std_logic;
    n19059: inout std_logic
  );
end Cookbook__fec_check__part64;

architecture Cookbook__fec_check__part64_behav of Cookbook__fec_check__part64 is
signal n13462,n13463,n13464,n13465,n13466,n13467,n13468,n13469,n13470: std_logic;
begin
    n13462 <= not (( not lo3742 and not lo3730 ));
    n13463 <= not (( not lo3706 and not lo3694 ));
    n13464 <= not (( not lo3718 and not n13463 ));
    n13465 <= not (( not n13462 and not n13464 ));
    n13466 <= not (( not lo3670 and not lo3658 ));
    n13467 <= not (( not lo3682 and not n13466 ));
    n13468 <= not (( not lo3634 and not lo3622 ));
    n13469 <= not (( not lo3646 and not n13468 ));
    n13470 <= not (( not n13467 and not n13469 ));
    n19059 <= not (( not n13465 and not n13470 ));
end Cookbook__fec_check__part64_behav;
