--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__carpat__part135 is 
  Port (
    lo8761,lo8762: in std_logic;
    n49314_1,n49319_1: inout std_logic
  );
end Other__carpat__part135;

architecture Other__carpat__part135_behav of Other__carpat__part135 is
signal n37388,n37389,n135158,n135159: std_logic;
begin
    n37388 <= ( not lo8761 and lo8762 );
    n37389 <= not (( not n135159 and not n37388 ));
    n49314_1 <= ( not lo8761 and not n37389 );
    n49319_1 <= ( not n37389 and n135158 );
    n135158 <= ( not lo8762 and lo8761 )
      or ( lo8762 and not lo8761 );
    n135159 <= ( lo8762 and lo8761 );
end Other__carpat__part135_behav;
