--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi16,pi08,pi13,pi14,pi09,pi00,pi10,pi01,pi06,pi11,pi02,pi12,pi03: in std_logic;
    po00,po03,po04,po05,po06: inout std_logic
  );
end top;

architecture top_behav of top is
signal n65,n66,n111,n112,n113: std_logic;
begin
    po00 <= ( not pi16 and pi08 );
    po03 <= ( not pi08 and not n65 );
    po04 <= ( not pi13 and not pi08 );
    po05 <= ( pi14 and not pi08 );
    po06 <= ( not n66 );
    n65 <= ( pi09 and pi10 and not n111 )
      or ( not pi00 and pi10 and not n111 )
      or ( pi09 and not pi01 and not n111 )
      or ( not pi00 and not pi01 and not n111 );
    n66 <= ( not pi08 and pi06 );
    n111 <= ( not n112 )
      or ( not pi11 and pi02 )
      or ( not pi12 and pi03 );
    n112 <= ( not pi09 and not n113 )
      or ( pi00 and not n113 );
    n113 <= ( not pi01 and pi10 )
      or ( not pi02 and pi11 )
      or ( not pi03 and pi12 );
end top_behav;
