--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__pipe_equal__part10 is 
  Port (
    pi030,pi094,pi029,pi093,pi028,pi092: in std_logic;
    n344: inout std_logic
  );
end Cookbook__pipe_equal__part10;

architecture Cookbook__pipe_equal__part10_behav of Cookbook__pipe_equal__part10 is
signal n268,n269,n270,n271: std_logic;
begin
    n268 <= ( not pi030 and pi094 )
      or ( pi030 and not pi094 );
    n269 <= ( not pi029 and pi093 )
      or ( pi029 and not pi093 );
    n270 <= ( not pi028 and pi092 )
      or ( pi028 and not pi092 );
    n271 <= not (( not n269 and not n270 ));
    n344 <= ( not n268 and not n271 );
end Cookbook__pipe_equal__part10_behav;
