--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part33 is 
  Port (
    lo5669,lo5670,lo5671,lo5672: in std_logic;
    n27194_1,n28944_1,n28949_1,n28954_1,n28959_1,n28964,n28969,n28974_1,n28979: inout std_logic
  );
end Other__sudoku_check__part33;

architecture Other__sudoku_check__part33_behav of Other__sudoku_check__part33 is
begin
    n27194_1 <= ( lo5669 and not lo5670 and not lo5671 and not lo5672 );
    n28944_1 <= ( lo5669 and not lo5670 and not lo5671 and lo5672 );
    n28949_1 <= ( not lo5669 and not lo5670 and not lo5671 and lo5672 );
    n28954_1 <= ( lo5669 and lo5670 and lo5671 and not lo5672 );
    n28959_1 <= ( not lo5669 and lo5670 and lo5671 and not lo5672 );
    n28964 <= ( lo5669 and not lo5670 and lo5671 and not lo5672 );
    n28969 <= ( not lo5669 and not lo5670 and lo5671 and not lo5672 );
    n28974_1 <= ( lo5669 and lo5670 and not lo5671 and not lo5672 );
    n28979 <= ( not lo5669 and lo5670 and not lo5671 and not lo5672 );
end Other__sudoku_check__part33_behav;
