--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part59 is 
  Port (
    lo5773,lo5774,lo5775,lo5776: in std_logic;
    n27519_1,n29319_1,n29504,n29684,n29864_1,n30044,n30224,n30404,n30584: inout std_logic
  );
end Other__sudoku_check__part59;

architecture Other__sudoku_check__part59_behav of Other__sudoku_check__part59 is
begin
    n27519_1 <= ( lo5773 and not lo5774 and not lo5775 and not lo5776 );
    n29319_1 <= ( lo5773 and not lo5774 and not lo5775 and lo5776 );
    n29504 <= ( not lo5773 and not lo5774 and not lo5775 and lo5776 );
    n29684 <= ( lo5773 and lo5774 and lo5775 and not lo5776 );
    n29864_1 <= ( not lo5773 and lo5774 and lo5775 and not lo5776 );
    n30044 <= ( lo5773 and not lo5774 and lo5775 and not lo5776 );
    n30224 <= ( not lo5773 and not lo5774 and lo5775 and not lo5776 );
    n30404 <= ( lo5773 and lo5774 and not lo5775 and not lo5776 );
    n30584 <= ( not lo5773 and lo5774 and not lo5775 and not lo5776 );
end Other__sudoku_check__part59_behav;
