--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part66 is 
  Port (
    lo1599,lo1600,lo1601: in std_logic;
    n11370_1,n11375_1,n11380_1: inout std_logic
  );
end Other__fp_operators__part66;

architecture Other__fp_operators__part66_behav of Other__fp_operators__part66 is
signal n22784,n22785,n37126,n37127,n37128,n37129: std_logic;
begin
    n22784 <= ( lo1599 and not lo1600 and lo1601 );
    n22785 <= not (( not n37129 and not n22784 ));
    n11370_1 <= ( not lo1599 and not n22785 );
    n11375_1 <= ( not n22785 and n37126 );
    n11380_1 <= ( not n22785 and n37128 );
    n37126 <= ( not lo1600 and lo1599 )
      or ( lo1600 and not lo1599 );
    n37127 <= ( lo1600 and lo1599 );
    n37128 <= ( not lo1601 and n37127 )
      or ( lo1601 and not n37127 );
    n37129 <= ( lo1601 and n37127 );
end Other__fp_operators__part66_behav;
