--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part40 is 
  Port (
    lo5697,lo5698,lo5699,lo5700: in std_logic;
    n27264_1,n29414_1,n29599_1,n29779_1,n29959_1,n30139,n30319,n30499,n30679: inout std_logic
  );
end Other__sudoku_check__part40;

architecture Other__sudoku_check__part40_behav of Other__sudoku_check__part40 is
begin
    n27264_1 <= ( lo5697 and not lo5698 and not lo5699 and not lo5700 );
    n29414_1 <= ( lo5697 and not lo5698 and not lo5699 and lo5700 );
    n29599_1 <= ( not lo5697 and not lo5698 and not lo5699 and lo5700 );
    n29779_1 <= ( lo5697 and lo5698 and lo5699 and not lo5700 );
    n29959_1 <= ( not lo5697 and lo5698 and lo5699 and not lo5700 );
    n30139 <= ( lo5697 and not lo5698 and lo5699 and not lo5700 );
    n30319 <= ( not lo5697 and not lo5698 and lo5699 and not lo5700 );
    n30499 <= ( lo5697 and lo5698 and not lo5699 and not lo5700 );
    n30679 <= ( not lo5697 and lo5698 and not lo5699 and not lo5700 );
end Other__sudoku_check__part40_behav;
