--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__sudoku_check__part39 is 
  Port (
    lo5693,lo5694,lo5695,lo5696: in std_logic;
    n27259_1,n27879_1,n27884_1,n27889_1,n27894_1,n27899_1,n27904_1,n27909_1,n27914_1: inout std_logic
  );
end Other__sudoku_check__part39;

architecture Other__sudoku_check__part39_behav of Other__sudoku_check__part39 is
begin
    n27259_1 <= ( lo5693 and not lo5694 and not lo5695 and not lo5696 );
    n27879_1 <= ( lo5693 and not lo5694 and not lo5695 and lo5696 );
    n27884_1 <= ( not lo5693 and not lo5694 and not lo5695 and lo5696 );
    n27889_1 <= ( lo5693 and lo5694 and lo5695 and not lo5696 );
    n27894_1 <= ( not lo5693 and lo5694 and lo5695 and not lo5696 );
    n27899_1 <= ( lo5693 and not lo5694 and lo5695 and not lo5696 );
    n27904_1 <= ( not lo5693 and not lo5694 and lo5695 and not lo5696 );
    n27909_1 <= ( lo5693 and lo5694 and not lo5695 and not lo5696 );
    n27914_1 <= ( not lo5693 and lo5694 and not lo5695 and not lo5696 );
end Other__sudoku_check__part39_behav;
