--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity QUIP__nut_000__part2 is 
  Port (
    lo002,lo006,lo007,lo068,lo008,lo009,lo063,lo064,lo066,lo067,lo118,lo119,lo122,lo116,lo117,lo005: in std_logic;
    po02,po08,po09,po10,po11,po12,po13,n101,n121,n396,n91,n116,n401,n411,n416,n676,n421,n431,n661,n666,po05,n406: inout std_logic
  );
end QUIP__nut_000__part2;

architecture QUIP__nut_000__part2_behav of QUIP__nut_000__part2 is
signal n1028,n1327,n1341: std_logic;
begin
    po02 <= ( not lo002 );
    po08 <= ( not lo006 );
    po09 <= ( not lo006 );
    po10 <= ( not lo006 );
    po11 <= ( not lo006 );
    po12 <= ( not lo006 );
    po13 <= ( not lo006 );
    n101 <= ( not lo007 );
    n121 <= ( not lo068 );
    n1028 <= ( not lo008 and lo009 and not lo002 );
    n396 <= ( not lo063 );
    n91 <= ( lo002 and lo006 )
      or ( not lo006 and not lo063 );
    n116 <= ( lo007 and lo064 )
      or ( lo007 and lo066 )
      or ( lo064 and not lo066 and lo067 )
      or ( lo064 and lo066 and not lo067 );
    n401 <= not (( not lo064 and lo067 ));
    n411 <= ( lo064 and n1327 )
      or ( not n1327 and lo066 and not lo118 );
    n416 <= not (( lo064 and not lo067 ));
    n676 <= ( not lo118 );
    n421 <= ( lo068 and not n1341 )
      or ( n1341 and not lo119 );
    n431 <= ( lo118 and not lo122 );
    n661 <= ( lo116 )
      or ( lo002 and not lo117 );
    n666 <= not (( not lo002 and not lo117 ));
    po05 <= ( not lo005 and not lo006 and lo007 )
      or ( lo007 and not n1028 );
    n1327 <= ( not lo005 and not lo006 and not lo008 )
      or ( lo005 and lo008 )
      or ( lo006 and lo008 );
    n406 <= ( not lo002 and lo116 );
    n1341 <= ( not lo002 and lo118 )
      or ( lo116 and not lo118 );
end QUIP__nut_000__part2_behav;
