--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15: in std_logic;
    po0: inout std_logic
  );
end top;

architecture top_behav of top is
signal n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31: std_logic;
begin
    po0 <= ( not n18 and n19 )
      or ( n18 and not n19 );
    n18 <= ( not n28 and n29 )
      or ( n28 and not n29 );
    n19 <= ( not n30 and n31 )
      or ( n30 and not n31 );
    n20 <= ( not pi15 and pi14 )
      or ( pi15 and not pi14 );
    n21 <= ( not pi13 and pi12 )
      or ( pi13 and not pi12 );
    n22 <= ( not pi11 and pi10 )
      or ( pi11 and not pi10 );
    n23 <= ( not pi09 and pi08 )
      or ( pi09 and not pi08 );
    n24 <= ( not pi07 and pi06 )
      or ( pi07 and not pi06 );
    n25 <= ( not pi05 and pi04 )
      or ( pi05 and not pi04 );
    n26 <= ( not pi03 and pi02 )
      or ( pi03 and not pi02 );
    n27 <= ( not pi01 and pi00 )
      or ( pi01 and not pi00 );
    n28 <= ( not n20 and n21 )
      or ( n20 and not n21 );
    n29 <= ( not n22 and n23 )
      or ( n22 and not n23 );
    n30 <= ( not n24 and n25 )
      or ( n24 and not n25 );
    n31 <= ( not n26 and n27 )
      or ( n26 and not n27 );
end top_behav;
