--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Cookbook__gearbox_40_67__part2 is 
  Port (
    lo245,lo247,lo261,lo246,lo248,lo237,lo241,lo238,lo242,lo239,lo243,lo240,lo244,lo249,lo251,lo250,lo252: in std_logic;
    n1484,n1489_1,n1494_1,n1499,n1504_1,n1509_1,n1514,n1519_1: inout std_logic
  );
end Cookbook__gearbox_40_67__part2;

architecture Cookbook__gearbox_40_67__part2_behav of Cookbook__gearbox_40_67__part2 is
begin
    n1484 <= ( lo245 and not lo261 )
      or ( lo247 and lo261 );
    n1489_1 <= ( lo246 and not lo261 )
      or ( lo248 and lo261 );
    n1494_1 <= ( lo237 and not lo261 )
      or ( lo241 and lo261 );
    n1499 <= ( lo238 and not lo261 )
      or ( lo242 and lo261 );
    n1504_1 <= ( lo239 and not lo261 )
      or ( lo243 and lo261 );
    n1509_1 <= ( lo240 and not lo261 )
      or ( lo244 and lo261 );
    n1514 <= ( lo249 and not lo261 )
      or ( lo251 and lo261 );
    n1519_1 <= ( lo250 and not lo261 )
      or ( lo252 and lo261 );
end Cookbook__gearbox_40_67__part2_behav;
