--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2: in std_logic;
    po0,po1: inout std_logic
  );
end top;

architecture top_behav of top is
begin
    po1 <= ( not pi0 and not pi1 and pi2 )
      or ( not pi0 and pi1 and not pi2 )
      or ( pi0 and not pi1 and not pi2 )
      or ( pi0 and pi1 and pi2 );
    po0 <= ( pi0 and pi1 )
      or ( pi0 and pi2 )
      or ( pi1 and pi2 );
end top_behav;
