--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity Other__fp_operators__part25 is 
  Port (
    lo0116,lo0117,lo0115,lo0114,lo0118: in std_logic;
    po106,po108,po107: inout std_logic
  );
end Other__fp_operators__part25;

architecture Other__fp_operators__part25_behav of Other__fp_operators__part25 is
signal n6796,n6797,n6798,n6799,n6800,n6801,n6802,n6804,n6805,n29379,n29380: std_logic;
begin
    n6796 <= not (( not lo0116 and not lo0117 ));
    n6797 <= ( lo0115 and not n6796 );
    n6798 <= ( lo0114 and n6797 );
    n6799 <= not (( not lo0115 and not lo0116 ));
    n6800 <= ( lo0117 and n6799 );
    n6801 <= ( lo0115 and lo0116 );
    n6802 <= not (( not n6797 and not n6799 and not n6800 and not n6801 ));
    po106 <= not (( not n6798 and n6802 ));
    n6804 <= not (( not lo0116 and not lo0118 ));
    n6805 <= ( lo0115 and n6804 );
    po108 <= not (( lo0115 and not n6796 ));
    n29379 <= ( lo0117 and n6799 );
    n29380 <= ( not lo0117 and n6805 );
    po107 <= not (( not n29379 and not n29380 ));
end Other__fp_operators__part25_behav;
