--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity mux is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20: in std_logic;
    po0: inout std_logic
  );
end mux;

architecture mux_behav of mux is
signal n23,n24,n25,n26,n27: std_logic;
begin
    po0 <= ( pi20 and n27 );
    n23 <= ( not pi12 and not pi13 and pi18 )
      or ( not pi14 and not pi15 and not pi18 )
      or ( not pi12 and not pi14 and pi19 )
      or ( not pi12 and pi18 and pi19 )
      or ( not pi14 and not pi18 and pi19 )
      or ( not pi13 and not pi15 and not pi19 )
      or ( not pi13 and pi18 and not pi19 )
      or ( not pi15 and not pi18 and not pi19 )
      or ( not pi12 and not pi13 and not pi14 and not pi15 );
    n24 <= ( not pi08 and not pi09 and pi18 )
      or ( not pi10 and not pi11 and not pi18 )
      or ( not pi08 and not pi10 and pi19 )
      or ( not pi08 and pi18 and pi19 )
      or ( not pi10 and not pi18 and pi19 )
      or ( not pi09 and not pi11 and not pi19 )
      or ( not pi09 and pi18 and not pi19 )
      or ( not pi11 and not pi18 and not pi19 )
      or ( not pi08 and not pi09 and not pi10 and not pi11 );
    n25 <= ( not pi04 and not pi05 and pi18 )
      or ( not pi06 and not pi07 and not pi18 )
      or ( not pi04 and not pi06 and pi19 )
      or ( not pi04 and pi18 and pi19 )
      or ( not pi06 and not pi18 and pi19 )
      or ( not pi05 and not pi07 and not pi19 )
      or ( not pi05 and pi18 and not pi19 )
      or ( not pi07 and not pi18 and not pi19 )
      or ( not pi04 and not pi05 and not pi06 and not pi07 );
    n26 <= ( not pi00 and not pi01 and pi18 )
      or ( not pi02 and not pi03 and not pi18 )
      or ( not pi00 and not pi02 and pi19 )
      or ( not pi00 and pi18 and pi19 )
      or ( not pi02 and not pi18 and pi19 )
      or ( not pi01 and not pi03 and not pi19 )
      or ( not pi01 and pi18 and not pi19 )
      or ( not pi03 and not pi18 and not pi19 )
      or ( not pi00 and not pi01 and not pi02 and not pi03 );
    n27 <= ( not pi16 and not pi17 and not n23 )
      or ( not pi16 and pi17 and not n24 )
      or ( not pi16 and not n23 and not n24 )
      or ( pi16 and not pi17 and not n25 )
      or ( not pi17 and not n23 and not n25 )
      or ( pi16 and pi17 and not n26 )
      or ( pi17 and not n24 and not n26 )
      or ( pi16 and not n25 and not n26 )
      or ( not n23 and not n24 and not n25 and not n26 );
end mux_behav;
