--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity CM42 is 
  Port (
    pi0,pi1,pi2,pi3: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7,po8,po9: inout std_logic
  );
end CM42;

architecture CM42_behav of CM42 is
signal n24,n25,n26: std_logic;
begin
    po0 <= ( pi0 )
      or ( pi1 )
      or ( not n25 );
    po1 <= ( not pi0 )
      or ( pi1 )
      or ( not n25 );
    po2 <= ( pi0 )
      or ( not pi1 )
      or ( not n25 );
    po3 <= ( not pi0 )
      or ( not pi1 )
      or ( not n25 );
    po4 <= ( pi0 )
      or ( pi1 )
      or ( not n26 );
    po5 <= ( not pi0 )
      or ( pi1 )
      or ( not n26 );
    po6 <= ( pi0 )
      or ( not pi1 )
      or ( not n26 );
    po7 <= ( not pi0 )
      or ( not pi1 )
      or ( not n26 );
    po8 <= ( pi0 )
      or ( not n24 );
    po9 <= ( not pi0 )
      or ( not n24 );
    n24 <= ( not pi1 and not pi2 and pi3 );
    n25 <= ( not pi2 and not pi3 );
    n26 <= ( not n25 and not pi3 );
end CM42_behav;
