--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1, CLK: in std_logic;
    po0,po1: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,li2,n20,n21,li0,n23,li1,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,li3: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    po0 <= ( n20 );
    li2 <= ( pi0 );
    po1 <= ( lo1 );
    n20 <= ( n33 and n28 );
    n21 <= ( not lo0 );
    li0 <= ( n20 )
      or ( n23 );
    n23 <= ( not lo0 );
    li1 <= ( n26 )
      or ( n25 );
    n25 <= ( lo0 and lo1 );
    n26 <= ( n21 and n27 );
    n27 <= ( not n33 );
    n28 <= ( n32 )
      or ( n29 );
    n29 <= ( n31 and n30 );
    n30 <= ( not lo2 );
    n31 <= ( not li2 );
    n32 <= ( li2 and lo2 );
    n33 <= ( n37 )
      or ( n34 );
    n34 <= ( n36 and n35 );
    n35 <= ( not lo3 );
    n36 <= ( not lo2 );
    n37 <= ( lo2 and lo3 );
    li3 <= ( lo2 );
end top_behav;
