--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity b02 is 
  Port (
    pi0, CLK: in std_logic;
    po0: inout std_logic
  );
end b02;

architecture b02_behav of b02 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,li0,li3,li1,n17,n18,n19,n20,li2,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    li0 <= ( n18 and n20 and lo1 );
    li3 <= not (( n31 and n30 ));
    li1 <= not (( n25 and n24 ));
    n17 <= ( not lo1 );
    n18 <= ( not lo3 );
    n19 <= ( not pi0 );
    n20 <= ( not lo2 );
    li2 <= not (( n35 and n34 ));
    n22 <= not (( n33 and n32 and n18 ));
    n23 <= not (( not lo1 and not pi0 ));
    n24 <= not (( lo3 and n23 ));
    n25 <= not (( lo2 and n22 ));
    n26 <= not (( not pi0 and not lo2 ));
    n27 <= not (( n17 and n26 ));
    n28 <= not (( pi0 and n17 ));
    n29 <= not (( lo3 and n28 ));
    n30 <= not (( not pi0 and not lo3 and not lo1 ));
    n31 <= not (( n29 and n20 ));
    n32 <= not (( pi0 and n17 ));
    n33 <= not (( lo1 and n19 ));
    n34 <= not (( lo3 and n27 ));
    n35 <= not (( lo2 and n17 and n18 ));
    po0 <= ( lo0 );
end b02_behav;
