--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2,pi3, CLK: in std_logic;
    po0,po1,po2,po3: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,li0,li1,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    po0 <= ( not n33 );
    po1 <= ( not n34 );
    po2 <= ( not n35 );
    po3 <= ( not n36 );
    li0 <= ( not n31 );
    li1 <= ( not n32 );
    n20 <= ( not pi0 and pi1 and not pi2 and not pi3 );
    n21 <= ( not pi0 and not pi1 and pi2 and not pi3 );
    n22 <= ( pi0 and not pi1 and not pi2 and not pi3 );
    n23 <= ( not pi0 and not pi1 and not pi2 and pi3 );
    n24 <= ( pi1 and not pi2 and lo0 and lo1 );
    n25 <= ( not pi1 and pi2 and lo0 and lo1 );
    n26 <= ( pi0 and lo0 and lo1 );
    n27 <= ( pi3 and lo0 and lo1 );
    n28 <= ( not lo0 and not lo1 );
    n29 <= ( lo0 and lo1 );
    n30 <= ( not lo0 );
    n31 <= ( not n30 );
    n32 <= ( not n28 and not n29 );
    n33 <= ( not n22 and not n26 );
    n34 <= ( not n20 and not n24 );
    n35 <= ( not n21 and not n25 );
    n36 <= ( not n23 and not n27 );
end top_behav;
