--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity bitscan is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15: inout std_logic
  );
end bitscan;

architecture bitscan_behav of bitscan is
signal n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100,n101: std_logic;
begin
    n32 <= '0';
    n33 <= '1';
    n34 <= ( not n33 );
    n35 <= ( not n32 );
    n36 <= ( not n32 );
    n37 <= ( not n32 );
    n38 <= ( not n32 );
    n39 <= ( not n32 );
    n40 <= ( not n32 );
    n41 <= ( not n32 );
    n42 <= ( not n32 );
    n43 <= ( not n32 );
    n44 <= ( not n32 );
    n45 <= ( not n32 );
    n46 <= ( not n32 );
    n47 <= ( not n32 );
    n48 <= ( not n32 );
    n49 <= ( not n32 );
    n51 <= '1';
    n52 <= ( not n51 and not pi15 and n34 )
      or ( not n51 and pi15 and not n34 )
      or ( n51 and not pi15 and not n34 )
      or ( n51 and pi15 and n34 );
    n53 <= ( not n51 and pi15 and n34 )
      or ( n51 and not pi15 and n34 )
      or ( n51 and pi15 and not n34 )
      or ( n51 and pi15 and n34 );
    n54 <= ( not n53 and not pi14 and n35 )
      or ( not n53 and pi14 and not n35 )
      or ( n53 and not pi14 and not n35 )
      or ( n53 and pi14 and n35 );
    n55 <= ( not n53 and pi14 and n35 )
      or ( n53 and not pi14 and n35 )
      or ( n53 and pi14 and not n35 )
      or ( n53 and pi14 and n35 );
    n56 <= ( not n55 and not pi13 and n36 )
      or ( not n55 and pi13 and not n36 )
      or ( n55 and not pi13 and not n36 )
      or ( n55 and pi13 and n36 );
    n57 <= ( not n55 and pi13 and n36 )
      or ( n55 and not pi13 and n36 )
      or ( n55 and pi13 and not n36 )
      or ( n55 and pi13 and n36 );
    n58 <= ( not n57 and not pi12 and n37 )
      or ( not n57 and pi12 and not n37 )
      or ( n57 and not pi12 and not n37 )
      or ( n57 and pi12 and n37 );
    n59 <= ( not n57 and pi12 and n37 )
      or ( n57 and not pi12 and n37 )
      or ( n57 and pi12 and not n37 )
      or ( n57 and pi12 and n37 );
    n60 <= ( not n59 and not pi11 and n38 )
      or ( not n59 and pi11 and not n38 )
      or ( n59 and not pi11 and not n38 )
      or ( n59 and pi11 and n38 );
    n61 <= ( not n59 and pi11 and n38 )
      or ( n59 and not pi11 and n38 )
      or ( n59 and pi11 and not n38 )
      or ( n59 and pi11 and n38 );
    n62 <= ( not n61 and not pi10 and n39 )
      or ( not n61 and pi10 and not n39 )
      or ( n61 and not pi10 and not n39 )
      or ( n61 and pi10 and n39 );
    n63 <= ( not n61 and pi10 and n39 )
      or ( n61 and not pi10 and n39 )
      or ( n61 and pi10 and not n39 )
      or ( n61 and pi10 and n39 );
    n64 <= ( not n63 and not pi09 and n40 )
      or ( not n63 and pi09 and not n40 )
      or ( n63 and not pi09 and not n40 )
      or ( n63 and pi09 and n40 );
    n65 <= ( not n63 and pi09 and n40 )
      or ( n63 and not pi09 and n40 )
      or ( n63 and pi09 and not n40 )
      or ( n63 and pi09 and n40 );
    n66 <= ( not n65 and not pi08 and n41 )
      or ( not n65 and pi08 and not n41 )
      or ( n65 and not pi08 and not n41 )
      or ( n65 and pi08 and n41 );
    n67 <= ( not n65 and pi08 and n41 )
      or ( n65 and not pi08 and n41 )
      or ( n65 and pi08 and not n41 )
      or ( n65 and pi08 and n41 );
    n68 <= ( not n67 and not pi07 and n42 )
      or ( not n67 and pi07 and not n42 )
      or ( n67 and not pi07 and not n42 )
      or ( n67 and pi07 and n42 );
    n69 <= ( not n67 and pi07 and n42 )
      or ( n67 and not pi07 and n42 )
      or ( n67 and pi07 and not n42 )
      or ( n67 and pi07 and n42 );
    n70 <= ( not n69 and not pi06 and n43 )
      or ( not n69 and pi06 and not n43 )
      or ( n69 and not pi06 and not n43 )
      or ( n69 and pi06 and n43 );
    n71 <= ( not n69 and pi06 and n43 )
      or ( n69 and not pi06 and n43 )
      or ( n69 and pi06 and not n43 )
      or ( n69 and pi06 and n43 );
    n72 <= ( not n71 and not pi05 and n44 )
      or ( not n71 and pi05 and not n44 )
      or ( n71 and not pi05 and not n44 )
      or ( n71 and pi05 and n44 );
    n73 <= ( not n71 and pi05 and n44 )
      or ( n71 and not pi05 and n44 )
      or ( n71 and pi05 and not n44 )
      or ( n71 and pi05 and n44 );
    n74 <= ( not n73 and not pi04 and n45 )
      or ( not n73 and pi04 and not n45 )
      or ( n73 and not pi04 and not n45 )
      or ( n73 and pi04 and n45 );
    n75 <= ( not n73 and pi04 and n45 )
      or ( n73 and not pi04 and n45 )
      or ( n73 and pi04 and not n45 )
      or ( n73 and pi04 and n45 );
    n76 <= ( not n75 and not pi03 and n46 )
      or ( not n75 and pi03 and not n46 )
      or ( n75 and not pi03 and not n46 )
      or ( n75 and pi03 and n46 );
    n77 <= ( not n75 and pi03 and n46 )
      or ( n75 and not pi03 and n46 )
      or ( n75 and pi03 and not n46 )
      or ( n75 and pi03 and n46 );
    n78 <= ( not n77 and not pi02 and n47 )
      or ( not n77 and pi02 and not n47 )
      or ( n77 and not pi02 and not n47 )
      or ( n77 and pi02 and n47 );
    n79 <= ( not n77 and pi02 and n47 )
      or ( n77 and not pi02 and n47 )
      or ( n77 and pi02 and not n47 )
      or ( n77 and pi02 and n47 );
    n80 <= ( not n79 and not pi01 and n48 )
      or ( not n79 and pi01 and not n48 )
      or ( n79 and not pi01 and not n48 )
      or ( n79 and pi01 and n48 );
    n81 <= ( not n79 and pi01 and n48 )
      or ( n79 and not pi01 and n48 )
      or ( n79 and pi01 and not n48 )
      or ( n79 and pi01 and n48 );
    n82 <= ( not n81 and not pi00 and n49 )
      or ( not n81 and pi00 and not n49 )
      or ( n81 and not pi00 and not n49 )
      or ( n81 and pi00 and n49 );
    n86 <= ( not n52 );
    n87 <= ( not n54 );
    n88 <= ( not n56 );
    n89 <= ( not n58 );
    n90 <= ( not n60 );
    n91 <= ( not n62 );
    n92 <= ( not n64 );
    n93 <= ( not n66 );
    n94 <= ( not n68 );
    n95 <= ( not n70 );
    n96 <= ( not n72 );
    n97 <= ( not n74 );
    n98 <= ( not n76 );
    n99 <= ( not n78 );
    n100 <= ( not n80 );
    n101 <= ( not n82 );
    po15 <= ( pi15 and n86 );
    po14 <= ( pi14 and n87 );
    po13 <= ( pi13 and n88 );
    po12 <= ( pi12 and n89 );
    po11 <= ( pi11 and n90 );
    po10 <= ( pi10 and n91 );
    po09 <= ( pi09 and n92 );
    po08 <= ( pi08 and n93 );
    po07 <= ( pi07 and n94 );
    po06 <= ( pi06 and n95 );
    po05 <= ( pi05 and n96 );
    po04 <= ( pi04 and n97 );
    po03 <= ( pi03 and n98 );
    po02 <= ( pi02 and n99 );
    po01 <= ( pi01 and n100 );
    po00 <= ( pi00 and n101 );
end bitscan_behav;
