--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity traffic_cl is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po0: inout std_logic
  );
end traffic_cl;

architecture traffic_cl_behav of traffic_cl is
signal n7: std_logic;
begin
    po0 <= ( not n7 );
    n7 <= ( not pi3 and not pi0 and not pi1 )
      or ( not pi3 and not pi0 and not pi2 )
      or ( not pi3 and not pi1 and not pi2 )
      or ( not pi3 and not pi0 and not pi4 )
      or ( not pi3 and not pi1 and not pi4 )
      or ( not pi3 and not pi2 and not pi4 );
end traffic_cl_behav;
