--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity CM85 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10: in std_logic;
    po0,po1,po2: inout std_logic
  );
end CM85;

architecture CM85_behav of CM85 is
signal n17,n18,n19,n20,n21,n22,n23,n24,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37: std_logic;
begin
    po0 <= ( not n32 )
      or ( not n36 and not n34 );
    po1 <= ( not n36 and not n37 );
    po2 <= ( not n30 )
      or ( not n36 and not n35 );
    n17 <= ( not pi04 and pi03 );
    n18 <= ( not pi01 and not pi02 )
      or ( not n17 and not pi02 );
    n19 <= ( pi04 and not pi03 );
    n20 <= ( not pi01 and not pi00 )
      or ( not n19 and not pi00 );
    n21 <= ( pi03 and pi04 )
      or ( not pi03 and not pi04 );
    n22 <= ( not pi06 )
      or ( pi05 );
    n23 <= ( pi06 )
      or ( not pi05 );
    n24 <= ( not pi01 )
      or ( not n21 );
    n25 <= ( not pi05 and pi06 )
      or ( pi05 and not pi06 );
    n26 <= ( not n24 and not n25 );
    n27 <= ( not n18 )
      or ( not n23 and not n24 );
    n28 <= ( not n20 )
      or ( not n24 and not n22 );
    n29 <= ( not pi08 and pi07 );
    n30 <= ( not n26 and not n27 )
      or ( not n29 and not n27 );
    n31 <= ( pi08 and not pi07 );
    n32 <= ( not n26 and not n28 )
      or ( not n31 and not n28 );
    n33 <= ( pi07 and pi08 )
      or ( not pi07 and not pi08 );
    n34 <= ( not pi10 )
      or ( pi09 );
    n35 <= ( pi10 )
      or ( not pi09 );
    n36 <= ( not n26 )
      or ( not n33 );
    n37 <= ( not pi09 and pi10 )
      or ( pi09 and not pi10 );
end CM85_behav;
