--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity tcon is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15: inout std_logic
  );
end tcon;

architecture tcon_behav of tcon is
begin
    po08 <= ( not pi08 and pi09 )
      or ( pi08 and pi00 )
      or ( pi09 and pi00 );
    po09 <= ( not pi08 and pi10 )
      or ( pi08 and pi01 )
      or ( pi10 and pi01 );
    po10 <= ( not pi08 and pi11 )
      or ( pi08 and pi02 )
      or ( pi11 and pi02 );
    po11 <= ( not pi08 and pi12 )
      or ( pi08 and pi03 )
      or ( pi12 and pi03 );
    po12 <= ( not pi08 and pi13 )
      or ( pi08 and pi04 )
      or ( pi13 and pi04 );
    po13 <= ( not pi08 and pi14 )
      or ( pi08 and pi05 )
      or ( pi14 and pi05 );
    po14 <= ( not pi08 and pi15 )
      or ( pi08 and pi06 )
      or ( pi15 and pi06 );
    po15 <= ( not pi08 and pi16 )
      or ( pi08 and pi07 )
      or ( pi16 and pi07 );
    po00 <= ( pi09 );
    po01 <= ( pi10 );
    po02 <= ( pi11 );
    po03 <= ( pi12 );
    po04 <= ( pi13 );
    po05 <= ( pi14 );
    po06 <= ( pi15 );
    po07 <= ( pi16 );
end tcon_behav;
