--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity iter_addsub is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5, CLK: in std_logic;
    po0: inout std_logic
  );
end iter_addsub;

architecture iter_addsub_behav of iter_addsub is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,n10,n11,n12,n13,n15,n16,n17,n18,n19,li0: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    n10 <= '0';
    n11 <= ( pi3 and not pi5 )
      or ( not pi3 and pi5 );
    n12 <= ( pi4 and not n11 )
      or ( not pi4 and n11 );
    n13 <= ( lo0 and not pi2 )
      or ( pi3 and pi2 );
    po0 <= ( n12 and not n13 )
      or ( not n12 and n13 );
    n15 <= ( pi4 and n11 );
    n16 <= ( pi4 and n13 );
    n17 <= ( not n15 and n16 )
      or ( n15 and not n16 )
      or ( n15 and n16 );
    n18 <= ( n11 and n13 );
    n19 <= ( not n17 and n18 )
      or ( n17 and not n18 )
      or ( n17 and n18 );
    li0 <= ( n19 and not pi1 )
      or ( n10 and pi1 );
end iter_addsub_behav;
