--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity clock_mux is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7, CLK: in std_logic;
    po0: inout std_logic
  );
end clock_mux;

architecture clock_mux_behav of clock_mux is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo00,lo01,lo02,lo03,lo04,lo05,lo06,lo07,lo08,lo09,lo10,lo11,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n56,n57,n58,n59,n60,n61,n62,n63,n65,n66,n67,n68,n69,n70,n71,n72,n74,n75,n76,n77,n78,n79,n80,n81,li11,li02,li05,li08,n87,n88,n90,n91,n92,n93,li00,li01,li03,li04,li06,li07,li09,li10: std_logic;
begin
    DFF0: DFF port map (li00, CLK, lo00);
    DFF1: DFF port map (li01, CLK, lo01);
    DFF2: DFF port map (li02, CLK, lo02);
    DFF3: DFF port map (li03, CLK, lo03);
    DFF4: DFF port map (li04, CLK, lo04);
    DFF5: DFF port map (li05, CLK, lo05);
    DFF6: DFF port map (li06, CLK, lo06);
    DFF7: DFF port map (li07, CLK, lo07);
    DFF8: DFF port map (li08, CLK, lo08);
    DFF9: DFF port map (li09, CLK, lo09);
    DFF10: DFF port map (li10, CLK, lo10);
    DFF11: DFF port map (li11, CLK, lo11);
    n45 <= '0';
    n46 <= '1';
    n47 <= ( lo01 and n45 );
    n48 <= ( lo04 and n46 );
    n49 <= ( lo07 and n46 );
    n50 <= ( lo10 and n46 );
    n51 <= ( not n47 and n48 )
      or ( n47 and not n48 )
      or ( n47 and n48 );
    n52 <= ( not n49 and n50 )
      or ( n49 and not n50 )
      or ( n49 and n50 );
    n53 <= ( not n51 and n52 )
      or ( n51 and not n52 )
      or ( n51 and n52 );
    n54 <= ( not n53 );
    n56 <= ( lo01 and n46 );
    n57 <= ( lo04 and n45 );
    n58 <= ( lo07 and n46 );
    n59 <= ( lo10 and n46 );
    n60 <= ( not n56 and n57 )
      or ( n56 and not n57 )
      or ( n56 and n57 );
    n61 <= ( not n58 and n59 )
      or ( n58 and not n59 )
      or ( n58 and n59 );
    n62 <= ( not n60 and n61 )
      or ( n60 and not n61 )
      or ( n60 and n61 );
    n63 <= ( not n62 );
    n65 <= ( lo01 and n46 );
    n66 <= ( lo04 and n46 );
    n67 <= ( lo07 and n45 );
    n68 <= ( lo10 and n46 );
    n69 <= ( not n65 and n66 )
      or ( n65 and not n66 )
      or ( n65 and n66 );
    n70 <= ( not n67 and n68 )
      or ( n67 and not n68 )
      or ( n67 and n68 );
    n71 <= ( not n69 and n70 )
      or ( n69 and not n70 )
      or ( n69 and n70 );
    n72 <= ( not n71 );
    n74 <= ( lo01 and n46 );
    n75 <= ( lo04 and n46 );
    n76 <= ( lo07 and n46 );
    n77 <= ( lo10 and n45 );
    n78 <= ( not n74 and n75 )
      or ( n74 and not n75 )
      or ( n74 and n75 );
    n79 <= ( not n76 and n77 )
      or ( n76 and not n77 )
      or ( n76 and n77 );
    n80 <= ( not n78 and n79 )
      or ( n78 and not n79 )
      or ( n78 and n79 );
    n81 <= ( not n80 );
    li11 <= ( pi7 and n54 );
    li02 <= ( pi6 and n63 );
    li05 <= ( pi5 and n72 );
    li08 <= ( pi4 and n81 );
    n87 <= ( not n90 and n91 )
      or ( n90 and not n91 )
      or ( n90 and n91 );
    n88 <= ( not n92 and n93 )
      or ( n92 and not n93 )
      or ( n92 and n93 );
    po0 <= ( not n87 and n88 )
      or ( n87 and not n88 )
      or ( n87 and n88 );
    n90 <= ( pi3 and lo01 );
    n91 <= ( pi2 and lo04 );
    n92 <= ( pi1 and lo07 );
    n93 <= ( pi0 and lo10 );
    li00 <= ( lo11 );
    li01 <= ( lo00 );
    li03 <= ( lo02 );
    li04 <= ( lo03 );
    li06 <= ( lo05 );
    li07 <= ( lo06 );
    li09 <= ( lo08 );
    li10 <= ( lo09 );
end clock_mux_behav;
