--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity b01 is 
  Port (
    pi0,pi1, CLK: in std_logic;
    po0,po1: inout std_logic
  );
end b01;

architecture b01_behav of b01 is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,li0,li3,li2,n22,n23,n24,n25,n26,n27,n28,li4,li1,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    li0 <= ( lo2 and n23 and lo3 );
    li3 <= not (( n53 and n52 and n51 and n50 ));
    li2 <= not (( n42 and n40 and n41 ));
    n22 <= not (( not pi1 and not pi0 ));
    n23 <= ( not lo1 );
    n24 <= ( not lo2 );
    n25 <= ( not pi1 );
    n26 <= ( not pi0 );
    n27 <= ( not lo3 );
    n28 <= not (( lo2 and n27 ));
    li4 <= not (( n58 and n57 ));
    li1 <= not (( n45 and n44 ));
    n31 <= not (( n55 and n54 ));
    n32 <= not (( pi0 and pi1 ));
    n33 <= not (( lo1 and n28 ));
    n34 <= ( not n22 );
    n35 <= not (( n34 and n27 ));
    n36 <= ( not n32 );
    n37 <= ( not n28 );
    n38 <= not (( n32 and n28 ));
    n39 <= not (( lo1 and n32 ));
    n40 <= not (( lo3 and n24 and n32 ));
    n41 <= not (( n37 and n39 ));
    n42 <= not (( n47 and n46 and lo1 ));
    n43 <= ( not n33 );
    n44 <= not (( n38 and n23 ));
    n45 <= not (( n35 and n24 and lo1 ));
    n46 <= not (( lo2 and n34 ));
    n47 <= not (( n22 and n27 ));
    n48 <= not (( lo3 and n32 ));
    n49 <= not (( n36 and n27 ));
    n50 <= not (( n49 and n48 and n24 and n23 ));
    n51 <= not (( n28 and n22 and lo1 ));
    n52 <= not (( li0 and n32 ));
    n53 <= not (( n36 and n37 ));
    n54 <= not (( pi0 and n25 ));
    n55 <= not (( pi1 and n26 ));
    n56 <= ( not n31 );
    n57 <= not (( n43 and n56 ));
    n58 <= not (( n31 and n33 ));
    po0 <= ( lo4 );
    po1 <= ( lo0 );
end b01_behav;
