--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity i1 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15: inout std_logic
  );
end i1;

architecture i1_behav of i1 is
signal n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n64,n65: std_logic;
begin
    n41 <= ( not pi01 );
    n42 <= ( not pi02 );
    n43 <= ( not pi03 );
    n44 <= ( not pi04 );
    n45 <= ( not pi05 );
    n46 <= ( not pi06 );
    n47 <= ( not pi07 );
    n48 <= ( n47 and n45 and n43 and n41 and n42 and n44 and n46 );
    n49 <= ( not pi00 );
    n50 <= ( n49 and pi19 );
    n51 <= ( not pi08 );
    n52 <= ( n51 and pi19 and n48 );
    n53 <= ( not pi09 );
    n54 <= ( n53 and n52 );
    n55 <= ( pi09 and n48 and pi19 and pi08 );
    n56 <= ( not n48 );
    n57 <= ( n56 and pi19 and pi00 );
    n58 <= ( n53 and n48 and pi19 and pi08 );
    po01 <= not (( not n55 and not n50 and not n54 ));
    po02 <= not (( not n58 and not n57 ));
    po04 <= not (( not pi20 and not pi21 ));
    po05 <= not (( not n52 and not pi10 ));
    po07 <= ( pi24 and pi18 );
    n64 <= ( not pi24 );
    n65 <= ( n64 and pi11 );
    po09 <= ( pi24 and pi11 );
    po10 <= ( n64 and pi14 and pi22 );
    po11 <= ( n64 and pi17 and pi22 );
    po12 <= ( n64 and pi14 and pi23 );
    po13 <= ( n64 and pi17 and pi23 );
    po14 <= ( n64 and pi16 );
    po08 <= not (( not po09 and not n65 ));
    po15 <= not (( not pi15 and not pi13 and not pi12 and not pi14 ));
    po00 <= ( pi00 );
    po03 <= ( pi20 );
    po06 <= ( pi19 );
end i1_behav;
