--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity b06_opt is 
  Port (
    pi0,pi1, CLK: in std_logic;
    po0,po1,po2,po3,po4,po5: inout std_logic
  );
end b06_opt;

architecture b06_opt_behav of b06_opt is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,lo3,lo4,lo5,lo6,lo7,lo8,n35,n36,n37,li2,li1,li0,li4,li3,li6,li5,li7,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59,n60,n61,n62,n63,n64,n65,n66,n67,n68,n69,n70,n71,n72,li8: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    DFF3: DFF port map (li3, CLK, lo3);
    DFF4: DFF port map (li4, CLK, lo4);
    DFF5: DFF port map (li5, CLK, lo5);
    DFF6: DFF port map (li6, CLK, lo6);
    DFF7: DFF port map (li7, CLK, lo7);
    DFF8: DFF port map (li8, CLK, lo8);
    n35 <= not (( lo1 and n68 ));
    n36 <= not (( not n53 and not pi0 ));
    n37 <= ( n71 and n70 );
    li2 <= not (( n37 and n60 ));
    li1 <= not (( n63 and n62 and n49 and n54 ));
    li0 <= not (( n61 and n36 ));
    li4 <= not (( n69 and n52 and n35 and n72 ));
    li3 <= not (( n67 and n53 and n66 ));
    li6 <= not (( pi0 and n58 and n37 ));
    li5 <= not (( n54 and n57 ));
    li7 <= not (( n65 and n64 ));
    n46 <= ( lo0 and lo1 and lo2 );
    n47 <= ( not lo1 );
    n48 <= ( not pi0 );
    n49 <= not (( pi0 and lo1 ));
    n50 <= ( not lo0 );
    n51 <= ( not lo2 );
    n52 <= not (( not lo0 and not lo2 ));
    n53 <= not (( n47 and n50 and lo2 ));
    n54 <= not (( lo0 and n51 and n47 and n48 ));
    n55 <= ( not n52 );
    n56 <= ( not n49 );
    n57 <= not (( lo0 and n56 ));
    n58 <= not (( lo0 and lo1 ));
    n59 <= not (( not lo1 and not lo2 ));
    n60 <= not (( n48 and n59 ));
    n61 <= not (( lo0 and n60 ));
    n62 <= not (( pi0 and n50 and lo2 ));
    n63 <= not (( n55 and lo1 ));
    n64 <= not (( lo1 and n48 and n55 ));
    n65 <= not (( not pi1 and not n46 ));
    n66 <= not (( n56 and n51 ));
    n67 <= not (( lo0 and n60 ));
    n68 <= not (( pi0 and n51 ));
    n69 <= not (( lo2 and lo0 ));
    n70 <= not (( n55 and n47 ));
    n71 <= not (( lo2 and lo1 ));
    n72 <= not (( pi0 and n47 ));
    li8 <= ( li7 );
    po0 <= ( lo3 );
    po1 <= ( lo4 );
    po2 <= ( lo5 );
    po3 <= ( lo6 );
    po4 <= ( lo7 );
    po5 <= ( lo8 );
end b06_opt_behav;
