--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity fec_rot_17 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26,pi27,pi28,pi29,pi30,pi31: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17,po18,po19,po20,po21,po22,po23,po24,po25,po26,po27,po28,po29,po30,po31: inout std_logic
  );
end fec_rot_17;

architecture fec_rot_17_behav of fec_rot_17 is
signal n70,n71,n72,n73,n74,n75,n76,n77,n78,n79,n80,n81,n82,n83,n84,n85,n86,n87,n88,n89,n90,n91,n92,n93,n94,n95,n96,n97,n98,n99,n100,n101,n102,n103,n104,n105,n106,n107,n108,n109,n110,n111,n112,n113,n114,n115: std_logic;
begin
    po15 <= ( pi11 );
    po16 <= ( pi12 );
    po17 <= ( pi13 );
    po18 <= ( pi14 );
    po19 <= ( pi15 );
    po20 <= ( pi16 );
    n70 <= ( po20 and not pi07 )
      or ( not po20 and pi07 );
    n71 <= ( po19 and not pi06 )
      or ( not po19 and pi06 );
    n72 <= ( po20 and not po18 )
      or ( not po20 and po18 );
    n73 <= ( n72 and not pi07 )
      or ( not n72 and pi07 );
    n74 <= ( po19 and not po17 )
      or ( not po19 and po17 );
    n75 <= ( n74 and not pi06 )
      or ( not n74 and pi06 );
    n76 <= ( po18 and not po16 )
      or ( not po18 and po16 );
    n77 <= ( n76 and not pi05 )
      or ( not n76 and pi05 );
    n78 <= ( po17 and not po15 )
      or ( not po17 and po15 );
    n79 <= ( n78 and not pi04 )
      or ( not n78 and pi04 );
    n80 <= ( po16 and not pi10 )
      or ( not po16 and pi10 );
    n81 <= ( po15 and not pi09 )
      or ( not po15 and pi09 );
    n82 <= ( pi10 and not pi08 )
      or ( not pi10 and pi08 );
    n83 <= ( pi09 and not pi07 )
      or ( not pi09 and pi07 );
    n84 <= ( pi27 and not po20 )
      or ( not pi27 and po20 );
    n85 <= ( n84 and not pi07 )
      or ( not n84 and pi07 );
    n86 <= ( n85 and not pi06 )
      or ( not n85 and pi06 );
    n87 <= ( pi26 and not po19 )
      or ( not pi26 and po19 );
    n88 <= ( n87 and not pi06 )
      or ( not n87 and pi06 );
    n89 <= ( n88 and not pi05 )
      or ( not n88 and pi05 );
    n90 <= ( pi25 and not po20 )
      or ( not pi25 and po20 );
    n91 <= ( n90 and not po18 )
      or ( not n90 and po18 );
    n92 <= ( n91 and not pi07 )
      or ( not n91 and pi07 );
    n93 <= ( n92 and not pi04 )
      or ( not n92 and pi04 );
    n94 <= ( pi24 and not po19 )
      or ( not pi24 and po19 );
    n95 <= ( n94 and not po17 )
      or ( not n94 and po17 );
    n96 <= ( n95 and not pi06 )
      or ( not n95 and pi06 );
    n97 <= ( n96 and not pi03 )
      or ( not n96 and pi03 );
    n98 <= ( pi23 and not po18 )
      or ( not pi23 and po18 );
    n99 <= ( n98 and not po16 )
      or ( not n98 and po16 );
    n100 <= ( n99 and not pi05 )
      or ( not n99 and pi05 );
    n101 <= ( n100 and not pi02 )
      or ( not n100 and pi02 );
    n102 <= ( pi22 and not po17 )
      or ( not pi22 and po17 );
    n103 <= ( n102 and not po15 )
      or ( not n102 and po15 );
    n104 <= ( n103 and not pi04 )
      or ( not n103 and pi04 );
    n105 <= ( n104 and not pi01 )
      or ( not n104 and pi01 );
    n106 <= ( pi21 and not po16 )
      or ( not pi21 and po16 );
    n107 <= ( n106 and not pi10 )
      or ( not n106 and pi10 );
    n108 <= ( n107 and not pi03 )
      or ( not n107 and pi03 );
    n109 <= ( pi20 and not po15 )
      or ( not pi20 and po15 );
    n110 <= ( n109 and not pi09 )
      or ( not n109 and pi09 );
    n111 <= ( pi19 and not pi10 )
      or ( not pi19 and pi10 );
    n112 <= ( n111 and not pi08 )
      or ( not n111 and pi08 );
    n113 <= ( pi18 and not pi09 )
      or ( not pi18 and pi09 );
    n114 <= ( n113 and not pi07 )
      or ( not n113 and pi07 );
    n115 <= ( pi17 and not pi08 )
      or ( not pi17 and pi08 );
    po31 <= ( n70 and not pi05 )
      or ( not n70 and pi05 );
    po30 <= ( n71 and not pi04 )
      or ( not n71 and pi04 );
    po29 <= ( n73 and not pi03 )
      or ( not n73 and pi03 );
    po28 <= ( n75 and not pi02 )
      or ( not n75 and pi02 );
    po27 <= ( n77 and not pi01 )
      or ( not n77 and pi01 );
    po26 <= ( n79 and not pi00 )
      or ( not n79 and pi00 );
    po25 <= ( n80 and not pi03 )
      or ( not n80 and pi03 );
    po24 <= ( n81 and not pi02 )
      or ( not n81 and pi02 );
    po23 <= ( n82 and not pi01 )
      or ( not n82 and pi01 );
    po22 <= ( n83 and not pi00 )
      or ( not n83 and pi00 );
    po21 <= ( pi08 and not pi06 )
      or ( not pi08 and pi06 );
    po14 <= ( pi31 and not pi10 )
      or ( not pi31 and pi10 );
    po13 <= ( pi30 and not pi09 )
      or ( not pi30 and pi09 );
    po12 <= ( pi29 and not pi08 )
      or ( not pi29 and pi08 );
    po11 <= ( pi28 and not pi07 )
      or ( not pi28 and pi07 );
    po10 <= ( n86 and not pi05 )
      or ( not n86 and pi05 );
    po09 <= ( n89 and not pi04 )
      or ( not n89 and pi04 );
    po08 <= ( n93 and not pi03 )
      or ( not n93 and pi03 );
    po07 <= ( n97 and not pi02 )
      or ( not n97 and pi02 );
    po06 <= ( n101 and not pi01 )
      or ( not n101 and pi01 );
    po05 <= ( n105 and not pi00 )
      or ( not n105 and pi00 );
    po04 <= ( n108 and not pi00 )
      or ( not n108 and pi00 );
    po03 <= ( n110 and not pi02 )
      or ( not n110 and pi02 );
    po02 <= ( n112 and not pi01 )
      or ( not n112 and pi01 );
    po01 <= ( n114 and not pi00 )
      or ( not n114 and pi00 );
    po00 <= ( n115 and not pi06 )
      or ( not n115 and pi06 );
end fec_rot_17_behav;
