--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity clock_crossing_fifo is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19, CLK: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17: inout std_logic
  );
end clock_crossing_fifo;

architecture clock_crossing_fifo_behav of clock_crossing_fifo is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,n57,n58,n59,n62,n63,n64,n65,n66,li0,n68: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    po01 <= '0';
    po02 <= '0';
    po03 <= '0';
    po04 <= '0';
    po05 <= '0';
    po06 <= '0';
    po07 <= '0';
    po08 <= '0';
    po09 <= '0';
    po10 <= '0';
    po11 <= '0';
    po12 <= '0';
    po13 <= '0';
    po14 <= '0';
    po15 <= '0';
    po16 <= '0';
    n57 <= '0';
    n58 <= '0';
    n59 <= '1';
    po00 <= ( not n57 );
    n62 <= ( not n58 );
    n63 <= ( not lo0 );
    n64 <= ( not n63 and pi19 )
      or ( n63 and not pi19 )
      or ( n63 and pi19 );
    n65 <= ( n62 and n64 );
    n66 <= ( lo0 and not pi19 )
      or ( n68 and pi19 );
    li0 <= ( n66 and not n65 )
      or ( n59 and n65 );
    n68 <= '0';
    po17 <= ( lo0 );
end clock_crossing_fifo_behav;
