--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity three_two_comp is 
  Port (
    pi0,pi1,pi2: in std_logic;
    po0,po1: inout std_logic
  );
end three_two_comp;

architecture three_two_comp_behav of three_two_comp is
signal n5,n6,n7,n8,n9,n10,n11,n12,n14,n15,n16,n17,n18,n19: std_logic;
begin
    n5 <= '0';
    n6 <= '1';
    n7 <= ( n5 and not pi2 )
      or ( n6 and pi2 );
    n8 <= ( n6 and not pi2 )
      or ( n5 and pi2 );
    n9 <= ( n7 and not pi1 )
      or ( n8 and pi1 );
    n10 <= ( n6 and not pi2 )
      or ( n5 and pi2 );
    n11 <= ( n5 and not pi2 )
      or ( n6 and pi2 );
    n12 <= ( n10 and not pi1 )
      or ( n11 and pi1 );
    po1 <= ( n9 and not pi0 )
      or ( n12 and pi0 );
    n14 <= ( n5 and not pi2 )
      or ( n5 and pi2 );
    n15 <= ( n5 and not pi2 )
      or ( n6 and pi2 );
    n16 <= ( n14 and not pi1 )
      or ( n15 and pi1 );
    n17 <= ( n5 and not pi2 )
      or ( n6 and pi2 );
    n18 <= ( n6 and not pi2 )
      or ( n6 and pi2 );
    n19 <= ( n17 and not pi1 )
      or ( n18 and pi1 );
    po0 <= ( n16 and not pi0 )
      or ( n19 and pi0 );
end three_two_comp_behav;
