--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1, CLK: in std_logic;
    po0: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,li0,li1,n12,n13,n14,n15,n16,n17,n18,n19,n20: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    po0 <= ( not n20 );
    li0 <= ( not n18 );
    li1 <= ( not n19 );
    n12 <= ( not pi0 and not pi1 and lo0 );
    n13 <= ( pi0 and pi1 );
    n14 <= ( pi1 and not lo1 );
    n15 <= ( pi0 and not lo1 );
    n16 <= ( pi1 and lo1 );
    n17 <= ( pi0 and lo1 );
    n18 <= ( not n12 and not n13 and not n14 and not n15 );
    n19 <= ( not n12 and not n13 and not n16 and not n17 );
    n20 <= ( not n12 and not n14 and not n15 and not n16 and not n17 );
end top_behav;
