--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity ldd is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5,pi6,pi7,pi8: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17,po18: inout std_logic
  );
end ldd;

architecture ldd_behav of ldd is
signal n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58: std_logic;
begin
    po00 <= ( n48 )
      or ( n49 )
      or ( n53 )
      or ( po08 )
      or ( po09 )
      or ( n47 )
      or ( po10 )
      or ( n58 )
      or ( po11 )
      or ( n54 )
      or ( n55 );
    po01 <= ( n50 )
      or ( n51 )
      or ( n53 )
      or ( n56 )
      or ( po08 )
      or ( n57 )
      or ( po09 )
      or ( po10 )
      or ( po11 )
      or ( n54 )
      or ( n55 );
    po02 <= ( n48 )
      or ( n50 )
      or ( po18 )
      or ( n52 )
      or ( n53 )
      or ( po08 )
      or ( n57 )
      or ( po09 )
      or ( po10 )
      or ( n58 )
      or ( n55 );
    po03 <= ( n56 )
      or ( po08 )
      or ( n57 )
      or ( po09 )
      or ( n58 )
      or ( po11 );
    po04 <= ( n47 )
      or ( po10 );
    po05 <= ( n54 )
      or ( n55 );
    po06 <= ( n52 )
      or ( n53 );
    po07 <= ( n48 )
      or ( n49 )
      or ( n50 )
      or ( n51 )
      or ( po18 )
      or ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and not pi7 );
    po08 <= ( not pi0 and pi1 and not pi2 and pi8 );
    po09 <= ( not pi0 and pi1 and pi2 and pi8 );
    po10 <= ( pi0 and not pi1 and not pi2 and pi8 );
    po11 <= ( pi0 and not pi1 and pi2 and pi8 );
    po12 <= ( n48 )
      or ( n49 )
      or ( n50 )
      or ( n51 )
      or ( po08 )
      or ( po09 )
      or ( po10 )
      or ( n58 )
      or ( po11 );
    po13 <= ( n48 )
      or ( n49 )
      or ( n50 )
      or ( n51 )
      or ( po08 )
      or ( po09 )
      or ( po10 )
      or ( po11 );
    po14 <= ( n48 )
      or ( n49 )
      or ( n50 )
      or ( n51 )
      or ( po08 )
      or ( po09 )
      or ( po10 )
      or ( po11 );
    po15 <= ( n49 )
      or ( n51 )
      or ( po08 )
      or ( po10 );
    po16 <= ( n48 )
      or ( n51 )
      or ( po08 )
      or ( po11 );
    po17 <= ( n49 )
      or ( n50 )
      or ( n51 )
      or ( po11 );
    po18 <= ( not pi0 and not pi1 and not pi2 and pi3 );
    n47 <= ( pi0 and not pi1 and not pi2 and not pi8 );
    n48 <= ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and not pi6 and pi7 );
    n49 <= ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and not pi5 and pi6 );
    n50 <= ( not pi0 and not pi1 and not pi2 and not pi3 and not pi4 and pi5 );
    n51 <= ( not pi0 and not pi1 and not pi2 and not pi3 and pi4 );
    n52 <= ( not pi0 and not pi1 and pi2 and not pi8 );
    n53 <= ( not pi0 and not pi1 and pi2 and pi8 );
    n54 <= ( pi0 and pi1 and not pi2 and not pi8 );
    n55 <= ( pi0 and pi1 and not pi2 and pi8 );
    n56 <= ( not pi0 and pi1 and not pi2 and not pi8 );
    n57 <= ( not pi0 and pi1 and pi2 and not pi8 );
    n58 <= ( pi0 and not pi1 and pi2 and not pi8 );
end ldd_behav;
