--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity fec_rot_7 is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18,pi19,pi20,pi21,pi22,pi23,pi24,pi25,pi26,pi27,pi28,pi29,pi30,pi31: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15,po16,po17,po18,po19,po20,po21,po22,po23,po24,po25,po26,po27,po28,po29,po30,po31: inout std_logic
  );
end fec_rot_7;

architecture fec_rot_7_behav of fec_rot_7 is
signal n73,n74,n75,n76,n77: std_logic;
begin
    po30 <= ( pi05 );
    po31 <= ( pi06 );
    po00 <= ( pi07 );
    po01 <= ( pi08 );
    po11 <= ( pi18 );
    po12 <= ( pi19 );
    po13 <= ( pi20 );
    po21 <= ( pi28 );
    po22 <= ( pi29 );
    n73 <= ( pi15 and not po31 )
      or ( not pi15 and po31 );
    n74 <= ( pi14 and not po30 )
      or ( not pi14 and po30 );
    n75 <= ( pi13 and not pi04 )
      or ( not pi13 and pi04 );
    n76 <= ( pi12 and not pi03 )
      or ( not pi12 and pi03 );
    n77 <= ( pi11 and not pi02 )
      or ( not pi11 and pi02 );
    po29 <= ( po31 and not pi04 )
      or ( not po31 and pi04 );
    po28 <= ( po30 and not pi03 )
      or ( not po30 and pi03 );
    po27 <= ( pi04 and not pi02 )
      or ( not pi04 and pi02 );
    po26 <= ( pi03 and not pi01 )
      or ( not pi03 and pi01 );
    po25 <= ( pi02 and not pi00 )
      or ( not pi02 and pi00 );
    po24 <= ( pi31 and not pi01 )
      or ( not pi31 and pi01 );
    po23 <= ( pi30 and not pi00 )
      or ( not pi30 and pi00 );
    po20 <= ( pi27 and not po31 )
      or ( not pi27 and po31 );
    po19 <= ( pi26 and not po30 )
      or ( not pi26 and po30 );
    po18 <= ( pi25 and not pi04 )
      or ( not pi25 and pi04 );
    po17 <= ( pi24 and not pi03 )
      or ( not pi24 and pi03 );
    po16 <= ( pi23 and not pi02 )
      or ( not pi23 and pi02 );
    po15 <= ( pi22 and not pi01 )
      or ( not pi22 and pi01 );
    po14 <= ( pi21 and not pi00 )
      or ( not pi21 and pi00 );
    po10 <= ( pi17 and not po31 )
      or ( not pi17 and po31 );
    po09 <= ( pi16 and not po30 )
      or ( not pi16 and po30 );
    po08 <= ( n73 and not pi04 )
      or ( not n73 and pi04 );
    po07 <= ( n74 and not pi03 )
      or ( not n74 and pi03 );
    po06 <= ( n75 and not pi02 )
      or ( not n75 and pi02 );
    po05 <= ( n76 and not pi01 )
      or ( not n76 and pi01 );
    po04 <= ( n77 and not pi00 )
      or ( not n77 and pi00 );
    po03 <= ( pi10 and not pi01 )
      or ( not pi10 and pi01 );
    po02 <= ( pi09 and not pi00 )
      or ( not pi09 and pi00 );
end fec_rot_7_behav;
