--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity CM138 is 
  Port (
    pi0,pi1,pi2,pi3,pi4,pi5: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7: inout std_logic
  );
end CM138;

architecture CM138_behav of CM138 is
signal n22: std_logic;
begin
    po0 <= ( pi0 )
      or ( pi1 )
      or ( pi2 )
      or ( n22 );
    po1 <= ( not pi0 )
      or ( pi1 )
      or ( pi2 )
      or ( n22 );
    po2 <= ( pi0 )
      or ( not pi1 )
      or ( pi2 )
      or ( n22 );
    po3 <= ( not pi0 )
      or ( not pi1 )
      or ( pi2 )
      or ( n22 );
    po4 <= ( pi0 )
      or ( pi1 )
      or ( not pi2 )
      or ( n22 );
    po5 <= ( not pi0 )
      or ( pi1 )
      or ( not pi2 )
      or ( n22 );
    po6 <= ( pi0 )
      or ( not pi1 )
      or ( not pi2 )
      or ( n22 );
    po7 <= ( not pi0 )
      or ( not pi1 )
      or ( not pi2 )
      or ( n22 );
    n22 <= ( pi5 )
      or ( pi4 )
      or ( not pi3 );
end CM138_behav;
