--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity pcle_cl is 
  Port (
    pi00,pi01,pi02,pi03,pi04,pi05,pi06,pi07,pi08,pi09,pi10,pi11,pi12,pi13,pi14,pi15,pi16,pi17,pi18: in std_logic;
    po0,po1,po2,po3,po4,po5,po6,po7,po8: inout std_logic
  );
end pcle_cl;

architecture pcle_cl_behav of pcle_cl is
signal n37,n38,n39,n40,n41,n42,n43: std_logic;
begin
    po0 <= ( pi18 and n38 and n37 );
    po1 <= ( pi00 and pi08 )
      or ( not pi11 and n37 );
    po2 <= ( pi01 and pi08 )
      or ( n37 and not pi11 and pi12 )
      or ( n37 and pi11 and not pi12 );
    po3 <= ( pi02 and pi08 )
      or ( n37 and not pi13 and n43 )
      or ( n37 and pi13 and not n43 );
    po4 <= ( pi03 and pi08 )
      or ( n37 and not pi14 and n42 )
      or ( n37 and pi14 and not n42 );
    po5 <= ( pi04 and pi08 )
      or ( n37 and not pi15 and n41 )
      or ( n37 and pi15 and not n41 );
    po6 <= ( pi05 and pi08 )
      or ( n37 and not pi16 and n40 )
      or ( n37 and pi16 and not n40 );
    po7 <= ( pi06 and pi08 )
      or ( n37 and not pi17 and n39 )
      or ( n37 and pi17 and not n39 );
    po8 <= ( pi07 and pi08 )
      or ( n37 and not pi18 and n38 )
      or ( n37 and pi18 and not n38 );
    n37 <= ( not pi08 and pi09 and not pi10 );
    n38 <= ( pi17 and n39 );
    n39 <= ( pi16 and n40 );
    n40 <= ( pi15 and n41 );
    n41 <= ( pi14 and n42 );
    n42 <= ( pi13 and n43 );
    n43 <= ( pi11 and pi12 );
end pcle_cl_behav;
