--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity DFF is
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end DFF;

architecture Behavior of DFF is
begin
  process(CLK)
  begin
    if CLK'event and CLK = '1' then
      Q <= D;
    end if;
  end process;
end Behavior;

Library IEEE;
use IEEE.std_logic_1164.all;

entity top is 
  Port (
    pi0,pi1,pi2, CLK: in std_logic;
    po0,po1,po2,po3,po4: inout std_logic
  );
end top;

architecture top_behav of top is
component DFF
  Port ( D, CLK: in std_logic;
     Q: out std_logic);
end component;

signal lo0,lo1,lo2,li0,li1,li2,n25,n26,n27,n28,n29,n30,n31,n32,n33,n34,n35,n36,n37,n38,n39,n40,n41,n42,n43,n44,n45,n46,n47,n48,n49,n50,n51,n52,n53,n54,n55,n56,n57,n58,n59: std_logic;
begin
    DFF0: DFF port map (li0, CLK, lo0);
    DFF1: DFF port map (li1, CLK, lo1);
    DFF2: DFF port map (li2, CLK, lo2);
    po0 <= ( not n55 );
    po1 <= ( not n56 );
    po2 <= ( not n57 );
    po3 <= ( not n58 );
    po4 <= ( not n59 );
    li0 <= ( not n52 );
    li1 <= ( not n53 );
    li2 <= ( not n54 );
    n25 <= ( not pi0 and pi1 and not pi2 and not lo1 and lo2 );
    n26 <= ( pi0 and pi1 and not pi2 and not lo1 and lo2 );
    n27 <= ( pi0 and not pi2 and lo0 and lo1 );
    n28 <= ( not pi0 and not pi1 and not lo0 and not lo1 );
    n29 <= ( not pi0 and pi1 and not pi2 and not lo0 );
    n30 <= ( not pi1 and not pi2 and not lo0 and not lo1 );
    n31 <= ( pi0 and not pi1 and not lo0 and lo1 );
    n32 <= ( pi0 and pi1 and not pi2 and lo0 and not lo2 );
    n33 <= ( pi0 and not pi1 and pi2 and not lo2 );
    n34 <= ( not pi1 and pi2 and lo1 and not lo2 );
    n35 <= ( pi0 and not pi1 and not pi2 and not lo1 );
    n36 <= ( pi0 and pi2 and lo0 and not lo2 );
    n37 <= ( pi1 and pi2 and not lo1 and lo2 );
    n38 <= ( pi0 and pi1 and lo0 and lo1 );
    n39 <= ( not pi0 and pi1 and pi2 and not lo2 );
    n40 <= ( pi0 and pi2 and not lo1 and lo2 );
    n41 <= ( not pi0 and pi2 and lo1 );
    n42 <= ( not pi1 and pi2 and not lo1 );
    n43 <= ( not pi0 and pi1 and not lo2 );
    n44 <= ( not pi0 and not pi1 and not lo1 );
    n45 <= ( not pi0 and pi1 and lo1 and lo2 );
    n46 <= ( pi0 and pi2 and not lo0 and not lo2 );
    n47 <= ( pi0 and pi2 and not lo0 and lo1 );
    n48 <= ( not pi1 and lo1 and lo2 );
    n49 <= ( pi1 and not pi2 and not lo0 and not lo2 );
    n50 <= ( pi1 and not pi2 and not lo0 and lo1 );
    n51 <= ( not pi1 and not pi2 and lo1 );
    n52 <= ( not n26 and not n35 and not n45 and not n46 and not n47 and not n48 and not n49 and not n50 and not n51 );
    n53 <= ( not n25 and not n27 and not n29 and not n31 and not n32 and not n34 and not n42 and not n45 );
    n54 <= ( not n32 and not n34 and not n36 and not n37 and not n38 and not n39 and not n40 and not n44 and not n45 and not n46 and not n47 and not n48 and not n49 and not n50 and not n51 );
    n55 <= ( not n28 and not n30 and not n33 and not n34 and not n43 and not n46 and not n47 and not n49 and not n50 );
    n56 <= ( not n25 and not n26 and not n37 and not n40 and not n51 );
    n57 <= ( not n32 and not n36 and not n38 and not n39 and not n41 and not n49 and not n50 );
    n58 <= ( not n26 and not n35 and not n40 and not n44 );
    n59 <= ( not n45 and not n46 and not n47 and not n48 and not n49 and not n50 and not n51 );
end top_behav;
