--- VHDL generated by LogSynth framework (c) Petr Fiser
Library IEEE;
use IEEE.std_logic_1164.all;

entity decod is 
  Port (
    pi0,pi1,pi2,pi3,pi4: in std_logic;
    po00,po01,po02,po03,po04,po05,po06,po07,po08,po09,po10,po11,po12,po13,po14,po15: inout std_logic
  );
end decod;

architecture decod_behav of decod is
signal n37,n38: std_logic;
begin
    po00 <= ( pi3 and pi2 and pi1 and n38 );
    po01 <= ( not pi3 and pi2 and pi1 and n38 );
    po02 <= ( pi3 and not pi2 and pi1 and n38 );
    po03 <= ( not pi3 and not pi2 and pi1 and n38 );
    po04 <= ( pi3 and pi2 and not pi1 and n38 );
    po05 <= ( not pi3 and pi2 and not pi1 and n38 );
    po06 <= ( pi3 and not pi2 and not pi1 and n38 );
    po07 <= ( not pi3 and not pi2 and not pi1 and n38 );
    po08 <= ( pi3 and pi2 and pi1 and n37 );
    po09 <= ( not pi3 and pi2 and pi1 and n37 );
    po10 <= ( pi3 and not pi2 and pi1 and n37 );
    po11 <= ( not pi3 and not pi2 and pi1 and n37 );
    po12 <= ( pi3 and pi2 and not pi1 and n37 );
    po13 <= ( not pi3 and pi2 and not pi1 and n37 );
    po14 <= ( pi3 and not pi2 and not pi1 and n37 );
    po15 <= ( not pi3 and not pi2 and not pi1 and n37 );
    n37 <= ( not pi0 and pi4 );
    n38 <= ( pi0 and pi4 );
end decod_behav;
