Digital Design & Dependability Research Group


People

Head

Members

Name & webpge Research areas E-mail
Ing. Miloš Bečvář CPU architecture, digital design milos.becvar@centrum.cz
Ing. Jaroslav Borecký, Ph.D. Self testing circuits based on FPGA borecjar@fit.cvut.cz
Ing. Martin Daňhel Prediction and analysis of mission critical systems dependability danhema1@fit.cvut.cz
Ing. Radek Dobiáš, Ph.D. Fault-tolerant design in FPGA
Railway sefety devices with programable HW
dobiasr@fit.cvut.cz
doc. Ing. Jiří Douša, CSc. Logic design, simulation dousa@fit.cvut.cz
doc. Ing. Petr Fišer, Ph.D. Synchronous & asynchronous logic design
Two-level minimization, multi-level logic synthesis
Diagnostics, BIST, on-line testing
Logic synthesis benchmarks
fiserp@fit.cvut.cz
doc. Ing. Kateřina Hyniová, CSc. Control systems Katerina.Hyniova@fit.cvut.cz
Ing. Pavel Kubalík, Ph.D. Self testing circuits based on FPGA
High-speed wireless networks
xkubalik@fit.cvut.cz
Ing. Martin Kohlík, Ph.D. Formal dependability models kohlimar@fit.cvut.cz
doc. Ing. Hana Kubátová, CSc. Formal methods (Petri nets) in modelling, simulation and hardware design
Automata theory
Digital systems design
Dependable design
kubatova@fit.cvut.cz
Dr.-Ing. Martin Novotný Digital design
Arithmetics
Cryptography
Embedded systems
novotnym@fit.cvut.cz
doc. Ing. Alois Pluháček, CSc. Arithmetics, coding pluhacek@fit.cvut.cz
doc. Dipl.-Ing. Dr. techn. Stefan Ratschan Formal verification
Hybrid (continuous/discrete) systems
stefan.ratschan@cs.cas.cz
doc. Ing. Jan Schmidt, Ph.D. Implicit methods, test generation
Logic synthesis
Finite-field arithmetics
EDA systems
schmidt@fit.cvut.cz
Ing. Miroslav Skrbek, Ph.D. Control systems, robotics skrbek@fit.cvut.cz
Dr. Ing. Sven Ubik Hardware acceleration of video transmissions ubik@cesnet.cz

Ph.D. Students

Name & webpge Research areas E-mail Supervisor
Ing. Tomáš Apeltauer Automated Testing of Models of Cyber-Physical Systems apelttom@fit.cvut.cz doc. Dipl.-Ing. Dr. techn. Stefan Ratschan
Ing. Matěj Bartík ASIC and FPGA architectures bartimat@fit.cvut.cz Dr. Ing. Sven Ubik
Ing. Jan Bělohoubek Asynchronous circuits belohja4@fit.cvut.cz doc. Ing. Petr Fišer, Ph.D.
doc. Ing. Jan Schmidt, Ph.D.
Ing. Tomáš Čejka Computer networks: traffic monitoring, security, anomalies detection
Network configuration (using NETCONF protocol)
cejkato2@fit.cvut.cz doc. Ing. Hana Kubátová, CSc.
Mgr. Rudolf Blažek, Ph.D.
Ing. Marek Danel Robot behavior modeling danelmar@fit.cvut.cz Ing. Miroslav Skrbek, Ph.D.
Ing. Martin Daňhel Prediction and analysis of mission critical systems dependability danhema1@fit.cvut.cz doc. Ing. Hana Kubátová, CSc.
Ing. Ivo Háleček Logic synthesis, XOR-based synthesis halecivo@fit.cvut.cz doc. Ing. Petr Fišer, Ph.D.
doc. Ing. Jan Schmidt, Ph.D.
Ing. Robert Hülle BIST design, output response compaction hullerob@fit.cvut.cz doc. Ing. Petr Fišer, Ph.D.
Ing. Stanislav Jeřábek FT & AR design in FPGA jerabst1@fit.cvut.cz doc. Ing. Jan Schmidt, Ph.D.
Dr.-Ing. Martin Novotný
Ing. Vojtěch Miškovský Attack-resistant and fault-tolerant architectures miskovoj@fit.cvut.cz doc. Ing. Hana Kubátová, CSc.
Ing. Jan Pospíšil Modeling of FPGA architectures
FPGAs depenadability models
pospij17@fit.cvut.cz doc. Ing. Jan Schmidt, Ph.D.
Ing. Ladislava Smítková Janků Ad-hoc networks jankul@fit.cvut.cz doc. Ing. Kateřina Hyniová, CSc.
Ing. Tomáš Vaňát Practical experiments with fault injection into programable HW
Decomposition of dependable systems
vanattom@fit.cvut.cz doc. Ing. Hana Kubátová, CSc.
Ing. Pavel Vít Design of fault-tolerant circuits with user defined level of dependability vitpave1@fit.cvut.cz doc. Ing. Hana Kubátová, CSc.

Defended Ph.D. Students

Name Supervisor Thesis Year of defence
Pavel Benáček doc. Ing. Hana Kubátová, CSc.
Ing. Viktor Puš, Ph.D.
Generation of High-Speed Network Device from High-Level Description 2017
Jiří Balcárek doc. Ing. Jan Schmidt, Ph.D.
doc. Ing. Petr Fišer, Ph.D.
Implicit Representations in the Testing and Dependability of Digital Circuits 2017
Martin Chloupek prof. Ing. Ondřej Novák, CSc. Digital Circuits Testing Based on Pattern Ovelapping and Broadcasting 2017
Jaroslav Borecký doc. Ing. Hana Kubátová, CSc. Dependable Systems Design Methods for FPGAs 2015
Martin Kohlík doc. Ing. Hana Kubátová, CSc. Hierarchical Dependability Models Based on Markov Chains 2015
Jaroslav Sýkora Ing. Martin Daněk, Ph.D. Programmable and Customizable Hardware Accelerators for Self-adaptive Virtual Processors in FPGA 2014
Petr Žejdl doc. Ing. Hana Kubátová, CSc.
Dr. Ing. Sven Ubik
Low-Latency Video Transmissions for Real-Time Collaboration with a Scalable Hardware Acceleration 2014
Jiří Kvasnička doc. Ing. Hana Kubátová, CSc. Reliability Analysis of SRAM-based Field-Programmable Gate Arrays 2014
Jiří Halák doc. Ing. Hana Kubátová, CSc.
Dr. Ing. Sven Ubik
Extendable and Scalable FPGA-based High-speed Packet Processing 2013
Martin Šťáva prof. Ing. Ondřej Novák, CSc. Overlapping Non-dedicated Clusters Architecture 2013 (defended at FEL)
Leoš Kafka prof. Ing. Ondřej Novák, CSc. Fault Emulation Techniques for Generic Netlists in FPGAs 2012 (defended at FEL)